OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /funbase_ip_library
    from Rev 134 to Rev 135
    ↔ Reverse comparison
  •

Rev 134 → Rev 135

/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/a2_ddr2_dimm_1GB_phy_autodetectedpins.tcl
0,0 → 1,35
ddr_pin addrcmd_2t {ddr2_dimm_addr[0]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[10]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[11]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[12]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[13]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[1]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[2]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[3]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[4]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[5]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[6]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[7]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[8]} pins
ddr_pin addrcmd_2t {ddr2_dimm_addr[9]} pins
ddr_pin addrcmd_2t {ddr2_dimm_ba[0]} pins
ddr_pin addrcmd_2t {ddr2_dimm_ba[1]} pins
ddr_pin addrcmd_2t {ddr2_dimm_ba[2]} pins
ddr_pin addrcmd_2t ddr2_dimm_cas_n pins
ddr_pin addrcmd_2t ddr2_dimm_ras_n pins
ddr_pin addrcmd_2t ddr2_dimm_we_n pins
ddr_pin ck_p {ddr2_dimm_clk[0]} pins
ddr_pin ck_p {ddr2_dimm_clk[1]} pins
ddr_pin dqsgroup {{ddr2_dimm_dqs[0]} {{ddr2_dimm_dm[0]}} {{ddr2_dimm_dq[0]} {ddr2_dimm_dq[1]} {ddr2_dimm_dq[2]} {ddr2_dimm_dq[3]} {ddr2_dimm_dq[4]} {ddr2_dimm_dq[5]} {ddr2_dimm_dq[6]} {ddr2_dimm_dq[7]}} {ddr2_dimm_dqs_n[0]}} pins
ddr_pin dqsgroup {{ddr2_dimm_dqs[1]} {{ddr2_dimm_dm[1]}} {{ddr2_dimm_dq[10]} {ddr2_dimm_dq[11]} {ddr2_dimm_dq[12]} {ddr2_dimm_dq[13]} {ddr2_dimm_dq[14]} {ddr2_dimm_dq[15]} {ddr2_dimm_dq[8]} {ddr2_dimm_dq[9]}} {ddr2_dimm_dqs_n[1]}} pins
ddr_pin dqsgroup {{ddr2_dimm_dqs[2]} {{ddr2_dimm_dm[2]}} {{ddr2_dimm_dq[16]} {ddr2_dimm_dq[17]} {ddr2_dimm_dq[18]} {ddr2_dimm_dq[19]} {ddr2_dimm_dq[20]} {ddr2_dimm_dq[21]} {ddr2_dimm_dq[22]} {ddr2_dimm_dq[23]}} {ddr2_dimm_dqs_n[2]}} pins
ddr_pin dqsgroup {{ddr2_dimm_dqs[3]} {{ddr2_dimm_dm[3]}} {{ddr2_dimm_dq[24]} {ddr2_dimm_dq[25]} {ddr2_dimm_dq[26]} {ddr2_dimm_dq[27]} {ddr2_dimm_dq[28]} {ddr2_dimm_dq[29]} {ddr2_dimm_dq[30]} {ddr2_dimm_dq[31]}} {ddr2_dimm_dqs_n[3]}} pins
ddr_pin dqsgroup {{ddr2_dimm_dqs[4]} {{ddr2_dimm_dm[4]}} {{ddr2_dimm_dq[32]} {ddr2_dimm_dq[33]} {ddr2_dimm_dq[34]} {ddr2_dimm_dq[35]} {ddr2_dimm_dq[36]} {ddr2_dimm_dq[37]} {ddr2_dimm_dq[38]} {ddr2_dimm_dq[39]}} {ddr2_dimm_dqs_n[4]}} pins
ddr_pin dqsgroup {{ddr2_dimm_dqs[5]} {{ddr2_dimm_dm[5]}} {{ddr2_dimm_dq[40]} {ddr2_dimm_dq[41]} {ddr2_dimm_dq[42]} {ddr2_dimm_dq[43]} {ddr2_dimm_dq[44]} {ddr2_dimm_dq[45]} {ddr2_dimm_dq[46]} {ddr2_dimm_dq[47]}} {ddr2_dimm_dqs_n[5]}} pins
ddr_pin dqsgroup {{ddr2_dimm_dqs[6]} {{ddr2_dimm_dm[6]}} {{ddr2_dimm_dq[48]} {ddr2_dimm_dq[49]} {ddr2_dimm_dq[50]} {ddr2_dimm_dq[51]} {ddr2_dimm_dq[52]} {ddr2_dimm_dq[53]} {ddr2_dimm_dq[54]} {ddr2_dimm_dq[55]}} {ddr2_dimm_dqs_n[6]}} pins
ddr_pin dqsgroup {{ddr2_dimm_dqs[7]} {{ddr2_dimm_dm[7]}} {{ddr2_dimm_dq[56]} {ddr2_dimm_dq[57]} {ddr2_dimm_dq[58]} {ddr2_dimm_dq[59]} {ddr2_dimm_dq[60]} {ddr2_dimm_dq[61]} {ddr2_dimm_dq[62]} {ddr2_dimm_dq[63]}} {ddr2_dimm_dqs_n[7]}} pins
ddr_pin ck_n {ddr2_dimm_clk_n[0]} pins
ddr_pin ck_n {ddr2_dimm_clk_n[1]} pins
ddr_pin addrcmd ddr2_dimm_cke pins
ddr_pin addrcmd ddr2_dimm_odt pins
ddr_pin addrcmd ddr2_dimm_cs_n pins
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/ddr2_sodimm.out.sdc
0,0 → 1,1514
## Generated SDC file "ddr2_sodimm.out.sdc"
 
## Copyright (C) 1991-2011 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
 
 
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version"
 
## DATE "Thu Jul 14 18:33:46 2011"
 
##
## DEVICE "EP2AGX125EF35C4ES"
##
 
 
#**************************************************************
# Time Information
#**************************************************************
 
set_time_format -unit ns -decimal_places 3
 
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name {clkin_top_p} -period 8.000 -waveform { 0.000 4.000 } [get_ports {clkin_top_p}]
create_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]} -period 0.800 -waveform { 0.000 0.400 } [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]}]
create_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll6|clk[0]} -period 0.800 -waveform { 0.000 0.400 } [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll6|clk[0]}]
create_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll5|clk[0]} -period 0.800 -waveform { 0.000 0.400 } [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll5|clk[0]}]
create_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll7|clk[0]} -period 0.800 -waveform { 0.000 0.400 } [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll7|clk[0]}]
create_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll1|clk[0]} -period 0.800 -waveform { 0.000 0.400 } [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll1|clk[0]}]
create_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll3|clk[0]} -period 0.800 -waveform { 0.000 0.400 } [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll3|clk[0]}]
create_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll0|clk[0]} -period 0.800 -waveform { 0.000 0.400 } [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll0|clk[0]}]
create_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll2|clk[0]} -period 0.800 -waveform { 0.000 0.400 } [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll2|clk[0]}]
create_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll4|clk[0]} -period 0.800 -waveform { 0.000 0.400 } [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll4|clk[0]}]
create_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]} -period 5.000 -waveform { 0.000 2.500 } [get_ports {ddr2_dimm_dqs[0]}] -add
create_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]} -period 5.000 -waveform { 0.000 2.500 } [get_ports {ddr2_dimm_dqs[1]}] -add
create_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]} -period 5.000 -waveform { 0.000 2.500 } [get_ports {ddr2_dimm_dqs[2]}] -add
create_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]} -period 5.000 -waveform { 0.000 2.500 } [get_ports {ddr2_dimm_dqs[3]}] -add
create_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]} -period 5.000 -waveform { 0.000 2.500 } [get_ports {ddr2_dimm_dqs[4]}] -add
create_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]} -period 5.000 -waveform { 0.000 2.500 } [get_ports {ddr2_dimm_dqs[5]}] -add
create_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]} -period 5.000 -waveform { 0.000 2.500 } [get_ports {ddr2_dimm_dqs[6]}] -add
create_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]} -period 5.000 -waveform { 0.000 2.500 } [get_ports {ddr2_dimm_dqs[7]}] -add
create_clock -name {pcie_refclk_p} -period 10.000 -waveform { 0.000 5.000 } [get_ports {pcie_refclk_p}]
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -divide_by 5 -phase 31.500 -master_clock {clkin_top_p} [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -master_clock {clkin_top_p} [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -phase -90.000 -master_clock {clkin_top_p} [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}]
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -master_clock {clkin_top_p} [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -divide_by 5 -master_clock {clkin_top_p} [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -duty_cycle 50.000 -multiply_by 1 -divide_by 2 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock} [get_pins {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|analogrefclkpulse} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|analogrefclkpulse}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|refclkout} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|refclkout}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|coreclkout} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|coreclkout}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|analogrefclkout[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|analogrefclkout[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|analogfastrefclkout[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|tx_pll0|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|analogfastrefclkout[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma6|deserclock[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll6|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll6|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma6|deserclock[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma7|deserclock[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll7|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll7|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma7|deserclock[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma5|deserclock[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll5|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll5|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma5|deserclock[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma4|deserclock[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll4|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll4|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma4|deserclock[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma0|deserclock[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll0|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll0|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma0|deserclock[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma1|deserclock[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll1|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll1|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma1|deserclock[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma2|deserclock[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll2|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll2|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma2|deserclock[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma3|deserclock[0]} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll3|clk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 5 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|rx_cdr_pll3|clk[0]} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma3|deserclock[0]}]
create_generated_clock -name {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div1|refclkout} -source [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|refclkout}] -duty_cycle 50.000 -multiply_by 1 -master_clock {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|refclkout} [get_pins {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div1|refclkout}]
create_generated_clock -name {pcie_refclk_p~input~INSERTED_REFCLK_DIVIDER|clkout} -source [get_pins {pcie_refclk_p~input|o}] -duty_cycle 50.000 -multiply_by 1 -master_clock {pcie_refclk_p} [get_pins {pcie_refclk_p~input~INSERTED_REFCLK_DIVIDER|clkout}]
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_clk[0]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_clk[0]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_rise} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_clk[0]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_clk[0]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_clk[1]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_clk[1]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_rise} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_clk[1]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_clk[1]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {ddr2_dimm_clk_n[0]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {ddr2_dimm_clk_n[0]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_rise} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {ddr2_dimm_clk_n[0]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {ddr2_dimm_clk_n[0]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {ddr2_dimm_clk_n[1]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {ddr2_dimm_clk_n[1]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_rise} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {ddr2_dimm_clk_n[1]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} -invert [get_ports {ddr2_dimm_clk_n[1]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -divide_by 2 -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]} [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q}]
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_dqs[0]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_dqs[1]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_dqs[2]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_dqs[3]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_dqs[4]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_dqs[5]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_dqs[6]}] -add
create_generated_clock -name {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]} -source [get_pins {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]} [get_ports {ddr2_dimm_dqs[7]}] -add
 
 
#**************************************************************
# Set Clock Latency
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
 
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.000
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.000
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -rise_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -fall_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -rise_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|coreclkout}] 0.010
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -fall_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|coreclkout}] 0.010
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -rise_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -fall_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -rise_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|coreclkout}] 0.010
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] -fall_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|coreclkout}] 0.010
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.050
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -rise_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.010
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -fall_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.010
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.050
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -rise_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.010
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|ep_plus|epmap|serdes|a2_pex_x8_serdes_alt4gxb_de9b_component|central_clk_div0|rateswitchbaseclock}] -fall_to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}] 0.010
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 0.030
set_clock_uncertainty -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 0.030
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 0.030
set_clock_uncertainty -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 0.030
 
 
#**************************************************************
# Set Input Delay
#**************************************************************
 
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] 0.250 [get_ports {ddr2_dimm_dq[0]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -0.047 [get_ports {ddr2_dimm_dq[0]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] 0.250 [get_ports {ddr2_dimm_dq[1]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -0.047 [get_ports {ddr2_dimm_dq[1]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] 0.250 [get_ports {ddr2_dimm_dq[2]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -0.047 [get_ports {ddr2_dimm_dq[2]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] 0.250 [get_ports {ddr2_dimm_dq[3]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -0.047 [get_ports {ddr2_dimm_dq[3]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] 0.250 [get_ports {ddr2_dimm_dq[4]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -0.047 [get_ports {ddr2_dimm_dq[4]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] 0.250 [get_ports {ddr2_dimm_dq[5]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -0.047 [get_ports {ddr2_dimm_dq[5]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] 0.250 [get_ports {ddr2_dimm_dq[6]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -0.047 [get_ports {ddr2_dimm_dq[6]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] 0.250 [get_ports {ddr2_dimm_dq[7]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -0.047 [get_ports {ddr2_dimm_dq[7]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] 0.250 [get_ports {ddr2_dimm_dq[8]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -0.047 [get_ports {ddr2_dimm_dq[8]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] 0.250 [get_ports {ddr2_dimm_dq[9]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -0.047 [get_ports {ddr2_dimm_dq[9]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] 0.250 [get_ports {ddr2_dimm_dq[10]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -0.047 [get_ports {ddr2_dimm_dq[10]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] 0.250 [get_ports {ddr2_dimm_dq[11]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -0.047 [get_ports {ddr2_dimm_dq[11]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] 0.250 [get_ports {ddr2_dimm_dq[12]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -0.047 [get_ports {ddr2_dimm_dq[12]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] 0.250 [get_ports {ddr2_dimm_dq[13]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -0.047 [get_ports {ddr2_dimm_dq[13]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] 0.250 [get_ports {ddr2_dimm_dq[14]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -0.047 [get_ports {ddr2_dimm_dq[14]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] 0.250 [get_ports {ddr2_dimm_dq[15]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -0.047 [get_ports {ddr2_dimm_dq[15]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] 0.250 [get_ports {ddr2_dimm_dq[16]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -0.047 [get_ports {ddr2_dimm_dq[16]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] 0.250 [get_ports {ddr2_dimm_dq[17]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -0.047 [get_ports {ddr2_dimm_dq[17]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] 0.250 [get_ports {ddr2_dimm_dq[18]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -0.047 [get_ports {ddr2_dimm_dq[18]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] 0.250 [get_ports {ddr2_dimm_dq[19]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -0.047 [get_ports {ddr2_dimm_dq[19]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] 0.250 [get_ports {ddr2_dimm_dq[20]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -0.047 [get_ports {ddr2_dimm_dq[20]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] 0.250 [get_ports {ddr2_dimm_dq[21]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -0.047 [get_ports {ddr2_dimm_dq[21]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] 0.250 [get_ports {ddr2_dimm_dq[22]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -0.047 [get_ports {ddr2_dimm_dq[22]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] 0.250 [get_ports {ddr2_dimm_dq[23]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -0.047 [get_ports {ddr2_dimm_dq[23]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] 0.250 [get_ports {ddr2_dimm_dq[24]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -0.047 [get_ports {ddr2_dimm_dq[24]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] 0.250 [get_ports {ddr2_dimm_dq[25]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -0.047 [get_ports {ddr2_dimm_dq[25]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] 0.250 [get_ports {ddr2_dimm_dq[26]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -0.047 [get_ports {ddr2_dimm_dq[26]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] 0.250 [get_ports {ddr2_dimm_dq[27]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -0.047 [get_ports {ddr2_dimm_dq[27]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] 0.250 [get_ports {ddr2_dimm_dq[28]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -0.047 [get_ports {ddr2_dimm_dq[28]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] 0.250 [get_ports {ddr2_dimm_dq[29]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -0.047 [get_ports {ddr2_dimm_dq[29]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] 0.250 [get_ports {ddr2_dimm_dq[30]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -0.047 [get_ports {ddr2_dimm_dq[30]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] 0.250 [get_ports {ddr2_dimm_dq[31]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -0.047 [get_ports {ddr2_dimm_dq[31]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] 0.250 [get_ports {ddr2_dimm_dq[32]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -0.047 [get_ports {ddr2_dimm_dq[32]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] 0.250 [get_ports {ddr2_dimm_dq[33]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -0.047 [get_ports {ddr2_dimm_dq[33]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] 0.250 [get_ports {ddr2_dimm_dq[34]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -0.047 [get_ports {ddr2_dimm_dq[34]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] 0.250 [get_ports {ddr2_dimm_dq[35]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -0.047 [get_ports {ddr2_dimm_dq[35]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] 0.250 [get_ports {ddr2_dimm_dq[36]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -0.047 [get_ports {ddr2_dimm_dq[36]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] 0.250 [get_ports {ddr2_dimm_dq[37]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -0.047 [get_ports {ddr2_dimm_dq[37]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] 0.250 [get_ports {ddr2_dimm_dq[38]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -0.047 [get_ports {ddr2_dimm_dq[38]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] 0.250 [get_ports {ddr2_dimm_dq[39]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -0.047 [get_ports {ddr2_dimm_dq[39]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] 0.250 [get_ports {ddr2_dimm_dq[40]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -0.047 [get_ports {ddr2_dimm_dq[40]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] 0.250 [get_ports {ddr2_dimm_dq[41]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -0.047 [get_ports {ddr2_dimm_dq[41]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] 0.250 [get_ports {ddr2_dimm_dq[42]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -0.047 [get_ports {ddr2_dimm_dq[42]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] 0.250 [get_ports {ddr2_dimm_dq[43]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -0.047 [get_ports {ddr2_dimm_dq[43]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] 0.250 [get_ports {ddr2_dimm_dq[44]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -0.047 [get_ports {ddr2_dimm_dq[44]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] 0.250 [get_ports {ddr2_dimm_dq[45]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -0.047 [get_ports {ddr2_dimm_dq[45]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] 0.250 [get_ports {ddr2_dimm_dq[46]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -0.047 [get_ports {ddr2_dimm_dq[46]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] 0.250 [get_ports {ddr2_dimm_dq[47]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -0.047 [get_ports {ddr2_dimm_dq[47]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] 0.250 [get_ports {ddr2_dimm_dq[48]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -0.047 [get_ports {ddr2_dimm_dq[48]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] 0.250 [get_ports {ddr2_dimm_dq[49]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -0.047 [get_ports {ddr2_dimm_dq[49]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] 0.250 [get_ports {ddr2_dimm_dq[50]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -0.047 [get_ports {ddr2_dimm_dq[50]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] 0.250 [get_ports {ddr2_dimm_dq[51]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -0.047 [get_ports {ddr2_dimm_dq[51]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] 0.250 [get_ports {ddr2_dimm_dq[52]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -0.047 [get_ports {ddr2_dimm_dq[52]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] 0.250 [get_ports {ddr2_dimm_dq[53]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -0.047 [get_ports {ddr2_dimm_dq[53]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] 0.250 [get_ports {ddr2_dimm_dq[54]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -0.047 [get_ports {ddr2_dimm_dq[54]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] 0.250 [get_ports {ddr2_dimm_dq[55]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -0.047 [get_ports {ddr2_dimm_dq[55]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] 0.250 [get_ports {ddr2_dimm_dq[56]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -0.047 [get_ports {ddr2_dimm_dq[56]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] 0.250 [get_ports {ddr2_dimm_dq[57]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -0.047 [get_ports {ddr2_dimm_dq[57]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] 0.250 [get_ports {ddr2_dimm_dq[58]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -0.047 [get_ports {ddr2_dimm_dq[58]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] 0.250 [get_ports {ddr2_dimm_dq[59]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -0.047 [get_ports {ddr2_dimm_dq[59]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] 0.250 [get_ports {ddr2_dimm_dq[60]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -0.047 [get_ports {ddr2_dimm_dq[60]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] 0.250 [get_ports {ddr2_dimm_dq[61]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -0.047 [get_ports {ddr2_dimm_dq[61]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] 0.250 [get_ports {ddr2_dimm_dq[62]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -0.047 [get_ports {ddr2_dimm_dq[62]}]
set_input_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] 0.250 [get_ports {ddr2_dimm_dq[63]}]
set_input_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -0.047 [get_ports {ddr2_dimm_dq[63]}]
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
 
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[3]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[3]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[3]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[3]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[4]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[4]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[4]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[4]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[5]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[5]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[5]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[5]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[6]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[6]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[6]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[6]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[7]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[7]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[7]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[7]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[8]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[8]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[8]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[8]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[8]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[8]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[8]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[8]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[9]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[9]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[9]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[9]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[9]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[9]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[9]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[9]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[10]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[10]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[10]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[10]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[10]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[10]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[10]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[10]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[11]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[11]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[11]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[11]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[11]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[11]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[11]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[11]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[12]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[12]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[12]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[12]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[12]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[12]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[12]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[12]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[13]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[13]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[13]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[13]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[13]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[13]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_addr[13]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_addr[13]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ba[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ba[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cas_n}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cas_n}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cas_n}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cas_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cas_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cas_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cas_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cas_n}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cke}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cke}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cke}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cke}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cke}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cke}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cke}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cke}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cs_n}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cs_n}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cs_n}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cs_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cs_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cs_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_cs_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_cs_n}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dm[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dm[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dm[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dm[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dm[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dm[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dm[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dm[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dm[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dm[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dm[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dm[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dm[3]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dm[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dm[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dm[3]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dm[4]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dm[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dm[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dm[4]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dm[5]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dm[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dm[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dm[5]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dm[6]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dm[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dm[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dm[6]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dm[7]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dm[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dm[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dm[7]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[3]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[3]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[4]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[4]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[5]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[5]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[6]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[6]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[7]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] 0.370 [get_ports {ddr2_dimm_dq[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -0.415 [get_ports {ddr2_dimm_dq[7]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[8]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[8]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[8]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[8]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[9]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[9]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[9]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[9]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[10]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[10]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[10]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[10]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[11]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[11]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[11]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[11]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[12]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[12]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[12]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[12]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[13]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[13]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[13]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[13]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[14]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[14]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[14]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[14]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[15]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[15]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] 0.370 [get_ports {ddr2_dimm_dq[15]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -0.415 [get_ports {ddr2_dimm_dq[15]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[16]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[16]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[16]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[16]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[17]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[17]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[17]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[17]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[18]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[18]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[18]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[18]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[19]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[19]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[19]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[19]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[20]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[20]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[20]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[20]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[21]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[21]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[21]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[21]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[22]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[22]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[22]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[22]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[23]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[23]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] 0.370 [get_ports {ddr2_dimm_dq[23]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -0.415 [get_ports {ddr2_dimm_dq[23]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[24]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[24]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[24]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[24]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[25]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[25]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[25]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[25]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[26]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[26]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[26]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[26]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[27]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[27]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[27]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[27]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[28]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[28]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[28]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[28]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[29]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[29]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[29]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[29]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[30]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[30]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[30]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[30]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[31]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[31]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] 0.370 [get_ports {ddr2_dimm_dq[31]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -0.415 [get_ports {ddr2_dimm_dq[31]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[32]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[32]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[32]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[32]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[33]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[33]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[33]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[33]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[34]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[34]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[34]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[34]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[35]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[35]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[35]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[35]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[36]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[36]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[36]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[36]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[37]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[37]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[37]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[37]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[38]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[38]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[38]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[38]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[39]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[39]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] 0.370 [get_ports {ddr2_dimm_dq[39]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -0.415 [get_ports {ddr2_dimm_dq[39]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[40]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[40]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[40]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[40]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[41]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[41]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[41]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[41]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[42]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[42]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[42]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[42]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[43]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[43]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[43]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[43]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[44]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[44]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[44]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[44]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[45]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[45]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[45]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[45]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[46]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[46]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[46]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[46]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[47]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[47]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] 0.370 [get_ports {ddr2_dimm_dq[47]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -0.415 [get_ports {ddr2_dimm_dq[47]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[48]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[48]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[48]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[48]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[49]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[49]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[49]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[49]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[50]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[50]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[50]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[50]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[51]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[51]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[51]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[51]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[52]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[52]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[52]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[52]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[53]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[53]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[53]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[53]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[54]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[54]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[54]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[54]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[55]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[55]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] 0.370 [get_ports {ddr2_dimm_dq[55]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -0.415 [get_ports {ddr2_dimm_dq[55]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[56]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[56]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[56]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[56]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[57]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[57]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[57]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[57]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[58]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[58]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[58]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[58]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[59]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[59]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[59]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[59]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[60]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[60]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[60]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[60]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[61]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[61]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[61]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[61]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[62]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[62]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[62]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[62]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[63]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[63]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] 0.370 [get_ports {ddr2_dimm_dq[63]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -0.415 [get_ports {ddr2_dimm_dq[63]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[0]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[1]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[2]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[3]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[4]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[5]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[6]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] 1.020 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}] -1.020 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 3.770 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}] 1.230 [get_ports {ddr2_dimm_dqs[7]}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_odt}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_odt}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_odt}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_odt}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_odt}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_odt}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_odt}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_odt}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ras_n}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ras_n}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ras_n}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ras_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ras_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ras_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_ras_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_ras_n}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_we_n}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_we_n}]
set_output_delay -add_delay -max -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_we_n}]
set_output_delay -add_delay -min -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_we_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] 0.395 [get_ports {ddr2_dimm_we_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}] -0.395 [get_ports {ddr2_dimm_we_n}]
set_output_delay -add_delay -max -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] 0.395 [get_ports {ddr2_dimm_we_n}]
set_output_delay -add_delay -min -clock_fall -clock [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}] -0.395 [get_ports {ddr2_dimm_we_n}]
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
 
 
 
#**************************************************************
# Set False Path
#**************************************************************
 
set_false_path -from [get_clocks {clkin_top_p}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {clkin_top_p}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[0]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}]
set_false_path -setup -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}]
set_false_path -setup -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}]
set_false_path -hold -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}]
set_false_path -hold -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}]
set_false_path -setup -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}]
set_false_path -setup -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}]
set_false_path -hold -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}]
set_false_path -hold -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[2]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}]
set_false_path -setup -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}]
set_false_path -setup -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}]
set_false_path -hold -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}]
set_false_path -hold -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}]
set_false_path -setup -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}]
set_false_path -setup -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}]
set_false_path -hold -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}]
set_false_path -hold -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}]
set_false_path -setup -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}]
set_false_path -setup -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}]
set_false_path -hold -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}]
set_false_path -hold -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[5]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}]
set_false_path -setup -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}]
set_false_path -setup -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}]
set_false_path -hold -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}]
set_false_path -hold -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[6]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}]
set_false_path -setup -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}]
set_false_path -setup -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}]
set_false_path -hold -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}]
set_false_path -hold -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDQSS}]
set_false_path -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDQSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_tDSS}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_tDSS}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsin_ddr2_dimm_dqs[7]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}]
set_false_path -setup -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}]
set_false_path -setup -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}]
set_false_path -hold -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}]
set_false_path -hold -fall_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[0]_ac_fall}]
set_false_path -rise_from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_n_ddr2_dimm_clk_n[1]_ac_fall}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_fall}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_fall}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[0]_ac_rise}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ck_p_ddr2_dimm_clk[1]_ac_rise}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {a2_pex_x8_app|ep_plus|epmap|wrapper|altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip|coreclkout}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_md9:dffpipe9|dffe10a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_ld9:dffpipe6|dffe7a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe20|dffe21a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe17|dffe18a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_nd9:dffpipe16|dffe17a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_fd9:dffpipe13|dffe14a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe13|dffe14a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe10|dffe11a*}]
set_false_path -from [get_ports {{ddr2_dimm_clk[0]} {ddr2_dimm_clk[1]}}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}]
set_false_path -to [get_ports {ddr2_dimm_clk[0]}]
set_false_path -to [get_ports {ddr2_dimm_clk[1]}]
set_false_path -to [get_ports {ddr2_dimm_clk_n[0]}]
set_false_path -to [get_ports {ddr2_dimm_clk_n[1]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs[0]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs_n[0]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[0]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs[1]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs_n[1]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[1]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs[2]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs_n[2]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[2]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs[3]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs_n[3]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[3]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs[4]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs_n[4]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[4]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs[5]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs_n[5]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[5]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs[6]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs_n[6]}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[6]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs[7]}]
set_false_path -from [all_registers] -to [get_ports {ddr2_dimm_dqs_n[7]}]
set_false_path -from [get_keepers {*bidir_dq_*_oe_ff_inst}]
set_false_path -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]}] -through [get_nets {*ams_pipe*}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_ddr_dqsout_ddr2_dimm_dqs[7]}]
set_false_path -from [get_keepers {{ddr2_dimm_dq[0]} {ddr2_dimm_dq[1]} {ddr2_dimm_dq[2]} {ddr2_dimm_dq[3]} {ddr2_dimm_dq[4]} {ddr2_dimm_dq[5]} {ddr2_dimm_dq[6]} {ddr2_dimm_dq[7]} {ddr2_dimm_dq[10]} {ddr2_dimm_dq[11]} {ddr2_dimm_dq[12]} {ddr2_dimm_dq[13]} {ddr2_dimm_dq[14]} {ddr2_dimm_dq[15]} {ddr2_dimm_dq[8]} {ddr2_dimm_dq[9]} {ddr2_dimm_dq[16]} {ddr2_dimm_dq[17]} {ddr2_dimm_dq[18]} {ddr2_dimm_dq[19]} {ddr2_dimm_dq[20]} {ddr2_dimm_dq[21]} {ddr2_dimm_dq[22]} {ddr2_dimm_dq[23]} {ddr2_dimm_dq[24]} {ddr2_dimm_dq[25]} {ddr2_dimm_dq[26]} {ddr2_dimm_dq[27]} {ddr2_dimm_dq[28]} {ddr2_dimm_dq[29]} {ddr2_dimm_dq[30]} {ddr2_dimm_dq[31]} {ddr2_dimm_dq[32]} {ddr2_dimm_dq[33]} {ddr2_dimm_dq[34]} {ddr2_dimm_dq[35]} {ddr2_dimm_dq[36]} {ddr2_dimm_dq[37]} {ddr2_dimm_dq[38]} {ddr2_dimm_dq[39]} {ddr2_dimm_dq[40]} {ddr2_dimm_dq[41]} {ddr2_dimm_dq[42]} {ddr2_dimm_dq[43]} {ddr2_dimm_dq[44]} {ddr2_dimm_dq[45]} {ddr2_dimm_dq[46]} {ddr2_dimm_dq[47]} {ddr2_dimm_dq[48]} {ddr2_dimm_dq[49]} {ddr2_dimm_dq[50]} {ddr2_dimm_dq[51]} {ddr2_dimm_dq[52]} {ddr2_dimm_dq[53]} {ddr2_dimm_dq[54]} {ddr2_dimm_dq[55]} {ddr2_dimm_dq[56]} {ddr2_dimm_dq[57]} {ddr2_dimm_dq[58]} {ddr2_dimm_dq[59]} {ddr2_dimm_dq[60]} {ddr2_dimm_dq[61]} {ddr2_dimm_dq[62]} {ddr2_dimm_dq[63]}}] -to [get_keepers {*datain_reg*}]
set_false_path -from [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|*seq_wrapper|*seq_inst|*dgrb|?d_lat*|clk}]
set_false_path -from [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|*seq_wrapper|*seq_inst|seq_mem_clk_disable*}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|*pll|altpll_component|auto_generated|pll_lock_sync|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|global_pre_clear|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|reset_master_ams|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|mem_clk_pipe|ams_pipe[*]|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|write_clk_pipe|ams_pipe[*]|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|measure_clk_pipe|ams_pipe[*]|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|clk_div_reset_ams_n_r|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|clk_div_reset_ams_n|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|pll_reconfig_reset_ams_n_r|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|pll_reconfig_reset_ams_n|clrn}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|phs_shft_busy_siii|d}]
set_false_path -through [get_pins -compatibility_mode {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy*_inst|clk|poa_clk_pipe|ams_pipe[*]|clrn}]
set_false_path -from [get_pins -compatibility_mode {*_alt_mem_phy_inst|*seq_wrapper|*seq_inst|*|seq_mmc_start*|*}] -to [get_keepers {*alt_mem_phy_mimic:mmc|seq_mmc_start_metastable*}]
set_false_path -from [get_keepers {*_alt_mem_phy_inst|*seq_wrapper|*seq_inst|seq_ac_add_1t_ac_lat_internal*}]
set_false_path -from [get_pins -compatibility_mode {*_alt_mem_phy_inst|*mmc|mimic_done_out*}] -to [get_keepers {*_alt_mem_phy_inst|*seq_wrapper|*seq_inst|*dgrb|*v_mmc_seq_done_1r*}]
set_false_path -from [all_registers] -to [get_keepers {ddr2_dimm_cke ddr2_dimm_odt ddr2_dimm_cs_n {ddr2_dimm_addr[0]} {ddr2_dimm_addr[10]} {ddr2_dimm_addr[11]} {ddr2_dimm_addr[12]} {ddr2_dimm_addr[13]} {ddr2_dimm_addr[1]} {ddr2_dimm_addr[2]} {ddr2_dimm_addr[3]} {ddr2_dimm_addr[4]} {ddr2_dimm_addr[5]} {ddr2_dimm_addr[6]} {ddr2_dimm_addr[7]} {ddr2_dimm_addr[8]} {ddr2_dimm_addr[9]} {ddr2_dimm_ba[0]} {ddr2_dimm_ba[1]} {ddr2_dimm_ba[2]} ddr2_dimm_cas_n ddr2_dimm_ras_n ddr2_dimm_we_n}]
set_false_path -to [get_keepers {*|a2_pex_x8_serdes:serdes|*|tx_digitalreset_reg0c[0]}]
set_false_path -to [get_keepers {*|a2_pex_x8_serdes:serdes|*|rx_digitalreset_reg0c[0]}]
 
 
#**************************************************************
# Set Multicycle Path
#**************************************************************
 
set_multicycle_path -setup -end -to [get_keepers {{ddr2_dimm_addr[0]} {ddr2_dimm_addr[10]} {ddr2_dimm_addr[11]} {ddr2_dimm_addr[12]} {ddr2_dimm_addr[13]} {ddr2_dimm_addr[1]} {ddr2_dimm_addr[2]} {ddr2_dimm_addr[3]} {ddr2_dimm_addr[4]} {ddr2_dimm_addr[5]} {ddr2_dimm_addr[6]} {ddr2_dimm_addr[7]} {ddr2_dimm_addr[8]} {ddr2_dimm_addr[9]} {ddr2_dimm_ba[0]} {ddr2_dimm_ba[1]} {ddr2_dimm_ba[2]} ddr2_dimm_cas_n ddr2_dimm_ras_n ddr2_dimm_we_n}] 2
set_multicycle_path -hold -end -to [get_keepers {{ddr2_dimm_addr[0]} {ddr2_dimm_addr[10]} {ddr2_dimm_addr[11]} {ddr2_dimm_addr[12]} {ddr2_dimm_addr[13]} {ddr2_dimm_addr[1]} {ddr2_dimm_addr[2]} {ddr2_dimm_addr[3]} {ddr2_dimm_addr[4]} {ddr2_dimm_addr[5]} {ddr2_dimm_addr[6]} {ddr2_dimm_addr[7]} {ddr2_dimm_addr[8]} {ddr2_dimm_addr[9]} {ddr2_dimm_ba[0]} {ddr2_dimm_ba[1]} {ddr2_dimm_ba[2]} ddr2_dimm_cas_n ddr2_dimm_ras_n ddr2_dimm_we_n}] 1
set_multicycle_path -setup -start -from [get_keepers {*|a2_pex_x8_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_wr}] 1
set_multicycle_path -setup -end -from [get_keepers {*|a2_pex_x8_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] 3
set_multicycle_path -hold -end -from [get_keepers {*|a2_pex_x8_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] 3
 
 
#**************************************************************
# Set Maximum Delay
#**************************************************************
 
set_max_delay -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 9.000
set_max_delay -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] 9.000
set_max_delay -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] 5.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[4] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma2~OBSERVABLE_FORCE_ELEC_IDLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma2~OBSERVABLE_TX_DET_RX }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[2] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs5~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs5~OBSERVABLEQUADRESET }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[14] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma7~OBSERVABLE_FORCE_ELEC_IDLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma7~OBSERVABLE_TX_DET_RX }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[7] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs4~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs4~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma2~OBSERVABLE_LOCK_TO_REF }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLEDPRIOLOAD }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLEDPRIODISABLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLERXDIGITALRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLETXDIGITALRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLERXANALOGRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLEDPRIORESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs5~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs5~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs3~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs3~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma3~OBSERVABLE_LOCK_TO_REF }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[8] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma4~OBSERVABLE_FORCE_ELEC_IDLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma4~OBSERVABLE_TX_DET_RX }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[4] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs7~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs7~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma5~OBSERVABLE_LOCK_TO_REF }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs0~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs0~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs0~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs0~OBSERVABLEQUADRESET }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[0] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma0~OBSERVABLE_FORCE_ELEC_IDLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma0~OBSERVABLE_TX_DET_RX }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[0] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs6~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs6~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLEDPRIOLOAD }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLEDPRIODISABLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLERXDIGITALRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLETXDIGITALRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLERXANALOGRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLEDPRIORESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs1~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs1~OBSERVABLEQUADRESET }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[10] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma5~OBSERVABLE_FORCE_ELEC_IDLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma5~OBSERVABLE_TX_DET_RX }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[5] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma6~OBSERVABLE_LOCK_TO_REF }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma0~OBSERVABLE_LOCK_TO_REF }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[2] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma1~OBSERVABLE_FORCE_ELEC_IDLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma1~OBSERVABLE_TX_DET_RX }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[1] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs7~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs7~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs4~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs4~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs2~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs2~OBSERVABLEQUADRESET }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[12] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma6~OBSERVABLE_FORCE_ELEC_IDLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma6~OBSERVABLE_TX_DET_RX }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[6] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma7~OBSERVABLE_LOCK_TO_REF }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs1~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs1~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma1~OBSERVABLE_LOCK_TO_REF }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs3~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs3~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs2~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs2~OBSERVABLEQUADRESET }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[6] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma3~OBSERVABLE_FORCE_ELEC_IDLE }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma3~OBSERVABLE_TX_DET_RX }] 20.000
set_max_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[3] }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs6~OBSERVABLE_DIGITAL_RESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs6~OBSERVABLEQUADRESET }] 20.000
set_max_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma4~OBSERVABLE_LOCK_TO_REF }] 20.000
set_max_delay -from [get_keepers {{ddr2_dimm_dq[0]} {ddr2_dimm_dq[1]} {ddr2_dimm_dq[2]} {ddr2_dimm_dq[3]} {ddr2_dimm_dq[4]} {ddr2_dimm_dq[5]} {ddr2_dimm_dq[6]} {ddr2_dimm_dq[7]}}] -0.036
set_max_delay -from [get_keepers {{ddr2_dimm_dq[10]} {ddr2_dimm_dq[11]} {ddr2_dimm_dq[12]} {ddr2_dimm_dq[13]} {ddr2_dimm_dq[14]} {ddr2_dimm_dq[15]} {ddr2_dimm_dq[8]} {ddr2_dimm_dq[9]}}] -0.036
set_max_delay -from [get_keepers {{ddr2_dimm_dq[16]} {ddr2_dimm_dq[17]} {ddr2_dimm_dq[18]} {ddr2_dimm_dq[19]} {ddr2_dimm_dq[20]} {ddr2_dimm_dq[21]} {ddr2_dimm_dq[22]} {ddr2_dimm_dq[23]}}] -0.036
set_max_delay -from [get_keepers {{ddr2_dimm_dq[24]} {ddr2_dimm_dq[25]} {ddr2_dimm_dq[26]} {ddr2_dimm_dq[27]} {ddr2_dimm_dq[28]} {ddr2_dimm_dq[29]} {ddr2_dimm_dq[30]} {ddr2_dimm_dq[31]}}] -0.036
set_max_delay -from [get_keepers {{ddr2_dimm_dq[32]} {ddr2_dimm_dq[33]} {ddr2_dimm_dq[34]} {ddr2_dimm_dq[35]} {ddr2_dimm_dq[36]} {ddr2_dimm_dq[37]} {ddr2_dimm_dq[38]} {ddr2_dimm_dq[39]}}] -0.036
set_max_delay -from [get_keepers {{ddr2_dimm_dq[40]} {ddr2_dimm_dq[41]} {ddr2_dimm_dq[42]} {ddr2_dimm_dq[43]} {ddr2_dimm_dq[44]} {ddr2_dimm_dq[45]} {ddr2_dimm_dq[46]} {ddr2_dimm_dq[47]}}] -0.036
set_max_delay -from [get_keepers {{ddr2_dimm_dq[48]} {ddr2_dimm_dq[49]} {ddr2_dimm_dq[50]} {ddr2_dimm_dq[51]} {ddr2_dimm_dq[52]} {ddr2_dimm_dq[53]} {ddr2_dimm_dq[54]} {ddr2_dimm_dq[55]}}] -0.036
set_max_delay -from [get_keepers {{ddr2_dimm_dq[56]} {ddr2_dimm_dq[57]} {ddr2_dimm_dq[58]} {ddr2_dimm_dq[59]} {ddr2_dimm_dq[60]} {ddr2_dimm_dq[61]} {ddr2_dimm_dq[62]} {ddr2_dimm_dq[63]}}] -0.036
 
 
#**************************************************************
# Set Minimum Delay
#**************************************************************
 
set_min_delay -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -9.000
set_min_delay -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|scan_clk|q_clock}] -9.000
set_min_delay -from [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]}] -to [get_clocks {a2_pex_x8_app|test_app|\gen_2:mem_ctrl|a2_ddr2_dimm_1GB_controller_phy_inst|a2_ddr2_dimm_1GB_phy_inst|a2_ddr2_dimm_1GB_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]}] -5.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[2] }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[4] }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma2~OBSERVABLE_FORCE_ELEC_IDLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma2~OBSERVABLE_TX_DET_RX }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs5~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs5~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[7] }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[14] }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma7~OBSERVABLE_FORCE_ELEC_IDLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma7~OBSERVABLE_TX_DET_RX }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs4~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs4~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma2~OBSERVABLE_LOCK_TO_REF }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLEDPRIORESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLEDPRIOLOAD }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLEDPRIODISABLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLERXDIGITALRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLETXDIGITALRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit0~OBSERVABLERXANALOGRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs5~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs5~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs3~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs3~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma3~OBSERVABLE_LOCK_TO_REF }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[4] }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[8] }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma4~OBSERVABLE_FORCE_ELEC_IDLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma4~OBSERVABLE_TX_DET_RX }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs7~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs7~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma5~OBSERVABLE_LOCK_TO_REF }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs0~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs0~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs0~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs0~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[0] }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[0] }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma0~OBSERVABLE_FORCE_ELEC_IDLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma0~OBSERVABLE_TX_DET_RX }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs6~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs6~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLEDPRIORESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLEDPRIOLOAD }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLEDPRIODISABLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLERXDIGITALRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLETXDIGITALRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|cent_unit1~OBSERVABLERXANALOGRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs1~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs1~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[5] }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[10] }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma5~OBSERVABLE_FORCE_ELEC_IDLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma5~OBSERVABLE_TX_DET_RX }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma6~OBSERVABLE_LOCK_TO_REF }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma0~OBSERVABLE_LOCK_TO_REF }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[1] }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[2] }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma1~OBSERVABLE_FORCE_ELEC_IDLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma1~OBSERVABLE_TX_DET_RX }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs7~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs7~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs4~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs4~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs2~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs2~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[6] }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[12] }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma6~OBSERVABLE_FORCE_ELEC_IDLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma6~OBSERVABLE_TX_DET_RX }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma7~OBSERVABLE_LOCK_TO_REF }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs1~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs1~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma1~OBSERVABLE_LOCK_TO_REF }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs3~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pcs3~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs2~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs2~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|tx_rxdetectvalidout[3] }] 0.000
set_min_delay -from [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|rx_pcs_rxfound_wire[6] }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma3~OBSERVABLE_FORCE_ELEC_IDLE }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pma3~OBSERVABLE_TX_DET_RX }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs6~OBSERVABLEQUADRESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|transmit_pcs6~OBSERVABLE_DIGITAL_RESET }] 0.000
set_min_delay -to [get_ports { a2_pex_x8_app_if:a2_pex_x8_app|a2_pex_x8_plus:ep_plus|a2_pex_x8:epmap|a2_pex_x8_serdes:serdes|a2_pex_x8_serdes_alt4gxb_de9b:a2_pex_x8_serdes_alt4gxb_de9b_component|receive_pma4~OBSERVABLE_LOCK_TO_REF }] 0.000
set_min_delay -from [get_keepers {{ddr2_dimm_dq[0]} {ddr2_dimm_dq[1]} {ddr2_dimm_dq[2]} {ddr2_dimm_dq[3]} {ddr2_dimm_dq[4]} {ddr2_dimm_dq[5]} {ddr2_dimm_dq[6]} {ddr2_dimm_dq[7]}}] -1.931
set_min_delay -from [get_keepers {{ddr2_dimm_dq[10]} {ddr2_dimm_dq[11]} {ddr2_dimm_dq[12]} {ddr2_dimm_dq[13]} {ddr2_dimm_dq[14]} {ddr2_dimm_dq[15]} {ddr2_dimm_dq[8]} {ddr2_dimm_dq[9]}}] -1.931
set_min_delay -from [get_keepers {{ddr2_dimm_dq[16]} {ddr2_dimm_dq[17]} {ddr2_dimm_dq[18]} {ddr2_dimm_dq[19]} {ddr2_dimm_dq[20]} {ddr2_dimm_dq[21]} {ddr2_dimm_dq[22]} {ddr2_dimm_dq[23]}}] -1.931
set_min_delay -from [get_keepers {{ddr2_dimm_dq[24]} {ddr2_dimm_dq[25]} {ddr2_dimm_dq[26]} {ddr2_dimm_dq[27]} {ddr2_dimm_dq[28]} {ddr2_dimm_dq[29]} {ddr2_dimm_dq[30]} {ddr2_dimm_dq[31]}}] -1.931
set_min_delay -from [get_keepers {{ddr2_dimm_dq[32]} {ddr2_dimm_dq[33]} {ddr2_dimm_dq[34]} {ddr2_dimm_dq[35]} {ddr2_dimm_dq[36]} {ddr2_dimm_dq[37]} {ddr2_dimm_dq[38]} {ddr2_dimm_dq[39]}}] -1.931
set_min_delay -from [get_keepers {{ddr2_dimm_dq[40]} {ddr2_dimm_dq[41]} {ddr2_dimm_dq[42]} {ddr2_dimm_dq[43]} {ddr2_dimm_dq[44]} {ddr2_dimm_dq[45]} {ddr2_dimm_dq[46]} {ddr2_dimm_dq[47]}}] -1.931
set_min_delay -from [get_keepers {{ddr2_dimm_dq[48]} {ddr2_dimm_dq[49]} {ddr2_dimm_dq[50]} {ddr2_dimm_dq[51]} {ddr2_dimm_dq[52]} {ddr2_dimm_dq[53]} {ddr2_dimm_dq[54]} {ddr2_dimm_dq[55]}}] -1.931
set_min_delay -from [get_keepers {{ddr2_dimm_dq[56]} {ddr2_dimm_dq[57]} {ddr2_dimm_dq[58]} {ddr2_dimm_dq[59]} {ddr2_dimm_dq[60]} {ddr2_dimm_dq[61]} {ddr2_dimm_dq[62]} {ddr2_dimm_dq[63]}}] -1.931
 
 
#**************************************************************
# Set Input Transition
#**************************************************************
 
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/a2gx_dev_kit_golden_top.v
0,0 → 1,754
//--------------------------------------------------------------------------//
// Title: a2gx_pcie_top.v //
// Rev: Rev 3 //
//--------------------------------------------------------------------------//
// Description: Golden Top file contains Stratix IV GX PCI Express Board //
// pins and I/O Standards. //
//--------------------------------------------------------------------------//
// Revision History: //
// 1: Initial //
// 2: Swap user_pb[1:0] with ddr2_dimm_a[4:0] //
// 3: Correct pin locations. //
//------ 1 ------- 2 ------- 3 ------- 4 ------- 5 ------- 6 ------- 7 ------7
//------ 0 ------- 0 ------- 0 ------- 0 ------- 0 ------- 0 ------- 0 ------8
 
//are protected under numerous U.S. and foreign patents, maskwork rights,
//copyrights and other intellectual property laws.
//
//This reference design file, and your use thereof, is subject to and
//governed by the terms and conditions of the applicable Altera Reference
//Design License Agreement. By using this reference design file, you
//indicate your acceptance of such terms and conditions between you and
//Altera Corporation. In the event that you do not agree with such terms and
//conditions, you may not use the reference design file. Please promptly
//destroy any copies you have made.
//
//This reference design file being provided on an "as-is" basis and as an
//accommodation and therefore all warranties, representations or guarantees
//of any kind(whether express, implied or statutory) including, without
//limitation, warranties of merchantability, non-infringement, or fitness for
//a particular purpose, are specifically disclaimed. By making this
//reference design file available, Altera expressly does not recommend,
//suggest or require that this reference design file be used in combination
//with any other product not provided by Altera
//----------------------------------------------------------------------------
 
//`default_nettype none
 
module a2gx_dev_kit_golden_top(
//CLK-Inputs---------------------------//15 pins
//wired through XCVR blocks, all AC-coupled)
// input clkin_ref_q1_1_p, //LVDS //adj. defaut 100.000 MHz osc
// input clkin_ref_q1_2_p, //LVDS //adj. defaut 125.000 MHz osc
// input clkin_ref_q2_p, //LVDS //adj. default 125.000 MHz osc
// input clkin_ref_q3_p, //LVDS //adj. default 125.000 MHz osc
// input clkin_155_p, //LVPECL //155.520 MHz osc
input clkin_bot_p, //LVDS //ADJ default 100.000 MHz osc or sma in(Requires external termination.)
input clkin_top_p, //LVDS //ADJ default 125.000 MHz osc(Requires external termination.)
output clkout_sma, //1.8V //PLL CLK sma out
 
////DDR3-SDRAM-PORTS -> 64Mx16 Interface ---------------------//49 pins
/* output [14:0] ddr3_a, //SSTL15 //Address(1Gb max)
output [2:0] ddr3_ba, //SSTL15 //Bank address
inout [15:0] ddr3_dq, //SSTL15 //Data
inout [1:0] ddr3_dqs_p, //SSTL15 //Strobe Pos
inout [1:0] ddr3_dqs_n, //SSTL15 //Strobe Neg
output [1:0] ddr3_dm, //SSTL15 //Byte write mask
output ddr3_wen, //SSTL15 //Write enable
output ddr3_rasn, //SSTL15 //Row address select
output ddr3_casn, //SSTL15 //Column address select
inout ddr3_ck_p, //SSTL15 //System Clock Pos
inout ddr3_ck_n, //SSTL15 //System Clock Neg
output ddr3_cke, //SSTL15 //Clock Enable
output ddr3_csn, //SSTL15 //Chip Select
output ddr3_resetn, //SSTL15 //Reset
output ddr3_odt, //SSTL15 //On-die termination enable*/
//DDR2 SDRAM SoDIMM -------------------------------------//x64 -> 117 pins(Default)
//x64 -> 125 pins
output [15:0] ddr2_dimm_addr, //SSTL18 //Address OK
output [2:0] ddr2_dimm_ba, //SSTL18 //Bank address OK
inout [63:0] ddr2_dimm_dq, //SSTL18 //Data x64 SODIMM OK
inout [7:0] ddr2_dimm_dqs, //SSTL18 //Strobe Pos OK
inout [7:0] ddr2_dimm_dqs_n, //SSTL18 //Strobe Neg OK
output [7:0] ddr2_dimm_dm, //SSTL18 //Byte write mask OK
output ddr2_dimm_cke, //SSTL18 //System Clock Enable OK
inout [1:0] ddr2_dimm_clk, //SSTL18 //System Clock Pos OK
inout [1:0] ddr2_dimm_clk_n, //SSTL18 //System Clock Neg OK
output ddr2_dimm_we_n, //SSTL18 //Write enable OK
output ddr2_dimm_ras_n, //SSTL18 //Row address select OK
output ddr2_dimm_cas_n, //SSTL18 //Column address select OK
output ddr2_dimm_cs_n, //SSTL18 //Chip Select OK
// output ddr2_dimm_resetn, //SSTL18 //Reset
output ddr2_dimm_odt, //SSTL18 //On-die termination enable OK
 
//////////////////////////////////////////////////////////////////
//ETHERNET-10/100/1000-RGMII-----------
output enet_gtx_clk, //2.5V //RGMII Transmit Clock
output [3:0] enet_tx_d, //2.5V //TX to PHY
input [3:0] enet_rx_d, //2.5V //RX from PHY
output enet_tx_en, //2.5V //RGMII Transmit Control
input enet_rx_clk, //2.5V //Derived Received Clock
input enet_rx_dv, //2.5V //RGMII Receive Control
output enet_resetn, //2.5V //Reset to PHY(TR=0)
output enet_mdc, //2.5V //MDIO Control(TR=0)
inout enet_mdio, //2.5V //MDIO Data(TR=0)
input enet_intn, //2.5V //MDIO Interrupt(TR=0)
///////////////////////////////////////////////////////////////////
 
//FLASH-SRAM-MAX-------------FSM-Bus---//90 pins
output [25:0] fsm_a, //2.5V //FSM Address Bus(1Gb Flash)
inout [31:0] fsm_d, //2.5V //FSM Data Bus
output flash_clk, //2.5V
output flash_cen, //2.5V
output flash_oen, //2.5V
output flash_wen, //2.5V
output flash_advn, //2.5V
input flash_rdybsyn, //2.5V
output flash_resetn, //2.5V //(TR=0)
output sram_clk, //2.5V
output sram_cen, //2.5V
inout [3:0] sram_dqp, //2.5V //Parity bits only go to SRAM
output [3:0] sram_bwn, //2.5V
output sram_gwn, //2.5V
output sram_bwen, //2.5V
output sram_oen, //2.5V
output sram_advn, //2.5V
output sram_adspn, //2.5V
output sram_adscn, //2.5V
output sram_zz, //2.5V //(TR=0)
/* output max2_clk, //1.8V
output max2_csn, //1.8V
output [3:0] max2_ben, //1.8V
output max2_oen, //1.8V
output max2_wen, //1.8V*/
 
////LCD----------------------------------//11 pins
inout [7:0] lcd_data, //2.5V
output lcd_d_cn, //2.5V
output lcd_wen, //2.5V
output lcd_csn, //2.5V
//
////User-IO------------------------------//22 pins
input [3:0] user_dipsw, //1.8V/2.5V //(TR=0)
// output [7:0] user_led, //2.5V
output [3:0] user_led, //2.5V
input [1:0] user_pb, //1.8V/2.5V //(TR=0)
// input [1:0] user_pb, //1.8V/2.5V //(TR=0)
input cpu_resetn, //2.5V(DEV_CLRn) //(TR=0)
//// //PCI-EXPRESS-EDGE---------------------
input pcie_refclk_p, //HCSL
output [7:0] pcie_tx_p, //1.4V PCML
input [7:0] pcie_rx_p, //1.4V PCML
// input pcie_smbclk, //2.5V //(TR=0)
// inout pcie_smbdat, //2.5V //(TR=0)
input pcie_perstn, //2.5V //(TR=0)
// output pcie_waken, //2.5V //(TR=0)
output pcie_led_x1, //2.5V
output pcie_led_x4, //2.5V
output pcie_led_x8, //2.5V
// output pcie_led_g2, //2.5V
input cal_blk_clk, //Virtual Pin
//HIGH-SPEED-MEZZANINE-CARD------------//198 pins(HSMB is only connected on EP2AGX260 devices)
//Port A --> single samtec conn //107 pins //------------------
// output [3:0] hsma_tx_p, //1.4V PCML
// input [3:0] hsma_rx_p, //1.4V PCML
//Enable below for CMOS HSMC
//inout [79:0] hsma_d, //2.5V
//Enable below for LVDS HSMC
output [16:0] hsma_tx_d_p, //LVDS //69 pins
input [16:0] hsma_rx_d_p, //LVDS
inout [3:0] hsma_d, //2.5V
input hsma_clk_in0, //2.5V
output hsma_clk_out0, //2.5V
input hsma_clk_in_p1, //LVDS //Requires external termination
output hsma_clk_out_p1, //LVDS
input hsma_clk_in_p2, //LVDS //Requires external termination
output hsma_clk_out_p2, //LVDS
inout hsma_sda, //2.5V //(TR=0)
output hsma_scl, //2.5V //(TR=0)
output hsma_tx_led, //2.5V
output hsma_rx_led, //2.5V
input hsma_prsntn , //2.5V //(TR=0)
// //Port B --> single samtec conn //107 pins //------------------
// //output [3:0] hsmb_tx_p, //1.4V PCML
// //input [3:0] hsmb_rx_p, //1.4V PCML
// //Enable below for CMOS HSMC
// //inout [79:0] hsmb_d, //2.5V
// //Enable below for LVDS HSMC
// output [16:0] hsmb_tx_d_p, //LVDS
// input [16:0] hsmb_rx_d_p, //LVDS
// inout [3:0] hsmb_d, //2.5V
input hsmb_clk_in0 //2.5V
// output hsmb_clk_out0, //2.5V
// output hsmb_clk_out_p1, //LVDS
// output hsmb_clk_out_p2, //LVDS
// inout hsmb_sda, //2.5V //(TR=0)
// output hsmb_scl, //2.5V //(TR=0)
// output hsmb_tx_led, //2.5V
// output hsmb_rx_led, //2.5V
// input hsmb_prsntn //2.5V //(TR=0)
);
reg L0_led;
reg [ 25: 0] alive_cnt;
reg alive_led;
wire any_rstn;
reg any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */;
reg any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */;
wire clk_out_buf;
reg comp_led;
reg [ 3: 0] lane_active_led;
wire local_rstn;
wire in_sys_rstn;
wire in_sys_source;
wire safe_mode;
wire [ 39: 0] test_in;
wire [ 8: 0] test_out_icm;
wire lmi_ack;
wire [ 11: 0] lmi_addr;
wire [ 31: 0] lmi_din;
wire [ 31: 0] lmi_dout;
wire lmi_rden;
wire lmi_wren;
wire [ 4: 0] pex_msi_num_icm;
wire [ 3: 0] tl_cfg_add;
wire [ 31: 0] tl_cfg_ctl;
wire tl_cfg_ctl_wr;
wire [ 52: 0] tl_cfg_sts;
wire tl_cfg_sts_wr;
wire pme_to_sr;
wire [ 3: 0] lane_act;
wire [ 4: 0] dl_ltssm;
wire phystatus_ext;
wire [ 1: 0] powerdown_ext;
wire rate_ext;
wire rc_pll_locked;
wire [ 8: 0] test_out_int;
wire reconfig_clk;
wire clk_pcie;
wire open_rx_st_err0;
wire rx_stream_ready0;
wire rx_stream_valid0;
wire clk_sys_out;
wire rx_mask0;
wire [ 7: 0] rx_st_bardec0;
wire [ 15: 0] rx_st_be0;
wire [127: 0] rx_st_data0;
wire rx_st_empty0;
wire rx_st_eop0;
wire rx_st_sop0;
wire [127: 0] tx_st_data0;
wire tx_st_empty0;
wire tx_st_eop0;
wire tx_st_err0;
wire tx_st_sop0;
wire tx_stream_ready0;
wire tx_stream_valid0;
wire [ 35: 0] tx_stream_cred0;
wire app_int_ack_icm;
wire app_int_sts_icm;
wire app_msi_ack;
wire [ 4: 0] app_msi_num;
wire app_msi_req;
wire [ 2: 0] app_msi_tc;
wire srstn;
wire [6:0] cpl_err_in;
wire [6:0] cpl_err_icm;
wire open_cplerr_lmi_busy;
wire [127:0] err_desc;
assign cpl_err_in = 0;
assign err_desc = 0;
assign tx_st_err0 = 0;
assign safe_mode = 0;
assign local_rstn = safe_mode | user_pb[0];
assign in_sys_rstn = local_rstn & in_sys_source;
assign any_rstn = pcie_perstn & local_rstn;
assign test_in[39 : 32] = 0;
assign test_in[31 : 9] = 0;
assign test_in[8 : 5] = safe_mode ? 4'b0101 : user_dipsw[3:0];
assign test_in[4 : 0] = 5'b01000;
in_sys_sp in_sys_sp_0 (
.probe(0),
.source(in_sys_source)
);
//reset Synchronizer
always @(posedge clk_out_buf or negedge any_rstn)
begin
if (any_rstn == 0)
begin
any_rstn_r <= 0;
any_rstn_rr <= 0;
end
else
begin
any_rstn_r <= 1;
any_rstn_rr <= any_rstn_r;
end
end
 
 
//LED logic
always @(posedge clk_out_buf or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
alive_cnt <= 0;
alive_led <= 0;
comp_led <= 0;
L0_led <= 0;
lane_active_led <= 0;
end
else
begin
alive_cnt <= alive_cnt +1;
alive_led <= alive_cnt[25];
comp_led <= ~(test_out_icm[4 : 0] == 5'b00011);
L0_led <= ~(test_out_icm[4 : 0] == 5'b01111);
lane_active_led[3 : 0] <= ~(test_out_icm[8 : 5]);
end
end
 
 
pll_125To50 pll_125To50( //for reconfig_clk
.areset (local_rstn),
.inclk0 (clkin_top_p), //input clk
.c0 (reconfig_clk) //output clk
);
top_plus a2_pex_x8_plus_0 (
.local_rstn(local_rstn),
.pcie_rstn(pcie_perstn),
.refclk(pcie_refclk_p),
.core_clk_out(clk_pcie),
.pld_clk(clk_pcie),
.rx_st_bardec0 (rx_st_bardec0),
.rx_st_be0 (rx_st_be0),
.rx_st_data0 (rx_st_data0),
.rx_st_empty0 (rx_st_empty0),
.rx_st_eop0 (rx_st_eop0),
.rx_st_err0 (open_rx_st_err0),
.rx_st_mask0 (rx_mask0),
.rx_st_ready0 (rx_stream_ready0),
.rx_st_sop0 (rx_st_sop0),
.rx_st_valid0 (rx_stream_valid0),
.tx_st_data0 (tx_st_data0),
.tx_st_empty0 (tx_st_empty0),
.tx_st_eop0 (tx_st_eop0),
.tx_st_err0 (tx_st_err0),
.tx_st_ready0 (tx_stream_ready0),
.tx_st_sop0 (tx_st_sop0),
.tx_st_valid0 (tx_stream_valid0),
.tx_cred0 (tx_stream_cred0),
.rx_in0(pcie_rx_p[0]),
.rx_in1(pcie_rx_p[1]),
.rx_in2(pcie_rx_p[2]),
.rx_in3(pcie_rx_p[3]),
.rx_in4(pcie_rx_p[4]),
.rx_in5(pcie_rx_p[5]),
.rx_in6(pcie_rx_p[6]),
.rx_in7(pcie_rx_p[7]),
.tx_out0(pcie_tx_p[0]),
.tx_out1(pcie_tx_p[1]),
.tx_out2(pcie_tx_p[2]),
.tx_out3(pcie_tx_p[3]),
.tx_out4(pcie_tx_p[4]),
.tx_out5(pcie_tx_p[5]),
.tx_out6(pcie_tx_p[6]),
.tx_out7(pcie_tx_p[7]),
.app_int_ack(app_int_ack_icm),
.app_int_sts(app_int_sts_icm),
.app_msi_ack(app_msi_ack),
.app_msi_num(app_msi_num),
.app_msi_req(app_msi_req),
.app_msi_tc(app_msi_tc),
.tl_cfg_add (tl_cfg_add),
.tl_cfg_ctl (tl_cfg_ctl),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.reconfig_clk(reconfig_clk),
// .reconfig_clk_locked(reconfig_clk_locked),
.pme_to_cr (pme_to_sr),
.pme_to_sr (pme_to_sr),
.test_in(40'b010101000),
.pipe_mode(1'b0),
.pm_auxpwr(1'b0),
.pm_data(0),
.pm_event(1'b0),
.srstn(srstn),
.cpl_err (cpl_err_icm),
.cpl_pending (1'b0),
// .fixedclk_serdes (fixedclk_serdes),
.lane_act (lane_act),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
.lmi_din (lmi_din),
.lmi_dout (lmi_dout),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.ltssm (dl_ltssm),
.pex_msi_num (pex_msi_num_icm),
.phystatus_ext (phystatus_ext),
.powerdown_ext (powerdown_ext),
.rate_ext (rate_ext),
.rc_pll_locked (rc_pll_locked),
.test_out(test_out_int),
.tl_cfg_sts (tl_cfg_sts),
.tl_cfg_sts_wr (tl_cfg_sts_wr)
// .tx_fifo_empty0 (tx_fifo_empty0)
);
/* top_plus ep_plus (
.app_int_ack (app_int_ack_icm),
.app_int_sts (app_int_sts_icm),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.clk250_out (clk250_out),
.clk500_out (clk500_out),
.core_clk_out (core_clk_out),
.cpl_err (cpl_err_icm),
.cpl_pending (cpl_pending_icm),
.lane_act (lane_act),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
.lmi_din (lmi_din),
.lmi_dout (lmi_dout),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.local_rstn (local_rstn),
.ltssm (dl_ltssm),
.pcie_rstn (pcie_perstn),
.pclk_in (pclk_in),
.pex_msi_num (pex_msi_num_icm),
.phystatus_ext (phystatus_ext),
.pipe_mode (pipe_mode),
.pld_clk (pld_clk),
.pm_auxpwr (1'b0),
.pm_data (gnd_pm_data),
.pm_event (1'b0),
.pme_to_cr (pme_to_sr),
.pme_to_sr (pme_to_sr),
.powerdown_ext (powerdown_ext),
.rate_ext (rate_ext),
.rc_pll_locked (rc_pll_locked),
.reconfig_clk (reconfig_clk),
.refclk (pcie_refclk_p),
.rx_in0 (pcie_rx_p[0]),
.rx_in1 (pcie_rx_p[1]),
.rx_in2 (pcie_rx_p[2]),
.rx_in3 (pcie_rx_p[3]),
.rx_in4 (pcie_rx_p[4]),
.rx_in5 (pcie_rx_p[5]),
.rx_in6 (pcie_rx_p[6]),
.rx_in7 (pcie_rx_p[7]),
.rx_st_bardec0 (rx_st_bardec0),
.rx_st_be0 (rx_st_be0),
.rx_st_data0 (rx_st_data0),
.rx_st_empty0 (rx_st_empty0),
.rx_st_eop0 (rx_st_eop0),
.rx_st_err0 (open_rx_st_err0),
.rx_st_mask0 (rx_mask0),
.rx_st_ready0 (rx_stream_ready0),
.rx_st_sop0 (rx_st_sop0),
.rx_st_valid0 (rx_stream_valid0),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdata4_ext (rxdata4_ext),
.rxdata5_ext (rxdata5_ext),
.rxdata6_ext (rxdata6_ext),
.rxdata7_ext (rxdata7_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxdatak4_ext (rxdatak4_ext),
.rxdatak5_ext (rxdatak5_ext),
.rxdatak6_ext (rxdatak6_ext),
.rxdatak7_ext (rxdatak7_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxelecidle4_ext (rxelecidle4_ext),
.rxelecidle5_ext (rxelecidle5_ext),
.rxelecidle6_ext (rxelecidle6_ext),
.rxelecidle7_ext (rxelecidle7_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxpolarity4_ext (rxpolarity4_ext),
.rxpolarity5_ext (rxpolarity5_ext),
.rxpolarity6_ext (rxpolarity6_ext),
.rxpolarity7_ext (rxpolarity7_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxstatus4_ext (rxstatus4_ext),
.rxstatus5_ext (rxstatus5_ext),
.rxstatus6_ext (rxstatus6_ext),
.rxstatus7_ext (rxstatus7_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.rxvalid4_ext (rxvalid4_ext),
.rxvalid5_ext (rxvalid5_ext),
.rxvalid6_ext (rxvalid6_ext),
.rxvalid7_ext (rxvalid7_ext),
.srstn (srstn),
.test_in (test_in),
.test_out (test_out_int),
.tl_cfg_add (tl_cfg_add),
.tl_cfg_ctl (tl_cfg_ctl),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts),
.tl_cfg_sts_wr (tl_cfg_sts_wr),
.tx_cred0 (tx_stream_cred0),
.tx_fifo_empty0 (tx_fifo_empty0),
.tx_out0 (pcie_tx_p[0]),
.tx_out1 (pcie_tx_p[1]),
.tx_out2 (pcie_tx_p[2]),
.tx_out3 (pcie_tx_p[3]),
.tx_out4 (pcie_tx_p[4]),
.tx_out5 (pcie_tx_p[5]),
.tx_out6 (pcie_tx_p[6]),
.tx_out7 (pcie_tx_p[7]),
.tx_st_data0 (tx_st_data0),
.tx_st_empty0 (tx_st_empty0),
.tx_st_eop0 (tx_st_eop0),
.tx_st_err0 (tx_st_err0),
.tx_st_ready0 (tx_stream_ready0),
.tx_st_sop0 (tx_st_sop0),
.tx_st_valid0 (tx_stream_valid0),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txcompl4_ext (txcompl4_ext),
.txcompl5_ext (txcompl5_ext),
.txcompl6_ext (txcompl6_ext),
.txcompl7_ext (txcompl7_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdata4_ext (txdata4_ext),
.txdata5_ext (txdata5_ext),
.txdata6_ext (txdata6_ext),
.txdata7_ext (txdata7_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdatak4_ext (txdatak4_ext),
.txdatak5_ext (txdatak5_ext),
.txdatak6_ext (txdatak6_ext),
.txdatak7_ext (txdatak7_ext),
.txdetectrx_ext (txdetectrx_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext),
.txelecidle4_ext (txelecidle4_ext),
.txelecidle5_ext (txelecidle5_ext),
.txelecidle6_ext (txelecidle6_ext),
.txelecidle7_ext (txelecidle7_ext) );*/
 
 
/* altpcierd_tl_cfg_sample cfgbus (
.cfg_busdev (cfg_busdev_icm),
.cfg_devcsr (cfg_devcsr_icm),
.cfg_io_bas (cfg_io_bas),
.cfg_linkcsr (cfg_linkcsr_icm),
.cfg_msicsr (cfg_msicsr),
.cfg_np_bas (cfg_np_bas),
.cfg_pr_bas (cfg_pr_bas),
.cfg_prmcsr (cfg_prmcsr_icm),
.cfg_tcvcmap (open_cfg_tcvcmap),
.pld_clk (pld_clk),
.rstn (srstn),
.tl_cfg_add (tl_cfg_add),
.tl_cfg_ctl (tl_cfg_ctl),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts),
.tl_cfg_sts_wr (tl_cfg_sts_wr) );
 
defparam cfgbus.HIP_SV = 0;*/
 
altpcierd_cplerr_lmi lmi_blk (
.clk_in(clk_pcie),
.cpl_err_in (cpl_err_in),
.cpl_err_out (cpl_err_icm),
.cplerr_lmi_busy (open_cplerr_lmi_busy),
.err_desc (err_desc),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
.lmi_din (lmi_din),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.rstn (srstn) );
 
pcie_to_hibi_test_app
#( .HIBI_DATA_WIDTH(32),
.HIBI_ADDR_SPACE_WIDTH(11),
.PCIE_DATA_WIDTH(128),
.PCIE_ADDR_WIDTH(64),
.PCIE_LOWER_ADDR_WIDTH(7),
.PCIE_RW_LENGTH_WIDTH(13),
.PCIE_ID_WIDTH(16),
.PCIE_FUNC_WIDTH(3),
.PCIE_TAG_WIDTH(6),
// .PKT_TAG_WIDTH(9),
.PCIE_CRED_WIDTH(36),
.PCIE_CPL_LENGTH_MIN(128),
.P2H_ADDR_SPACES(4),
.P2H_HDMA_ADDR_SPACES(1),
.HIBI_IF_ADDR(32'h10000000),
.P2H_ADDR_0_WIDTH(16),
.P2H_ADDR_0_PCIE_BASE(64'h0),
.P2H_ADDR_0_HIBI_BASE(32'h00000000),
.P2H_ADDR_1_WIDTH(8),
.P2H_ADDR_1_PCIE_BASE(64'h0000000000010000),
.P2H_ADDR_1_HIBI_BASE(32'h00020000),
.P2H_ADDR_2_WIDTH(8),
.P2H_ADDR_2_PCIE_BASE(64'h0000000000010100),
.P2H_ADDR_2_HIBI_BASE(32'h00020100),
.P2H_ADDR_3_WIDTH(8),
.P2H_ADDR_3_PCIE_BASE(64'h0000000000010200),
.P2H_ADDR_3_HIBI_BASE(32'h00020200),
.HDMA_REQS_MIN(4),
.H2P_WR_CHANS(16),
.H2P_RD_CHANS(16),
.P2H_WR_CHANS(16),
.P2H_RD_CHANS(16) )
 
test_app (
.clk_pcie(clk_pcie),
.clk_ref(clkin_bot_p),
.rst_n(in_sys_rstn),
.rst_n_pcie(local_rstn),
.clk_sys_out(clk_sys_out),
.rx_st_data_i(rx_st_data0),
.rx_st_valid_i(rx_stream_valid0),
.rx_st_sop_i(rx_st_sop0),
.rx_st_eop_i(rx_st_eop0),
.rx_st_empty_i(rx_st_empty0),
.rx_st_bardec_i(rx_st_bardec0),
.rx_st_ready_o(rx_stream_ready0),
.rx_st_mask_o(rx_mask0),
.tx_st_sop_o(tx_st_sop0),
.tx_st_eop_o(tx_st_eop0),
.tx_st_empty_o(tx_st_empty0),
.tx_st_valid_o(tx_stream_valid0),
.tx_st_data_o(tx_st_data0),
.tx_st_ready_i(tx_stream_ready0),
.txcred_i(tx_stream_cred0),
.app_msi_req_out(app_msi_req),
.app_msi_ack_in(app_msi_ack),
.app_msi_tc_out(app_msi_tc),
.app_msi_num_out(app_msi_num),
.pex_msi_num_out(pex_msi_num_icm),
.app_int_sts_out(app_int_sts_icm),
.app_int_ack_in(app_int_ack_icm),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_ctl_wr(tl_cfg_ctl_wr),
.ddr2_clk(ddr2_dimm_clk),
.ddr2_clk_n(ddr2_dimm_clk_n),
.ddr2_odt(ddr2_dimm_odt),
.ddr2_cs_n(ddr2_dimm_cs_n),
.ddr2_cke(ddr2_dimm_cke),
.ddr2_addr(ddr2_dimm_addr),
.ddr2_ba(ddr2_dimm_ba),
.ddr2_ras_n(ddr2_dimm_ras_n),
.ddr2_cas_n(ddr2_dimm_cas_n),
.ddr2_we_n(ddr2_dimm_we_n),
.ddr2_dm(ddr2_dimm_dm),
.ddr2_dq(ddr2_dimm_dq),
.ddr2_dqs(ddr2_dimm_dqs),
.ddr2_dqs_n(ddr2_dimm_dqs_n),
.dummy_debug_out(user_led[0]),
.debug_out(debug) );
 
wire clk;
wire [31:0] sys_count;
 
sys_cnt sys_cnt_0 (
.rst_n(user_pb[0]),
.clk(clk_sys_out),
.cont(1),
.clear(debug),
.sys_cnt_out(sys_count) );
 
/*a2_pex_x8_app_if a2_pex_x8_app (
.rst_n(user_pb[0]),
.rst_n_pcie(pcie_perstn),
.rst_n_debug(user_pb[1]),
.clk_free_100(clkin_bot_p),
.clk_pcie_ref(pcie_refclk_p),
.clk_ddr2_ref(clkin_top_p),
.clk_sys_out(clk),
.pcie_rx_in(pcie_rx_p),
.pcie_tx_out(pcie_tx_p),
.ddr2_clk(ddr2_dimm_clk),
.ddr2_clk_n(ddr2_dimm_clk_n),
.ddr2_odt(ddr2_dimm_odt),
.ddr2_cs_n(ddr2_dimm_cs_n),
.ddr2_cke(ddr2_dimm_cke),
.ddr2_addr(ddr2_dimm_addr[13:0]),
.ddr2_ba(ddr2_dimm_ba),
.ddr2_ras_n(ddr2_dimm_ras_n),
.ddr2_cas_n(ddr2_dimm_cas_n),
.ddr2_we_n(ddr2_dimm_we_n),
.ddr2_dm(ddr2_dimm_dm),
.ddr2_dq(ddr2_dimm_dq),
.ddr2_dqs(ddr2_dimm_dqs),
.ddr2_dqs_n(ddr2_dimm_dqs_n) );*/
 
endmodule
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/arria_II_gx_test.qip
0,0 → 1,7
set_global_assignment -name VERILOG_FILE D:/svn/koski/trunk/lib/hw_lib/ips/adapters/avalon_to_hibi/verilog/avalon_to_hibi.v
set_global_assignment -name VERILOG_FILE a2h2.v
set_global_assignment -name TCL_FILE D:/svn/koski/trunk/lib/hw_lib/ips/adapters/avalon_to_hibi/verilog/avalon_to_hibi_hw.tcl
set_global_assignment -name VERILOG_FILE a2h.v
set_global_assignment -name QIP_FILE pcie.qip
set_global_assignment -name SOPC_BUILDER_SIGNATURE_ID 001E4FF5C40E000001288812FE1B
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/in_sys_sp.cmp
0,0 → 1,22
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
component in_sys_sp
PORT
(
probe : IN STD_LOGIC ;
source : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
end component;
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/in_sys_sp.vhd
0,0 → 1,118
-- megafunction wizard: %In-System Sources and Probes%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsource_probe
 
-- ============================================================
-- File Name: in_sys_sp.vhd
-- Megafunction Name(s):
-- altsource_probe
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.0 Build 157 04/27/2011 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY in_sys_sp IS
PORT
(
probe : IN STD_LOGIC ;
source : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END in_sys_sp;
 
 
ARCHITECTURE SYN OF in_sys_sp IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
COMPONENT altsource_probe
GENERIC (
enable_metastability : STRING;
instance_id : STRING;
probe_width : NATURAL;
sld_auto_instance_index : STRING;
sld_instance_index : NATURAL;
source_initial_value : STRING;
source_width : NATURAL;
lpm_type : STRING
);
PORT (
probe : IN STD_LOGIC ;
source : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
source <= sub_wire0(0 DOWNTO 0);
 
altsource_probe_component : altsource_probe
GENERIC MAP (
enable_metastability => "NO",
instance_id => "NONE",
probe_width => 0,
sld_auto_instance_index => "YES",
sld_instance_index => 0,
source_initial_value => " 1",
source_width => 1,
lpm_type => "altsource_probe"
)
PORT MAP (
probe => probe,
source => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "NO"
-- Retrieval info: CONSTANT: INSTANCE_ID STRING "NONE"
-- Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0"
-- Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
-- Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
-- Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 1"
-- Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe"
-- Retrieval info: USED_PORT: source 0 0 1 0 OUTPUT NODEFVAL "source[0..0]"
-- Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0
-- Retrieval info: CONNECT: source 0 0 1 0 @source 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL in_sys_sp.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL in_sys_sp.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL in_sys_sp.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL in_sys_sp.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL in_sys_sp_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/ddr2_sodimm.pin
0,0 → 1,1232
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
 
 
 
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the requirements of the configuration device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (0.9V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 3C: 2.5V
-- Bank 3A: 1.8V
-- Bank 4A: 1.8V
-- Bank 4B: 1.8V
-- Bank 5A: 2.5V
-- Bank 6A: 2.5V
-- Bank 7B: 2.5V
-- Bank 7A: 1.8V
-- Bank 8A: 2.5V
-- Bank 8C: 2.5V
-- RREF : External reference resistor for the quad, MUST be connected to
-- GND via a 2k Ohm resistor.
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND*
-- either individually through a 10k Ohm resistor to GND or tie all pins
-- together and connect through a single 10k Ohm resistor to GND.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
-- GXB_GND* : Unused GXB Receiver or dedicated reference clock pin. This pin
-- must be connected to GXB_GND through a 10k Ohm resistor.
-- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
-- must not be connected.
---------------------------------------------------------------------------------
 
 
 
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
 
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
CHIP "ddr2_sodimm" ASSIGNED TO AN: EP2AGX125EF35C4ES
 
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7A :
fsm_d[19] : A17 : bidir : 2.5 V : : 8A : Y
fsm_d[24] : A18 : bidir : 2.5 V : : 8A : Y
fsm_d[0] : A19 : bidir : 2.5 V : : 8A : Y
sram_adspn : A20 : output : 2.5 V : : 8A : Y
fsm_d[29] : A21 : bidir : 2.5 V : : 8A : Y
fsm_d[31] : A22 : bidir : 2.5 V : : 8A : Y
fsm_a[8] : A23 : output : 2.5 V : : 8A : Y
sram_dqp[0] : A24 : bidir : 2.5 V : : 8A : Y
fsm_d[11] : A25 : bidir : 2.5 V : : 8A : Y
fsm_d[13] : A26 : bidir : 2.5 V : : 8A : Y
fsm_d[15] : A27 : bidir : 2.5 V : : 8A : Y
GND : A28 : gnd : : : :
RREF : A29 : : : : :
GND : A30 : gnd : : : :
GND : A31 : gnd : : : :
GND : A32 : gnd : : : :
GND : A33 : gnd : : : :
hsma_rx_d_p[6](n) : AA1 : input : LVDS : : 5A : Y
GND : AA2 : gnd : : : :
VCCIO5A : AA3 : power : : 2.5V : 5A :
hsma_tx_d_p[10](n) : AA4 : output : LVDS : : 5A : Y
GND : AA5 : gnd : : : :
VCCIO5A : AA6 : power : : 2.5V : 5A :
hsma_tx_d_p[8] : AA7 : output : LVDS : : 5A : Y
GND : AA8 : gnd : : : :
hsma_tx_d_p[0](n) : AA9 : output : LVDS : : 5A : Y
hsma_tx_d_p[0] : AA10 : output : LVDS : : 5A : Y
GND : AA11 : gnd : : : :
VCCPD5A : AA12 : power : : 2.5V : 5A :
VCC : AA13 : power : : 0.9V : :
GND : AA14 : gnd : : : :
VCC : AA15 : power : : 0.9V : :
GND : AA16 : gnd : : : :
VCC : AA17 : power : : 0.9V : :
GND : AA18 : gnd : : : :
VCC : AA19 : power : : 0.9V : :
GND : AA20 : gnd : : : :
VCC : AA21 : power : : 0.9V : :
GND : AA22 : gnd : : : :
VCC : AA23 : power : : 0.9V : :
VCCA : AA24 : power : : 2.5V : :
GND : AA25 : gnd : : : :
GND : AA26 : gnd : : : :
VCCH_GXB : AA27 : power : : 1.5V : :
GND : AA28 : gnd : : : :
GXB_GND* : AA29 : : : : QL1 :
GXB_GND* : AA30 : : : : QL1 :
GND : AA31 : gnd : : : :
GND : AA32 : gnd : : : :
pcie_rx_p[6] : AA33 : input : 1.5-V PCML : : QL1 : Y
pcie_rx_p[6](n) : AA34 : input : 1.5-V PCML : : QL1 : N
hsma_rx_d_p[5](n) : AB1 : input : LVDS : : 5A : Y
hsma_rx_d_p[5] : AB2 : input : LVDS : : 5A : Y
hsma_rx_d_p[12](n) : AB3 : input : LVDS : : 5A : Y
hsma_rx_d_p[12] : AB4 : input : LVDS : : 5A : Y
hsma_rx_d_p[13](n) : AB5 : input : LVDS : : 5A : Y
hsma_rx_d_p[13] : AB6 : input : LVDS : : 5A : Y
hsma_rx_d_p[15](n) : AB7 : input : LVDS : : 5A : Y
hsma_rx_d_p[15] : AB8 : input : LVDS : : 5A : Y
hsma_tx_d_p[3](n) : AB9 : output : LVDS : : 5A : Y
hsma_tx_d_p[3] : AB10 : output : LVDS : : 5A : Y
VREFB5AN0 : AB11 : power : : : 5A :
VCC : AB12 : power : : 0.9V : :
GND : AB13 : gnd : : : :
VCC : AB14 : power : : 0.9V : :
GND : AB15 : gnd : : : :
VCC : AB16 : power : : 0.9V : :
GND : AB17 : gnd : : : :
VCC : AB18 : power : : 0.9V : :
GND : AB19 : gnd : : : :
VCC : AB20 : power : : 0.9V : :
GND : AB21 : gnd : : : :
VCC : AB22 : power : : 0.9V : :
GND : AB23 : gnd : : : :
VCC : AB24 : power : : 0.9V : :
nCE : AB25 : : : : 3C :
MSEL3 : AB26 : : : : 3C :
GND : AB27 : gnd : : : :
VCCH_GXB : AB28 : power : : 1.5V : :
GND : AB29 : gnd : : : :
GND : AB30 : gnd : : : :
pcie_tx_p[5] : AB31 : output : 1.5-V PCML : : QL1 : Y
pcie_tx_p[5](n) : AB32 : output : 1.5-V PCML : : QL1 : N
GND : AB33 : gnd : : : :
GND : AB34 : gnd : : : :
hsma_rx_d_p[4] : AC1 : input : LVDS : : 5A : Y
hsma_tx_d_p[11](n) : AC2 : output : LVDS : : 5A : Y
hsma_tx_d_p[11] : AC3 : output : LVDS : : 5A : Y
hsma_rx_d_p[0](n) : AC4 : input : LVDS : : 5A : Y
hsma_rx_d_p[0] : AC5 : input : LVDS : : 5A : Y
hsma_rx_d_p[16](n) : AC6 : input : LVDS : : 5A : Y
hsma_rx_d_p[16] : AC7 : input : LVDS : : 5A : Y
NC : AC8 : : : : :
NC : AC9 : : : : :
NC : AC10 : : : : :
NC : AC11 : : : : :
NC : AC12 : : : : :
VCCPD4B : AC13 : power : : 2.5V : 4B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A :
ddr2_dimm_dm[6] : AC15 : output : SSTL-18 Class I : : 4A : Y
VCCPD4A : AC16 : power : : 2.5V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A :
ddr2_dimm_dq[36] : AC18 : bidir : SSTL-18 Class I : : 4A : Y
VCCPD3A : AC19 : power : : 2.5V : 3A :
VCCPD3A : AC20 : power : : 2.5V : 3A :
NC : AC21 : : : : :
NC : AC22 : : : : :
VCC : AC23 : power : : 0.9V : :
VCCPD3C : AC24 : power : : 2.5V : 3C :
MSEL1 : AC25 : : : : 3C :
nCONFIG : AC26 : : : : 3C :
MSEL0 : AC27 : : : : 3C :
nIO_PULLUP : AC28 : : : : 3C :
GXB_GND* : AC29 : : : : QL0 :
GXB_GND* : AC30 : : : : QL0 :
GND : AC31 : gnd : : : :
GND : AC32 : gnd : : : :
pcie_rx_p[5] : AC33 : input : 1.5-V PCML : : QL1 : Y
pcie_rx_p[5](n) : AC34 : input : 1.5-V PCML : : QL1 : N
hsma_rx_d_p[4](n) : AD1 : input : LVDS : : 5A : Y
GND : AD2 : gnd : : : :
VCCIO5A : AD3 : power : : 2.5V : 5A :
hsma_tx_d_p[6] : AD4 : output : LVDS : : 5A : Y
GND : AD5 : gnd : : : :
hsma_clk_out_p1(n) : AD6 : output : LVDS : : 5A : Y
hsma_clk_out_p1 : AD7 : output : LVDS : : 5A : Y
GND : AD8 : gnd : : : :
NC : AD9 : : : : :
NC : AD10 : : : : :
NC : AD11 : : : : :
NC : AD12 : : : : :
VREFB4BN0 : AD13 : power : : 0.9V : 4B :
GND : AD14 : gnd : : : :
VREFB4AN0 : AD15 : power : : 0.9V : 4A :
VCCPD4A : AD16 : power : : 2.5V : 4A :
GND : AD17 : gnd : : : :
VCCCB : AD18 : power : : 1.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 3A :
GND : AD20 : gnd : : : :
NC : AD21 : : : : :
NC : AD22 : : : : :
GND : AD23 : gnd : : : :
MSEL2 : AD24 : : : : 3C :
VCCIO3C : AD25 : power : : 2.5V : 3C :
GND : AD26 : gnd : : : :
GND : AD27 : gnd : : : :
nSTATUS : AD28 : : : : 3C :
GND : AD29 : gnd : : : :
GND : AD30 : gnd : : : :
pcie_tx_p[4] : AD31 : output : 1.5-V PCML : : QL1 : Y
pcie_tx_p[4](n) : AD32 : output : 1.5-V PCML : : QL1 : N
GND : AD33 : gnd : : : :
GND : AD34 : gnd : : : :
hsma_rx_d_p[3](n) : AE1 : input : LVDS : : 5A : Y
hsma_rx_d_p[3] : AE2 : input : LVDS : : 5A : Y
hsma_tx_d_p[6](n) : AE3 : output : LVDS : : 5A : Y
hsma_rx_d_p[1] : AE4 : input : LVDS : : 5A : Y
NC : AE5 : : : : :
NC : AE6 : : : : :
NC : AE7 : : : : :
NC : AE8 : : : : :
VCCD_PLL_3 : AE9 : power : : 0.9V : :
GND : AE10 : gnd : : : :
NC : AE11 : : : : :
ddr2_dimm_addr[2] : AE12 : output : SSTL-18 Class I : : 4B : Y
ddr2_dimm_addr[9] : AE13 : output : SSTL-18 Class I : : 4B : Y
ddr2_dimm_ba[2] : AE14 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dm[7] : AE15 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[54] : AE16 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[37] : AE17 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[26] : AE18 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dm[1] : AE19 : output : SSTL-18 Class I : : 3A : Y
VREFB3AN0 : AE20 : power : : 0.9V : 3A :
NC : AE21 : : : : :
NC : AE22 : : : : :
NC : AE23 : : : : :
NC : AE24 : : : : :
CONF_DONE : AE25 : : : : 3C :
NC : AE26 : : : : :
NC : AE27 : : : : :
NC : AE28 : : : : :
pcie_refclk_p : AE29 : input : HCSL : : QL0 : Y
pcie_refclk_p(n) : AE30 : input : HCSL : : QL0 : N
GND : AE31 : gnd : : : :
GND : AE32 : gnd : : : :
pcie_rx_p[4] : AE33 : input : 1.5-V PCML : : QL1 : Y
pcie_rx_p[4](n) : AE34 : input : 1.5-V PCML : : QL1 : N
hsma_rx_d_p[2] : AF1 : input : LVDS : : 5A : Y
hsma_tx_d_p[5](n) : AF2 : output : LVDS : : 5A : Y
hsma_tx_d_p[5] : AF3 : output : LVDS : : 5A : Y
hsma_rx_d_p[1](n) : AF4 : input : LVDS : : 5A : Y
NC : AF5 : : : : :
NC : AF6 : : : : :
NC : AF7 : : : : :
NC : AF8 : : : : :
GND : AF9 : gnd : : : :
VCCA_PLL_3 : AF10 : power : : 2.5V : :
NC : AF11 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4B :
ddr2_dimm_addr[12] : AF13 : output : SSTL-18 Class I : : 4B : Y
ddr2_dimm_addr[4] : AF14 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[57] : AF15 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[52] : AF16 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[35] : AF17 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[31] : AF18 : bidir : SSTL-18 Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 3A :
NC : AF21 : : : : :
NC : AF22 : : : : :
NC : AF23 : : : : :
NC : AF24 : : : : :
NC : AF25 : : : : :
VCCD_PLL_4 : AF26 : power : : 0.9V : :
NC : AF27 : : : : :
NC : AF28 : : : : :
GND : AF29 : gnd : : : :
GND : AF30 : gnd : : : :
pcie_tx_p[3] : AF31 : output : 1.5-V PCML : : QL0 : Y
pcie_tx_p[3](n) : AF32 : output : 1.5-V PCML : : QL0 : N
GND : AF33 : gnd : : : :
GND : AF34 : gnd : : : :
hsma_rx_d_p[2](n) : AG1 : input : LVDS : : 5A : Y
GND : AG2 : gnd : : : :
VCCIO5A : AG3 : power : : 2.5V : 5A :
NC : AG4 : : : : :
GND : AG5 : gnd : : : :
NC : AG6 : : : : :
NC : AG7 : : : : :
GND : AG8 : gnd : : : :
NC : AG9 : : : : :
NC : AG10 : : : : :
GND : AG11 : gnd : : : :
ddr2_dimm_addr[5] : AG12 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_addr[8] : AG13 : output : SSTL-18 Class I : : 4A : Y
GND : AG14 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 4A :
ddr2_dimm_dm[5] : AG16 : output : SSTL-18 Class I : : 4A : Y
GND : AG17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 3A :
ddr2_dimm_dm[2] : AG19 : output : SSTL-18 Class I : : 3A : Y
GND : AG20 : gnd : : : :
ddr2_dimm_dq[0] : AG21 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[14] : AG22 : bidir : SSTL-18 Class I : : 3A : Y
GND : AG23 : gnd : : : :
NC : AG24 : : : : :
VCCA_PLL_4 : AG25 : power : : 2.5V : :
GND : AG26 : gnd : : : :
NC : AG27 : : : : :
NC : AG28 : : : : :
GND : AG29 : gnd : : : :
NC : AG30 : : : : :
GND : AG31 : gnd : : : :
GND : AG32 : gnd : : : :
pcie_rx_p[3] : AG33 : input : 1.5-V PCML : : QL0 : Y
pcie_rx_p[3](n) : AG34 : input : 1.5-V PCML : : QL0 : N
hsma_tx_d_p[2](n) : AH1 : output : LVDS : : 5A : Y
hsma_tx_d_p[2] : AH2 : output : LVDS : : 5A : Y
NC : AH3 : : : : :
NC : AH4 : : : : :
NC : AH5 : : : : :
NC : AH6 : : : : :
NC : AH7 : : : : :
NC : AH8 : : : : :
NC : AH9 : : : : :
NC : AH10 : : : : :
VCCIO4B : AH11 : power : : 1.8V : 4B :
ddr2_dimm_ras_n : AH12 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_addr[3] : AH13 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_addr[0] : AH14 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[41] : AH15 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[40] : AH16 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[34] : AH17 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dm[4] : AH18 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[28] : AH19 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[23] : AH20 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[15] : AH21 : bidir : SSTL-18 Class I : : 3A : Y
VCCIO3A : AH22 : power : : 1.8V : 3A :
ddr2_dimm_addr[11] : AH23 : output : SSTL-18 Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 3A :
NC : AH26 : : : : :
NC : AH27 : : : : :
NC : AH28 : : : : :
NC : AH29 : : : : :
NC : AH30 : : : : :
pcie_tx_p[2] : AH31 : output : 1.5-V PCML : : QL0 : Y
pcie_tx_p[2](n) : AH32 : output : 1.5-V PCML : : QL0 : N
GND : AH33 : gnd : : : :
GND : AH34 : gnd : : : :
NC : AJ1 : : : : :
NC : AJ2 : : : : :
NC : AJ3 : : : : :
NC : AJ4 : : : : :
NC : AJ5 : : : : :
NC : AJ6 : : : : :
ddr2_dimm_clk[0] : AJ7 : bidir : Differential 1.8-V SSTL Class I : : 4B : Y
NC : AJ8 : : : : :
NC : AJ9 : : : : :
ddr2_dimm_odt : AJ10 : output : SSTL-18 Class I : : 4B : Y
ddr2_dimm_ba[0] : AJ11 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[59] : AJ12 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_ba[1] : AJ13 : output : SSTL-18 Class I : : 4A : Y
VCCIO4A : AJ14 : power : : 1.8V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AJ15 : : : : 4A :
ddr2_dimm_dq[60] : AJ16 : bidir : SSTL-18 Class I : : 4A : Y
VCCIO4A : AJ17 : power : : 1.8V : 4A :
ddr2_dimm_addr[6] : AJ18 : output : SSTL-18 Class I : : 3A : Y
clkin_bot_p : AJ19 : input : LVDS : : 3A : Y
VCCIO3A : AJ20 : power : : 1.8V : 3A :
ddr2_dimm_dq[22] : AJ21 : bidir : SSTL-18 Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22 : : : : 3A :
ddr2_dimm_dq[12] : AJ23 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[6] : AJ24 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[7] : AJ25 : bidir : SSTL-18 Class I : : 3A : Y
NC : AJ26 : : : : :
NC : AJ27 : : : : :
NC : AJ28 : : : : :
NC : AJ29 : : : : :
NC : AJ30 : : : : :
GND : AJ31 : gnd : : : :
GND : AJ32 : gnd : : : :
pcie_rx_p[2] : AJ33 : input : 1.5-V PCML : : QL0 : Y
pcie_rx_p[2](n) : AJ34 : input : 1.5-V PCML : : QL0 : N
NC : AK1 : : : : :
GND : AK2 : gnd : : : :
NC : AK3 : : : : :
NC : AK4 : : : : :
GND : AK5 : gnd : : : :
ddr2_dimm_clk[1] : AK6 : bidir : Differential 1.8-V SSTL Class I : : 4B : Y
ddr2_dimm_clk_n[0] : AK7 : bidir : Differential 1.8-V SSTL Class I : : 4B : Y
GND : AK8 : gnd : : : :
user_pb[0] : AK9 : input : 1.8 V : : 4B : Y
ddr2_dimm_addr[10] : AK10 : output : SSTL-18 Class I : : 4B : Y
GND : AK11 : gnd : : : :
ddr2_dimm_addr[1] : AK12 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dqs[6] : AK13 : bidir : Differential 1.8-V SSTL Class I : : 4A : Y
GND : AK14 : gnd : : : :
ddr2_dimm_dqs[5] : AK15 : bidir : Differential 1.8-V SSTL Class I : : 4A : Y
ddr2_dimm_dq[45] : AK16 : bidir : SSTL-18 Class I : : 4A : Y
GND : AK17 : gnd : : : :
ddr2_dimm_dq[30] : AK18 : bidir : SSTL-18 Class I : : 3A : Y
clkin_bot_p(n) : AK19 : input : LVDS : : 3A : N
GND : AK20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AK21 : : : : 3A :
ddr2_dimm_dm[0] : AK22 : output : SSTL-18 Class I : : 3A : Y
GND : AK23 : gnd : : : :
VCCIO3A : AK24 : power : : 1.8V : 3A :
ddr2_dimm_dq[17] : AK25 : bidir : SSTL-18 Class I : : 3A : Y
GND : AK26 : gnd : : : :
NC : AK27 : : : : :
NC : AK28 : : : : :
GND : AK29 : gnd : : : :
NC : AK30 : : : : :
pcie_tx_p[1] : AK31 : output : 1.5-V PCML : : QL0 : Y
pcie_tx_p[1](n) : AK32 : output : 1.5-V PCML : : QL0 : N
GND : AK33 : gnd : : : :
GND : AK34 : gnd : : : :
NC : AL1 : : : : :
NC : AL2 : : : : :
NC : AL3 : : : : :
NC : AL4 : : : : :
NC : AL5 : : : : :
ddr2_dimm_clk_n[1] : AL6 : bidir : Differential 1.8-V SSTL Class I : : 4B : Y
user_pb[1] : AL7 : input : 1.8 V : : 4B : Y
ddr2_dimm_cas_n : AL8 : output : SSTL-18 Class I : : 4B : Y
ddr2_dimm_addr[14] : AL9 : output : SSTL-18 Class I : : 4B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : AL10 : : : : 4A :
ddr2_dimm_dq[55] : AL11 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dqs_n[6] : AL12 : bidir : Differential 1.8-V SSTL Class I : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AL13 : : : : 4A :
ddr2_dimm_dq[53] : AL14 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dqs_n[5] : AL15 : bidir : Differential 1.8-V SSTL Class I : : 4A : Y
ddr2_dimm_dq[44] : AL16 : bidir : SSTL-18 Class I : : 4A : Y
VCCIO4A : AL17 : power : : 1.8V : 4A :
ddr2_dimm_dqs[3] : AL18 : bidir : Differential 1.8-V SSTL Class I : : 3A : Y
ddr2_dimm_addr[7] : AL19 : output : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[21] : AL20 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[20] : AL21 : bidir : SSTL-18 Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AL22 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AL23 : : : : 3A :
ddr2_dimm_dq[13] : AL24 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[16] : AL25 : bidir : SSTL-18 Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AL26 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AL27 : : : : 3A :
NC : AL28 : : : : :
ddr2_dimm_dq[1] : AL29 : bidir : SSTL-18 Class I : : 3A : Y
NC : AL30 : : : : :
GND : AL31 : gnd : : : :
GND : AL32 : gnd : : : :
pcie_rx_p[1] : AL33 : input : 1.5-V PCML : : QL0 : Y
pcie_rx_p[1](n) : AL34 : input : 1.5-V PCML : : QL0 : N
NC : AM1 : : : : :
NC : AM2 : : : : :
NC : AM3 : : : : :
NC : AM4 : : : : :
ddr2_dimm_addr[13] : AM5 : output : SSTL-18 Class I : : 4B : Y
ddr2_dimm_we_n : AM6 : output : SSTL-18 Class I : : 4B : Y
ddr2_dimm_dqs[7] : AM7 : bidir : Differential 1.8-V SSTL Class I : : 4A : Y
ddr2_dimm_dqs_n[7] : AM8 : bidir : Differential 1.8-V SSTL Class I : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AM9 : : : : 4A :
ddr2_dimm_dq[56] : AM10 : bidir : SSTL-18 Class I : : 4A : Y
VCCIO4A : AM11 : power : : 1.8V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AM12 : : : : 4A :
ddr2_dimm_cs_n : AM13 : output : SSTL-18 Class I : : 4A : Y
VCCIO4A : AM14 : power : : 1.8V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AM15 : : : : 4A :
ddr2_dimm_dqs[4] : AM16 : bidir : Differential 1.8-V SSTL Class I : : 4A : Y
ddr2_dimm_dqs_n[4] : AM17 : bidir : Differential 1.8-V SSTL Class I : : 4A : Y
ddr2_dimm_dqs_n[3] : AM18 : bidir : Differential 1.8-V SSTL Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AM19 : : : : 3A :
VCCIO3A : AM20 : power : : 1.8V : 3A :
ddr2_dimm_dq[25] : AM21 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[19] : AM22 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[10] : AM23 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[9] : AM24 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dqs[0] : AM25 : bidir : Differential 1.8-V SSTL Class I : : 3A : Y
ddr2_dimm_dqs_n[0] : AM26 : bidir : Differential 1.8-V SSTL Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AM27 : : : : 3A :
ddr2_dimm_dq[3] : AM28 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dq[2] : AM29 : bidir : SSTL-18 Class I : : 3A : Y
NC : AM30 : : : : :
pcie_tx_p[0] : AM31 : output : 1.5-V PCML : : QL0 : Y
pcie_tx_p[0](n) : AM32 : output : 1.5-V PCML : : QL0 : N
GND : AM33 : gnd : : : :
GND : AM34 : gnd : : : :
NC : AN1 : : : : :
GND : AN2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AN3 : : : : 4A :
ddr2_dimm_dq[63] : AN4 : bidir : SSTL-18 Class I : : 4A : Y
GND : AN5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AN6 : : : : 4A :
ddr2_dimm_dq[48] : AN7 : bidir : SSTL-18 Class I : : 4A : Y
GND : AN8 : gnd : : : :
ddr2_dimm_dq[61] : AN9 : bidir : SSTL-18 Class I : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AN10 : : : : 4A :
GND : AN11 : gnd : : : :
ddr2_dimm_dq[47] : AN12 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[39] : AN13 : bidir : SSTL-18 Class I : : 4A : Y
GND : AN14 : gnd : : : :
ddr2_dimm_dq[33] : AN15 : bidir : SSTL-18 Class I : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AN16 : : : : 4A :
GND : AN17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AN18 : : : : 3A :
ddr2_dimm_dq[29] : AN19 : bidir : SSTL-18 Class I : : 3A : Y
GND : AN20 : gnd : : : :
ddr2_dimm_dq[24] : AN21 : bidir : SSTL-18 Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AN22 : : : : 3A :
GND : AN23 : gnd : : : :
ddr2_dimm_dqs[1] : AN24 : bidir : Differential 1.8-V SSTL Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AN25 : : : : 3A :
GND : AN26 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AN27 : : : : 3A :
ddr2_dimm_dq[5] : AN28 : bidir : SSTL-18 Class I : : 3A : Y
GND : AN29 : gnd : : : :
GND : AN30 : gnd : : : :
GND : AN31 : gnd : : : :
GND : AN32 : gnd : : : :
pcie_rx_p[0] : AN33 : input : 1.5-V PCML : : QL0 : Y
pcie_rx_p[0](n) : AN34 : input : 1.5-V PCML : : QL0 : N
ddr2_dimm_dq[58] : AP2 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[62] : AP3 : bidir : SSTL-18 Class I : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AP4 : : : : 4A :
ddr2_dimm_dq[51] : AP5 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[50] : AP6 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[49] : AP7 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_cke : AP8 : output : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[43] : AP9 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[42] : AP10 : bidir : SSTL-18 Class I : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AP11 : : : : 4A :
ddr2_dimm_dq[46] : AP12 : bidir : SSTL-18 Class I : : 4A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AP13 : : : : 4A :
ddr2_dimm_dq[38] : AP14 : bidir : SSTL-18 Class I : : 4A : Y
ddr2_dimm_dq[32] : AP15 : bidir : SSTL-18 Class I : : 4A : Y
hsmb_clk_in0 : AP16 : input : 1.8 V : : 4A : Y
hsma_clk_in0 : AP17 : input : 1.8 V : : 4A : Y
ddr2_dimm_dq[27] : AP18 : bidir : SSTL-18 Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AP19 : : : : 3A :
ddr2_dimm_dm[3] : AP20 : output : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dqs[2] : AP21 : bidir : Differential 1.8-V SSTL Class I : : 3A : Y
ddr2_dimm_dqs_n[2] : AP22 : bidir : Differential 1.8-V SSTL Class I : : 3A : Y
ddr2_dimm_dq[18] : AP23 : bidir : SSTL-18 Class I : : 3A : Y
ddr2_dimm_dqs_n[1] : AP24 : bidir : Differential 1.8-V SSTL Class I : : 3A : Y
ddr2_dimm_dq[11] : AP25 : bidir : SSTL-18 Class I : : 3A : Y
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : AP26 : output : 1.8 V : : 3A : Y
ddr2_dimm_dq[8] : AP27 : bidir : SSTL-18 Class I : : 3A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AP28 : : : : 3A :
ddr2_dimm_dq[4] : AP29 : bidir : SSTL-18 Class I : : 3A : Y
GND : AP30 : gnd : : : :
RREF : AP31 : : : : :
GND : AP32 : gnd : : : :
GND : AP33 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 7A :
GND : B2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 7A :
GND : B5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 7A :
GND : B8 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7A :
GND : B11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 7A :
GND : B14 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7A :
GND : B17 : gnd : : : :
fsm_d[25] : B18 : bidir : 2.5 V : : 8A : Y
fsm_d[3] : B19 : bidir : 2.5 V : : 8A : Y
GND : B20 : gnd : : : :
fsm_d[28] : B21 : bidir : 2.5 V : : 8A : Y
sram_dqp[1] : B22 : bidir : 2.5 V : : 8A : Y
GND : B23 : gnd : : : :
fsm_a[9] : B24 : output : 2.5 V : : 8A : Y
fsm_d[12] : B25 : bidir : 2.5 V : : 8A : Y
GND : B26 : gnd : : : :
sram_zz : B27 : output : 2.5 V : : 8A : Y
GND : B28 : gnd : : : :
GND : B29 : gnd : : : :
GND : B30 : gnd : : : :
NC : B31 : : : : :
NC : B32 : : : : :
GND : B33 : gnd : : : :
GND : B34 : gnd : : : :
lcd_data[7] : C1 : bidir : 2.5 V : : 6A : Y
lcd_data[6] : C2 : bidir : 2.5 V : : 6A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 7A :
DNU : C4 : : : : :
NC : C5 : : : : :
NC : C6 : : : : :
flash_wen : C7 : output : 2.5 V : : 7B : Y
fsm_a[5] : C8 : output : 2.5 V : : 7B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7A :
sram_adscn : C10 : output : 2.5 V : : 7B : Y
VCCIO7A : C11 : power : : 1.8V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7A :
VCCIO7A : C14 : power : : 1.8V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7A :
VCCIO8A : C17 : power : : 2.5V : 8A :
fsm_d[1] : C18 : bidir : 2.5 V : : 8A : Y
fsm_d[26] : C19 : bidir : 2.5 V : : 8A : Y
VCCIO8A : C20 : power : : 2.5V : 8A :
fsm_d[30] : C21 : bidir : 2.5 V : : 8A : Y
sram_dqp[3] : C22 : bidir : 2.5 V : : 8A : Y
VCCIO8A : C23 : power : : 2.5V : 8A :
fsm_a[10] : C24 : output : 2.5 V : : 8A : Y
enet_tx_d[1] : C25 : output : 2.5 V : : 8A : Y
fsm_d[14] : C26 : bidir : 2.5 V : : 8A : Y
pcie_led_x8 : C27 : output : 2.5 V : : 8A : Y
pcie_led_x1 : C28 : output : 2.5 V : : 8A : Y
hsma_tx_led : C29 : output : 2.5 V : : 8A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 8A :
GND : C31 : gnd : : : :
GND : C32 : gnd : : : :
NC : C33 : : : : :
NC : C34 : : : : :
lcd_data[5] : D1 : bidir : 2.5 V : : 6A : Y
lcd_data[4] : D2 : bidir : 2.5 V : : 6A : Y
NC : D3 : : : : :
NC : D4 : : : : :
NC : D5 : : : : :
NC : D6 : : : : :
NC : D7 : : : : :
VCCIO7B : D8 : power : : 2.5V : 7B :
sram_advn : D9 : output : 2.5 V : : 7B : Y
sram_oen : D10 : output : 2.5 V : : 7B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7A :
enet_rx_dv : D17 : input : 2.5 V : : 8A : Y
enet_intn : D18 : input : 2.5 V : : 8A : Y
fsm_d[27] : D19 : bidir : 2.5 V : : 8A : Y
fsm_a[7] : D20 : output : 2.5 V : : 8A : Y
fsm_d[8] : D21 : bidir : 2.5 V : : 8A : Y
fsm_d[20] : D22 : bidir : 2.5 V : : 8A : Y
fsm_d[9] : D23 : bidir : 2.5 V : : 8A : Y
fsm_d[10] : D24 : bidir : 2.5 V : : 8A : Y
enet_gtx_clk : D25 : output : 2.5 V : : 8A : Y
pcie_led_x4 : D26 : output : 2.5 V : : 8A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 8A :
fsm_d[2] : D28 : bidir : 2.5 V : : 8A : Y
fsm_a[2] : D29 : output : 2.5 V : : 8A : Y
NC : D30 : : : : :
NC : D31 : : : : :
NC : D32 : : : : :
GND : D33 : gnd : : : :
GND : D34 : gnd : : : :
lcd_data[2] : E1 : bidir : 2.5 V : : 6A : Y
GND : E2 : gnd : : : :
NC : E3 : : : : :
NC : E4 : : : : :
GND : E5 : gnd : : : :
NC : E6 : : : : :
NC : E7 : : : : :
GND : E8 : gnd : : : :
sram_bwn[2] : E9 : output : 2.5 V : : 7B : Y
sram_cen : E10 : output : 2.5 V : : 7B : Y
GND : E11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7A :
GND : E14 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7A :
GND : E17 : gnd : : : :
fsm_d[5] : E18 : bidir : 2.5 V : : 8A : Y
fsm_d[4] : E19 : bidir : 2.5 V : : 8A : Y
GND : E20 : gnd : : : :
enet_rx_d[0] : E21 : input : 2.5 V : : 8A : Y
enet_rx_d[2] : E22 : input : 2.5 V : : 8A : Y
GND : E23 : gnd : : : :
enet_rx_d[1] : E24 : input : 2.5 V : : 8A : Y
fsm_a[11] : E25 : output : 2.5 V : : 8A : Y
GND : E26 : gnd : : : :
NC : E27 : : : : :
NC : E28 : : : : :
GND : E29 : gnd : : : :
NC : E30 : : : : :
GND : E31 : gnd : : : :
GND : E32 : gnd : : : :
NC : E33 : : : : :
NC : E34 : : : : :
lcd_data[0] : F1 : bidir : 2.5 V : : 6A : Y
lcd_data[3] : F2 : bidir : 2.5 V : : 6A : Y
NC : F3 : : : : :
NC : F4 : : : : :
NC : F5 : : : : :
NC : F6 : : : : :
NC : F7 : : : : :
NC : F8 : : : : :
NC : F9 : : : : :
fsm_a[23] : F10 : output : 2.5 V : : 7B : Y
VCCIO7A : F11 : power : : 1.8V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 7A :
VCCIO7A : F14 : power : : 1.8V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7A :
clkin_top_p(n) : F17 : input : LVDS : : 8A : N
clkin_top_p : F18 : input : LVDS : : 8A : Y
fsm_d[7] : F19 : bidir : 2.5 V : : 8A : Y
VCCIO8A : F20 : power : : 2.5V : 8A :
fsm_a[12] : F21 : output : 2.5 V : : 8A : Y
VCCIO8A : F22 : power : : 2.5V : 8A :
clkout_sma : F23 : output : 2.5 V : : 8A : Y
enet_rx_d[3] : F24 : input : 2.5 V : : 8A : Y
fsm_a[17] : F25 : output : 2.5 V : : 8A : Y
fsm_a[18] : F26 : output : 2.5 V : : 8A : Y
NC : F27 : : : : :
NC : F28 : : : : :
NC : F29 : : : : :
NC : F30 : : : : :
NC : F31 : : : : :
NC : F32 : : : : :
GND : F33 : gnd : : : :
GND : F34 : gnd : : : :
user_led[0] : G1 : output : 2.5 V : : 6A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 6A :
NC : G3 : : : : :
NC : G4 : : : : :
NC : G5 : : : : :
NC : G6 : : : : :
NC : G7 : : : : :
NC : G8 : : : : :
NC : G9 : : : : :
NC : G10 : : : : :
termination_blk0~_rdn_pad : G11 : input : 1.8 V : : 7A : Y
termination_blk0~_rup_pad : G12 : input : 1.8 V : : 7A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7A :
fsm_d[6] : G19 : bidir : 2.5 V : : 8A : Y
enet_tx_en : G20 : output : 2.5 V : : 8A : Y
enet_tx_d[3] : G21 : output : 2.5 V : : 8A : Y
enet_tx_d[2] : G22 : output : 2.5 V : : 8A : Y
fsm_a[19] : G23 : output : 2.5 V : : 8A : Y
NC : G24 : : : : :
NC : G25 : : : : :
NC : G26 : : : : :
NC : G27 : : : : :
NC : G28 : : : : :
NC : G29 : : : : :
NC : G30 : : : : :
GND : G31 : gnd : : : :
GND : G32 : gnd : : : :
NC : G33 : : : : :
NC : G34 : : : : :
lcd_wen : H1 : output : 2.5 V : : 6A : Y
GND : H2 : gnd : : : :
lcd_data[1] : H3 : bidir : 2.5 V : : 6A : Y
NC : H4 : : : : :
GND : H5 : gnd : : : :
NC : H6 : : : : :
NC : H7 : : : : :
GND : H8 : gnd : : : :
NC : H9 : : : : :
NC : H10 : : : : :
GND : H11 : gnd : : : :
sram_bwn[1] : H12 : output : 2.5 V : : 7B : Y
sram_bwn[3] : H13 : output : 2.5 V : : 7B : Y
GND : H14 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7A :
GND : H17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7A :
fsm_a[14] : H19 : output : 2.5 V : : 8A : Y
GND : H20 : gnd : : : :
fsm_a[20] : H21 : output : 2.5 V : : 8A : Y
NC : H22 : : : : :
GND : H23 : gnd : : : :
NC : H24 : : : : :
VCCA_PLL_1 : H25 : power : : 2.5V : :
GND : H26 : gnd : : : :
NC : H27 : : : : :
NC : H28 : : : : :
GND : H29 : gnd : : : :
NC : H30 : : : : :
NC : H31 : : : : :
NC : H32 : : : : :
GND : H33 : gnd : : : :
GND : H34 : gnd : : : :
lcd_d_cn : J1 : output : 2.5 V : : 6A : Y
lcd_csn : J2 : output : 2.5 V : : 6A : Y
fsm_a[1] : J3 : output : 2.5 V : : 6A : Y
user_led[1] : J4 : output : 2.5 V : : 6A : Y
user_led[2] : J5 : output : 2.5 V : : 6A : Y
NC : J6 : : : : :
NC : J7 : : : : :
NC : J8 : : : : :
GND : J9 : gnd : : : :
VCCA_PLL_2 : J10 : power : : 2.5V : :
sram_bwen : J11 : output : 2.5 V : : 7B : Y
sram_clk : J12 : output : 2.5 V : : 7B : Y
sram_bwn[0] : J13 : output : 2.5 V : : 7B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7A :
ddr2_dimm_addr[15] : J17 : output : SSTL-18 Class I : : 7A : N
hsma_clk_in_p2(n) : J18 : input : LVDS : : 7A : Y
fsm_a[13] : J19 : output : 2.5 V : : 8A : Y
enet_tx_d[0] : J20 : output : 2.5 V : : 8A : Y
fsm_a[3] : J21 : output : 2.5 V : : 8A : Y
NC : J22 : : : : :
NC : J23 : : : : :
NC : J24 : : : : :
NC : J25 : : : : :
VCCD_PLL_1 : J26 : power : : 0.9V : :
NC : J27 : : : : :
NC : J28 : : : : :
NC : J29 : : : : :
NC : J30 : : : : :
GND : J31 : gnd : : : :
GND : J32 : gnd : : : :
NC : J33 : : : : :
NC : J34 : : : : :
hsma_d[2] : K1 : bidir : 2.5 V : : 6A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 6A :
cal_blk_clk : K3 : input : 2.5 V : : 6A : N
fsm_a[25] : K4 : output : 2.5 V : : 6A : Y
flash_oen : K5 : output : 2.5 V : : 6A : Y
NC : K6 : : : : :
NC : K7 : : : : :
NC : K8 : : : : :
VCCD_PLL_2 : K9 : power : : 0.9V : :
GND : K10 : gnd : : : :
NC : K11 : : : : :
sram_gwn : K12 : output : 2.5 V : : 7B : Y
VREFB7BN0 : K13 : power : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7A :
hsma_clk_in_p2 : K18 : input : LVDS : : 7A : Y
VREFB8AN0 : K19 : power : : : 8A :
enet_mdc : K20 : output : 2.5 V : : 8A : Y
fsm_a[15] : K21 : output : 2.5 V : : 8A : Y
NC : K22 : : : : :
NC : K23 : : : : :
NC : K24 : : : : :
DNU : K25 : : : : :
VCCIO8C : K26 : power : : 2.5V : 8C :
ASDO : K27 : : : : 8C :
NC : K28 : : : : :
GND : K29 : gnd : : : :
GND : K30 : gnd : : : :
GXB_NC : K31 : : : : QL2 :
GXB_NC : K32 : : : : QL2 :
GND : K33 : gnd : : : :
GND : K34 : gnd : : : :
hsma_d[0] : L1 : bidir : 2.5 V : : 6A : Y
GND : L2 : gnd : : : :
VCCIO6A : L3 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 6A :
GND : L5 : gnd : : : :
NC : L6 : : : : :
NC : L7 : : : : :
GND : L8 : gnd : : : :
NC : L9 : : : : :
NC : L10 : : : : :
NC : L11 : : : : :
VCCPD7B : L12 : power : : 2.5V : 7B :
fsm_a[4] : L13 : output : 2.5 V : : 7B : Y
GND : L14 : gnd : : : :
VREFB7AN0 : L15 : power : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 7A :
GND : L17 : gnd : : : :
VCCCB : L18 : power : : 1.5V : :
VCCPD8A : L19 : power : : 2.5V : 8A :
GND : L20 : gnd : : : :
fsm_a[16] : L21 : output : 2.5 V : : 8A : Y
NC : L22 : : : : :
GND : L23 : gnd : : : :
altera_reserved_tck : L24 : input : 2.5 V : : 8C : N
DCLK : L25 : bidir : : : 8C :
GND : L26 : gnd : : : :
VCCBAT : L27 : power : : 2.5V : :
NC : L28 : : : : :
NC : L29 : : : : :
NC : L30 : : : : :
GND : L31 : gnd : : : :
GND : L32 : gnd : : : :
GXB_GND* : L33 : : : : QL2 :
GXB_GND* : L34 : : : : QL2 :
hsma_d[3] : M1 : bidir : 2.5 V : : 6A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 6A :
flash_cen : M3 : output : 2.5 V : : 6A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 6A :
NC : M5 : : : : :
NC : M6 : : : : :
NC : M7 : : : : :
NC : M8 : : : : :
NC : M9 : : : : :
NC : M10 : : : : :
NC : M11 : : : : :
NC : M12 : : : : :
fsm_a[21] : M13 : output : 2.5 V : : 7B : Y
VCCPD7A : M14 : power : : 2.5V : 7A :
VCCPD7A : M15 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M18 : : : : 8A :
VCCPD8A : M19 : power : : 2.5V : 8A :
enet_resetn : M20 : output : 2.5 V : : 8A : Y
fsm_a[0] : M21 : output : 2.5 V : : 8A : Y
NC : M22 : : : : :
NC : M23 : : : : :
VCCPD8C : M24 : power : : 2.5V : 8C :
altera_reserved_tdi : M25 : input : 2.5 V : : 8C : N
nCSO : M26 : : : : 8C :
altera_reserved_tdo : M27 : output : 2.5 V : : 8C : N
GND : M28 : gnd : : : :
GND : M29 : gnd : : : :
GND : M30 : gnd : : : :
GXB_NC : M31 : : : : QL2 :
GXB_NC : M32 : : : : QL2 :
GND : M33 : gnd : : : :
GND : M34 : gnd : : : :
pcie_perstn : N1 : input : 2.5 V : : 6A : Y
user_dipsw[0] : N2 : input : 2.5 V : : 6A : Y
flash_resetn : N3 : output : 2.5 V : : 6A : Y
flash_clk : N4 : output : 2.5 V : : 6A : Y
hsma_rx_led : N5 : output : 2.5 V : : 6A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 6A :
NC : N7 : : : : :
NC : N8 : : : : :
fsm_a[6] : N9 : output : 2.5 V : : 6A : Y
cpu_resetn : N10 : input : 2.5 V : : 6A : Y
VREFB6AN0 : N11 : power : : : 6A :
GND : N12 : gnd : : : :
VCC : N13 : power : : 0.9V : :
GND : N14 : gnd : : : :
VCC : N15 : power : : 0.9V : :
GND : N16 : gnd : : : :
VCC : N17 : power : : 0.9V : :
GND : N18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N19 : : : : 8A :
enet_mdio : N20 : bidir : 2.5 V : : 8A : Y
VCC : N21 : power : : 0.9V : :
GND : N22 : gnd : : : :
VCC : N23 : power : : 0.9V : :
GND : N24 : gnd : : : :
altera_reserved_tms : N25 : input : 2.5 V : : 8C : N
DATA0 : N26 : input : : : 8C :
GND : N27 : gnd : : : :
VCCH_GXB : N28 : power : : 1.5V : :
NC : N29 : : : : :
NC : N30 : : : : :
GND : N31 : gnd : : : :
GND : N32 : gnd : : : :
GXB_GND* : N33 : : : : QL2 :
GXB_GND* : N34 : : : : QL2 :
hsma_tx_d_p[14](n) : P1 : output : LVDS : : 6A : Y
GND : P2 : gnd : : : :
VCCIO6A : P3 : power : : 2.5V : 6A :
fsm_d[22] : P4 : bidir : 2.5 V : : 6A : Y
GND : P5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 6A :
fsm_a[22] : P7 : output : 2.5 V : : 6A : Y
GND : P8 : gnd : : : :
sram_dqp[2] : P9 : bidir : 2.5 V : : 6A : Y
hsma_clk_out0 : P10 : output : 2.5 V : : 6A : Y
GND : P11 : gnd : : : :
VCC : P12 : power : : 0.9V : :
GND : P13 : gnd : : : :
VCC : P14 : power : : 0.9V : :
GND : P15 : gnd : : : :
VCC : P16 : power : : 0.9V : :
GND : P17 : gnd : : : :
VCC : P18 : power : : 0.9V : :
GND : P19 : gnd : : : :
VCC : P20 : power : : 0.9V : :
GND : P21 : gnd : : : :
VCC : P22 : power : : 0.9V : :
GND : P23 : gnd : : : :
VCC : P24 : power : : 0.9V : :
GND : P25 : gnd : : : :
GND : P26 : gnd : : : :
VCCH_GXB : P27 : power : : 1.5V : :
GND : P28 : gnd : : : :
GND : P29 : gnd : : : :
GND : P30 : gnd : : : :
GXB_NC : P31 : : : : QL2 :
GXB_NC : P32 : : : : QL2 :
GND : P33 : gnd : : : :
GND : P34 : gnd : : : :
hsma_sda : R1 : bidir : 2.5 V : : 6A : Y
hsma_tx_d_p[14] : R2 : output : LVDS : : 6A : Y
flash_rdybsyn : R3 : input : 2.5 V : : 6A : Y
fsm_a[24] : R4 : output : 2.5 V : : 6A : Y
user_led[3] : R5 : output : 2.5 V : : 6A : Y
hsma_d[1] : R6 : bidir : 2.5 V : : 6A : Y
hsma_tx_d_p[13] : R7 : output : LVDS : : 6A : Y
fsm_d[18] : R8 : bidir : 2.5 V : : 6A : Y
fsm_d[16] : R9 : bidir : 2.5 V : : 6A : Y
fsm_d[17] : R10 : bidir : 2.5 V : : 6A : Y
fsm_d[23] : R11 : bidir : 2.5 V : : 6A : Y
VCCPD6A : R12 : power : : 2.5V : 6A :
VCC : R13 : power : : 0.9V : :
GND : R14 : gnd : : : :
VCC : R15 : power : : 0.9V : :
GND : R16 : gnd : : : :
VCC : R17 : power : : 0.9V : :
GND : R18 : gnd : : : :
VCC : R19 : power : : 0.9V : :
GND : R20 : gnd : : : :
VCC : R21 : power : : 0.9V : :
GND : R22 : gnd : : : :
VCC : R23 : power : : 0.9V : :
VCCA : R24 : power : : 2.5V : :
VCCL_GXB : R25 : power : : 1.1V : :
GND : R26 : gnd : : : :
VCCL_GXB : R27 : power : : 1.1V : :
GND : R28 : gnd : : : :
GXB_GND* : R29 : : : : QL2 :
GXB_GND* : R30 : : : : QL2 :
GND : R31 : gnd : : : :
GND : R32 : gnd : : : :
GXB_GND* : R33 : : : : QL2 :
GXB_GND* : R34 : : : : QL2 :
hsma_scl : T1 : output : 2.5 V : : 6A : Y
GND : T2 : gnd : : : :
VCCIO6A : T3 : power : : 2.5V : 6A :
flash_advn : T4 : output : 2.5 V : : 6A : Y
GND : T5 : gnd : : : :
VCCIO6A : T6 : power : : 2.5V : 6A :
hsma_tx_d_p[13](n) : T7 : output : LVDS : : 6A : Y
GND : T8 : gnd : : : :
VCCA_PLL_5 : T9 : power : : 2.5V : :
fsm_d[21] : T10 : bidir : 2.5 V : : 6A : Y
GND : T11 : gnd : : : :
VCCPD6A : T12 : power : : 2.5V : 6A :
GND : T13 : gnd : : : :
VCC : T14 : power : : 0.9V : :
GND : T15 : gnd : : : :
VCC : T16 : power : : 0.9V : :
GND : T17 : gnd : : : :
VCC : T18 : power : : 0.9V : :
GND : T19 : gnd : : : :
VCC : T20 : power : : 0.9V : :
GND : T21 : gnd : : : :
VCC : T22 : power : : 0.9V : :
GND : T23 : gnd : : : :
VCC : T24 : power : : 0.9V : :
GND : T25 : gnd : : : :
VCCL_GXB : T26 : power : : 1.1V : :
GND : T27 : gnd : : : :
VCCL_GXB : T28 : power : : 1.1V : :
GND : T29 : gnd : : : :
GND : T30 : gnd : : : :
GXB_NC : T31 : : : : QL2 :
GXB_NC : T32 : : : : QL2 :
GND : T33 : gnd : : : :
GND : T34 : gnd : : : :
hsma_rx_d_p[10](n) : U1 : input : LVDS : : 6A : Y
hsma_rx_d_p[10] : U2 : input : LVDS : : 6A : Y
hsma_prsntn : U3 : input : 2.5 V : : 6A : Y
user_dipsw[3] : U4 : input : 2.5 V : : 6A : Y
hsma_clk_in_p1(n) : U5 : input : LVDS : : 6A : Y
hsma_clk_in_p1 : U6 : input : LVDS : : 6A : Y
hsma_rx_d_p[14] : U7 : input : LVDS : : 5A : Y
VCCD_PLL_5 : U8 : power : : 0.9V : :
user_dipsw[1] : U9 : input : 2.5 V : : 6A : Y
hsma_tx_d_p[16](n) : U10 : output : LVDS : : 6A : Y
hsma_tx_d_p[16] : U11 : output : LVDS : : 6A : Y
VCCCB : U12 : power : : 1.5V : :
VCC : U13 : power : : 0.9V : :
GND : U14 : gnd : : : :
VCC : U15 : power : : 0.9V : :
GND : U16 : gnd : : : :
GND : U17 : gnd : : : :
GND : U18 : gnd : : : :
VCC : U19 : power : : 0.9V : :
GND : U20 : gnd : : : :
VCC : U21 : power : : 0.9V : :
GND : U22 : gnd : : : :
VCCCB : U23 : power : : 1.5V : :
VCCA : U24 : power : : 2.5V : :
VCCL_GXB : U25 : power : : 1.1V : :
GND : U26 : gnd : : : :
VCCL_GXB : U27 : power : : 1.1V : :
GND : U28 : gnd : : : :
GXB_GND* : U29 : : : : QL2 :
GXB_GND* : U30 : : : : QL2 :
GND : U31 : gnd : : : :
GND : U32 : gnd : : : :
GXB_GND* : U33 : : : : QL2 :
GXB_GND* : U34 : : : : QL2 :
hsma_rx_d_p[8](n) : V1 : input : LVDS : : 5A : Y
hsma_rx_d_p[8] : V2 : input : LVDS : : 5A : Y
hsma_tx_d_p[7](n) : V3 : output : LVDS : : 5A : Y
hsma_tx_d_p[7] : V4 : output : LVDS : : 5A : Y
GND+ : V5 : : : : 5A :
enet_rx_clk : V6 : input : 2.5 V : : 5A : Y
hsma_rx_d_p[14](n) : V7 : input : LVDS : : 5A : Y
VCCD_PLL_6 : V8 : power : : 0.9V : :
user_dipsw[2] : V9 : input : 2.5 V : : 6A : Y
hsma_tx_d_p[15](n) : V10 : output : LVDS : : 5A : Y
hsma_tx_d_p[15] : V11 : output : LVDS : : 5A : Y
hsma_clk_out_p2 : V12 : output : LVDS : : 5A : Y
GND : V13 : gnd : : : :
VCC : V14 : power : : 0.9V : :
GND : V15 : gnd : : : :
VCC : V16 : power : : 0.9V : :
DNU : V17 : : : : :
VCC : V18 : power : : 0.9V : :
GND : V19 : gnd : : : :
VCC : V20 : power : : 0.9V : :
GND : V21 : gnd : : : :
VCC : V22 : power : : 0.9V : :
GND : V23 : gnd : : : :
VCC : V24 : power : : 0.9V : :
GND : V25 : gnd : : : :
VCCL_GXB : V26 : power : : 1.1V : :
GND : V27 : gnd : : : :
VCCL_GXB : V28 : power : : 1.1V : :
GND : V29 : gnd : : : :
GND : V30 : gnd : : : :
pcie_tx_p[7] : V31 : output : 1.5-V PCML : : QL1 : Y
pcie_tx_p[7](n) : V32 : output : 1.5-V PCML : : QL1 : N
GND : V33 : gnd : : : :
GND : V34 : gnd : : : :
hsma_rx_d_p[7](n) : W1 : input : LVDS : : 5A : Y
GND : W2 : gnd : : : :
hsma_rx_d_p[9](n) : W3 : input : LVDS : : 5A : Y
hsma_rx_d_p[9] : W4 : input : LVDS : : 5A : Y
GND : W5 : gnd : : : :
hsma_tx_d_p[9](n) : W6 : output : LVDS : : 5A : Y
hsma_tx_d_p[9] : W7 : output : LVDS : : 5A : Y
GND : W8 : gnd : : : :
VCCA_PLL_6 : W9 : power : : 2.5V : :
hsma_tx_d_p[12] : W10 : output : LVDS : : 5A : Y
GND : W11 : gnd : : : :
hsma_clk_out_p2(n) : W12 : output : LVDS : : 5A : Y
VCC : W13 : power : : 0.9V : :
GND : W14 : gnd : : : :
VCC : W15 : power : : 0.9V : :
GND : W16 : gnd : : : :
VCC : W17 : power : : 0.9V : :
GND : W18 : gnd : : : :
VCC : W19 : power : : 0.9V : :
GND : W20 : gnd : : : :
VCC : W21 : power : : 0.9V : :
GND : W22 : gnd : : : :
VCC : W23 : power : : 0.9V : :
NC : W24 : : : : :
VCCL_GXB : W25 : power : : 1.1V : :
GND : W26 : gnd : : : :
NC : W27 : : : : :
GND : W28 : gnd : : : :
GXB_GND* : W29 : : : : QL1 :
GXB_GND* : W30 : : : : QL1 :
GND : W31 : gnd : : : :
GND : W32 : gnd : : : :
pcie_rx_p[7] : W33 : input : 1.5-V PCML : : QL1 : Y
pcie_rx_p[7](n) : W34 : input : 1.5-V PCML : : QL1 : N
hsma_rx_d_p[6] : Y1 : input : LVDS : : 5A : Y
hsma_rx_d_p[7] : Y2 : input : LVDS : : 5A : Y
hsma_rx_d_p[11](n) : Y3 : input : LVDS : : 5A : Y
hsma_rx_d_p[11] : Y4 : input : LVDS : : 5A : Y
hsma_tx_d_p[10] : Y5 : output : LVDS : : 5A : Y
hsma_tx_d_p[8](n) : Y6 : output : LVDS : : 5A : Y
hsma_tx_d_p[4](n) : Y7 : output : LVDS : : 5A : Y
hsma_tx_d_p[4] : Y8 : output : LVDS : : 5A : Y
hsma_tx_d_p[12](n) : Y9 : output : LVDS : : 5A : Y
hsma_tx_d_p[1](n) : Y10 : output : LVDS : : 5A : Y
hsma_tx_d_p[1] : Y11 : output : LVDS : : 5A : Y
VCCPD5A : Y12 : power : : 2.5V : 5A :
GND : Y13 : gnd : : : :
VCC : Y14 : power : : 0.9V : :
GND : Y15 : gnd : : : :
VCC : Y16 : power : : 0.9V : :
GND : Y17 : gnd : : : :
VCC : Y18 : power : : 0.9V : :
GND : Y19 : gnd : : : :
VCC : Y20 : power : : 0.9V : :
GND : Y21 : gnd : : : :
VCC : Y22 : power : : 0.9V : :
GND : Y23 : gnd : : : :
VCC : Y24 : power : : 0.9V : :
GND : Y25 : gnd : : : :
NC : Y26 : : : : :
GND : Y27 : gnd : : : :
NC : Y28 : : : : :
GND : Y29 : gnd : : : :
GND : Y30 : gnd : : : :
pcie_tx_p[6] : Y31 : output : 1.5-V PCML : : QL1 : Y
pcie_tx_p[6](n) : Y32 : output : 1.5-V PCML : : QL1 : N
GND : Y33 : gnd : : : :
GND : Y34 : gnd : : : :
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/ddr2_sodimm.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 222 10/21/2009 SJ Full Version
# Date created = 13:17:30 January 19, 2010
#
# -------------------------------------------------------------------------- #
 
QUARTUS_VERSION = "9.1"
DATE = "13:17:30 January 19, 2010"
 
# Revisions
 
PROJECT_REVISION = "ddr2_sodimm"
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/a2_pex_x8_serdes.qip
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/ddr2_sodimm.qsf
0,0 → 1,2139
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 222 10/21/2009 SJ Full Version
# Date created = 13:17:30 January 19, 2010
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ddr2_sodimm_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
 
 
set_global_assignment -name FAMILY "Arria II GX"
set_global_assignment -name DEVICE EP2AGX125EF35C4ES
set_global_assignment -name TOP_LEVEL_ENTITY a2gx_dev_kit_golden_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:17:30 JANUARY 19, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION 11.1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH ddr2_sodimm_tb -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name SEARCH_PATH ./
set_global_assignment -name SEARCH_PATH testbench/ -tag from_archive
set_global_assignment -name SEARCH_PATH "C:/altera/81bi160/ip/altera/ddr3_high_perf/lib/"
set_global_assignment -name SEARCH_PATH "in Q8.1 b160_example_design(31_10_2008_friday)/"
set_global_assignment -name SEARCH_PATH "altmemphy-library/" -tag from_archive
set_global_assignment -name SEARCH_PATH "ddr2_high_performance_controller-library/" -tag from_archive
set_global_assignment -name SEARCH_PATH simulation/modelsim/ -tag from_archive
set_global_assignment -name SEARCH_PATH ./top_examples
set_global_assignment -name SEARCH_PATH ./top_examples/chaining_dma
 
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name LL_ROOT_REGION ON -entity ddr2_sodimm -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -entity ddr2_sodimm -section_id "Root Region"
set_location_assignment PIN_G12 -to termination_blk0~_rup_pad
set_location_assignment PIN_G11 -to termination_blk0~_rdn_pad
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE ../a2gx_pcie_to_hibi_4/stp7.stp
set_global_assignment -name EDA_TEST_BENCH_NAME ddr2_sodimm_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME dut -section_id ddr2_sodimm_tb
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id ddr2_sodimm_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ddr2_sodimm_example_top_tb -section_id ddr2_sodimm_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/ddr2_sodimm_example_top_tb_4.v -section_id ddr2_sodimm_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/ddr2_sodimm_mem_model.v -section_id ddr2_sodimm_tb
set_global_assignment -name MISC_FILE ddr2_sodimm.dpf
#set_global_assignment -name POWER_HSSI "Opportunistically power off"
set_instance_assignment -name IO_STANDARD LVDS -to clkin_bot_p
set_location_assignment PIN_AJ19 -to clkin_bot_p
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb
set_location_assignment PIN_AK9 -to user_pb[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr
set_location_assignment PIN_AH14 -to ddr2_dimm_addr[0]
set_location_assignment PIN_AK12 -to ddr2_dimm_addr[1]
set_location_assignment PIN_AE12 -to ddr2_dimm_addr[2]
set_location_assignment PIN_AH13 -to ddr2_dimm_addr[3]
set_location_assignment PIN_AF14 -to ddr2_dimm_addr[4]
set_location_assignment PIN_AG12 -to ddr2_dimm_addr[5]
set_location_assignment PIN_AJ18 -to ddr2_dimm_addr[6]
set_location_assignment PIN_AL19 -to ddr2_dimm_addr[7]
set_location_assignment PIN_AG13 -to ddr2_dimm_addr[8]
set_location_assignment PIN_AE13 -to ddr2_dimm_addr[9]
set_location_assignment PIN_AK10 -to ddr2_dimm_addr[10]
set_location_assignment PIN_AH23 -to ddr2_dimm_addr[11]
set_location_assignment PIN_AF13 -to ddr2_dimm_addr[12]
set_location_assignment PIN_AM5 -to ddr2_dimm_addr[13]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_ba
set_location_assignment PIN_AJ11 -to ddr2_dimm_ba[0]
set_location_assignment PIN_AJ13 -to ddr2_dimm_ba[1]
set_location_assignment PIN_AE14 -to ddr2_dimm_ba[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_cas_n
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_cke
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_clk
set_location_assignment PIN_AJ7 -to ddr2_dimm_clk[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_clk_n
set_location_assignment PIN_AK7 -to ddr2_dimm_clk_n[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_cs_n
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dm
set_location_assignment PIN_AK22 -to ddr2_dimm_dm[0]
set_location_assignment PIN_AE19 -to ddr2_dimm_dm[1]
set_location_assignment PIN_AG19 -to ddr2_dimm_dm[2]
set_location_assignment PIN_AP20 -to ddr2_dimm_dm[3]
set_location_assignment PIN_AH18 -to ddr2_dimm_dm[4]
set_location_assignment PIN_AG16 -to ddr2_dimm_dm[5]
set_location_assignment PIN_AC15 -to ddr2_dimm_dm[6]
set_location_assignment PIN_AE15 -to ddr2_dimm_dm[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq
set_location_assignment PIN_AG21 -to ddr2_dimm_dq[0]
set_location_assignment PIN_AL29 -to ddr2_dimm_dq[1]
set_location_assignment PIN_AM29 -to ddr2_dimm_dq[2]
set_location_assignment PIN_AM28 -to ddr2_dimm_dq[3]
set_location_assignment PIN_AP29 -to ddr2_dimm_dq[4]
set_location_assignment PIN_AN28 -to ddr2_dimm_dq[5]
set_location_assignment PIN_AJ24 -to ddr2_dimm_dq[6]
set_location_assignment PIN_AJ25 -to ddr2_dimm_dq[7]
set_location_assignment PIN_AP27 -to ddr2_dimm_dq[8]
set_location_assignment PIN_AM24 -to ddr2_dimm_dq[9]
set_location_assignment PIN_AM23 -to ddr2_dimm_dq[10]
set_location_assignment PIN_AP25 -to ddr2_dimm_dq[11]
set_location_assignment PIN_AJ23 -to ddr2_dimm_dq[12]
set_location_assignment PIN_AL24 -to ddr2_dimm_dq[13]
set_location_assignment PIN_AG22 -to ddr2_dimm_dq[14]
set_location_assignment PIN_AH21 -to ddr2_dimm_dq[15]
set_location_assignment PIN_AL25 -to ddr2_dimm_dq[16]
set_location_assignment PIN_AK25 -to ddr2_dimm_dq[17]
set_location_assignment PIN_AP23 -to ddr2_dimm_dq[18]
set_location_assignment PIN_AM22 -to ddr2_dimm_dq[19]
set_location_assignment PIN_AL21 -to ddr2_dimm_dq[20]
set_location_assignment PIN_AL20 -to ddr2_dimm_dq[21]
set_location_assignment PIN_AJ21 -to ddr2_dimm_dq[22]
set_location_assignment PIN_AH20 -to ddr2_dimm_dq[23]
set_location_assignment PIN_AN21 -to ddr2_dimm_dq[24]
set_location_assignment PIN_AM21 -to ddr2_dimm_dq[25]
set_location_assignment PIN_AE18 -to ddr2_dimm_dq[26]
set_location_assignment PIN_AP18 -to ddr2_dimm_dq[27]
set_location_assignment PIN_AH19 -to ddr2_dimm_dq[28]
set_location_assignment PIN_AN19 -to ddr2_dimm_dq[29]
set_location_assignment PIN_AK18 -to ddr2_dimm_dq[30]
set_location_assignment PIN_AF18 -to ddr2_dimm_dq[31]
set_location_assignment PIN_AP15 -to ddr2_dimm_dq[32]
set_location_assignment PIN_AN15 -to ddr2_dimm_dq[33]
set_location_assignment PIN_AH17 -to ddr2_dimm_dq[34]
set_location_assignment PIN_AF17 -to ddr2_dimm_dq[35]
set_location_assignment PIN_AC18 -to ddr2_dimm_dq[36]
set_location_assignment PIN_AE17 -to ddr2_dimm_dq[37]
set_location_assignment PIN_AP14 -to ddr2_dimm_dq[38]
set_location_assignment PIN_AN13 -to ddr2_dimm_dq[39]
set_location_assignment PIN_AH16 -to ddr2_dimm_dq[40]
set_location_assignment PIN_AH15 -to ddr2_dimm_dq[41]
set_location_assignment PIN_AP10 -to ddr2_dimm_dq[42]
set_location_assignment PIN_AP9 -to ddr2_dimm_dq[43]
set_location_assignment PIN_AL16 -to ddr2_dimm_dq[44]
set_location_assignment PIN_AK16 -to ddr2_dimm_dq[45]
set_location_assignment PIN_AP12 -to ddr2_dimm_dq[46]
set_location_assignment PIN_AN12 -to ddr2_dimm_dq[47]
set_location_assignment PIN_AN7 -to ddr2_dimm_dq[48]
set_location_assignment PIN_AP7 -to ddr2_dimm_dq[49]
set_location_assignment PIN_AP6 -to ddr2_dimm_dq[50]
set_location_assignment PIN_AP5 -to ddr2_dimm_dq[51]
set_location_assignment PIN_AF16 -to ddr2_dimm_dq[52]
set_location_assignment PIN_AL14 -to ddr2_dimm_dq[53]
set_location_assignment PIN_AE16 -to ddr2_dimm_dq[54]
set_location_assignment PIN_AL11 -to ddr2_dimm_dq[55]
set_location_assignment PIN_AM10 -to ddr2_dimm_dq[56]
set_location_assignment PIN_AF15 -to ddr2_dimm_dq[57]
set_location_assignment PIN_AP2 -to ddr2_dimm_dq[58]
set_location_assignment PIN_AJ12 -to ddr2_dimm_dq[59]
set_location_assignment PIN_AJ16 -to ddr2_dimm_dq[60]
set_location_assignment PIN_AN9 -to ddr2_dimm_dq[61]
set_location_assignment PIN_AP3 -to ddr2_dimm_dq[62]
set_location_assignment PIN_AN4 -to ddr2_dimm_dq[63]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs
set_location_assignment PIN_AM25 -to ddr2_dimm_dqs[0]
set_location_assignment PIN_AN24 -to ddr2_dimm_dqs[1]
set_location_assignment PIN_AP21 -to ddr2_dimm_dqs[2]
set_location_assignment PIN_AL18 -to ddr2_dimm_dqs[3]
set_location_assignment PIN_AM16 -to ddr2_dimm_dqs[4]
set_location_assignment PIN_AK15 -to ddr2_dimm_dqs[5]
set_location_assignment PIN_AK13 -to ddr2_dimm_dqs[6]
set_location_assignment PIN_AM7 -to ddr2_dimm_dqs[7]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs_n
set_location_assignment PIN_AM26 -to ddr2_dimm_dqs_n[0]
set_location_assignment PIN_AP24 -to ddr2_dimm_dqs_n[1]
set_location_assignment PIN_AP22 -to ddr2_dimm_dqs_n[2]
set_location_assignment PIN_AM18 -to ddr2_dimm_dqs_n[3]
set_location_assignment PIN_AM17 -to ddr2_dimm_dqs_n[4]
set_location_assignment PIN_AL15 -to ddr2_dimm_dqs_n[5]
set_location_assignment PIN_AL12 -to ddr2_dimm_dqs_n[6]
set_location_assignment PIN_AM8 -to ddr2_dimm_dqs_n[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_odt
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_ras_n
set_location_assignment PIN_AH12 -to ddr2_dimm_ras_n
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_we_n
set_location_assignment PIN_AM6 -to ddr2_dimm_we_n
set_instance_assignment -name IO_STANDARD LVDS -to clkin_155_p
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to clkin_155_p -disable
set_location_assignment PIN_AK19 -to clkin_bot_n
set_instance_assignment -name IO_STANDARD LVDS -to clkin_ref_q1_1_p
set_location_assignment PIN_AA29 -to clkin_ref_q1_1_p
set_instance_assignment -name IO_STANDARD LVDS -to clkin_ref_q1_2_p
set_location_assignment PIN_W29 -to clkin_ref_q1_2_p
set_instance_assignment -name IO_STANDARD LVDS -to clkin_ref_q2_p
set_location_assignment PIN_U29 -to clkin_ref_q2_p
set_location_assignment PIN_F17 -to clkin_ref_q3_p
set_location_assignment PIN_F17 -to clkin_top_n
set_location_assignment PIN_F18 -to clkin_top_p
set_instance_assignment -name IO_STANDARD LVDS -to clkin_top_p
set_instance_assignment -name IO_STANDARD "2.5 V" -to clkout_sma
set_location_assignment PIN_F23 -to clkout_sma
set_instance_assignment -name IO_STANDARD "2.5 V" -to cpu_resetn
set_location_assignment PIN_N10 -to cpu_resetn
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a
set_location_assignment PIN_G16 -to ddr3_a[0]
set_location_assignment PIN_A12 -to ddr3_a[1]
set_location_assignment PIN_H18 -to ddr3_a[2]
set_location_assignment PIN_F16 -to ddr3_a[3]
set_location_assignment PIN_A7 -to ddr3_a[4]
set_location_assignment PIN_G17 -to ddr3_a[5]
set_location_assignment PIN_C13 -to ddr3_a[6]
set_location_assignment PIN_K14 -to ddr3_a[7]
set_location_assignment PIN_D11 -to ddr3_a[8]
set_location_assignment PIN_M16 -to ddr3_a[9]
set_location_assignment PIN_A11 -to ddr3_a[10]
set_location_assignment PIN_E15 -to ddr3_a[11]
set_location_assignment PIN_A8 -to ddr3_a[12]
set_location_assignment PIN_M17 -to ddr3_a[13]
set_location_assignment PIN_B15 -to ddr3_a[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba
set_location_assignment PIN_D16 -to ddr3_ba[0]
set_location_assignment PIN_C12 -to ddr3_ba[1]
set_location_assignment PIN_C16 -to ddr3_ba[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_casn
set_location_assignment PIN_D15 -to ddr3_casn
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_n
set_location_assignment PIN_B12 -to ddr3_ck_n
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_p
set_location_assignment PIN_B13 -to ddr3_ck_p
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke
set_location_assignment PIN_B10 -to ddr3_cke
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_csn
set_location_assignment PIN_A10 -to ddr3_csn
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm
set_location_assignment PIN_B9 -to ddr3_dm[0]
set_location_assignment PIN_K15 -to ddr3_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq
set_location_assignment PIN_J16 -to ddr3_dq[0]
set_location_assignment PIN_B7 -to ddr3_dq[1]
set_location_assignment PIN_K17 -to ddr3_dq[2]
set_location_assignment PIN_A6 -to ddr3_dq[3]
set_location_assignment PIN_A3 -to ddr3_dq[4]
set_location_assignment PIN_A4 -to ddr3_dq[5]
set_location_assignment PIN_L16 -to ddr3_dq[6]
set_location_assignment PIN_B3 -to ddr3_dq[7]
set_location_assignment PIN_D13 -to ddr3_dq[8]
set_location_assignment PIN_F13 -to ddr3_dq[9]
set_location_assignment PIN_A2 -to ddr3_dq[10]
set_location_assignment PIN_J15 -to ddr3_dq[11]
set_location_assignment PIN_D12 -to ddr3_dq[12]
set_location_assignment PIN_G15 -to ddr3_dq[13]
set_location_assignment PIN_B4 -to ddr3_dq[14]
set_location_assignment PIN_G13 -to ddr3_dq[15]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n
set_location_assignment PIN_F15 -to ddr3_dqs_n[0]
set_location_assignment PIN_E12 -to ddr3_dqs_n[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p
set_location_assignment PIN_G14 -to ddr3_dqs_p[0]
set_location_assignment PIN_F12 -to ddr3_dqs_p[1]
set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_odt
set_location_assignment PIN_E16 -to ddr3_odt
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_rasn
set_location_assignment PIN_A13 -to ddr3_rasn
set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_resetn
set_location_assignment PIN_G18 -to ddr3_resetn
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_wen
set_location_assignment PIN_A15 -to ddr3_wen
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_gtx_clk
set_location_assignment PIN_D25 -to enet_gtx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_intn
set_location_assignment PIN_D18 -to enet_intn
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_mdc
set_location_assignment PIN_K20 -to enet_mdc
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_mdio
set_location_assignment PIN_N20 -to enet_mdio
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_resetn
set_location_assignment PIN_M20 -to enet_resetn
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_clk
set_location_assignment PIN_V6 -to enet_rx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d
set_location_assignment PIN_E21 -to enet_rx_d[0]
set_location_assignment PIN_E24 -to enet_rx_d[1]
set_location_assignment PIN_E22 -to enet_rx_d[2]
set_location_assignment PIN_F24 -to enet_rx_d[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_dv
set_location_assignment PIN_D17 -to enet_rx_dv
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d
set_location_assignment PIN_J20 -to enet_tx_d[0]
set_location_assignment PIN_C25 -to enet_tx_d[1]
set_location_assignment PIN_G22 -to enet_tx_d[2]
set_location_assignment PIN_G21 -to enet_tx_d[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_en
set_location_assignment PIN_G20 -to enet_tx_en
set_instance_assignment -name IO_STANDARD "2.5 V" -to flash_advn
set_location_assignment PIN_T4 -to flash_advn
set_instance_assignment -name IO_STANDARD "2.5 V" -to flash_cen
set_location_assignment PIN_M3 -to flash_cen
set_instance_assignment -name IO_STANDARD "2.5 V" -to flash_clk
set_location_assignment PIN_N4 -to flash_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to flash_oen
set_location_assignment PIN_K5 -to flash_oen
set_instance_assignment -name IO_STANDARD "2.5 V" -to flash_rdybsyn
set_location_assignment PIN_R3 -to flash_rdybsyn
set_instance_assignment -name IO_STANDARD "2.5 V" -to flash_resetn
set_location_assignment PIN_N3 -to flash_resetn
set_instance_assignment -name IO_STANDARD "2.5 V" -to flash_wen
set_location_assignment PIN_C7 -to flash_wen
set_instance_assignment -name IO_STANDARD "2.5 V" -to fsm_a
set_location_assignment PIN_M21 -to fsm_a[0]
set_location_assignment PIN_J3 -to fsm_a[1]
set_location_assignment PIN_D29 -to fsm_a[2]
set_location_assignment PIN_J21 -to fsm_a[3]
set_location_assignment PIN_L13 -to fsm_a[4]
set_location_assignment PIN_C8 -to fsm_a[5]
set_location_assignment PIN_N9 -to fsm_a[6]
set_location_assignment PIN_D20 -to fsm_a[7]
set_location_assignment PIN_A23 -to fsm_a[8]
set_location_assignment PIN_B24 -to fsm_a[9]
set_location_assignment PIN_C24 -to fsm_a[10]
set_location_assignment PIN_E25 -to fsm_a[11]
set_location_assignment PIN_F21 -to fsm_a[12]
set_location_assignment PIN_J19 -to fsm_a[13]
set_location_assignment PIN_H19 -to fsm_a[14]
set_location_assignment PIN_K21 -to fsm_a[15]
set_location_assignment PIN_L21 -to fsm_a[16]
set_location_assignment PIN_F25 -to fsm_a[17]
set_location_assignment PIN_F26 -to fsm_a[18]
set_location_assignment PIN_G23 -to fsm_a[19]
set_location_assignment PIN_H21 -to fsm_a[20]
set_location_assignment PIN_M13 -to fsm_a[21]
set_location_assignment PIN_P7 -to fsm_a[22]
set_location_assignment PIN_F10 -to fsm_a[23]
set_location_assignment PIN_R4 -to fsm_a[24]
set_location_assignment PIN_K4 -to fsm_a[25]
set_instance_assignment -name IO_STANDARD "2.5 V" -to fsm_d
set_location_assignment PIN_A19 -to fsm_d[0]
set_location_assignment PIN_C18 -to fsm_d[1]
set_location_assignment PIN_D28 -to fsm_d[2]
set_location_assignment PIN_B19 -to fsm_d[3]
set_location_assignment PIN_E19 -to fsm_d[4]
set_location_assignment PIN_E18 -to fsm_d[5]
set_location_assignment PIN_G19 -to fsm_d[6]
set_location_assignment PIN_F19 -to fsm_d[7]
set_location_assignment PIN_D21 -to fsm_d[8]
set_location_assignment PIN_D23 -to fsm_d[9]
set_location_assignment PIN_D24 -to fsm_d[10]
set_location_assignment PIN_A25 -to fsm_d[11]
set_location_assignment PIN_B25 -to fsm_d[12]
set_location_assignment PIN_A26 -to fsm_d[13]
set_location_assignment PIN_C26 -to fsm_d[14]
set_location_assignment PIN_A27 -to fsm_d[15]
set_location_assignment PIN_R9 -to fsm_d[16]
set_location_assignment PIN_R10 -to fsm_d[17]
set_location_assignment PIN_R8 -to fsm_d[18]
set_location_assignment PIN_A17 -to fsm_d[19]
set_location_assignment PIN_D22 -to fsm_d[20]
set_location_assignment PIN_T10 -to fsm_d[21]
set_location_assignment PIN_P4 -to fsm_d[22]
set_location_assignment PIN_R11 -to fsm_d[23]
set_location_assignment PIN_A18 -to fsm_d[24]
set_location_assignment PIN_B18 -to fsm_d[25]
set_location_assignment PIN_C19 -to fsm_d[26]
set_location_assignment PIN_D19 -to fsm_d[27]
set_location_assignment PIN_B21 -to fsm_d[28]
set_location_assignment PIN_A21 -to fsm_d[29]
set_location_assignment PIN_C21 -to fsm_d[30]
set_location_assignment PIN_A22 -to fsm_d[31]
set_instance_assignment -name IO_STANDARD "1.8 V" -to hsma_clk_in0
set_location_assignment PIN_AP17 -to hsma_clk_in0
set_instance_assignment -name IO_STANDARD LVDS -to hsma_clk_in_p1
set_location_assignment PIN_U6 -to hsma_clk_in_p1
set_location_assignment PIN_U5 -to "hsma_clk_in_p1(n)"
set_instance_assignment -name IO_STANDARD LVDS -to hsma_clk_in_p2
set_location_assignment PIN_K18 -to hsma_clk_in_p2
set_location_assignment PIN_J18 -to "hsma_clk_in_p2(n)"
set_instance_assignment -name IO_STANDARD "2.5 V" -to hsma_clk_out0
set_location_assignment PIN_P10 -to hsma_clk_out0
set_instance_assignment -name IO_STANDARD LVDS -to hsma_clk_out_p1
set_location_assignment PIN_AD7 -to hsma_clk_out_p1
set_location_assignment PIN_AD6 -to "hsma_clk_out_p1(n)"
set_instance_assignment -name IO_STANDARD LVDS -to hsma_clk_out_p2
set_location_assignment PIN_V12 -to hsma_clk_out_p2
set_location_assignment PIN_W12 -to "hsma_clk_out_p2(n)"
set_instance_assignment -name IO_STANDARD "2.5 V" -to hsma_d
set_location_assignment PIN_L1 -to hsma_d[0]
set_location_assignment PIN_R6 -to hsma_d[1]
set_location_assignment PIN_K1 -to hsma_d[2]
set_location_assignment PIN_M1 -to hsma_d[3]
set_location_assignment PIN_U3 -to hsma_prsntn
set_instance_assignment -name IO_STANDARD LVDS -to hsma_rx_d_p
set_location_assignment PIN_AC5 -to hsma_rx_d_p[0]
set_location_assignment PIN_AC4 -to "hsma_rx_d_p[0](n)"
set_location_assignment PIN_AE4 -to hsma_rx_d_p[1]
set_location_assignment PIN_AF4 -to "hsma_rx_d_p[1](n)"
set_location_assignment PIN_AF1 -to hsma_rx_d_p[2]
set_location_assignment PIN_AG1 -to "hsma_rx_d_p[2](n)"
set_location_assignment PIN_AE2 -to hsma_rx_d_p[3]
set_location_assignment PIN_AE1 -to "hsma_rx_d_p[3](n)"
set_location_assignment PIN_AC1 -to hsma_rx_d_p[4]
set_location_assignment PIN_AD1 -to "hsma_rx_d_p[4](n)"
set_location_assignment PIN_AB2 -to hsma_rx_d_p[5]
set_location_assignment PIN_AB1 -to "hsma_rx_d_p[5](n)"
set_location_assignment PIN_Y1 -to hsma_rx_d_p[6]
set_location_assignment PIN_AA1 -to "hsma_rx_d_p[6](n)"
set_location_assignment PIN_Y2 -to hsma_rx_d_p[7]
set_location_assignment PIN_W1 -to "hsma_rx_d_p[7](n)"
set_location_assignment PIN_V2 -to hsma_rx_d_p[8]
set_location_assignment PIN_V1 -to "hsma_rx_d_p[8](n)"
set_location_assignment PIN_W4 -to hsma_rx_d_p[9]
set_location_assignment PIN_W3 -to "hsma_rx_d_p[9](n)"
set_location_assignment PIN_U2 -to hsma_rx_d_p[10]
set_location_assignment PIN_U1 -to "hsma_rx_d_p[10](n)"
set_location_assignment PIN_Y4 -to hsma_rx_d_p[11]
set_location_assignment PIN_Y3 -to "hsma_rx_d_p[11](n)"
set_location_assignment PIN_AB4 -to hsma_rx_d_p[12]
set_location_assignment PIN_AB3 -to "hsma_rx_d_p[12](n)"
set_location_assignment PIN_AB6 -to hsma_rx_d_p[13]
set_location_assignment PIN_AB5 -to "hsma_rx_d_p[13](n)"
set_location_assignment PIN_U7 -to hsma_rx_d_p[14]
set_location_assignment PIN_V7 -to "hsma_rx_d_p[14](n)"
set_location_assignment PIN_AB8 -to hsma_rx_d_p[15]
set_location_assignment PIN_AB7 -to "hsma_rx_d_p[15](n)"
set_location_assignment PIN_AC7 -to hsma_rx_d_p[16]
set_location_assignment PIN_AC6 -to "hsma_rx_d_p[16](n)"
set_instance_assignment -name IO_STANDARD "2.5 V" -to hsma_rx_led
set_location_assignment PIN_N5 -to hsma_rx_led
set_location_assignment PIN_U34 -to hsma_rx_n[0]
set_location_assignment PIN_R34 -to hsma_rx_n[1]
set_location_assignment PIN_N34 -to hsma_rx_n[2]
set_location_assignment PIN_L34 -to hsma_rx_n[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsma_rx_p
set_location_assignment PIN_U33 -to hsma_rx_p[0]
set_location_assignment PIN_R33 -to hsma_rx_p[1]
set_location_assignment PIN_N33 -to hsma_rx_p[2]
set_location_assignment PIN_L33 -to hsma_rx_p[3]
set_location_assignment PIN_T1 -to hsma_scl
set_location_assignment PIN_R1 -to hsma_sda
set_instance_assignment -name IO_STANDARD LVDS -to hsma_tx_d_p
set_location_assignment PIN_AA10 -to hsma_tx_d_p[0]
set_location_assignment PIN_AA9 -to "hsma_tx_d_p[0](n)"
set_location_assignment PIN_Y11 -to hsma_tx_d_p[1]
set_location_assignment PIN_Y10 -to "hsma_tx_d_p[1](n)"
set_location_assignment PIN_AH2 -to hsma_tx_d_p[2]
set_location_assignment PIN_AH1 -to "hsma_tx_d_p[2](n)"
set_location_assignment PIN_AB10 -to hsma_tx_d_p[3]
set_location_assignment PIN_AB9 -to "hsma_tx_d_p[3](n)"
set_location_assignment PIN_Y8 -to hsma_tx_d_p[4]
set_location_assignment PIN_Y7 -to "hsma_tx_d_p[4](n)"
set_location_assignment PIN_AF3 -to hsma_tx_d_p[5]
set_location_assignment PIN_AF2 -to "hsma_tx_d_p[5](n)"
set_location_assignment PIN_AD4 -to hsma_tx_d_p[6]
set_location_assignment PIN_AE3 -to "hsma_tx_d_p[6](n)"
set_location_assignment PIN_V4 -to hsma_tx_d_p[7]
set_location_assignment PIN_V3 -to "hsma_tx_d_p[7](n)"
set_location_assignment PIN_AA7 -to hsma_tx_d_p[8]
set_location_assignment PIN_Y6 -to "hsma_tx_d_p[8](n)"
set_location_assignment PIN_W7 -to hsma_tx_d_p[9]
set_location_assignment PIN_W6 -to "hsma_tx_d_p[9](n)"
set_location_assignment PIN_Y5 -to hsma_tx_d_p[10]
set_location_assignment PIN_AA4 -to "hsma_tx_d_p[10](n)"
set_location_assignment PIN_AC3 -to hsma_tx_d_p[11]
set_location_assignment PIN_AC2 -to "hsma_tx_d_p[11](n)"
set_location_assignment PIN_W10 -to hsma_tx_d_p[12]
set_location_assignment PIN_Y9 -to "hsma_tx_d_p[12](n)"
set_location_assignment PIN_R7 -to hsma_tx_d_p[13]
set_location_assignment PIN_T7 -to "hsma_tx_d_p[13](n)"
set_location_assignment PIN_R2 -to hsma_tx_d_p[14]
set_location_assignment PIN_P1 -to "hsma_tx_d_p[14](n)"
set_location_assignment PIN_V11 -to hsma_tx_d_p[15]
set_location_assignment PIN_V10 -to "hsma_tx_d_p[15](n)"
set_location_assignment PIN_U11 -to hsma_tx_d_p[16]
set_location_assignment PIN_U10 -to "hsma_tx_d_p[16](n)"
set_instance_assignment -name IO_STANDARD "2.5 V" -to hsma_tx_led
set_location_assignment PIN_C29 -to hsma_tx_led
set_location_assignment PIN_T32 -to hsma_tx_n[0]
set_location_assignment PIN_P32 -to hsma_tx_n[1]
set_location_assignment PIN_M32 -to hsma_tx_n[2]
set_location_assignment PIN_K32 -to hsma_tx_n[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsma_tx_p
set_location_assignment PIN_T31 -to hsma_tx_p[0]
set_location_assignment PIN_P31 -to hsma_tx_p[1]
set_location_assignment PIN_M31 -to hsma_tx_p[2]
set_location_assignment PIN_K31 -to hsma_tx_p[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to hsmb_clk_in0
set_location_assignment PIN_AP16 -to hsmb_clk_in0
set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmb_clk_out0
set_instance_assignment -name IO_STANDARD LVDS -to hsmb_clk_out_p1
set_instance_assignment -name IO_STANDARD LVDS -to hsmb_clk_out_p2
set_instance_assignment -name IO_STANDARD "2.5 V" -to hsmb_d
set_instance_assignment -name IO_STANDARD LVDS -to hsmb_rx_d_p
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmb_rx_p
set_instance_assignment -name IO_STANDARD LVDS -to hsmb_tx_d_p
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hsmb_tx_p
set_instance_assignment -name IO_STANDARD "2.5 V" -to lcd_csn
set_location_assignment PIN_J2 -to lcd_csn
set_instance_assignment -name IO_STANDARD "2.5 V" -to lcd_d_cn
set_location_assignment PIN_J1 -to lcd_d_cn
set_instance_assignment -name IO_STANDARD "2.5 V" -to lcd_data
set_location_assignment PIN_F1 -to lcd_data[0]
set_location_assignment PIN_H3 -to lcd_data[1]
set_location_assignment PIN_E1 -to lcd_data[2]
set_location_assignment PIN_F2 -to lcd_data[3]
set_location_assignment PIN_D2 -to lcd_data[4]
set_location_assignment PIN_D1 -to lcd_data[5]
set_location_assignment PIN_C2 -to lcd_data[6]
set_location_assignment PIN_C1 -to lcd_data[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to lcd_wen
set_location_assignment PIN_H1 -to lcd_wen
set_instance_assignment -name IO_STANDARD "2.5 V" -to max2_ben
set_location_assignment PIN_C15 -to max2_ben[0]
set_location_assignment PIN_H16 -to max2_ben[1]
set_location_assignment PIN_D14 -to max2_ben[2]
set_location_assignment PIN_A9 -to max2_ben[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to max2_clk
set_location_assignment PIN_J14 -to max2_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to max2_csn
set_location_assignment PIN_A16 -to max2_csn
set_instance_assignment -name IO_STANDARD "2.5 V" -to max2_oen
set_location_assignment PIN_A14 -to max2_oen
set_instance_assignment -name IO_STANDARD "2.5 V" -to max2_wen
set_location_assignment PIN_B16 -to max2_wen
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_led_g2
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_led_x1
set_location_assignment PIN_C28 -to pcie_led_x1
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_led_x4
set_location_assignment PIN_D26 -to pcie_led_x4
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_led_x8
set_location_assignment PIN_C27 -to pcie_led_x8
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_perstn
set_location_assignment PIN_N1 -to pcie_perstn
set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_p
set_location_assignment PIN_AE29 -to pcie_refclk_p
set_location_assignment PIN_AE30 -to "pcie_refclk_p(n)" -disable
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_n -disable
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_p
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to pcie_rx_p -disable
set_location_assignment PIN_AN33 -to pcie_rx_p[0]
set_location_assignment PIN_AN34 -to "pcie_rx_p[0](n)" -disable
set_location_assignment PIN_AL33 -to pcie_rx_p[1]
set_location_assignment PIN_AL34 -to "pcie_rx_p[1](n)" -disable
set_location_assignment PIN_AJ33 -to pcie_rx_p[2]
set_location_assignment PIN_AJ34 -to "pcie_rx_p[2](n)" -disable
set_location_assignment PIN_AG33 -to pcie_rx_p[3]
set_location_assignment PIN_AG34 -to "pcie_rx_p[3](n)" -disable
set_location_assignment PIN_AE33 -to pcie_rx_p[4]
set_location_assignment PIN_AE34 -to "pcie_rx_p[4](n)" -disable
set_location_assignment PIN_AC33 -to pcie_rx_p[5]
set_location_assignment PIN_AC34 -to "pcie_rx_p[5](n)" -disable
set_location_assignment PIN_AA33 -to pcie_rx_p[6]
set_location_assignment PIN_AA34 -to "pcie_rx_p[6](n)" -disable
set_location_assignment PIN_W33 -to pcie_rx_p[7]
set_location_assignment PIN_W34 -to "pcie_rx_p[7](n)" -disable
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_smbclk
set_location_assignment PIN_M18 -to pcie_smbclk
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_smbdat
set_location_assignment PIN_D27 -to pcie_smbdat
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_n -disable
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_p
set_location_assignment PIN_AM31 -to pcie_tx_p[0]
set_location_assignment PIN_AM32 -to "pcie_tx_p[0](n)" -disable
set_location_assignment PIN_AK31 -to pcie_tx_p[1]
set_location_assignment PIN_AK32 -to "pcie_tx_p[1](n)" -disable
set_location_assignment PIN_AH31 -to pcie_tx_p[2]
set_location_assignment PIN_AH32 -to "pcie_tx_p[2](n)" -disable
set_location_assignment PIN_AF31 -to pcie_tx_p[3]
set_location_assignment PIN_AF32 -to "pcie_tx_p[3](n)" -disable
set_location_assignment PIN_AD31 -to pcie_tx_p[4]
set_location_assignment PIN_AD32 -to "pcie_tx_p[4](n)" -disable
set_location_assignment PIN_AB31 -to pcie_tx_p[5]
set_location_assignment PIN_AB32 -to "pcie_tx_p[5](n)" -disable
set_location_assignment PIN_Y31 -to pcie_tx_p[6]
set_location_assignment PIN_Y32 -to "pcie_tx_p[6](n)" -disable
set_location_assignment PIN_V31 -to pcie_tx_p[7]
set_location_assignment PIN_V32 -to "pcie_tx_p[7](n)" -disable
set_instance_assignment -name IO_STANDARD "2.5 V" -to pcie_waken
set_location_assignment PIN_C30 -to pcie_waken
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_adscn
set_location_assignment PIN_C10 -to sram_adscn
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_adspn
set_location_assignment PIN_A20 -to sram_adspn
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_advn
set_location_assignment PIN_D9 -to sram_advn
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_bwen
set_location_assignment PIN_J11 -to sram_bwen
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_bwn
set_location_assignment PIN_J13 -to sram_bwn[0]
set_location_assignment PIN_H12 -to sram_bwn[1]
set_location_assignment PIN_E9 -to sram_bwn[2]
set_location_assignment PIN_H13 -to sram_bwn[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_cen
set_location_assignment PIN_E10 -to sram_cen
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_clk
set_location_assignment PIN_J12 -to sram_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_dqp
set_location_assignment PIN_A24 -to sram_dqp[0]
set_location_assignment PIN_B22 -to sram_dqp[1]
set_location_assignment PIN_P9 -to sram_dqp[2]
set_location_assignment PIN_C22 -to sram_dqp[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_gwn
set_location_assignment PIN_K12 -to sram_gwn
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_oen
set_location_assignment PIN_D10 -to sram_oen
set_instance_assignment -name IO_STANDARD "2.5 V" -to sram_zz
set_location_assignment PIN_B27 -to sram_zz
set_instance_assignment -name IO_STANDARD "1.5 V" -to termination_blk0~_rdn_pad
set_instance_assignment -name IO_STANDARD "1.5 V" -to termination_blk0~_rup_pad
set_instance_assignment -name IO_STANDARD "1.8 V" -to termination_blk1~_rdn_pad
set_location_assignment PIN_AL27 -to termination_blk1~_rdn_pad
set_instance_assignment -name IO_STANDARD "1.8 V" -to termination_blk1~_rup_pad
set_location_assignment PIN_AL26 -to termination_blk1~_rup_pad
set_instance_assignment -name IO_STANDARD "2.5 V" -to termination_blk2~_rdn_pad
set_instance_assignment -name IO_STANDARD "2.5 V" -to termination_blk2~_rup_pad
set_instance_assignment -name IO_STANDARD "2.5 V" -to user_dipsw
set_location_assignment PIN_N2 -to user_dipsw[0]
set_location_assignment PIN_U9 -to user_dipsw[1]
set_location_assignment PIN_V9 -to user_dipsw[2]
set_location_assignment PIN_U4 -to user_dipsw[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to user_led
set_location_assignment PIN_G1 -to user_led[0]
set_location_assignment PIN_J4 -to user_led[1]
set_location_assignment PIN_J5 -to user_led[2]
set_location_assignment PIN_R5 -to user_led[3]
set_location_assignment PIN_AL7 -to user_pb[1]
set_location_assignment PIN_N6 -to ~ALTERA_DATA1~
set_location_assignment PIN_G2 -to ~ALTERA_DATA2~
set_location_assignment PIN_P6 -to ~ALTERA_DATA3~
set_location_assignment PIN_L4 -to ~ALTERA_DATA4~
set_location_assignment PIN_K3 -to ~ALTERA_DATA5~
set_location_assignment PIN_M4 -to ~ALTERA_DATA6~
set_location_assignment PIN_K2 -to ~ALTERA_DATA7~
set_location_assignment PIN_AP26 -to ~ALTERA_nCEO~
set_location_assignment PIN_AJ10 -to ddr2_dimm_odt
set_global_assignment -name MISC_FILE "D:/fpga/arria_II_gx_board/arria_II_gx_ddr2_test_3/ddr2_sodimm.dpf"
set_location_assignment PIN_AA30 -to clkin_ref_q1_1_n
set_location_assignment PIN_W30 -to clkin_ref_q1_2_n
set_location_assignment PIN_U30 -to clkin_ref_q2_n
set_location_assignment PIN_U29 -to clkin_ref_q3_n
set_location_assignment PIN_AL6 -to ddr2_dimm_clk_n[1]
set_location_assignment PIN_AK6 -to ddr2_dimm_clk[1]
set_location_assignment PIN_AP8 -to ddr2_dimm_cke
set_location_assignment PIN_AM13 -to ddr2_dimm_cs_n
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_clk[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_clk[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_clk_n[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_clk_n[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_addr[13]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_ba[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[14]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[15]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[16]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[17]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[18]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[19]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[20]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[21]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[22]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[23]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[24]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[25]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[26]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[27]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[28]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[29]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[30]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[31]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[32]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[33]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[34]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[35]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[36]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[37]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[38]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[39]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[40]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[41]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[42]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[43]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[44]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[45]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[46]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[47]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[48]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[49]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[50]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[51]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[52]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[53]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[54]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[55]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[56]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[57]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[58]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[59]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[60]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[61]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[62]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dq[63]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs[7]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs_n[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs_n[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs_n[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs_n[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs_n[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs_n[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs_n[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I" -to ddr2_dimm_dqs_n[7]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dm[2]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dm[3]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dm[4]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dm[5]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dm[6]
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to ddr2_dimm_dm[7]
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name MISC_FILE "D:/svn/koski/trunk/lib/hw_lib/ips/memories/memory_to_hibi_r2/ts/a2gx_m2h2/ddr2_sodimm.dpf"
set_location_assignment PIN_AL8 -to ddr2_dimm_cas_n
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name AUTO_RAM_RECOGNITION ON
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_we_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_we_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_we_n
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_we_n
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_we_n
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_we_n
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_we_n
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_we_n
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_we_n
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[12]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[11]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[10]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[9]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[8]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[7]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[6]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[5]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[4]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[3]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[2]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[1]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[0]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_ba[2]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_ba[1]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_ba[0]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_cas_n
set_instance_assignment -name BOARD_MODEL_FAR_C 0.25P -to mem_cke[0]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_odt[0]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_ras_n
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_reset_n
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_we_n
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.599 -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_FAR_C 0.25P -to mem_cs_n[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 2.614 -to mem_clk[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.66N -to mem_clk[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 3.74P -to mem_clk[0]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_clk[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 1.017 -to mem_clk[0]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_clk[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_clk[0]
set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R 200 -to mem_clk[0]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_clk[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.616 -to mem_clk[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.66N -to mem_clk[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 3.74P -to mem_clk[1]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_clk[1]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 1.020 -to mem_clk[1]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_clk[1]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_clk[1]
set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R 200 -to mem_clk[1]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_clk[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dm[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dm[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dm[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dm[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.457 -to mem_dm[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dm[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dm[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dm[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dq[63]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dq[62]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dq[61]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dq[60]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dq[59]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dq[58]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dq[57]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dq[56]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dq[55]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dq[54]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dq[53]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dq[52]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dq[51]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dq[50]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dq[49]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dq[48]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dq[47]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dq[46]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dq[45]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dq[44]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dq[43]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dq[42]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dq[41]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dq[40]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dq[39]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dq[38]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dq[37]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dq[36]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dq[35]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dq[34]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dq[33]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dq[32]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.457 -to mem_dq[31]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.457 -to mem_dq[30]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.457 -to mem_dq[29]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.457 -to mem_dq[28]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.457 -to mem_dq[27]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.457 -to mem_dq[26]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.457 -to mem_dq[25]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dq[24]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dq[23]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dq[22]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dq[21]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dq[20]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dq[19]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dq[18]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dq[17]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dq[16]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dq[15]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dq[14]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dq[13]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dq[12]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dq[11]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dq[10]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dq[9]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dq[8]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dq[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dq[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dq[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dq[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dq[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dq[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dq[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dq[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dm[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dm[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dm[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dm[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dm[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dm[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dm[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dm[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[63]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[62]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[61]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[60]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[59]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[58]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[57]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[56]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[55]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[54]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[53]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[52]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[51]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[50]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[49]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[48]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[47]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[46]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[45]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[44]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[43]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[42]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[41]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[40]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[39]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[38]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[37]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[36]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[35]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[34]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[33]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[32]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[31]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[30]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[29]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[28]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[27]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[26]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[25]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[24]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[23]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[22]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[21]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[20]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[19]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[18]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[17]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[16]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[15]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[14]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[13]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[12]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[11]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[10]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[9]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[8]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dq[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dm[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dm[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dm[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dm[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dm[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dm[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dm[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dm[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[63]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[62]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[61]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[60]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[59]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[58]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[57]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[56]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[55]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[54]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[53]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[52]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[51]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[50]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[49]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[48]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[47]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[46]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[45]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[44]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[43]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[42]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[41]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[40]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[39]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[38]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[37]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[36]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[35]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[34]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[33]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[32]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[31]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[30]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[29]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[28]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[27]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[26]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[25]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[24]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[23]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[22]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[21]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[20]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[19]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[18]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[17]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[16]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[15]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[14]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[13]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[12]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[11]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[10]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[9]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[8]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dq[0]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dm[7]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dm[6]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dm[5]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dm[4]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dm[3]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dm[2]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dm[1]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dm[0]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[63]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[62]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[61]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[60]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[59]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[58]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[57]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[56]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[55]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[54]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[53]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[52]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[51]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[50]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[49]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[48]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[47]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[46]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[45]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[44]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[43]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[42]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[41]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[40]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[39]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[38]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[37]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[36]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[35]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[34]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[33]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[32]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[31]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[30]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[29]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[28]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[27]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[26]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[25]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[24]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[23]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[22]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[21]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[20]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[19]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[18]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[17]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[16]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[15]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[14]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[13]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[12]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[11]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[10]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[9]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[8]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[7]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[6]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[5]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[4]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[3]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[2]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[1]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_dq[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dm[7]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dm[6]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dm[5]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dm[4]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dm[3]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dm[2]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dm[1]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dm[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dq[63]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dq[62]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dq[61]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dq[60]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dq[59]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dq[58]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dq[57]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dq[56]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dq[55]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dq[54]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dq[53]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dq[52]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dq[51]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dq[50]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dq[49]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dq[48]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dq[47]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dq[46]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dq[45]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dq[44]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dq[43]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dq[42]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dq[41]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dq[40]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dq[39]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dq[38]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dq[37]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dq[36]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dq[35]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dq[34]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dq[33]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dq[32]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dq[31]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dq[30]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dq[29]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dq[28]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dq[27]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dq[26]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dq[25]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dq[24]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dq[23]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dq[22]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dq[21]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dq[20]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dq[19]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dq[18]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dq[17]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dq[16]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dq[15]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dq[14]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dq[13]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dq[12]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dq[11]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dq[10]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dq[9]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dq[8]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dq[7]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dq[6]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dq[5]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dq[4]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dq[3]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dq[2]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dq[1]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dq[0]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dm[7]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dm[6]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dm[5]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dm[4]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dm[3]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dm[2]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dm[1]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dm[0]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[63]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[62]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[61]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[60]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[59]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[58]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[57]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[56]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[55]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[54]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[53]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[52]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[51]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[50]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[49]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[48]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[47]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[46]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[45]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[44]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[43]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[42]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[41]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[40]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[39]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[38]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[37]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[36]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[35]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[34]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[33]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[32]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[31]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[30]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[29]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[28]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[27]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[26]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[25]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[24]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[23]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[22]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[21]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[20]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[19]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[18]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[17]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[16]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[15]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[14]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[13]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[12]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[11]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[10]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[9]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[8]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[7]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[6]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[5]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[4]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[3]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[2]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[1]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dq[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dm[7]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dm[6]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dm[5]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dm[4]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dm[3]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dm[2]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dm[1]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dm[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[63]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[62]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[61]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[60]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[59]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[58]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[57]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[56]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[55]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[54]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[53]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[52]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[51]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[50]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[49]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[48]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[47]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[46]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[45]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[44]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[43]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[42]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[41]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[40]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[39]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[38]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[37]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[36]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[35]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[34]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[33]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[32]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[31]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[30]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[29]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[28]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[27]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[26]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[25]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[24]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[23]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[22]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[21]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[20]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[19]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[18]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[17]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[16]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[15]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[14]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[13]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[12]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[11]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[10]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[9]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[8]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[7]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[6]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[5]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[4]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[3]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[2]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[1]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dq[0]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dm[7]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dm[6]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dm[5]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dm[4]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dm[3]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dm[2]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dm[1]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dm[0]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[63]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[62]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[61]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[60]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[59]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[58]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[57]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[56]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[55]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[54]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[53]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[52]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[51]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[50]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[49]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[48]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[47]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[46]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[45]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[44]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[43]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[42]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[41]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[40]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[39]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[38]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[37]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[36]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[35]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[34]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[33]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[32]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[31]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[30]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[29]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[28]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[27]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[26]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[25]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[24]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[23]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[22]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[21]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[20]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[19]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[18]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[17]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[16]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[15]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[14]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[13]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[12]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[11]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[10]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[9]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[8]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[7]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[6]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[5]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[4]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[3]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[2]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[1]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dq[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.831 -to mem_dqs[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.677 -to mem_dqs[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.548 -to mem_dqs[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.450 -to mem_dqs[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.457 -to mem_dqs[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.437 -to mem_dqs[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.757 -to mem_dqs[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.866 -to mem_dqs[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dqs[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dqs[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dqs[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dqs[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dqs[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dqs[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dqs[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8N -to mem_dqs[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dqs[7]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dqs[6]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dqs[5]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dqs[4]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dqs[3]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dqs[2]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dqs[1]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_dqs[0]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 22 -to mem_dqs[7]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 22 -to mem_dqs[6]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 22 -to mem_dqs[5]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 22 -to mem_dqs[4]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 22 -to mem_dqs[3]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 22 -to mem_dqs[2]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 22 -to mem_dqs[1]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 22 -to mem_dqs[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.666 -to mem_dqs[7]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.665 -to mem_dqs[6]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.667 -to mem_dqs[5]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.749 -to mem_dqs[4]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.761 -to mem_dqs[3]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.741 -to mem_dqs[2]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.661 -to mem_dqs[1]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.637 -to mem_dqs[0]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dqs[7]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dqs[6]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dqs[5]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dqs[4]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dqs[3]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dqs[2]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dqs[1]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_dqs[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dqs[7]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dqs[6]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dqs[5]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dqs[4]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dqs[3]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dqs[2]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dqs[1]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_dqs[0]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dqs[7]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dqs[6]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dqs[5]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dqs[4]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dqs[3]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dqs[2]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dqs[1]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_dqs[0]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dqs[7]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dqs[6]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dqs[5]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dqs[4]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dqs[3]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dqs[2]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dqs[1]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dqs[0]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dm[7]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dm[6]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dm[5]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dm[4]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dm[3]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dm[2]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dm[1]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dm[0]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[63]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[62]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[61]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[60]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[59]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[58]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[57]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[56]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[55]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[54]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[53]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[52]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[51]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[50]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[49]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[48]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[47]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[46]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[45]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[44]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[43]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[42]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[41]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[40]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[39]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[38]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[37]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[36]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[35]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[34]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[33]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[32]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[31]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[30]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[29]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[28]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[27]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[26]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[25]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[24]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[23]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[22]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[21]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[20]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[19]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[18]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[17]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[16]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[15]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[14]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[13]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[12]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[11]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[10]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[9]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[8]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[7]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[6]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[5]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[4]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[3]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[2]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[1]
set_instance_assignment -name BOARD_MODEL_FAR_C 4P -to mem_dq[0]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH 1.743 -to mem_addr[13]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 8.0N -to mem_addr[13]
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 4.04P -to mem_addr[13]
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R SHORT -to mem_addr[13]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 2.230 -to mem_addr[13]
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH 10.6N -to mem_addr[13]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH 3.06P -to mem_addr[13]
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R 56 -to mem_addr[13]
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R 3 -to mem_addr[13]
set_instance_assignment -name BOARD_MODEL_FAR_C 2P -to mem_addr[13]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_clk
set_instance_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER ON -to ddr2_dimm_clk[0]
set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to ddr2_dimm_clk[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_clk_n
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dm
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1383251936 -to ddr2_dimm_dm
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dm
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1383251936 -to ddr2_dimm_dq
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1383251936 -to ddr2_dimm_dqs
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs_n
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1383251936 -to ddr2_dimm_dqs_n
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs_n
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to cpu_resetn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_casn
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_ck_n
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_ck_p
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_csn
set_instance_assignment -name OUTPUT_ENABLE_GROUP 57199071 -to ddr3_dm
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm
set_instance_assignment -name OUTPUT_ENABLE_GROUP 57199071 -to ddr3_dq
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq
set_instance_assignment -name OUTPUT_ENABLE_GROUP 57199071 -to ddr3_dqs_n
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n
set_instance_assignment -name OUTPUT_ENABLE_GROUP 57199071 -to ddr3_dqs_p
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_rasn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_resetn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_wen
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to enet_intn
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to enet_mdc
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to enet_mdio
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to enet_resetn
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to flash_resetn
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to fsm_d[28]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hsma_clk_out0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to hsma_d
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to hsma_prsntn
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to hsma_rx_d_p
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to hsma_scl
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to hsma_sda
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to hsmb_prsntn
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to hsmb_scl
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to hsmb_sda
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to pcie_perstn -disable
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to pcie_smbclk
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to pcie_smbdat
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to pcie_waken
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to sram_zz
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_dipsw
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_clk[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_clk[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_clk_n[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_clk_n[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_addr[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_ba[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_ba[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_ba[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_ras_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_cas_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_we_n
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[8]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[9]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[10]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[11]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[12]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[13]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[14]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[15]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[16]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[17]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[18]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[19]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[20]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[21]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[22]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[23]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[24]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[25]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[26]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[27]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[28]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[29]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[30]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[31]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[32]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[33]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[34]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[35]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[36]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[37]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[38]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[39]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[40]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[41]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[42]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[43]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[44]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[45]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[46]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[47]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[48]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[49]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[50]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[51]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[52]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[53]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[54]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[55]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[56]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[57]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[58]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[59]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[60]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[61]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[62]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dq[63]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs_n[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs_n[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs_n[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs_n[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs_n[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs_n[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs_n[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dqs_n[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dm[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dm[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dm[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dm[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dm[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dm[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dm[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr2_dimm_dm[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[8]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[9]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[10]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[11]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[12]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[13]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[14]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[15]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[16]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[17]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[18]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[19]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[20]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[21]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[22]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[23]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[24]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[25]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[26]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[27]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[28]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[29]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[30]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[31]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[32]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[33]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[34]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[35]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[36]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[37]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[38]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[39]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[40]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[41]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[42]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[43]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[44]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[45]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[46]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[47]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[48]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[49]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[50]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[51]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[52]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[53]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[54]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[55]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[56]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[57]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[58]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[59]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[60]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[61]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[62]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dq[63]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[8]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[9]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[10]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[11]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[12]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[13]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[14]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[15]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[16]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[17]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[18]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[19]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[20]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[21]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[22]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[23]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[24]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[25]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[26]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[27]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[28]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[29]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[30]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[31]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[32]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[33]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[34]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[35]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[36]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[37]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[38]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[39]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[40]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[41]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[42]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[43]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[44]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[45]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[46]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[47]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[48]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[49]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[50]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[51]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[52]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[53]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[54]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[55]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[56]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[57]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[58]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[59]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[60]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[61]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[62]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dq[63]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs_n[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs_n[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs_n[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs_n[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs_n[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs_n[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs_n[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dqs_n[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs_n[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs_n[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs_n[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs_n[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs_n[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs_n[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs_n[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dqs_n[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dm[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dm[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dm[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dm[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dm[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dm[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dm[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr2_dimm_dm[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dm[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dm[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dm[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dm[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dm[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dm[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dm[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 321236355 -to ddr2_dimm_dm[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_odt
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_cs_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr2_dimm_cke
set_global_assignment -name MISC_FILE "D:/user/arvio/svn/funbase/shared_lib/hw_lib/ips/communication/pcie_to_hibi/ts/a2gx_pcie_to_hibi_/ddr2_sodimm.dpf"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_instance_assignment -name IO_STANDARD HCSL -to refclk
set_instance_assignment -name INPUT_TERMINATION OFF -to refclk
set_global_assignment -name MISC_FILE "D:/user/arvio/svn/funbase/shared_lib/hw_lib/ips/communication/pcie_to_hibi/ts/a2gx_pcie_to_hibi_2/ddr2_sodimm.dpf"
set_instance_assignment -name INPUT_TERMINATION OFF -to pcie_refclk_p
set_global_assignment -name MISC_FILE "D:/user/arvio/svn/funbase/shared_lib/hw_lib/ips/communication/pcie_to_hibi/ts/a2gx_pcie_to_hibi_3/ddr2_sodimm.dpf"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VHDL_FILE ../../hdl/pkt_buf.vhd
set_global_assignment -name VHDL_FILE ../../hdl/pcie_tx.vhd
set_global_assignment -name VHDL_FILE ../../hdl/pcie_to_hibi.vhd
set_global_assignment -name VHDL_FILE ../../hdl/pcie_rx.vhd
set_global_assignment -name VHDL_FILE ../../hdl/pcie_dma.vhd
set_global_assignment -name VHDL_FILE ../../hdl/hibi_if.vhd
set_global_assignment -name VHDL_FILE ../../hdl/buf_ptr_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../hdl/req_ctrl.vhd
set_global_assignment -name VHDL_FILE ../../hdl/multi_mutex.vhd
set_global_assignment -name VERILOG_FILE a2gx_dev_kit_golden_top.v
set_global_assignment -name VHDL_FILE ../../tb/pcie_to_hibi_test_app.vhd
set_global_assignment -name VHDL_FILE ../../tb/hibiv3_seg_r3.vhd
set_global_assignment -name QIP_FILE in_sys_sp.qip
set_global_assignment -name QIP_FILE test.qip
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/ddr2_sodimm.sdc
0,0 → 1,6
derive_pll_clocks
derive_clock_uncertainty
create_clock -period "100 MHz" -name {refclk} {refclk}
create_clock -period "125 MHz" -name {pcie_refclk_p} {pcie_refclk_p}
set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }]
set_clock_groups -exclusive -group [get_clocks { *ddr2_sodimm_x64_phy_inst* }] -group [get_clocks { *_hssi_pcie_hip* }]
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/a2_ddr2_dimm_1GB_pin_assignments.tcl
0,0 → 1,540
# -------------------------------------------------------------------------
#
# ALTMEMPHY v10.0 DDR2 SDRAM pin constraints script for a2_ddr2_dimm_1GB
#
# Please run this script before compiling your design
#
# Directions: If your top level pin names do not match the default names,
# you should change the variables below to make the constraints
# match the specific pin names in your top level design.
#
#
# Make your changes below this line
# --------------------------------------------------------------------------
 
# Change sopc_mode value from NO to YES to create assignments that match the
# SOPC Builder top level pin names
if {![info exists sopc_mode]} {set sopc_mode NO}
 
# This is the name of your controller instance
set instance_name ""
 
# This is the prefix for all pin names. Change it if you wish to choose
# a prefix other than mem_
if {![info exists pin_prefix]} {set pin_prefix "ddr2_dimm_"}
 
 
# In SOPC builder, the pin names will be expanded as follow:
# Example: mem_cs_n_from_the_<your instance name>
#
# In standalone mode, the pin names will be expanded as follow:
# Example: mem_cs_n[0]
 
set mem_odt_pin_name ${pin_prefix}odt
set mem_odt_CURRENT_STRENGTH_NEW "MAXIMUM CURRENT"
set mem_odt_IO_STANDARD "SSTL-18 CLASS I"
 
set mem_clk_pin_name ${pin_prefix}clk
set mem_clk_IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I"
set mem_clk_XSTL_INPUT_ALLOW_SE_BUFFER "ON"
set mem_clk_OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION"
set mem_clk_TREAT_BIDIR_AS_OUTPUT "ON"
 
set mem_clk_n_pin_name ${pin_prefix}clk_n
set mem_clk_n_IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I"
set mem_clk_n_OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION"
 
set mem_cs_n_pin_name ${pin_prefix}cs_n
set mem_cs_n_CURRENT_STRENGTH_NEW "MAXIMUM CURRENT"
set mem_cs_n_IO_STANDARD "SSTL-18 CLASS I"
 
set mem_cke_pin_name ${pin_prefix}cke
set mem_cke_CURRENT_STRENGTH_NEW "MAXIMUM CURRENT"
set mem_cke_IO_STANDARD "SSTL-18 CLASS I"
 
set mem_addr_pin_name ${pin_prefix}addr
set mem_addr_CURRENT_STRENGTH_NEW "MAXIMUM CURRENT"
set mem_addr_IO_STANDARD "SSTL-18 CLASS I"
 
set mem_ba_pin_name ${pin_prefix}ba
set mem_ba_CURRENT_STRENGTH_NEW "MAXIMUM CURRENT"
set mem_ba_IO_STANDARD "SSTL-18 CLASS I"
 
set mem_ras_n_pin_name ${pin_prefix}ras_n
set mem_ras_n_CURRENT_STRENGTH_NEW "MAXIMUM CURRENT"
set mem_ras_n_IO_STANDARD "SSTL-18 CLASS I"
 
set mem_cas_n_pin_name ${pin_prefix}cas_n
set mem_cas_n_CURRENT_STRENGTH_NEW "MAXIMUM CURRENT"
set mem_cas_n_IO_STANDARD "SSTL-18 CLASS I"
 
set mem_we_n_pin_name ${pin_prefix}we_n
set mem_we_n_CURRENT_STRENGTH_NEW "MAXIMUM CURRENT"
set mem_we_n_IO_STANDARD "SSTL-18 CLASS I"
 
set mem_dq_pin_name ${pin_prefix}dq
set mem_dq_IO_STANDARD "SSTL-18 CLASS I"
set mem_dq_OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION"
 
set mem_dqs_pin_name ${pin_prefix}dqs
set mem_dqs_IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I"
set mem_dqs_OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION"
 
set mem_dqsn_pin_name ${pin_prefix}dqs_n
set mem_dqsn_IO_STANDARD "DIFFERENTIAL 1.8-V SSTL CLASS I"
set mem_dqsn_OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION"
 
set mem_dm_pin_name ${pin_prefix}dm
set mem_dm_IO_STANDARD "SSTL-18 CLASS I"
set mem_dm_OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION"
 
 
# Do not make any changes after this line
# ------------------------------------------------
 
# This single_bit variable is to define whether a [0] index will be added at the end of a single-bit bus pin name
# To not have indexing, replace [0] by "".
set single_bit {[0]}
 
switch $sopc_mode {
YES {
set output_suffix _from_the_${instance_name}
set bidir_suffix _to_and_from_the_${instance_name}
set input_suffix _to_the_${instance_name}
}
default {
set output_suffix ""
set bidir_suffix ""
set input_suffix ""
}
}
 
set delay_chain_config "Flexible_timing"
 
if {![info exists ::ppl_instance_name]} {set ::ppl_instance_name {}}
 
set mem_odt_pin_name ${::ppl_instance_name}${mem_odt_pin_name}${output_suffix}
set mem_clk_pin_name ${::ppl_instance_name}${mem_clk_pin_name}${bidir_suffix}
set mem_clk_n_pin_name ${::ppl_instance_name}${mem_clk_n_pin_name}${bidir_suffix}
set mem_cs_n_pin_name ${::ppl_instance_name}${mem_cs_n_pin_name}${output_suffix}
set mem_cke_pin_name ${::ppl_instance_name}${mem_cke_pin_name}${output_suffix}
set mem_addr_pin_name ${::ppl_instance_name}${mem_addr_pin_name}${output_suffix}
set mem_ba_pin_name ${::ppl_instance_name}${mem_ba_pin_name}${output_suffix}
set mem_ras_n_pin_name ${::ppl_instance_name}${mem_ras_n_pin_name}${output_suffix}
set mem_cas_n_pin_name ${::ppl_instance_name}${mem_cas_n_pin_name}${output_suffix}
set mem_we_n_pin_name ${::ppl_instance_name}${mem_we_n_pin_name}${output_suffix}
set mem_dq_pin_name ${::ppl_instance_name}${mem_dq_pin_name}${bidir_suffix}
set mem_dqs_pin_name ${::ppl_instance_name}${mem_dqs_pin_name}${bidir_suffix}
set mem_dqsn_pin_name ${::ppl_instance_name}${mem_dqsn_pin_name}${bidir_suffix}
set mem_dm_pin_name ${::ppl_instance_name}${mem_dm_pin_name}${output_suffix}
 
set_instance_assignment -name IO_STANDARD "${mem_odt_IO_STANDARD}" -to ${mem_odt_pin_name}${single_bit}
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_odt_CURRENT_STRENGTH_NEW}" -to ${mem_odt_pin_name}${single_bit}
set_instance_assignment -name IO_STANDARD "${mem_clk_IO_STANDARD}" -to ${mem_clk_pin_name}[0]
set_instance_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER "${mem_clk_XSTL_INPUT_ALLOW_SE_BUFFER}" -to ${mem_clk_pin_name}[0]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_clk_OUTPUT_TERMINATION}" -to ${mem_clk_pin_name}[0]
set_instance_assignment -name IO_STANDARD "${mem_clk_IO_STANDARD}" -to ${mem_clk_pin_name}[1]
set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT "${mem_clk_TREAT_BIDIR_AS_OUTPUT}" -to ${mem_clk_pin_name}[1]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_clk_OUTPUT_TERMINATION}" -to ${mem_clk_pin_name}[1]
set_instance_assignment -name IO_STANDARD "${mem_clk_n_IO_STANDARD}" -to ${mem_clk_n_pin_name}[0]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_clk_n_OUTPUT_TERMINATION}" -to ${mem_clk_n_pin_name}[0]
set_instance_assignment -name IO_STANDARD "${mem_clk_n_IO_STANDARD}" -to ${mem_clk_n_pin_name}[1]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_clk_n_OUTPUT_TERMINATION}" -to ${mem_clk_n_pin_name}[1]
set_instance_assignment -name IO_STANDARD "${mem_cs_n_IO_STANDARD}" -to ${mem_cs_n_pin_name}${single_bit}
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_cs_n_CURRENT_STRENGTH_NEW}" -to ${mem_cs_n_pin_name}${single_bit}
set_instance_assignment -name IO_STANDARD "${mem_cke_IO_STANDARD}" -to ${mem_cke_pin_name}${single_bit}
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_cke_CURRENT_STRENGTH_NEW}" -to ${mem_cke_pin_name}${single_bit}
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[0]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[1]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[2]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[3]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[4]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[5]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[6]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[7]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[8]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[9]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[10]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[11]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[12]
set_instance_assignment -name IO_STANDARD "${mem_addr_IO_STANDARD}" -to ${mem_addr_pin_name}[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_addr_CURRENT_STRENGTH_NEW}" -to ${mem_addr_pin_name}[13]
set_instance_assignment -name IO_STANDARD "${mem_ba_IO_STANDARD}" -to ${mem_ba_pin_name}[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_ba_CURRENT_STRENGTH_NEW}" -to ${mem_ba_pin_name}[0]
set_instance_assignment -name IO_STANDARD "${mem_ba_IO_STANDARD}" -to ${mem_ba_pin_name}[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_ba_CURRENT_STRENGTH_NEW}" -to ${mem_ba_pin_name}[1]
set_instance_assignment -name IO_STANDARD "${mem_ba_IO_STANDARD}" -to ${mem_ba_pin_name}[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_ba_CURRENT_STRENGTH_NEW}" -to ${mem_ba_pin_name}[2]
set_instance_assignment -name IO_STANDARD "${mem_ras_n_IO_STANDARD}" -to ${mem_ras_n_pin_name}
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_ras_n_CURRENT_STRENGTH_NEW}" -to ${mem_ras_n_pin_name}
set_instance_assignment -name IO_STANDARD "${mem_cas_n_IO_STANDARD}" -to ${mem_cas_n_pin_name}
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_cas_n_CURRENT_STRENGTH_NEW}" -to ${mem_cas_n_pin_name}
set_instance_assignment -name IO_STANDARD "${mem_we_n_IO_STANDARD}" -to ${mem_we_n_pin_name}
set_instance_assignment -name CURRENT_STRENGTH_NEW "${mem_we_n_CURRENT_STRENGTH_NEW}" -to ${mem_we_n_pin_name}
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[0]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[0]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[1]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[1]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[2]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[2]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[3]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[3]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[4]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[4]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[5]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[5]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[6]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[6]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[7]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[7]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[8]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[8]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[9]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[9]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[10]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[10]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[11]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[11]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[12]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[12]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[13]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[13]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[14]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[14]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[15]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[15]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[16]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[16]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[17]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[17]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[18]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[18]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[19]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[19]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[20]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[20]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[21]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[21]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[22]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[22]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[23]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[23]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[24]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[24]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[25]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[25]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[26]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[26]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[27]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[27]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[28]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[28]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[29]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[29]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[30]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[30]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[31]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[31]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[32]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[32]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[33]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[33]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[34]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[34]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[35]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[35]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[36]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[36]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[37]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[37]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[38]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[38]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[39]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[39]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[40]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[40]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[41]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[41]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[42]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[42]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[43]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[43]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[44]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[44]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[45]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[45]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[46]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[46]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[47]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[47]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[48]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[48]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[49]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[49]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[50]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[50]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[51]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[51]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[52]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[52]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[53]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[53]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[54]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[54]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[55]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[55]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[56]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[56]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[57]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[57]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[58]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[58]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[59]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[59]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[60]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[60]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[61]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[61]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[62]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[62]
set_instance_assignment -name IO_STANDARD "${mem_dq_IO_STANDARD}" -to ${mem_dq_pin_name}[63]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dq_OUTPUT_TERMINATION}" -to ${mem_dq_pin_name}[63]
set_instance_assignment -name IO_STANDARD "${mem_dqs_IO_STANDARD}" -to ${mem_dqs_pin_name}[0]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqs_OUTPUT_TERMINATION}" -to ${mem_dqs_pin_name}[0]
set_instance_assignment -name IO_STANDARD "${mem_dqs_IO_STANDARD}" -to ${mem_dqs_pin_name}[1]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqs_OUTPUT_TERMINATION}" -to ${mem_dqs_pin_name}[1]
set_instance_assignment -name IO_STANDARD "${mem_dqs_IO_STANDARD}" -to ${mem_dqs_pin_name}[2]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqs_OUTPUT_TERMINATION}" -to ${mem_dqs_pin_name}[2]
set_instance_assignment -name IO_STANDARD "${mem_dqs_IO_STANDARD}" -to ${mem_dqs_pin_name}[3]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqs_OUTPUT_TERMINATION}" -to ${mem_dqs_pin_name}[3]
set_instance_assignment -name IO_STANDARD "${mem_dqs_IO_STANDARD}" -to ${mem_dqs_pin_name}[4]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqs_OUTPUT_TERMINATION}" -to ${mem_dqs_pin_name}[4]
set_instance_assignment -name IO_STANDARD "${mem_dqs_IO_STANDARD}" -to ${mem_dqs_pin_name}[5]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqs_OUTPUT_TERMINATION}" -to ${mem_dqs_pin_name}[5]
set_instance_assignment -name IO_STANDARD "${mem_dqs_IO_STANDARD}" -to ${mem_dqs_pin_name}[6]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqs_OUTPUT_TERMINATION}" -to ${mem_dqs_pin_name}[6]
set_instance_assignment -name IO_STANDARD "${mem_dqs_IO_STANDARD}" -to ${mem_dqs_pin_name}[7]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqs_OUTPUT_TERMINATION}" -to ${mem_dqs_pin_name}[7]
set_instance_assignment -name IO_STANDARD "${mem_dqsn_IO_STANDARD}" -to ${mem_dqsn_pin_name}[0]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqsn_OUTPUT_TERMINATION}" -to ${mem_dqsn_pin_name}[0]
set_instance_assignment -name IO_STANDARD "${mem_dqsn_IO_STANDARD}" -to ${mem_dqsn_pin_name}[1]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqsn_OUTPUT_TERMINATION}" -to ${mem_dqsn_pin_name}[1]
set_instance_assignment -name IO_STANDARD "${mem_dqsn_IO_STANDARD}" -to ${mem_dqsn_pin_name}[2]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqsn_OUTPUT_TERMINATION}" -to ${mem_dqsn_pin_name}[2]
set_instance_assignment -name IO_STANDARD "${mem_dqsn_IO_STANDARD}" -to ${mem_dqsn_pin_name}[3]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqsn_OUTPUT_TERMINATION}" -to ${mem_dqsn_pin_name}[3]
set_instance_assignment -name IO_STANDARD "${mem_dqsn_IO_STANDARD}" -to ${mem_dqsn_pin_name}[4]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqsn_OUTPUT_TERMINATION}" -to ${mem_dqsn_pin_name}[4]
set_instance_assignment -name IO_STANDARD "${mem_dqsn_IO_STANDARD}" -to ${mem_dqsn_pin_name}[5]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqsn_OUTPUT_TERMINATION}" -to ${mem_dqsn_pin_name}[5]
set_instance_assignment -name IO_STANDARD "${mem_dqsn_IO_STANDARD}" -to ${mem_dqsn_pin_name}[6]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqsn_OUTPUT_TERMINATION}" -to ${mem_dqsn_pin_name}[6]
set_instance_assignment -name IO_STANDARD "${mem_dqsn_IO_STANDARD}" -to ${mem_dqsn_pin_name}[7]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dqsn_OUTPUT_TERMINATION}" -to ${mem_dqsn_pin_name}[7]
set_instance_assignment -name IO_STANDARD "${mem_dm_IO_STANDARD}" -to ${mem_dm_pin_name}[0]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dm_OUTPUT_TERMINATION}" -to ${mem_dm_pin_name}[0]
set_instance_assignment -name IO_STANDARD "${mem_dm_IO_STANDARD}" -to ${mem_dm_pin_name}[1]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dm_OUTPUT_TERMINATION}" -to ${mem_dm_pin_name}[1]
set_instance_assignment -name IO_STANDARD "${mem_dm_IO_STANDARD}" -to ${mem_dm_pin_name}[2]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dm_OUTPUT_TERMINATION}" -to ${mem_dm_pin_name}[2]
set_instance_assignment -name IO_STANDARD "${mem_dm_IO_STANDARD}" -to ${mem_dm_pin_name}[3]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dm_OUTPUT_TERMINATION}" -to ${mem_dm_pin_name}[3]
set_instance_assignment -name IO_STANDARD "${mem_dm_IO_STANDARD}" -to ${mem_dm_pin_name}[4]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dm_OUTPUT_TERMINATION}" -to ${mem_dm_pin_name}[4]
set_instance_assignment -name IO_STANDARD "${mem_dm_IO_STANDARD}" -to ${mem_dm_pin_name}[5]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dm_OUTPUT_TERMINATION}" -to ${mem_dm_pin_name}[5]
set_instance_assignment -name IO_STANDARD "${mem_dm_IO_STANDARD}" -to ${mem_dm_pin_name}[6]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dm_OUTPUT_TERMINATION}" -to ${mem_dm_pin_name}[6]
set_instance_assignment -name IO_STANDARD "${mem_dm_IO_STANDARD}" -to ${mem_dm_pin_name}[7]
set_instance_assignment -name OUTPUT_TERMINATION "${mem_dm_OUTPUT_TERMINATION}" -to ${mem_dm_pin_name}[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[8]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[9]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[10]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[11]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[12]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[13]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[14]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[15]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[16]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[17]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[18]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[19]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[20]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[21]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[22]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[23]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[24]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[25]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[26]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[27]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[28]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[29]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[30]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[31]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[32]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[33]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[34]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[35]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[36]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[37]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[38]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[39]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[40]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[41]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[42]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[43]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[44]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[45]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[46]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[47]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[48]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[49]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[50]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[51]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[52]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[53]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[54]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[55]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[56]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[57]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[58]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[59]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[60]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[61]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[62]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dq_pin_name}[63]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[8]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[9]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[10]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[11]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[12]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[13]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[14]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[15]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[16]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[17]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[18]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[19]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[20]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[21]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[22]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[23]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[24]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[25]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[26]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[27]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[28]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[29]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[30]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[31]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[32]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[33]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[34]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[35]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[36]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[37]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[38]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[39]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[40]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[41]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[42]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[43]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[44]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[45]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[46]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[47]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[48]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[49]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[50]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[51]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[52]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[53]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[54]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[55]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[56]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[57]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[58]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[59]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[60]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[61]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[62]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dq_pin_name}[63]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqs_pin_name}[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqs_pin_name}[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqs_pin_name}[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqs_pin_name}[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqs_pin_name}[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqs_pin_name}[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqs_pin_name}[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqs_pin_name}[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqs_pin_name}[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqs_pin_name}[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqs_pin_name}[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqs_pin_name}[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqs_pin_name}[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqs_pin_name}[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqs_pin_name}[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqs_pin_name}[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqsn_pin_name}[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqsn_pin_name}[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqsn_pin_name}[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqsn_pin_name}[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqsn_pin_name}[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqsn_pin_name}[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqsn_pin_name}[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dqsn_pin_name}[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqsn_pin_name}[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqsn_pin_name}[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqsn_pin_name}[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqsn_pin_name}[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqsn_pin_name}[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqsn_pin_name}[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqsn_pin_name}[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dqsn_pin_name}[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dm_pin_name}[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dm_pin_name}[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dm_pin_name}[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dm_pin_name}[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dm_pin_name}[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dm_pin_name}[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dm_pin_name}[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG "${delay_chain_config}" -to ${mem_dm_pin_name}[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dm_pin_name}[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dm_pin_name}[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dm_pin_name}[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dm_pin_name}[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dm_pin_name}[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dm_pin_name}[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dm_pin_name}[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP "321236355" -to ${mem_dm_pin_name}[7]
 
unset pin_prefix
/trunk/TUT/ip.hwp.interface/pcie/pcie_to_hibi.comp/2.0/ts/a2gx_pcie_to_hibi_perf_test/in_sys_sp.qip
0,0 → 1,4
set_global_assignment -name IP_TOOL_NAME "In-System Sources and Probes"
set_global_assignment -name IP_TOOL_VERSION "11.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "in_sys_sp.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "in_sys_sp.cmp"]

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.