URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
Subversion Repositories funbase_ip_library
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/trunk/TUT/soc/udp_flood_example_dm9000a/1.0/udp_flood_example_dm9000a.designcfg.1.0.xml
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/trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.a2_ddr2_dimm_1GB.2.0.png
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png
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--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.accelerator.picture_manip.1.0.png (revision 140)
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/arria_ii_gx_demo_soc_report.html
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/arria_ii_gx_demo_soc_report.html (revision 140)
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This document was generated by Kactus2 on 07.11.2011 14:06:01 by user matilail
-
- Table of contents
- 1. Component TUT - soc - arria_ii_gx_demo_soc - 1.0
- 1.1. Kactus2 attributes
- 1.2. Ports
- 1.3. Bus interfaces
- 1.4. Views
- 2. Component TUT - ip.hwp.interface - pcie_to_hibi_4x - 1.0
- 2.1. Model parameters
- 2.2. Kactus2 attributes
- 2.3. Ports
- 2.4. Bus interfaces
- 2.5. File sets
- 2.6. Views
- 3. Component TUT - ip.hwp.storage - a2_ddr2_dimm_1GB - 2.0
- 3.1. Kactus2 attributes
- 3.2. Ports
- 3.3. Bus interfaces
- 3.4. File sets
- 3.5. Views
- 4. Component TUT - ip.hwp.storage - hibi_mem_dma - 2.0
- 4.1. Kactus2 attributes
- 4.2. Ports
- 4.3. Bus interfaces
- 4.4. File sets
- 4.5. Views
- 5. Component TUT - ip.hwp.accelerator - picture_manip - 1.0
- 5.1. Kactus2 attributes
- 5.2. Ports
- 5.3. Bus interfaces
- 5.4. File sets
- 5.5. Views
- 6. Component TUT - ip.hwp.communication - hibi_segment_small - 2.0
- 6.1. Kactus2 attributes
- 6.2. Ports
- 6.3. Bus interfaces
- 6.4. File sets
- 6.5. Views
-
1. Component TUT - soc - arria_ii_gx_demo_soc - 1.0
-
- 
- IP-Xact file: arria_ii_gx_demo_soc.1.0.xml
-
1.1 Kactus2 attributes
-
- Product hierarchy: SoC
- Component implementation: HW
- Component firmness: Mutable
-
1.2 Ports
-| Name | -Direction | -Width | -Left bound | -Right bound | -Default value | -
|---|---|---|---|---|---|
| clkin_bot_p | -in | -1 | -0 | -0 | -- |
| ddr2_dimm_addr | -out | -16 | -15 | -0 | -- |
| ddr2_dimm_ba | -out | -3 | -2 | -0 | -- |
| ddr2_dimm_cas_n | -out | -1 | -0 | -0 | -- |
| ddr2_dimm_cke | -out | -1 | -0 | -0 | -- |
| ddr2_dimm_clk | -inout | -2 | -1 | -0 | -- |
| ddr2_dimm_clk_n | -inout | -2 | -1 | -0 | -- |
| ddr2_dimm_cs_n | -out | -1 | -0 | -0 | -- |
| ddr2_dimm_dm | -out | -8 | -7 | -0 | -- |
| ddr2_dimm_dq | -inout | -64 | -63 | -0 | -- |
| ddr2_dimm_dqs | -inout | -8 | -7 | -0 | -- |
| ddr2_dimm_dqs_n | -inout | -8 | -7 | -0 | -- |
| ddr2_dimm_odt | -out | -1 | -0 | -0 | -- |
| ddr2_dimm_ras_n | -out | -1 | -0 | -0 | -- |
| ddr2_dimm_we_n | -out | -1 | -0 | -0 | -- |
| pcie_refclk_p | -in | -1 | -0 | -0 | -- |
| pcie_rx_p | -in | -4 | -3 | -0 | -- |
| pcie_tx_p | -out | -4 | -3 | -0 | -- |
| rst_n_RESETn | -in | -1 | -0 | -0 | -- |
| user_pb | -in | -3 | -2 | -0 | -- |
1.3 Bus interfaces
-1.3.1 clk_in
-
- Description: Clock input for demo design
- Interface mode: slave
- Ports used in this interface:
-
-
-
- clkin_bot_p -
1.3.2 ddr2_p
-
- Description: DDR2 interface to DDR2 memory
- Interface mode: master
- Ports used in this interface:
-
-
-
- ddr2_dimm_addr -
- ddr2_dimm_ba -
- ddr2_dimm_cas_n -
- ddr2_dimm_cke -
- ddr2_dimm_clk_n -
- ddr2_dimm_clk -
- ddr2_dimm_cs_n -
- ddr2_dimm_dqs_n -
- ddr2_dimm_dqs -
- ddr2_dimm_dm -
- ddr2_dimm_dq -
- ddr2_dimm_odt -
- ddr2_dimm_ras_n -
- ddr2_dimm_we_n -
1.3.3 pcie_4x_p
-
- Description: PCIe 4x interface
- Interface mode: mirroredMaster
- Ports used in this interface:
-
-
-
- pcie_tx_p -
- pcie_rx_p -
- pcie_refclk_p -
- user_pb -
1.3.4 rst_n
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- user_pb -
1.4 Views
-1.4.1 View: structural
-
- 
- Type: hierarchical
-
1.4.1.1 Configuration TUT - soc - arria_ii_gx_demo_soc.designcfg - 1.0
-
- IP-Xact file: arria_ii_gx_demo_soc.designcfg.1.0.xml
-
-
1.4.1.2 Design TUT - soc - arria_ii_gx_demo_soc.design - 1.0
-
- IP-Xact file: arria_ii_gx_demo_soc.design.1.0.xml
-
-
| Instance name | -Component type | -Configurable values | -Active view | -Description | -
|---|---|---|---|---|
| pcie_to_hibi_4x_1 | -TUT - ip.hwp.interface - pcie_to_hibi_4x - 1.0 | -- | -rtl | -- |
| a2_ddr2_dimm_1GB_1 | -TUT - ip.hwp.storage - a2_ddr2_dimm_1GB - 2.0 | -- | -rtl | -- |
| hibi_mem_dma_1 | -TUT - ip.hwp.storage - hibi_mem_dma - 2.0 | -- | -rtl | -- |
| picture_manip_1 | -TUT - ip.hwp.accelerator - picture_manip - 1.0 | -- | -rtl | -- |
| hibi_segment_small_1 | -TUT - ip.hwp.communication - hibi_segment_small - 2.0 | -- | -rtl | -- |
1.4.2 View: rtl
-
- Type: non-hierarchical
-
2. Component TUT - ip.hwp.interface - pcie_to_hibi_4x - 1.0
-
- 
- Description: Adapter to connect HIBI based FPGA subsystem to PCIe bus.
- IP-Xact file: pcie_to_hibi_4x.1.0.xml
-
2.1 Model parameters
-| Name | -Data type | -Default value | -
|---|---|---|
| HIBI_DATA_WIDTH | -integer | -32 | -
2.2 Kactus2 attributes
-
- Product hierarchy: IP
- Component implementation: HW
- Component firmness: Parameterizable
-
2.3 Ports
-| Name | -Direction | -Width | -Left bound | -Right bound | -Default value | -
|---|---|---|---|---|---|
| clk_in | -in | -1 | -0 | -0 | -- |
| hibi_av_in | -in | -1 | -0 | -0 | -- |
| hibi_av_out | -out | -1 | -0 | -0 | -- |
| hibi_comm_in | -in | -5 | -4 | -0 | -- |
| hibi_comm_out | -out | -5 | -4 | -0 | -- |
| hibi_data_in | -in | -32 | -31 | -0 | -- |
| hibi_data_out | -out | -32 | -31 | -0 | -- |
| hibi_empty_in | -in | -1 | -0 | -0 | -- |
| hibi_full_in | -in | -1 | -0 | -0 | -- |
| hibi_one_d_in | -in | -1 | -0 | -0 | -- |
| hibi_one_p_in | -in | -1 | -0 | -0 | -- |
| hibi_re_out | -out | -1 | -0 | -0 | -- |
| hibi_we_out | -out | -1 | -0 | -0 | -- |
| pcie_ref_clk | -in | -1 | -0 | -0 | -- |
| pcie_rst_n | -in | -1 | -0 | -0 | -- |
| pcie_rx | -in | -4 | -3 | -0 | -- |
| pcie_tx | -out | -4 | -3 | -0 | -- |
| rst_n | -in | -1 | -0 | -0 | -- |
2.4 Bus interfaces
-2.4.1 clk_in
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- clk_in -
2.4.2 hibi_p
-
- Interface mode: master
- Ports used in this interface:
-
-
-
- hibi_av_out -
- hibi_one_d_in -
- hibi_data_in -
- hibi_data_out -
- hibi_av_in -
- hibi_full_in -
- hibi_comm_out -
- hibi_we_out -
- hibi_comm_in -
- hibi_empty_in -
- hibi_re_out -
- hibi_one_p_in -
2.4.3 pcie_4x_p
-
- Interface mode: mirroredMaster
- Ports used in this interface:
-
-
-
- pcie_tx -
- pcie_rx -
- pcie_rst_n -
- pcie_ref_clk -
2.4.4 rst_n
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- rst_n -
2.5 File sets
-2.5.1 hdlSources
-
- Identifiers:
- Default file builders:
-
| File type | -Command | -Flags | -Replace default flags | -
|---|---|---|---|
| verilogSource | -vlog | --quiet -work pcie_to_hibi_4x | -false | -
| vhdlSource | -vcom | --quiet -check_synthesis -work pcie_to_hibi_4x | -false | -
2.5.1.1 Files
-| File name | -Logical name | -Build command | -Build flags | -Specified file types | -Description | -
|---|---|---|---|---|---|
| pcie_to_hibi_4x.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie_to_hibi_4x_sopc.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie_to_hibi_4x_sopc_burst_0.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie_to_hibi_4x_sopc_burst_1.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie_to_hibi_4x_sopc_burst_2.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie_to_hibi_4x_sopc_burst_3.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie_to_hibi_4x_sopc_burst_4.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie_to_hibi_4x_sopc_burst_5.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| dma.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie_core.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| pcie_serdes.vhd | -pcie_to_hibi_4x | -- | - | vhdlSource | -- |
| a2h.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_64b_x4_pipen1b.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_hip_pipen1b.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pclk_align.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pclk_pll.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_phasefifo.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_100_125.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_100_250.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_125_250.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_15625_125.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_250_100.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_phy0.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_phy1_62p5.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_phy2.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_phy3_62p5.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_phy4_62p5.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_pll_phy5_62p5.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_serdes_2agx_x4d_gen1_08p.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| altpcie_serdes_2agx_x4d_gen1_16p.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| pciexp64_dlink.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| pciexp64_trans.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| pciexp_dcram.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| pciexpx8f_confctrl.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
| avalon_to_hibi.v | -pcie_to_hibi_4x | -- | - | verilogSource | -- |
2.5.2 Documentation
-
- Description: pcie_to_hibi IP documentations.
- Identifiers:
-
2.5.2.1 Files
-| File name | -Logical name | -Build command | -Build flags | -Specified file types | -Description | -
|---|---|---|---|---|---|
| PCI-E_to_hibi.docx | -- | - | - | documentation | -pcie_to_hibi IP block documentation in word document. | -
| PCI-E_to_hibi.pptx | -- | - | - | documentation | -pcie_to_hibi IP block documentation in powerpoint presentation. | -
2.5.3 fpga_settings
-
- Identifiers:
-
2.5.3.1 Files
-| File name | -Logical name | -Build command | -Build flags | -Specified file types | -Description | -
|---|---|---|---|---|---|
| pcie.sdc | -- | - | - | quartusSDCFile | -pcie_to_hibi timing and area constraints. | -
2.5.4 sopc_files
-
- Identifiers:
-
2.5.4.1 Files
-| File name | -Logical name | -Build command | -Build flags | -Specified file types | -Description | -
|---|---|---|---|---|---|
| pcie_to_hibi_4x_sopc.sopc | -- | - | - | quartusSOPCFILE | -SOPC project file | -
2.6 Views
-2.6.1 View: rtl
-
- Type: non-hierarchical
- File sets contained in this view:
-
-
-
- hdlSources -
3. Component TUT - ip.hwp.storage - a2_ddr2_dimm_1GB - 2.0
-
- 
- Description: Altera ddr2 memory controller
- IP-Xact file: alt_ddr2_a2.comp.1.0.xml
-
3.1 Kactus2 attributes
-
- Product hierarchy: IP
- Component implementation: HW
- Component firmness: Mutable
-
3.2 Ports
-| Name | -Direction | -Width | -Left bound | -Right bound | -Default value | -
|---|---|---|---|---|---|
| aux_full_rate_clk | -out | -1 | -0 | -0 | -- |
| aux_half_rate_clk | -out | -1 | -0 | -0 | -- |
| dll_reference_clk | -out | -1 | -0 | -0 | -- |
| dqs_delay_ctrl_export | -out | -6 | -5 | -0 | -- |
| global_reset_n | -in | -1 | -0 | -0 | -- |
| local_address | -in | -25 | -24 | -0 | -- |
| local_be | -in | -32 | -31 | -0 | -- |
| local_burstbegin | -in | -1 | -0 | -0 | -- |
| local_init_done | -out | -1 | -0 | -0 | -- |
| local_rdata | -out | -256 | -255 | -0 | -- |
| local_rdata_valid | -out | -1 | -0 | -0 | -- |
| local_read_req | -in | -1 | -0 | -0 | -- |
| local_ready | -out | -1 | -0 | -0 | -- |
| local_refresh_ack | -out | -1 | -0 | -0 | -- |
| local_size | -in | -3 | -2 | -0 | -- |
| local_wdata | -in | -256 | -255 | -0 | -- |
| local_write_req | -in | -1 | -0 | -0 | -- |
| mem_addr | -out | -14 | -13 | -0 | -- |
| mem_ba | -out | -3 | -2 | -0 | -- |
| mem_cas_n | -out | -1 | -0 | -0 | -- |
| mem_cke | -out | -1 | -0 | -0 | -- |
| mem_clk | -inout | -2 | -1 | -0 | -- |
| mem_clk_n | -inout | -2 | -1 | -0 | -- |
| mem_cs_n | -out | -1 | -0 | -0 | -- |
| mem_dm | -out | -8 | -7 | -0 | -- |
| mem_dq | -inout | -64 | -63 | -0 | -- |
| mem_dqs | -inout | -8 | -7 | -0 | -- |
| mem_dqsn | -inout | -8 | -7 | -0 | -- |
| mem_odt | -out | -1 | -0 | -0 | -- |
| mem_ras_n | -out | -1 | -0 | -0 | -- |
| mem_we_n | -out | -1 | -0 | -0 | -- |
| phy_clk | -out | -1 | -0 | -0 | -- |
| pll_ref_clk | -in | -1 | -0 | -0 | -- |
| reset_phy_clk_n | -out | -1 | -0 | -0 | -- |
| reset_request_n | -out | -1 | -0 | -0 | -- |
| soft_reset_n | -in | -1 | -0 | -0 | -- |
3.3 Bus interfaces
-3.3.1 alt_ddr2_p
-
- Interface mode: mirroredMaster
- Ports used in this interface:
-
-
-
- local_init_done -
- local_write_req -
- local_read_req -
- local_address -
- local_ready -
- local_rdata_valid -
- local_wdata -
- local_rdata -
- local_be -
- local_burstbegin -
- local_size -
3.3.2 clk_in
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- pll_ref_clk -
3.3.3 ddr2_p
-
- Interface mode: master
- Ports used in this interface:
-
-
-
- mem_clk -
- mem_clk_n -
- mem_cke -
- mem_cs_n -
- mem_cas_n -
- mem_ras_n -
- mem_odt -
- mem_we_n -
- mem_ba -
- mem_addr -
- mem_dm -
- mem_dqs -
- mem_dqsn -
- mem_dq -
3.3.4 phy_clk_out
-
- Interface mode: master
- Ports used in this interface:
-
-
-
- phy_clk -
3.3.5 rst_n
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- global_reset_n -
3.3.6 soft_rst_n
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- soft_reset_n -
3.4 File sets
-3.4.1 hdlSources
-
- Identifiers:
- Default file builders:
-
| File type | -Command | -Flags | -Replace default flags | -
|---|---|---|---|
| verilogSource | -vlog | --quiet -work alt_ddr2_a2 | -false | -
| vhdlSource | -vcom | --quiet -check_synthesis -work alt_ddr2_a2 | -false | -
3.4.1.1 Files
-| File name | -Logical name | -Build command | -Build flags | -Specified file types | -Description | -
|---|---|---|---|---|---|
| a2_ddr2_dimm_1GB.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| a2_ddr2_dimm_1GB_alt_ddrx_controller_wrapper.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| a2_ddr2_dimm_1GB_controller_phy.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| a2_ddr2_dimm_1GB_phy.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| a2_ddr2_dimm_1GB_phy_alt_mem_phy.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| a2_ddr2_dimm_1GB_phy_alt_mem_phy_dq_dqs.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| a2_ddr2_dimm_1GB_phy_alt_mem_phy_pll.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| a2_ddr2_dimm_1GB_phy_alt_mem_phy_seq.vhd | -alt_ddr2_a2 | -- | - | vhdlSource | -- |
| a2_ddr2_dimm_1GB_phy_alt_mem_phy_seq_wrapper.v | -alt_ddr2_a2 | -- | +incdir+D:/user/matilail/funbase/svn/release_2/lib/TUT/ip.hwp/stor.alt_ddr2_a2/1.0/hdl | -verilogSource | -- |
| alt_ddrx_addr_cmd.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_afi_block.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_avalon_if.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_bank_timer.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_bank_timer_info.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_bank_timer_wrapper.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_bank_tracking.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_bypass.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_cache.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_clock_and_reset.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_cmd_gen.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_cmd_queue.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_controller.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_csr.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_ddr2_odt_gen.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_ddr3_odt_gen.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_decoder.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_decoder_40.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_decoder_72.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_ecc.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_encoder.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_encoder_40.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_encoder_72.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_input_if.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_odt_gen.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_rank_monitor.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_state_machine.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_timers.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_timers_fsm.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_timing_param.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_ddrx_wdata_fifo.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| alt_mem_phy_defines.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
| altera_avalon_half_rate_bridge.v | -alt_ddr2_a2 | -- | - | verilogSource | -- |
3.5 Views
-3.5.1 View: rtl
-
- Type: non-hierarchical
-
4. Component TUT - ip.hwp.storage - hibi_mem_dma - 2.0
-
- 
- Description: HIBI memory DMA access IP.
- IP-Xact file: hibi_mem_dma.comp.xml
-
4.1 Kactus2 attributes
-
- Product hierarchy: IP
- Component implementation: HW
- Component firmness: Mutable
-
4.2 Ports
-| Name | -Direction | -Width | -Left bound | -Right bound | -Default value | -
|---|---|---|---|---|---|
| clk | -in | -1 | -0 | -0 | -- |
| hibi_addr_in | -in | -32 | -31 | -0 | -- |
| hibi_addr_out | -out | -32 | -31 | -0 | -- |
| hibi_av_out | -out | -1 | -0 | -0 | -- |
| hibi_comm_in | -in | -3 | -2 | -0 | -- |
| hibi_comm_out | -out | -3 | -2 | -0 | -- |
| hibi_data_in | -in | -32 | -31 | -0 | -- |
| hibi_data_out | -out | -32 | -31 | -0 | -- |
| hibi_empty_in | -in | -1 | -0 | -0 | -- |
| hibi_full_in | -in | -1 | -0 | -0 | -- |
| hibi_msg_addr_out | -out | -32 | -31 | -0 | -- |
| hibi_msg_av_out | -out | -1 | -0 | -0 | -- |
| hibi_msg_comm_in | -in | -3 | -2 | -0 | -- |
| hibi_msg_comm_out | -out | -3 | -2 | -0 | -- |
| hibi_msg_data_in | -in | -32 | -31 | -0 | -- |
| hibi_msg_data_out | -out | -32 | -31 | -0 | -- |
| hibi_msg_empty_in | -in | -1 | -0 | -0 | -- |
| hibi_msg_full_in | -in | -1 | -0 | -0 | -- |
| hibi_msg_re_out | -out | -1 | -0 | -0 | -- |
| hibi_msg_we_out | -out | -1 | -0 | -0 | -- |
| hibi_re_out | -out | -1 | -0 | -0 | -- |
| hibi_we_out | -out | -1 | -0 | -0 | -- |
| mem_addr_out | -out | -25 | -24 | -0 | -- |
| mem_be_out | -out | -32 | -31 | -0 | -- |
| mem_burst_begin_out | -out | -1 | -0 | -0 | -- |
| mem_burst_size_out | -out | -3 | -2 | -0 | -- |
| mem_init_done_in | -in | -1 | -0 | -0 | -- |
| mem_rd_req_out | -out | -1 | -0 | -0 | -- |
| mem_rdata_in | -in | -256 | -255 | -0 | -- |
| mem_rdata_valid_in | -in | -1 | -0 | -0 | -- |
| mem_ready_in | -in | -1 | -0 | -0 | -- |
| mem_wdata_out | -out | -256 | -255 | -0 | -- |
| mem_wr_req_out | -out | -1 | -0 | -0 | -- |
| rst_n | -in | -1 | -0 | -0 | -- |
4.3 Bus interfaces
-4.3.1 alt_ddr2_p
-
- Interface mode: master
- Ports used in this interface:
-
-
-
- mem_init_done_in -
- mem_wr_req_out -
- mem_rd_req_out -
- mem_addr_out -
- mem_ready_in -
- mem_rdata_valid_in -
- mem_wdata_out -
- mem_rdata_in -
- mem_be_out -
- mem_burst_begin_out -
- mem_burst_size_out -
4.3.2 clk_in
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- clk -
4.3.3 hibi_p
-
- Interface mode: master
- Ports used in this interface:
-
-
-
- hibi_addr_out -
- hibi_data_in -
- hibi_data_out -
- hibi_full_in -
- hibi_comm_out -
- hibi_we_out -
- hibi_comm_in -
- hibi_empty_in -
- hibi_re_out -
- hibi_msg_addr_out -
- hibi_msg_data_in -
- hibi_msg_data_out -
- hibi_msg_full_in -
- hibi_msg_comm_out -
- hibi_msg_we_out -
- hibi_msg_comm_in -
- hibi_msg_empty_in -
- hibi_msg_re_out -
- hibi_addr_in -
4.3.4 rst_n
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- rst_n -
4.4 File sets
-4.4.1 hdlSources
-
- Identifiers:
- Default file builders:
-
| File type | -Command | -Flags | -Replace default flags | -
|---|---|---|---|
| vhdlSource | -vcom | --quiet -check_synthesis -work hibi_mem_dma | -false | -
4.4.1.1 Files
-| File name | -Logical name | -Build command | -Build flags | -Specified file types | -Description | -
|---|---|---|---|---|---|
| fifo_ram.vhd | -hibi_mem_dma | -- | - | vhdlSource | -- |
| fifo_u.vhd | -hibi_mem_dma | -- | - | vhdlSource | -- |
| dual_port_ram_u.vhd | -hibi_mem_dma | -- | - | vhdlSource | -- |
| onchip_ram_u.vhd | -hibi_mem_dma | -- | - | vhdlSource | -- |
| dual_ram_async_read.vhd | -hibi_mem_dma | -- | - | vhdlSource | -- |
| hibi_mem_dma.vhd | -hibi_mem_dma | -- | - | vhdlSource | -- |
4.4.2 Documentation
-
- Identifiers:
-
4.4.2.1 Files
-| File name | -Logical name | -Build command | -Build flags | -Specified file types | -Description | -
|---|---|---|---|---|---|
| HIBI_MEM_DMA.docx | -- | - | - | documentation | -hibi_mem_dma IP block datasheet. | -
4.5 Views
-4.5.1 View: rtl
-
- Type: non-hierarchical
- Description: HIBI_MEM_DMA vhdl source view
- File sets contained in this view:
-
-
-
- hdlSources -
5. Component TUT - ip.hwp.accelerator - picture_manip - 1.0
-
- 
- Description: Simple picture manipulator IP to rotate 8-bit grayscale picture 90 degrees clockwise.
- IP-Xact file: picture_manip.1.0.xml
-
5.1 Kactus2 attributes
-
- Product hierarchy: IP
- Component implementation: HW
- Component firmness: Mutable
-
5.2 Ports
-| Name | -Direction | -Width | -Left bound | -Right bound | -Default value | -
|---|---|---|---|---|---|
| clk | -in | -1 | -0 | -0 | -- |
| hibi_av_in | -in | -1 | -0 | -0 | -- |
| hibi_av_out | -out | -1 | -0 | -0 | -- |
| hibi_comm_in | -in | -5 | -4 | -0 | -- |
| hibi_comm_out | -out | -5 | -4 | -0 | -- |
| hibi_data_in | -in | -32 | -31 | -0 | -- |
| hibi_data_out | -out | -32 | -31 | -0 | -- |
| hibi_empty_in | -in | -1 | -0 | -0 | -- |
| hibi_full_in | -in | -1 | -0 | -0 | -- |
| hibi_one_d_in | -in | -1 | -0 | -0 | -- |
| hibi_one_p_in | -in | -1 | -0 | -0 | -- |
| hibi_re_out | -out | -1 | -0 | -0 | -- |
| hibi_we_out | -out | -1 | -0 | -0 | -- |
| rst_n | -in | -1 | -0 | -0 | -- |
5.3 Bus interfaces
-5.3.1 clk
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- clk -
5.3.2 hibi_p
-
- Interface mode: master
- Ports used in this interface:
-
-
-
- hibi_av_out -
- hibi_one_d_in -
- hibi_data_in -
- hibi_data_out -
- hibi_av_in -
- hibi_full_in -
- hibi_comm_out -
- hibi_we_out -
- hibi_comm_in -
- hibi_empty_in -
- hibi_re_out -
- hibi_one_p_in -
5.3.3 rst_n
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- rst_n -
5.4 File sets
-5.4.1 hdlSources
-
- Identifiers:
-
5.4.1.1 Files
-| File name | -Logical name | -Build command | -Build flags | -Specified file types | -Description | -
|---|---|---|---|---|---|
| manip_memory.vhd | -picture_manip | -- | - | vhdlSource | -- |
| picture_manip_pkg.vhd | -picture_manip | -- | - | vhdlSource | -- |
| picture_manip.vhd | -pciture_manip | -- | - | vhdlSource | -- |
5.5 Views
-5.5.1 View: rtl
-
- Type: non-hierarchical
- File sets contained in this view:
-
-
-
- hdlSources -
6. Component TUT - ip.hwp.communication - hibi_segment_small - 2.0
-
- 
- Description: HIBI segment block including two r4_wrapper and one r3_wrapper interfaces.
- IP-Xact file: hibi_segment_small.2.0.xml
-
6.1 Kactus2 attributes
-
- Product hierarchy: IP
- Component implementation: HW
- Component firmness: Parameterizable
-
6.2 Ports
-| Name | -Direction | -Width | -Left bound | -Right bound | -Default value | -
|---|---|---|---|---|---|
| agent_addr_in_17 | -in | -32 | -31 | -0 | -- |
| agent_addr_out_17 | -out | -32 | -31 | -0 | -- |
| agent_av_in_1 | -in | -1 | -0 | -0 | -- |
| agent_av_in_2 | -in | -1 | -0 | -0 | -- |
| agent_av_in_3 | -in | -1 | -0 | -0 | -- |
| agent_av_in_4 | -in | -1 | -0 | -0 | -- |
| agent_av_in_5 | -in | -1 | -0 | -0 | -- |
| agent_av_in_6 | -in | -1 | -0 | -0 | -- |
| agent_av_in_7 | -in | -1 | -0 | -0 | -- |
| agent_av_in_8 | -in | -1 | -0 | -0 | -- |
| agent_av_out_1 | -out | -1 | -0 | -0 | -- |
| agent_av_out_2 | -out | -1 | -0 | -0 | -- |
| agent_av_out_3 | -out | -1 | -0 | -0 | -- |
| agent_av_out_4 | -out | -1 | -0 | -0 | -- |
| agent_av_out_5 | -out | -1 | -0 | -0 | -- |
| agent_av_out_6 | -out | -1 | -0 | -0 | -- |
| agent_av_out_7 | -out | -1 | -0 | -0 | -- |
| agent_av_out_8 | -out | -1 | -0 | -0 | -- |
| agent_comm_in_1 | -in | -3 | -2 | -0 | -- |
| agent_comm_in_17 | -in | -3 | -2 | -0 | -- |
| agent_comm_in_2 | -in | -3 | -2 | -0 | -- |
| agent_comm_in_3 | -in | -3 | -2 | -0 | -- |
| agent_comm_in_4 | -in | -3 | -2 | -0 | -- |
| agent_comm_in_5 | -in | -3 | -2 | -0 | -- |
| agent_comm_in_6 | -in | -3 | -2 | -0 | -- |
| agent_comm_in_7 | -in | -3 | -2 | -0 | -- |
| agent_comm_in_8 | -in | -3 | -2 | -0 | -- |
| agent_comm_out_1 | -out | -3 | -2 | -0 | -- |
| agent_comm_out_17 | -out | -3 | -2 | -0 | -- |
| agent_comm_out_2 | -out | -3 | -2 | -0 | -- |
| agent_comm_out_3 | -out | -3 | -2 | -0 | -- |
| agent_comm_out_4 | -out | -3 | -2 | -0 | -- |
| agent_comm_out_5 | -out | -3 | -2 | -0 | -- |
| agent_comm_out_6 | -out | -3 | -2 | -0 | -- |
| agent_comm_out_7 | -out | -3 | -2 | -0 | -- |
| agent_comm_out_8 | -out | -3 | -2 | -0 | -- |
| agent_data_in_1 | -in | -32 | -31 | -0 | -- |
| agent_data_in_17 | -in | -32 | -31 | -0 | -- |
| agent_data_in_2 | -in | -32 | -31 | -0 | -- |
| agent_data_in_3 | -in | -32 | -31 | -0 | -- |
| agent_data_in_4 | -in | -32 | -31 | -0 | -- |
| agent_data_in_5 | -in | -32 | -31 | -0 | -- |
| agent_data_in_6 | -in | -32 | -31 | -0 | -- |
| agent_data_in_7 | -in | -32 | -31 | -0 | -- |
| agent_data_in_8 | -in | -32 | -31 | -0 | -- |
| agent_data_out_1 | -out | -32 | -31 | -0 | -- |
| agent_data_out_17 | -out | -32 | -31 | -0 | -- |
| agent_data_out_2 | -out | -32 | -31 | -0 | -- |
| agent_data_out_3 | -out | -32 | -31 | -0 | -- |
| agent_data_out_4 | -out | -32 | -31 | -0 | -- |
| agent_data_out_5 | -out | -32 | -31 | -0 | -- |
| agent_data_out_6 | -out | -32 | -31 | -0 | -- |
| agent_data_out_7 | -out | -32 | -31 | -0 | -- |
| agent_data_out_8 | -out | -32 | -31 | -0 | -- |
| agent_empty_out_1 | -out | -1 | -0 | -0 | -- |
| agent_empty_out_17 | -out | -1 | -0 | -0 | -- |
| agent_empty_out_2 | -out | -1 | -0 | -0 | -- |
| agent_empty_out_3 | -out | -1 | -0 | -0 | -- |
| agent_empty_out_4 | -out | -1 | -0 | -0 | -- |
| agent_empty_out_5 | -out | -1 | -0 | -0 | -- |
| agent_empty_out_6 | -out | -1 | -0 | -0 | -- |
| agent_empty_out_7 | -out | -1 | -0 | -0 | -- |
| agent_empty_out_8 | -out | -1 | -0 | -0 | -- |
| agent_full_out_1 | -out | -1 | -0 | -0 | -- |
| agent_full_out_17 | -out | -1 | -0 | -0 | -- |
| agent_full_out_2 | -out | -1 | -0 | -0 | -- |
| agent_full_out_3 | -out | -1 | -0 | -0 | -- |
| agent_full_out_4 | -out | -1 | -0 | -0 | -- |
| agent_full_out_5 | -out | -1 | -0 | -0 | -- |
| agent_full_out_6 | -out | -1 | -0 | -0 | -- |
| agent_full_out_7 | -out | -1 | -0 | -0 | -- |
| agent_full_out_8 | -out | -1 | -0 | -0 | -- |
| agent_msg_addr_in_17 | -in | -32 | -31 | -0 | -- |
| agent_msg_addr_out_17 | -out | -32 | -31 | -0 | -- |
| agent_msg_comm_in_17 | -in | -3 | -2 | -0 | -- |
| agent_msg_comm_out_17 | -out | -3 | -2 | -0 | -- |
| agent_msg_data_in_17 | -in | -32 | -31 | -0 | -- |
| agent_msg_data_out_17 | -out | -32 | -31 | -0 | -- |
| agent_msg_empty_out_17 | -out | -1 | -0 | -0 | -- |
| agent_msg_full_out_17 | -out | -1 | -0 | -0 | -- |
| agent_msg_one_p_out_17 | -out | -1 | -0 | -0 | -- |
| agent_msg_re_in_17 | -in | -1 | -0 | -0 | -- |
| agent_msg_we_in_17 | -in | -1 | -0 | -0 | -- |
| agent_one_d_out_1 | -out | -1 | -0 | -0 | -- |
| agent_one_d_out_2 | -out | -1 | -0 | -0 | -- |
| agent_one_d_out_3 | -out | -1 | -0 | -0 | -- |
| agent_one_d_out_4 | -out | -1 | -0 | -0 | -- |
| agent_one_d_out_5 | -out | -1 | -0 | -0 | -- |
| agent_one_d_out_6 | -out | -1 | -0 | -0 | -- |
| agent_one_d_out_7 | -out | -1 | -0 | -0 | -- |
| agent_one_d_out_8 | -out | -1 | -0 | -0 | -- |
| agent_one_p_out_1 | -out | -1 | -0 | -0 | -- |
| agent_one_p_out_17 | -out | -1 | -0 | -0 | -- |
| agent_one_p_out_2 | -out | -1 | -0 | -0 | -- |
| agent_one_p_out_3 | -out | -1 | -0 | -0 | -- |
| agent_one_p_out_4 | -out | -1 | -0 | -0 | -- |
| agent_one_p_out_5 | -out | -1 | -0 | -0 | -- |
| agent_one_p_out_6 | -out | -1 | -0 | -0 | -- |
| agent_one_p_out_7 | -out | -1 | -0 | -0 | -- |
| agent_one_p_out_8 | -out | -1 | -0 | -0 | -- |
| agent_re_in_1 | -in | -1 | -0 | -0 | -- |
| agent_re_in_17 | -in | -1 | -0 | -0 | -- |
| agent_re_in_2 | -in | -1 | -0 | -0 | -- |
| agent_re_in_3 | -in | -1 | -0 | -0 | -- |
| agent_re_in_4 | -in | -1 | -0 | -0 | -- |
| agent_re_in_5 | -in | -1 | -0 | -0 | -- |
| agent_re_in_6 | -in | -1 | -0 | -0 | -- |
| agent_re_in_7 | -in | -1 | -0 | -0 | -- |
| agent_re_in_8 | -in | -1 | -0 | -0 | -- |
| agent_we_in_1 | -in | -1 | -0 | -0 | -- |
| agent_we_in_17 | -in | -1 | -0 | -0 | -- |
| agent_we_in_2 | -in | -1 | -0 | -0 | -- |
| agent_we_in_3 | -in | -1 | -0 | -0 | -- |
| agent_we_in_4 | -in | -1 | -0 | -0 | -- |
| agent_we_in_5 | -in | -1 | -0 | -0 | -- |
| agent_we_in_6 | -in | -1 | -0 | -0 | -- |
| agent_we_in_7 | -in | -1 | -0 | -0 | -- |
| agent_we_in_8 | -in | -1 | -0 | -0 | -- |
| clk | -in | -1 | -0 | -0 | -- |
| rst_n | -in | -1 | -0 | -0 | -- |
6.3 Bus interfaces
-6.3.1 clk_in
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- clk -
6.3.2 ddr2_ctrl_p
-
- Interface mode: mirroredMaster
- Ports used in this interface:
-
-
-
- agent_comm_in_17 -
- agent_data_in_17 -
- agent_addr_in_17 -
- agent_we_in_17 -
- agent_re_in_17 -
- agent_comm_out_17 -
- agent_data_out_17 -
- agent_addr_out_17 -
- agent_full_out_17 -
- agent_one_p_out_17 -
- agent_empty_out_17 -
- agent_msg_re_in_17 -
- agent_msg_we_in_17 -
- agent_msg_addr_in_17 -
- agent_msg_data_in_17 -
- agent_msg_comm_in_17 -
- agent_msg_full_out_17 -
- agent_msg_one_p_out_17 -
- agent_msg_addr_out_17 -
- agent_msg_data_out_17 -
- agent_msg_comm_out_17 -
- agent_msg_empty_out_17 -
6.3.3 hibi_p1
-
- Interface mode: mirroredMaster
- Ports used in this interface:
-
-
-
- agent_comm_in_1 -
- agent_data_in_1 -
- agent_av_in_1 -
- agent_we_in_1 -
- agent_re_in_1 -
- agent_comm_out_1 -
- agent_data_out_1 -
- agent_av_out_1 -
- agent_full_out_1 -
- agent_one_p_out_1 -
- agent_empty_out_1 -
- agent_one_d_out_1 -
6.3.4 hibi_p2
-
- Interface mode: mirroredMaster
- Ports used in this interface:
-
-
-
- agent_comm_in_2 -
- agent_data_in_2 -
- agent_av_in_2 -
- agent_we_in_2 -
- agent_re_in_2 -
- agent_comm_out_2 -
- agent_data_out_2 -
- agent_av_out_2 -
- agent_full_out_2 -
- agent_one_p_out_2 -
- agent_empty_out_2 -
- agent_one_d_out_2 -
6.3.5 rst_n
-
- Interface mode: slave
- Ports used in this interface:
-
-
-
- rst_n -
6.4 File sets
-6.4.1 hdlSources
-
- Identifiers:
- Default file builders:
-
| File type | -Command | -Flags | -Replace default flags | -
|---|---|---|---|
| vhdlSource | -vcom | --quiet -check_synthesis -work hibi_mem_dma | -false | -
6.4.1.1 Files
-| File name | -Logical name | -Build command | -Build flags | -Specified file types | -Description | -
|---|---|---|---|---|---|
| hibiv2_pkg.vhd | -hibi | -- | - | vhdlSource | -- |
| Hibi_segment.vhd | -hibi | -- | - | vhdlSource | -- |
| addr_data_demuxes.vhd | -hibi | -- | - | vhdlSource | -- |
| addr_data_muxes.vhd | -hibi | -- | - | vhdlSource | -- |
| addr_decoder.vhd | -hibi | -- | - | vhdlSource | -- |
| cfg_init_pkg.vhd | -hibi | -- | - | vhdlSource | -- |
| cfg_mem.vhd | -hibi | -- | - | vhdlSource | -- |
| copy_of_multiclk_fifo.vhd | -hibi | -- | - | vhdlSource | -- |
| double_fifo_demux_wr.vhd | -hibi | -- | - | vhdlSource | -- |
| double_fifo_mux_rd.vhd | -hibi | -- | - | vhdlSource | -- |
| dyn_arb.vhd | -hibi | -- | - | vhdlSource | -- |
| fifo.vhd | -hibi | -- | - | vhdlSource | -- |
| fifo_muxes.vhd | -hibi | -- | - | vhdlSource | -- |
| hibi_wrapper_r1.vhd | -hibi | -- | - | vhdlSource | -- |
| hibi_wrapper_r3.vhd | -hibi | -- | - | vhdlSource | -- |
| hibi_wrapper_r4.vhd | -hibi | -- | - | vhdlSource | -- |
| lfsr.vhd | -hibi | -- | - | vhdlSource | -- |
| receiver.vhd | -hibi | -- | - | vhdlSource | -- |
| rx_ctrl.vhd | -hibi | -- | - | vhdlSource | -- |
| transmitter.vhd | -hibi | -- | - | vhdlSource | -- |
| tx_ctrl.vhd | -hibi | -- | - | vhdlSource | -- |
6.5 Views
-6.5.1 View: rtl
-
- Type: non-hierarchical
- File sets contained in this view:
-
-
-
- hdlSources -
-
-
-
-
trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.png
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.interface.pcie_to_hibi_4x.1.0.png
===================================================================
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.interface.pcie_to_hibi_4x.1.0.png
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.interface.pcie_to_hibi_4x.1.0.png (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.interface.pcie_to_hibi_4x.1.0.png (nonexistent)
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png
===================================================================
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png (nonexistent)
trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.communication.hibi_segment_small.2.0.png
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.structural.png
===================================================================
Cannot display: file marked as a binary type.
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.structural.png
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.structural.png (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.structural.png (nonexistent)
trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.soc.arria_ii_gx_demo_soc.1.0.structural.png
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.hibi_mem_dma.2.0.png
===================================================================
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.hibi_mem_dma.2.0.png
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.hibi_mem_dma.2.0.png (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.hibi_mem_dma.2.0.png (nonexistent)
trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/kactus2_reports/TUT.ip.hwp.storage.hibi_mem_dma.2.0.png
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.docx
===================================================================
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.docx
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.docx (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.docx (nonexistent)
trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.docx
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.mdr
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.mdr (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.mdr (nonexistent)
@@ -1,259 +0,0 @@
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- mIncludePath ""
- mRemoveUsage FALSE
- mGenerateFieldInitializationInClass FALSE
- )
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- mGenEmptyDoc FALSE
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.mdzip
===================================================================
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.mdzip
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.mdzip (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.mdzip (nonexistent)
trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/Arria_II_GX_demo.mdzip
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/fig/Arria_II_GX_demo.pptx
===================================================================
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/fig/Arria_II_GX_demo.pptx
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/fig/Arria_II_GX_demo.pptx (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/fig/Arria_II_GX_demo.pptx (nonexistent)
trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/fig/Arria_II_GX_demo.pptx
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===================================================================
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/fig/arria_ii_gx_demo_00.png
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/fig/arria_ii_gx_demo_00.png (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/fig/arria_ii_gx_demo_00.png (nonexistent)
trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/doc/fig/arria_ii_gx_demo_00.png
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.nios_picture_manipulator.designcfg.1.0.xml
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.nios_picture_manipulator.designcfg.1.0.xml (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.nios_picture_manipulator.designcfg.1.0.xml (nonexistent)
@@ -1,29 +0,0 @@
-
-
-
- TUT
- soc
- arria_ii_gx_demo_soc.nios_picture_manipulator.designcfg
- 1.0
-
- a2_ddr2_dimm_1GB_1
- rtl
-
-
- hibi_mem_dma_1
- rtl
-
-
- hibi_segment_small_1
- rtl
-
-
- nios_ii_1
-
-
- pcie_to_hibi_4x_1
- rtl
-
-
Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.nios_picture_manipulator.design.1.0.xml
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.nios_picture_manipulator.design.1.0.xml (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.nios_picture_manipulator.design.1.0.xml (nonexistent)
@@ -1,372 +0,0 @@
-
-
-
- TUT
- soc
- arria_ii_gx_demo_soc.nios_picture_manipulator.design
- 1.0
-
-
- pcie_to_hibi_4x_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- a2_ddr2_dimm_1GB_1
-
-
-
-
-
-
-
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-
-
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-
-
-
-
-
-
-
- hibi_mem_dma_1
-
- 3
- 32
- 25
- 4
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-
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-
-
-
-
-
-
- nios_ii_1_clk_in_to_a2_ddr2_dimm_1GB_1_phy_clk_out
-
-
- nios_ii_1_hibi_p_to_hibi_segment_small_1_hibi_p2
-
-
- a2_ddr2_dimm_1GB_1_alt_ddr2_p_to_hibi_mem_dma_1_alt_ddr2_p
-
-
- hibi_segment_small_1_ddr2_ctrl_p_to_hibi_mem_dma_1_hibi_p
-
-
- a2_ddr2_dimm_1GB_1_phy_clk_out_to_pcie_to_hibi_4x_1_clk_in
-
-
- hibi_segment_small_1_clk_in_to_a2_ddr2_dimm_1GB_1_phy_clk_out
-
-
- a2_ddr2_dimm_1GB_1_phy_clk_out_to_hibi_mem_dma_1_clk_in
-
-
- hibi_segment_small_1_hibi_p1_to_pcie_to_hibi_4x_1_hibi_p
-
-
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Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.design.1.0.xml
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.design.1.0.xml (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.design.1.0.xml (nonexistent)
@@ -1,374 +0,0 @@
-
-
-
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- soc
- arria_ii_gx_demo_soc.design
- 1.0
-
-
- pcie_to_hibi_4x_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- a2_ddr2_dimm_1GB_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- hibi_mem_dma_1
-
- 3
- 32
- 25
- 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- picture_manip_1
-
-
-
-
-
-
-
-
-
-
-
-
- hibi_segment_small_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- a2_ddr2_dimm_1GB_1_alt_ddr2_p_to_hibi_mem_dma_1_alt_ddr2_p
-
-
- hibi_segment_small_1_ddr2_ctrl_p_to_hibi_mem_dma_1_hibi_p
-
-
- a2_ddr2_dimm_1GB_1_phy_clk_out_to_pcie_to_hibi_4x_1_clk_in
-
-
- hibi_segment_small_1_clk_in_to_a2_ddr2_dimm_1GB_1_phy_clk_out
-
-
- a2_ddr2_dimm_1GB_1_phy_clk_out_to_hibi_mem_dma_1_clk_in
-
-
- hibi_segment_small_1_hibi_p1_to_pcie_to_hibi_4x_1_hibi_p
-
-
- hibi_segment_small_1_hibi_p2_to_picture_manip_1_hibi_p
-
-
- a2_ddr2_dimm_1GB_1_phy_clk_out_to_picture_manip_1_clk
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Index: trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.designcfg.1.0.xml
===================================================================
--- trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.designcfg.1.0.xml (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_demo_soc/1.0/arria_ii_gx_demo_soc.designcfg.1.0.xml (nonexistent)
@@ -1,29 +0,0 @@
-
-
-
- TUT
- soc
- arria_ii_gx_demo_soc.designcfg
- 1.0
-
- a2_ddr2_dimm_1GB_1
- rtl
-
-
- hibi_mem_dma_1
- rtl
-
-
- hibi_segment_small_1
- rtl
-
-
- pcie_to_hibi_4x_1
- rtl
-
-
- picture_manip_1
- rtl
-
-
Index: trunk/TUT/soc/arria_ii_gx_template/1.0/arria_ii_gx_template.1.0.xml
===================================================================
--- trunk/TUT/soc/arria_ii_gx_template/1.0/arria_ii_gx_template.1.0.xml (revision 140)
+++ trunk/TUT/soc/arria_ii_gx_template/1.0/arria_ii_gx_template.1.0.xml (nonexistent)
@@ -1,196 +0,0 @@
-
-
-
- TUT
- soc
- arria_ii_gx_template
- 1.0
-
-
-
-
- clkin_bot_p
-
- in
-
- 0
- 0
-
-
-
-
- ddr2_dimm_addr
-
- out
-
- 15
- 0
-
-
-
-
- ddr2_dimm_ba
-
- out
-
- 2
- 0
-
-
-
-
- ddr2_dimm_cas_n
-
- out
-
-
-
- ddr2_dimm_cke
-
- out
-
- 0
- 0
-
-
-
-
- ddr2_dimm_clk
-
- inout
-
- 1
- 0
-
-
-
-
- ddr2_dimm_clk_n
-
- inout
-
- 1
- 0
-
-
-
-
- ddr2_dimm_cs_n
-
- out
-
-
-
- ddr2_dimm_dm
-
- out
-
- 7
- 0
-
-
-
-
- ddr2_dimm_dq
-
- inout
-
- 63
- 0
-
-
-
-
- ddr2_dimm_dqs
-
- inout
-
- 7
- 0
-
-
-
-
- ddr2_dimm_dqs_n
-
- inout
-
- 7
- 0
-
-
-
-
- ddr2_dimm_odt
-
- out
-
-
-
- ddr2_dimm_ras_n
-
- out
-
-
-
- ddr2_dimm_we_n
-
- out
-
- 0
- 0
-
-
-
-
- pcie_refclk_p
-
- in
-
- 0
- 0
-
-
-
-
- pcie_rx_p
-
- in
-
- 3
- 0
-
-
-
-
- pcie_tx_p
-
- out
-
- 3
- 0
-
-
-
-
- user_pb
-
- in
-
- 1
- 0
-
-
-
-
-
-
-
-
- SoC
- HW
- Template
-
-
-
-
Index: trunk/TUT/soc/udp_flood_example_lan91c111/1.0/udp_flood_example_lan91c111.design.1.0.xml
===================================================================
--- trunk/TUT/soc/udp_flood_example_lan91c111/1.0/udp_flood_example_lan91c111.design.1.0.xml (revision 140)
+++ trunk/TUT/soc/udp_flood_example_lan91c111/1.0/udp_flood_example_lan91c111.design.1.0.xml (nonexistent)
@@ -1,209 +0,0 @@
-
-
-
- TUT
- soc
- udp_flood_example_lan91c111.design
- 1.0
-
-
- udp_ip_lan91c111_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- simple_udp_flood_example_1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- altera_stratix2_pll_25_1
-
-
-
-
-
-
-
-
-
-
-
-
- altera_stratix2_pll_25_1_clk_out_to_udp_ip_lan91c111_1_clk
-
-
- altera_stratix2_pll_25_1_clk_out_to_simple_udp_flood_example_1_clk
-
-
- udp_ip_lan91c111_1_app_rx_to_simple_udp_flood_example_1_udp_ip_rx
-
-
- simple_udp_flood_example_1_udp_ip_tx_to_udp_ip_lan91c111_1_app_tx
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Index: trunk/TUT/soc/udp_flood_example_lan91c111/1.0/udp_flood_example_lan91c111.designcfg.1.0.xml
===================================================================
--- trunk/TUT/soc/udp_flood_example_lan91c111/1.0/udp_flood_example_lan91c111.designcfg.1.0.xml (revision 140)
+++ trunk/TUT/soc/udp_flood_example_lan91c111/1.0/udp_flood_example_lan91c111.designcfg.1.0.xml (nonexistent)
@@ -1,9 +0,0 @@
-
-
-
- TUT
- soc
- udp_flood_example_lan91c111.designcfg
- 1.0
-
Index: trunk/TUT/soc/udp_flood_example_lan91c111/1.0/udp_flood_example_lan91c111.1.0.xml
===================================================================
--- trunk/TUT/soc/udp_flood_example_lan91c111/1.0/udp_flood_example_lan91c111.1.0.xml (revision 140)
+++ trunk/TUT/soc/udp_flood_example_lan91c111/1.0/udp_flood_example_lan91c111.1.0.xml (nonexistent)
@@ -1,251 +0,0 @@
-
-
-
- TUT
- soc
- udp_flood_example_lan91c111
- 1.0
-
-
- LAN91C111
- false
-
-
-
- eth_data_inout
-
-
- LAN91C111_eth_data_inout
-
-
-
-
- eth_addr_out
-
-
- LAN91C111_eth_addr_out
-
-
-
-
- eth_interrupt_in
-
-
- LAN91C111_eth_interrupt_in
-
-
-
-
- eth_read_out
-
-
- LAN91C111_eth_read_out
-
-
-
-
- eth_write_out
-
-
- LAN91C111_eth_write_out
-
-
-
-
- eth_nADS_out
-
-
- LAN91C111_eth_nADS_out
-
-
-
-
- eth_nAEN_out
-
-
- LAN91C111_eth_nAEN_out
-
-
-
-
- eth_nBE_out
-
-
- LAN91C111_eth_nBE_out
-
-
-
- 8
- little
-
-
- clk_in
- false
-
-
-
- CLK
-
-
- clk_in_CLK
-
-
-
- 8
- little
-
-
- link_up_out
- false
-
-
-
- gpio_out
-
-
- link_up_out_gpio_out
-
-
-
- 8
- little
-
-
- rst_n
- false
-
-
-
- RESETn
-
-
- rst_n_RESETn
-
-
-
- 8
- little
-
-
-
-
-
- kactusHierarchical
-
-
-
-
- LAN91C111_eth_addr_out
-
- out
-
- 14
- 0
-
-
-
-
- LAN91C111_eth_data_inout
-
- inout
-
- 31
- 0
-
-
-
-
- LAN91C111_eth_interrupt_in
-
- in
-
- 0
- 0
-
-
-
-
- LAN91C111_eth_nADS_out
-
- out
-
- 0
- 0
-
-
-
-
- LAN91C111_eth_nAEN_out
-
- out
-
- 0
- 0
-
-
-
-
- LAN91C111_eth_nBE_out
-
- out
-
- 3
- 0
-
-
-
-
- LAN91C111_eth_read_out
-
- out
-
- 0
- 0
-
-
-
-
- LAN91C111_eth_write_out
-
- out
-
- 0
- 0
-
-
-
-
- clk_in_CLK
-
- in
-
-
-
- link_up_out_gpio_out
-
- out
-
-
-
- rst_n_RESETn
-
- in
-
-
-
-
-