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/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Testbenches/tb_mixed_clk_fifo_v3.vhd
0,0 → 1,229
-------------------------------------------------------------------------------
-- Title : Testbench for design "mixed_clk_fifo"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_mixed_clk_fifo.vhd
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 14.12.2006
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.txt_util.all;
 
-------------------------------------------------------------------------------
 
entity tb_mixed_clk_fifo is
 
end tb_mixed_clk_fifo;
 
-------------------------------------------------------------------------------
 
architecture rtl of tb_mixed_clk_fifo is
 
-- component generics
-- constant re_freq_g : integer := 1;
-- constant we_freq_g : integer := 3;
-- constant Period_re : time := 30 ns;
-- constant Period_we : time := 10 ns;
constant re_freq_g : integer := 2;
constant we_freq_g : integer := 1;
constant Period_re : time := 14 ns;
constant Period_we : time := 18 ns; -- HAS TO BE EVEN due to divide
constant re_faster_c : integer := 1;
 
constant depth_g : integer := 3;
constant data_width_g : integer := 4;
 
-- component ports
signal clk_re : std_logic;
signal clk_we : std_logic;
signal clk_ps_re : std_logic;
signal clk_ps_we : std_logic;
signal rst_n : std_logic;
signal data_to_dut : std_logic_vector (data_width_g-1 downto 0);
signal we_to_dut : std_logic;
signal full_from_dut : std_logic;
signal one_p_from_dut : std_logic;
signal re_to_dut : std_logic;
signal data_from_dut : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_dut : std_logic;
signal one_d_from_dut : std_logic;
signal data_cnt_r : std_logic_vector(data_width_g-1 downto 0);
 
-- to create periods of not reading or not writing,
-- full and empty cases
constant write_phase_c : integer := 7;
constant read_phase_c : integer := 6;
signal read_phase_r : integer;
signal write_phase_r : integer;
signal int_re_r : std_logic;
signal int_we_r : std_logic;
begin -- rtl
 
-- component instantiation
DUT : entity work.mixed_clk_fifo
generic map (
re_faster_g => re_faster_c,
depth_g => depth_g,
data_width_g => data_width_g)
port map (
clk_re => clk_re,
clk_we => clk_we,
clk_ps_re => clk_ps_re,
clk_ps_we => clk_ps_we,
rst_n => rst_n,
data_in => data_to_dut,
we_in => we_to_dut,
full_out => full_from_dut,
one_p_out => one_p_from_dut,
re_in => re_to_dut,
data_out => data_from_dut,
empty_out => empty_from_dut,
one_d_out => one_d_from_dut
);
 
we_to_dut <= (not full_from_dut) and int_we_r;
 
wr : process (clk_we, rst_n)
begin -- process write
if rst_n = '0' then -- asynchronous reset (active low)
data_to_dut <= (others => '0');
write_phase_r <= 0;
int_we_r <= '0';
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if we_to_dut = '1' then
if data_to_dut /= data_to_dut'high then
data_to_dut <= data_to_dut+1;
else
data_to_dut <= (others => '0');
end if;
else
data_to_dut <= data_to_dut;
end if;
 
if write_phase_r < write_phase_c then
write_phase_r <= write_phase_r+1;
int_we_r <= '1';
else
if write_phase_r < write_phase_c*2 then
int_we_r <= '0';
write_phase_r <= write_phase_r+1;
else
write_phase_r <= 0;
end if;
end if;
end if;
 
end process wr;
 
re_to_dut <= not empty_from_dut and int_re_r;
 
re : process (clk_re, rst_n)
begin -- process re
if rst_n = '0' then -- asynchronous reset (active low)
data_cnt_r <= conv_std_logic_vector(0, data_width_g);
read_phase_r <= 0;
int_re_r <= '1';
elsif clk_re'event and clk_re = '1' then -- rising clock edge
 
if re_to_dut = '1' then
assert data_cnt_r = data_from_dut report "wrong value read: " & str(data_from_dut) & "wait: " & str(data_cnt_r) severity error;
if data_cnt_r /= data_cnt_r'high then
data_cnt_r <= data_cnt_r+1;
else
data_cnt_r <= (others => '0');
end if;
else
data_cnt_r <= data_cnt_r;
end if;
 
if read_phase_r < read_phase_c then
int_re_r <= '1';
read_phase_r <= read_phase_r+1;
else
if read_phase_r < read_phase_c*2 then
int_re_r <= '0';
read_phase_r <= read_phase_r+1;
else
int_re_r <= '0';
read_phase_r <= 0;
end if;
end if;
end if;
end process re;
 
 
 
-- clock generation
-- PROC
CLOCK1 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
clktmp := not clktmp;
clk_re <= clktmp;
wait for Period_re/2;
end process CLOCK1;
 
CLOCK2 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
clktmp := not clktmp;
clk_we <= clktmp;
wait for Period_we/2;
end process CLOCK2;
 
CLOCK3 : process -- generate clock signal for design
begin
clk_ps_re <= '1';
wait for 2 ns;
clk_ps_re <= '0';
wait for (Period_re -4 ns);
clk_ps_re <= '1';
wait for 2 ns;
end process CLOCK3;
 
CLOCK4 : process -- generate clock signal for design
begin
clk_ps_we <= '1';
wait for 2 ns;
clk_ps_we <= '0';
wait for (Period_we -4 ns);
clk_ps_we <= '1';
wait for 2 ns;
end process CLOCK4;
 
-- clk_ps_we <= clk_we;
-- clk_ps_re <= clk_re;
 
-- PROC
RESET : process
begin
Rst_n <= '0'; -- Reset the testsystem
wait for 6*Period_re; -- Wait
Rst_n <= '1'; -- de-assert reset
wait;
end process RESET;
 
 
end rtl;
 
-------------------------------------------------------------------------------
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Testbenches/tb_mixed_clk_fifo_v2_fpga.vhd
0,0 → 1,181
-------------------------------------------------------------------------------
-- Title : Testbench for design "mixed_clk_fifo"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_mixed_clk_fifo.vhd
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 08.12.2006
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.txt_util.all;
 
-------------------------------------------------------------------------------
 
entity tb_mixed_clk_fifo is
port (
clk_we : in std_logic;
clk_re : in std_logic;
clk_ps_re : in std_logic;
clk_ps_we : in std_logic;
error_out : out std_logic;
rst_n : in std_logic
);
end tb_mixed_clk_fifo;
 
-------------------------------------------------------------------------------
 
architecture rtl of tb_mixed_clk_fifo is
 
-- component generics
 
constant depth_g : integer := 3;
constant data_width_g : integer := 4;
 
-- component ports
-- signal clk_re : std_logic;
-- signal clk_we : std_logic;
-- signal clk_ps_re : std_logic;
-- signal clk_ps_we : std_logic;
-- signal rst_n : std_logic;
signal data_to_dut : std_logic_vector (data_width_g-1 downto 0);
signal we_to_dut : std_logic;
signal full_from_dut : std_logic;
signal one_p_from_dut : std_logic;
signal re_to_dut : std_logic;
signal data_from_dut : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_dut : std_logic;
signal one_d_from_dut : std_logic;
signal data_cnt_r : std_logic_vector(data_width_g-1 downto 0);
 
-- to create periods of not reading or not writing,
-- full and empty cases
constant write_phase_c : integer := 7;
constant read_phase_c : integer := 6;
signal read_phase_r : integer;
signal write_phase_r : integer;
signal int_re_r : std_logic;
signal int_we_r : std_logic;
begin -- rtl
 
-- component instantiation
DUT : entity work.mixed_clk_fifo
generic map (
depth_g => depth_g,
data_width_g => data_width_g)
port map (
clk_re => clk_re,
clk_we => clk_we,
clk_ps_re => clk_ps_re,
clk_ps_we => clk_ps_we,
rst_n => rst_n,
data_in => data_to_dut,
we_in => we_to_dut,
full_out => full_from_dut,
one_p_out => one_p_from_dut,
re_in => re_to_dut,
data_out => data_from_dut,
empty_out => empty_from_dut,
one_d_out => one_d_from_dut
);
 
we_to_dut <= (not full_from_dut) and int_we_r;
 
wr : process (clk_we, rst_n)
begin -- process write
if rst_n = '0' then -- asynchronous reset (active low)
data_to_dut <= (others => '0');
-- we_to_dut <= '0';
write_phase_r <= 0;
int_we_r <= '0';
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if we_to_dut = '1' then
if data_to_dut /= data_to_dut'high then
data_to_dut <= data_to_dut+1;
else
data_to_dut <= (others => '0');
end if;
else
-- we_to_dut <= '1';
data_to_dut <= data_to_dut;
end if;
 
if write_phase_r < write_phase_c then
write_phase_r <= write_phase_r+1;
int_we_r <= '1';
else
if write_phase_r < write_phase_c*2 then
int_we_r <= '0';
-- we_to_dut <= '0';
write_phase_r <= write_phase_r+1;
else
write_phase_r <= 0;
-- we_to_dut <= '1';
end if;
end if;
end if;
 
end process wr;
 
re_to_dut <= not empty_from_dut and int_re_r;
 
re : process (clk_re, rst_n)
begin -- process re
if rst_n = '0' then -- asynchronous reset (active low)
-- re_to_dut <= '0';
data_cnt_r <= conv_std_logic_vector(0, data_width_g);
read_phase_r <= 0;
int_re_r <= '1';
elsif clk_re'event and clk_re = '1' then -- rising clock edge
error_out <= '0';
if re_to_dut = '1' then
if data_cnt_r /= data_from_dut then
error_out <= '1';
assert data_cnt_r = data_from_dut report "wrong value read: " & str(data_from_dut) & "wait: " & str(data_cnt_r) severity error;
end if;
if data_cnt_r /= data_cnt_r'high then
data_cnt_r <= data_cnt_r+1;
else
data_cnt_r <= (others => '0');
end if;
else
data_cnt_r <= data_cnt_r;
end if;
 
if read_phase_r < read_phase_c then
int_re_r <= '1';
read_phase_r <= read_phase_r+1;
else
if read_phase_r < read_phase_c*2 then
int_re_r <= '0';
read_phase_r <= read_phase_r+1;
else
int_re_r <= '0';
read_phase_r <= 0;
end if;
end if;
end if;
end process re;
 
 
end rtl;
 
-------------------------------------------------------------------------------
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Testbenches/tb_multiclk_fifo.vhd
0,0 → 1,231
-------------------------------------------------------------------------------
-- Title : Testbench for design "multiclk_fifo"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_multiclk_fifo.vhd
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 16.12.2005
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.txt_util.all;
 
-------------------------------------------------------------------------------
 
entity tb_multiclk_fifo is
 
end tb_multiclk_fifo;
 
-------------------------------------------------------------------------------
 
architecture rtl of tb_multiclk_fifo is
 
component multiclk_fifo
generic (
re_freq_g : integer;
we_freq_g : integer;
depth_g : integer;
data_width_g : integer);
port (
clk_re : in std_logic;
clk_we : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic);
end component;
 
-- component generics
constant re_freq_g : integer := 3;
constant we_freq_g : integer := 1;
constant Period_re : time := 10 ns;
constant Period_we : time := 30 ns;
-- constant re_freq_g : integer := 1;
-- constant we_freq_g : integer := 3;
-- constant Period_re : time := 30 ns;
-- constant Period_we : time := 10 ns;
constant re_freq_g : integer := 1;
constant we_freq_g : integer := 1;
constant Period_re : time := 10 ns;
constant Period_we : time := 10 ns;
 
constant depth_g : integer := 3;
constant data_width_g : integer := 4;
 
-- component ports
signal clk_re : std_logic;
signal clk_we : std_logic;
signal rst_n : std_logic;
signal data_to_dut : std_logic_vector (data_width_g-1 downto 0);
signal we_to_dut : std_logic;
signal full_from_dut : std_logic;
signal one_p_from_dut : std_logic;
signal re_to_dut : std_logic;
signal data_from_dut : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_dut : std_logic;
signal one_d_from_dut : std_logic;
signal data_cnt_r : std_logic_vector(data_width_g-1 downto 0);
 
-- to create periods of not reading or not writing,
-- full and empty cases
constant write_phase_c : integer := 7;
constant read_phase_c : integer := 6;
signal read_phase_r : integer;
signal write_phase_r : integer;
signal int_re_r : std_logic;
signal int_we_r : std_logic;
begin -- rtl
 
-- component instantiation
DUT : multiclk_fifo
generic map (
re_freq_g => re_freq_g,
we_freq_g => we_freq_g,
depth_g => depth_g,
data_width_g => data_width_g)
port map (
clk_re => clk_re,
clk_we => clk_we,
rst_n => rst_n,
data_in => data_to_dut,
we_in => we_to_dut,
full_out => full_from_dut,
one_p_out => one_p_from_dut,
re_in => re_to_dut,
data_out => data_from_dut,
empty_out => empty_from_dut,
one_d_out => one_d_from_dut
);
 
we_to_dut <= (not full_from_dut) and int_we_r;
 
wr : process (clk_we, rst_n)
begin -- process write
if rst_n = '0' then -- asynchronous reset (active low)
data_to_dut <= (others => '0');
-- we_to_dut <= '0';
write_phase_r <= 0;
int_we_r <= '0';
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if we_to_dut = '1' then
if data_to_dut /= data_to_dut'high then
data_to_dut <= data_to_dut+1;
else
data_to_dut <= (others => '0');
end if;
else
-- we_to_dut <= '1';
data_to_dut <= data_to_dut;
end if;
 
if write_phase_r < write_phase_c then
write_phase_r <= write_phase_r+1;
int_we_r <= '1';
else
if write_phase_r < write_phase_c*2 then
int_we_r <= '0';
-- we_to_dut <= '0';
write_phase_r <= write_phase_r+1;
else
write_phase_r <= 0;
-- we_to_dut <= '1';
end if;
end if;
end if;
 
end process wr;
 
re_to_dut <= not empty_from_dut and int_re_r;
 
re : process (clk_re, rst_n)
begin -- process re
if rst_n = '0' then -- asynchronous reset (active low)
-- re_to_dut <= '0';
data_cnt_r <= conv_std_logic_vector(0, data_width_g);
read_phase_r <= 0;
int_re_r <= '1';
elsif clk_re'event and clk_re = '1' then -- rising clock edge
 
if re_to_dut = '1' then
assert data_cnt_r = data_from_dut report "wrong value read: " & str(data_from_dut) & "wait: " & str(data_cnt_r) severity error;
if data_cnt_r /= data_cnt_r'high then
data_cnt_r <= data_cnt_r+1;
else
data_cnt_r <= (others => '0');
end if;
else
data_cnt_r <= data_cnt_r;
end if;
 
if read_phase_r < read_phase_c then
int_re_r <= '1';
read_phase_r <= read_phase_r+1;
else
if read_phase_r < read_phase_c*2 then
int_re_r <= '0';
read_phase_r <= read_phase_r+1;
else
int_re_r <= '0';
read_phase_r <= 0;
end if;
end if;
end if;
end process re;
 
 
 
-- clock generation
-- PROC
CLOCK1 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
clktmp := not clktmp;
clk_re <= clktmp;
wait for Period_re/2;
end process CLOCK1;
 
CLOCK2 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
clktmp := not clktmp;
clk_we <= clktmp;
wait for Period_we/2;
end process CLOCK2;
 
-- PROC
RESET : process
begin
Rst_n <= '0'; -- Reset the testsystem
wait for 6*Period_re; -- Wait
Rst_n <= '1'; -- de-assert reset
wait;
end process RESET;
 
 
end rtl;
 
-------------------------------------------------------------------------------
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Testbenches/tb_mixed_clk_fifo_v3_fpga.vhd
0,0 → 1,179
-------------------------------------------------------------------------------
-- Title : Testbench for design "mixed_clk_fifo"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_mixed_clk_fifo.vhd
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 14.12.2006
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.txt_util.all;
 
-------------------------------------------------------------------------------
 
entity tb_mixed_clk_fifo is
generic (
re_faster_g : integer := 0); -- 0 we faster, 1 re
port (
clk_we : in std_logic;
clk_re : in std_logic;
clk_ps_re : in std_logic;
clk_ps_we : in std_logic;
error_out : out std_logic;
rst_n : in std_logic
);
end tb_mixed_clk_fifo;
 
-------------------------------------------------------------------------------
 
architecture rtl of tb_mixed_clk_fifo is
 
-- component generics
 
constant depth_g : integer := 3;
constant data_width_g : integer := 4;
 
-- component ports
-- signal clk_re : std_logic;
-- signal clk_we : std_logic;
-- signal clk_ps_re : std_logic;
-- signal clk_ps_we : std_logic;
-- signal rst_n : std_logic;
signal data_to_dut : std_logic_vector (data_width_g-1 downto 0);
signal we_to_dut : std_logic;
signal full_from_dut : std_logic;
signal one_p_from_dut : std_logic;
signal re_to_dut : std_logic;
signal data_from_dut : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_dut : std_logic;
signal one_d_from_dut : std_logic;
signal data_cnt_r : std_logic_vector(data_width_g-1 downto 0);
 
-- to create periods of not reading or not writing,
-- full and empty cases
constant write_phase_c : integer := 7;
constant read_phase_c : integer := 6;
signal read_phase_r : integer;
signal write_phase_r : integer;
signal int_re_r : std_logic;
signal int_we_r : std_logic;
begin -- rtl
 
-- component instantiation
DUT : entity work.mixed_clk_fifo
generic map (
re_faster_g => re_faster_g,
depth_g => depth_g,
data_width_g => data_width_g)
port map (
clk_re => clk_re,
clk_we => clk_we,
clk_ps_re => clk_ps_re,
clk_ps_we => clk_ps_we,
rst_n => rst_n,
data_in => data_to_dut,
we_in => we_to_dut,
full_out => full_from_dut,
one_p_out => one_p_from_dut,
re_in => re_to_dut,
data_out => data_from_dut,
empty_out => empty_from_dut,
one_d_out => one_d_from_dut
);
 
we_to_dut <= (not full_from_dut) and int_we_r;
 
wr : process (clk_we, rst_n)
begin -- process write
if rst_n = '0' then -- asynchronous reset (active low)
data_to_dut <= (others => '0');
write_phase_r <= 0;
int_we_r <= '0';
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if we_to_dut = '1' then
if data_to_dut /= data_to_dut'high then
data_to_dut <= data_to_dut+1;
else
data_to_dut <= (others => '0');
end if;
else
data_to_dut <= data_to_dut;
end if;
 
if write_phase_r < write_phase_c then
write_phase_r <= write_phase_r+1;
int_we_r <= '1';
else
if write_phase_r < write_phase_c*2 then
int_we_r <= '0';
write_phase_r <= write_phase_r+1;
else
write_phase_r <= 0;
end if;
end if;
end if;
 
end process wr;
 
re_to_dut <= not empty_from_dut and int_re_r;
 
re : process (clk_re, rst_n)
begin -- process re
if rst_n = '0' then -- asynchronous reset (active low)
data_cnt_r <= conv_std_logic_vector(0, data_width_g);
read_phase_r <= 0;
int_re_r <= '1';
elsif clk_re'event and clk_re = '1' then -- rising clock edge
error_out <= '0';
if re_to_dut = '1' then
if data_cnt_r /= data_from_dut then
error_out <= '1';
assert data_cnt_r = data_from_dut report "wrong value read: " & str(data_from_dut) & "wait: " & str(data_cnt_r) severity error;
end if;
if data_cnt_r /= data_cnt_r'high then
data_cnt_r <= data_cnt_r+1;
else
data_cnt_r <= (others => '0');
end if;
else
data_cnt_r <= data_cnt_r;
end if;
 
if read_phase_r < read_phase_c then
int_re_r <= '1';
read_phase_r <= read_phase_r+1;
else
if read_phase_r < read_phase_c*2 then
int_re_r <= '0';
read_phase_r <= read_phase_r+1;
else
int_re_r <= '0';
read_phase_r <= 0;
end if;
end if;
end if;
end process re;
 
 
end rtl;
 
-------------------------------------------------------------------------------
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Testbenches/tb_mixed_clk_fifo_v2.vhd
0,0 → 1,227
-------------------------------------------------------------------------------
-- Title : Testbench for design "mixed_clk_fifo"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_mixed_clk_fifo.vhd
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 14.12.2006
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.txt_util.all;
 
-------------------------------------------------------------------------------
 
entity tb_mixed_clk_fifo is
 
end tb_mixed_clk_fifo;
 
-------------------------------------------------------------------------------
 
architecture rtl of tb_mixed_clk_fifo is
 
-- component generics
-- constant re_freq_g : integer := 1;
-- constant we_freq_g : integer := 3;
-- constant Period_re : time := 30 ns;
-- constant Period_we : time := 10 ns;
constant re_freq_g : integer := 2;
constant we_freq_g : integer := 1;
constant Period_re : time := 20 ns;
constant Period_we : time := 180 ns; -- HAS TO BE EVEN due to divide
 
constant depth_g : integer := 3;
constant data_width_g : integer := 4;
 
-- component ports
signal clk_re : std_logic;
signal clk_we : std_logic;
signal clk_ps_re : std_logic;
signal clk_ps_we : std_logic;
signal rst_n : std_logic;
signal data_to_dut : std_logic_vector (data_width_g-1 downto 0);
signal we_to_dut : std_logic;
signal full_from_dut : std_logic;
signal one_p_from_dut : std_logic;
signal re_to_dut : std_logic;
signal data_from_dut : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_dut : std_logic;
signal one_d_from_dut : std_logic;
signal data_cnt_r : std_logic_vector(data_width_g-1 downto 0);
 
-- to create periods of not reading or not writing,
-- full and empty cases
constant write_phase_c : integer := 7;
constant read_phase_c : integer := 6;
signal read_phase_r : integer;
signal write_phase_r : integer;
signal int_re_r : std_logic;
signal int_we_r : std_logic;
begin -- rtl
 
-- component instantiation
DUT : entity work.mixed_clk_fifo
generic map (
depth_g => depth_g,
data_width_g => data_width_g)
port map (
clk_re => clk_re,
clk_we => clk_we,
clk_ps_re => clk_ps_re,
clk_ps_we => clk_ps_we,
rst_n => rst_n,
data_in => data_to_dut,
we_in => we_to_dut,
full_out => full_from_dut,
one_p_out => one_p_from_dut,
re_in => re_to_dut,
data_out => data_from_dut,
empty_out => empty_from_dut,
one_d_out => one_d_from_dut
);
 
we_to_dut <= (not full_from_dut) and int_we_r;
 
wr : process (clk_we, rst_n)
begin -- process write
if rst_n = '0' then -- asynchronous reset (active low)
data_to_dut <= (others => '0');
write_phase_r <= 0;
int_we_r <= '0';
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if we_to_dut = '1' then
if data_to_dut /= data_to_dut'high then
data_to_dut <= data_to_dut+1;
else
data_to_dut <= (others => '0');
end if;
else
data_to_dut <= data_to_dut;
end if;
 
if write_phase_r < write_phase_c then
write_phase_r <= write_phase_r+1;
int_we_r <= '1';
else
if write_phase_r < write_phase_c*2 then
int_we_r <= '0';
write_phase_r <= write_phase_r+1;
else
write_phase_r <= 0;
end if;
end if;
end if;
 
end process wr;
 
re_to_dut <= not empty_from_dut and int_re_r;
 
re : process (clk_re, rst_n)
begin -- process re
if rst_n = '0' then -- asynchronous reset (active low)
data_cnt_r <= conv_std_logic_vector(0, data_width_g);
read_phase_r <= 0;
int_re_r <= '1';
elsif clk_re'event and clk_re = '1' then -- rising clock edge
 
if re_to_dut = '1' then
assert data_cnt_r = data_from_dut report "wrong value read: " & str(data_from_dut) & "wait: " & str(data_cnt_r) severity error;
if data_cnt_r /= data_cnt_r'high then
data_cnt_r <= data_cnt_r+1;
else
data_cnt_r <= (others => '0');
end if;
else
data_cnt_r <= data_cnt_r;
end if;
 
if read_phase_r < read_phase_c then
int_re_r <= '1';
read_phase_r <= read_phase_r+1;
else
if read_phase_r < read_phase_c*2 then
int_re_r <= '0';
read_phase_r <= read_phase_r+1;
else
int_re_r <= '0';
read_phase_r <= 0;
end if;
end if;
end if;
end process re;
 
 
 
-- clock generation
-- PROC
CLOCK1 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
clktmp := not clktmp;
clk_re <= clktmp;
wait for Period_re/2;
end process CLOCK1;
 
CLOCK2 : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
clktmp := not clktmp;
clk_we <= clktmp;
wait for Period_we/2;
end process CLOCK2;
 
CLOCK3 : process -- generate clock signal for design
begin
clk_ps_re <= '1';
wait for 2 ns;
clk_ps_re <= '0';
wait for (Period_re -4 ns);
clk_ps_re <= '1';
wait for 2 ns;
end process CLOCK3;
 
CLOCK4 : process -- generate clock signal for design
begin
clk_ps_we <= '1';
wait for 2 ns;
clk_ps_we <= '0';
wait for (Period_we -4 ns);
clk_ps_we <= '1';
wait for 2 ns;
end process CLOCK4;
 
-- clk_ps_we <= clk_we;
-- clk_ps_re <= clk_re;
 
-- PROC
RESET : process
begin
Rst_n <= '0'; -- Reset the testsystem
wait for 6*Period_re; -- Wait
Rst_n <= '1'; -- de-assert reset
wait;
end process RESET;
 
 
end rtl;
 
-------------------------------------------------------------------------------
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Vhdl/multiclk_fifo_v3.vhd
0,0 → 1,229
-------------------------------------------------------------------------------
-- Title : Multiclock FIFO
-- Project :
-------------------------------------------------------------------------------
-- File : multiclk_fifo.vhd
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 02.01.2006
-- Description: Synchronous multi-clock FIFO. Note that clock frequencies MUST
-- be realted (synchronized) in order to avoid metastability.
-- Clocks that are asynchronous wrt. each other do not work.
--
-- Note! data must be ready in the data in wrt. faster clock when writing!
-- same applies for re and we
--
-- In this implementation we really utilize both clocks, whch can be a problem
-- in some systems (routing the another clock).
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity multiclk_fifo is
generic (
re_freq_g : integer := 0; -- integer multiple of clk_we
we_freq_g : integer := 0; -- or vice versa
depth_g : integer := 0;
data_width_g : integer := 0
);
port (
clk_re : in std_logic;
clk_we : in std_logic;
rst_n : in std_logic;
 
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
 
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic
);
end multiclk_fifo;
 
architecture rtl of multiclk_fifo is
 
component fifo
generic (
data_width_g : integer;
depth_g : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic);
end component;
 
constant re_per_we_c : integer := re_freq_g / we_freq_g;
constant we_per_re_c : integer := we_freq_g / re_freq_g;
 
-- no 0 to x-1, cuz otherwise range 0 to -1 is possible
signal re_cnt_r : integer range 0 to re_per_we_c;
signal we_cnt_r : integer range 0 to we_per_re_c;
 
signal data_to_fifo : std_logic_vector (data_width_g-1 downto 0);
signal we_to_fifo : std_logic;
signal full_from_fifo : std_logic;
signal one_p_from_fifo : std_logic;
signal re_to_fifo : std_logic;
signal data_from_fifo : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_fifo : std_logic;
signal one_d_from_fifo : std_logic;
signal clk_fifo : std_logic;
signal slow_r : std_logic; -- frequncy halver for slower clock
signal slow_was_r : std_logic;
signal rst_cnt : std_logic;
signal clk_slow : std_logic;
begin -- rtl
 
data_to_fifo <= data_in;
full_out <= full_from_fifo;
one_p_out <= one_p_from_fifo;
data_out <= data_from_fifo;
empty_out <= empty_from_fifo;
one_d_out <= one_d_from_fifo;
 
regular_fifo: fifo
generic map (
data_width_g => data_width_g,
depth_g => depth_g)
port map (
clk => clk_fifo, -- this is the difference
rst_n => rst_n,
data_in => data_to_fifo,
we_in => we_to_fifo,
full_out => full_from_fifo,
one_p_out => one_p_from_fifo,
re_in => re_to_fifo,
data_out => data_from_fifo,
empty_out => empty_from_fifo,
one_d_out => one_d_from_fifo
);
 
process (clk_slow, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
slow_r <= '0';
elsif clk_slow'event and clk_slow = '1' then -- rising clock edge
slow_r <= not slow_r;
end if;
end process;
 
process (clk_fifo, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
slow_was_r <= '0';
elsif clk_fifo'event and clk_fifo = '1' then -- rising clock edge
slow_was_r <= slow_r;
end if;
end process;
nullify: process (slow_r, slow_was_r)
begin -- process nullify
rst_cnt <= slow_was_r xor slow_r;
end process nullify;
re_gt_we : if re_freq_g >= we_freq_g generate
clk_fifo <= clk_re;
clk_slow <= clk_we;
re_to_fifo <= re_in;
 
equal : if re_per_we_c = 1 generate
we_to_fifo <= we_in;
end generate equal;
 
greater : if re_per_we_c > 1 generate
-- re clk is faster than we
gen_we : process (re_cnt_r, we_in, rst_cnt)
begin -- process gen_we
if we_in = '1' then
if re_cnt_r = re_per_we_c-2 and rst_cnt = '0' then
we_to_fifo <= '1';
else
we_to_fifo <= '0';
end if;
else
we_to_fifo <= '0';
end if;
end process gen_we;
 
process (clk_re, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
re_cnt_r <= 0;
elsif clk_re'event and clk_re = '1' then -- rising clock edge
if rst_cnt = '1' then
re_cnt_r <= 0;
else
re_cnt_r <= re_cnt_r+1;
end if;
end if;
end process;
end generate greater;
 
end generate re_gt_we;
 
we_gt_re : if re_freq_g < we_freq_g generate
 
clk_fifo <= clk_we;
clk_slow <= clk_re;
we_to_fifo <= we_in;
 
-- we clk is faster than re
gen_we : process (we_cnt_r, re_in, rst_cnt)
begin -- process gen_we
if re_in = '1' then
if we_cnt_r = we_per_re_c-2 and rst_cnt = '0' then
re_to_fifo <= '1';
else
re_to_fifo <= '0';
end if;
else
re_to_fifo <= '0';
end if;
end process gen_we;
 
process (clk_we, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
we_cnt_r <= 0;
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if rst_cnt = '1' then
we_cnt_r <= 0;
else
we_cnt_r <= we_cnt_r+1;
end if;
end if;
end process;
 
end generate we_gt_re;
end rtl;
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Vhdl/multiclk_fifo_v4.vhd
0,0 → 1,256
-------------------------------------------------------------------------------
-- Title : Multiclock FIFO
-- Project :
-------------------------------------------------------------------------------
-- File : multiclk_fifo.vhd
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 16.08.2006
-- Description: Synchronous multi-clock FIFO. Note that clock frequencies MUST
-- be related (synchronized) in order to avoid metastability.
-- Clocks that are asynchronous wrt. each other do not work.
--
-- Note! data must be ready in the data in wrt. faster clock when writing!
-- same applies for re and we
--
-- This one uses slow full and empty for the corresponding slower clock (i.e.
-- reader is slower -> empty is delayed). eg. empty transition from 1->0 is
-- delayed.
--
-- In this implementation we really utilize both clocks, whch can be a problem
-- in some systems (routing the another clock).
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity multiclk_fifo is
generic (
re_freq_g : integer := 1; -- integer multiple of clk_we
we_freq_g : integer := 1; -- or vice versa
depth_g : integer := 0;
data_width_g : integer := 0
);
port (
clk_re : in std_logic;
clk_we : in std_logic;
rst_n : in std_logic;
 
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
 
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic
);
end multiclk_fifo;
 
architecture rtl of multiclk_fifo is
 
component fifo
generic (
data_width_g : integer;
depth_g : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic);
end component;
 
constant re_per_we_c : integer := re_freq_g / we_freq_g;
constant we_per_re_c : integer := we_freq_g / re_freq_g;
 
-- no 0 to x-1, cuz otherwise range 0 to -1 is possible
signal re_cnt_r : integer range 0 to re_per_we_c;
signal we_cnt_r : integer range 0 to we_per_re_c;
 
signal data_to_fifo : std_logic_vector (data_width_g-1 downto 0);
signal we_to_fifo : std_logic;
signal full_from_fifo : std_logic;
signal one_p_from_fifo : std_logic;
signal re_to_fifo : std_logic;
signal data_from_fifo : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_fifo : std_logic;
signal one_d_from_fifo : std_logic;
signal empty_out_r : std_logic;
signal full_out_r : std_logic;
signal clk_fifo : std_logic;
signal slow_r : std_logic; -- frequncy halver for slower clock
signal slow_was_r : std_logic;
signal rst_cnt : std_logic;
signal clk_slow : std_logic;
begin -- rtl
 
data_to_fifo <= data_in;
full_out <= full_out_r; --from_fifo;
one_p_out <= one_p_from_fifo;
data_out <= data_from_fifo;
empty_out <= empty_out_r; --empty_from_fifo;
one_d_out <= one_d_from_fifo;
 
regular_fifo: fifo
generic map (
data_width_g => data_width_g,
depth_g => depth_g)
port map (
clk => clk_fifo, -- this is the difference
rst_n => rst_n,
data_in => data_to_fifo,
we_in => we_to_fifo,
full_out => full_from_fifo,
one_p_out => one_p_from_fifo,
re_in => re_to_fifo,
data_out => data_from_fifo,
empty_out => empty_from_fifo,
one_d_out => one_d_from_fifo
);
 
process (clk_slow, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
slow_r <= '0';
elsif clk_slow'event and clk_slow = '1' then -- rising clock edge
slow_r <= not slow_r;
end if;
end process;
 
process (clk_fifo, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
slow_was_r <= '0';
elsif clk_fifo'event and clk_fifo = '1' then -- rising clock edge
slow_was_r <= slow_r;
end if;
end process;
nullify: process (slow_r, slow_was_r)
begin -- process nullify
rst_cnt <= slow_was_r xor slow_r;
end process nullify;
re_gt_we : if re_freq_g >= we_freq_g generate
clk_fifo <= clk_re;
clk_slow <= clk_we;
re_to_fifo <= re_in;
 
equal : if re_per_we_c = 1 generate
we_to_fifo <= we_in;
empty_out_r <= empty_from_fifo;
full_out_r <= full_from_fifo;
end generate equal;
 
greater : if re_per_we_c > 1 generate
-- re clk is faster than we
gen_we : process (re_cnt_r, we_in, rst_cnt)
begin -- process gen_we
if we_in = '1' then
if re_cnt_r = re_per_we_c-2 and rst_cnt = '0' then
we_to_fifo <= '1';
else
we_to_fifo <= '0';
end if;
else
we_to_fifo <= '0';
end if;
end process gen_we;
 
empty_out_r <= empty_from_fifo;
process (clk_re, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
re_cnt_r <= 0;
elsif clk_re'event and clk_re = '1' then -- rising clock edge
if rst_cnt = '1' then
re_cnt_r <= 0;
else
re_cnt_r <= re_cnt_r+1;
end if;
 
if re_cnt_r = 0 then
full_out_r <= full_from_fifo;
else
full_out_r <= full_out_r;
end if;
end if;
end process;
end generate greater;
 
end generate re_gt_we;
 
we_gt_re : if re_freq_g < we_freq_g generate
 
clk_fifo <= clk_we;
clk_slow <= clk_re;
we_to_fifo <= we_in;
 
-- we clk is faster than re
gen_we : process (we_cnt_r, re_in, rst_cnt)
begin -- process gen_we
if re_in = '1' then
if we_cnt_r = we_per_re_c-2 and rst_cnt = '0' then
re_to_fifo <= '1';
else
re_to_fifo <= '0';
end if;
else
re_to_fifo <= '0';
end if;
 
end process gen_we;
 
full_out_r <= full_from_fifo;
process (clk_we, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
we_cnt_r <= 0;
empty_out_r <= '1';
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if rst_cnt = '1' then
we_cnt_r <= 0;
else
we_cnt_r <= we_cnt_r+1;
end if;
 
if we_cnt_r = 0 then
empty_out_r <= empty_from_fifo;
else
empty_out_r <= empty_out_r;
end if;
end if;
end process;
 
end generate we_gt_re;
end rtl;
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Vhdl/we_pulse_synchronizer.vhd
0,0 → 1,136
-------------------------------------------------------------------------------
-- Title : Write pulse synchronizer for Mixed clock FIFO
-- Project :
-------------------------------------------------------------------------------
-- File :
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 18.12.2006
-- Description: Re faster than WE
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-- one p may be a bit suspicious if blindly trusted. should not be used.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity we_pulse_synchronizer is
generic (
data_width_g : integer := 0
);
port (
clk_re : in std_logic; -- THIS IS ALWAYS THE FASTER CLOCK!!!
clk_ps_re : in std_logic; -- phase shifted pulse
clk_we : in std_logic;
clk_ps_we : in std_logic; -- phase shifted pulse
rst_n : in std_logic;
 
-- to synchronize clk_we -> clk_re
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
-- from synchronization to clk_re, we pulse width adjusted
data_out : out std_logic_vector (data_width_g-1 downto 0);
we_out : out std_logic;
 
-- From clk_re domain FIFO
full_in : in std_logic;
one_p_in : in std_logic
 
 
);
end we_pulse_synchronizer;
 
architecture rtl of we_pulse_synchronizer is
 
 
signal data_to_fifo : std_logic_vector (data_width_g-1 downto 0);
signal we_to_fifo : std_logic;
signal we_local_r : std_logic;
signal clk_we_was_r : std_logic;
 
signal data_between_r : std_logic_vector (data_width_g-1 downto 0);
signal we_between_r : std_logic;
signal full_between_r : std_logic;
signal one_p_between_r : std_logic;
signal full_from_fifo : std_logic;
signal one_p_from_fifo : std_logic;
signal full_out_r : std_logic;
signal clk_we_period_r : std_logic;
 
signal derived_clk : std_logic;
begin -- rtl
 
full_out <= full_out_r; --from_fifo;
data_out <= data_to_fifo;
we_out <= we_to_fifo;
one_p_from_fifo <= one_p_in;
full_from_fifo <= full_in;
refaster : process (clk_we, rst_n)
begin -- process refaster
if rst_n = '0' then -- asynchronous reset (active low)
full_out_r <= '1';
data_between_r <= (others => '0');
we_between_r <= '0';
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if full_between_r = '0' then
data_between_r <= data_in;
we_between_r <= we_in;
end if;
full_out_r <= full_between_r or one_p_between_r;
end if;
end process refaster;
 
 
derived_clk <= (clk_ps_we nand clk_ps_re) and clk_we;
 
derclk : process (derived_clk, rst_n)
begin -- process derclk
if rst_n = '0' then -- asynchronous reset (active low)
data_to_fifo <= (others => '0');
we_local_r <= '0';
full_between_r <= '0';
one_p_between_r <= '0';
clk_we_period_r <= '0';
elsif derived_clk'event and derived_clk = '1' then -- rising clock edge
if full_from_fifo = '0' then
data_to_fifo <= data_between_r;
we_local_r <= we_between_r;
else
we_local_r <= '0';
end if;
full_between_r <= full_from_fifo;
one_p_between_r <= one_p_from_fifo;
clk_we_period_r <= not clk_we_period_r;
end if;
end process derclk;
 
one_p_out <= one_p_between_r; -- follows one_p_between.
we_to_fifo <= (clk_we_period_r xor clk_we_was_r) and we_local_r;
 
process (clk_re, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
clk_we_was_r <= '0';
elsif clk_re'event and clk_re = '1' then -- rising clock edge
clk_we_was_r <= clk_we_period_r;
end if;
end process;
 
end rtl;
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Vhdl/multiclk_fifo.vhd
0,0 → 1,223
-------------------------------------------------------------------------------
-- Title : Multiclock FIFO
-- Project :
-------------------------------------------------------------------------------
-- File : multiclk_fifo.vhd
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 2010-04-27
-- Description: Synchronous multi-clock FIFO. Note that clock frequencies MUST
-- be realted (synchronized) in order to avoid metastability.
-- Clocks that are asynchronous wrt. each other do not work.
--
-- Note! data must be ready in the data in wrt. faster clock when writing!
-- same applies for re and we
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- This file is part of Transaction Generator.
--
-- Transaction Generator is free software: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Transaction Generator is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity multiclk_fifo is
generic (
re_freq_g : integer := 0; -- integer multiple of clk_we
we_freq_g : integer := 0; -- or vice versa
depth_g : integer := 0;
data_width_g : integer := 0
);
port (
clk_re : in std_logic;
clk_we : in std_logic;
rst_n : in std_logic;
 
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
 
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic
);
end multiclk_fifo;
 
architecture rtl of multiclk_fifo is
 
component fifo
generic (
data_width_g : integer;
depth_g : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic);
end component;
 
constant re_per_we_c : integer := re_freq_g / we_freq_g;
constant we_per_re_c : integer := we_freq_g / re_freq_g;
 
-- no 0 to x-1, cuz otherwise range 0 to -1 is possible
signal re_cnt_r : integer range 0 to re_per_we_c;
signal we_cnt_r : integer range 0 to we_per_re_c;
 
signal data_to_fifo : std_logic_vector (data_width_g-1 downto 0);
signal we_to_fifo : std_logic;
signal full_from_fifo : std_logic;
signal one_p_from_fifo : std_logic;
signal re_to_fifo : std_logic;
signal data_from_fifo : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_fifo : std_logic;
signal one_d_from_fifo : std_logic;
begin -- rtl
 
data_to_fifo <= data_in;
full_out <= full_from_fifo;
one_p_out <= one_p_from_fifo;
data_out <= data_from_fifo;
empty_out <= empty_from_fifo;
one_d_out <= one_d_from_fifo;
 
re_gt_we : if re_freq_g >= we_freq_g generate
 
fifo_re_gt_we : fifo
generic map (
data_width_g => data_width_g,
depth_g => depth_g)
port map (
clk => clk_re, -- this is the difference
rst_n => rst_n,
data_in => data_to_fifo,
we_in => we_to_fifo,
full_out => full_from_fifo,
one_p_out => one_p_from_fifo,
re_in => re_to_fifo,
data_out => data_from_fifo,
empty_out => empty_from_fifo,
one_d_out => one_d_from_fifo
);
 
re_to_fifo <= re_in;
 
equal : if re_per_we_c = 1 generate
we_to_fifo <= we_in;
end generate equal;
 
greater : if re_per_we_c > 1 generate
-- re clk is faster than we
process (clk_re, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
we_to_fifo <= '0';--we_in;
re_cnt_r <= 0;
elsif clk_re'event and clk_re = '1' then -- rising clock edge
if we_in = '1' then
if re_cnt_r = re_per_we_c-2 then
we_to_fifo <= '1';
else
we_to_fifo <= '0';
end if;
if re_cnt_r /= re_per_we_c-1 then
re_cnt_r <= re_cnt_r+1;
else
re_cnt_r <= 0;
end if;
else
we_to_fifo <= '0';
re_cnt_r <= 0;
end if;
end if;
end process;
end generate greater;
 
end generate re_gt_we;
 
we_gt_re : if re_freq_g < we_freq_g generate
 
fifo_re_gt_we : fifo
generic map (
data_width_g => data_width_g,
depth_g => depth_g)
port map (
clk => clk_we,
rst_n => rst_n,
data_in => data_to_fifo,
we_in => we_to_fifo,
full_out => full_from_fifo,
one_p_out => one_p_from_fifo,
re_in => re_to_fifo,
data_out => data_from_fifo,
empty_out => empty_from_fifo,
one_d_out => one_d_from_fifo
);
 
we_to_fifo <= we_in;
 
-- we clk is faster than re
process (clk_we, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
re_to_fifo <= '0';--re_in;
we_cnt_r <= 0;
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if re_in = '1' then
if we_cnt_r = we_per_re_c-2 then
re_to_fifo <= '1';
else
re_to_fifo <= '0';
end if;
if we_cnt_r /= we_per_re_c-1 then
we_cnt_r <= we_cnt_r+1;
else
we_cnt_r <= 0;
end if;
else
re_to_fifo <= '0';
we_cnt_r <= 0;
end if;
end if;
end process;
 
end generate we_gt_re;
end rtl;
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Vhdl/mixed_clk_fifo_v2.vhd
0,0 → 1,169
-------------------------------------------------------------------------------
-- Title : Mixed clock FIFO
-- Project :
-------------------------------------------------------------------------------
-- File :
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 14.12.2006
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-- Works in fpga testbench.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity mixed_clk_fifo is
generic (
depth_g : integer := 0;
data_width_g : integer := 0
);
port (
clk_re : in std_logic;
clk_ps_re : in std_logic; -- phase shifted pulse
clk_we : in std_logic;
clk_ps_we : in std_logic; -- phase shifted pulse
rst_n : in std_logic;
 
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
 
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic
);
end mixed_clk_fifo;
 
architecture rtl of mixed_clk_fifo is
 
component fifo
generic (
data_width_g : integer;
depth_g : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic);
end component;
 
signal data_to_fifo : std_logic_vector (data_width_g-1 downto 0);
signal we_to_fifo : std_logic;
signal we_local_r : std_logic;
signal clk_we_was_r : std_logic;
 
signal data_between_r : std_logic_vector (data_width_g-1 downto 0);
signal we_between_r : std_logic;
signal full_between_r : std_logic;
signal one_p_between_r : std_logic;
signal full_from_fifo : std_logic;
signal one_p_from_fifo : std_logic;
signal re_to_fifo : std_logic;
signal data_from_fifo : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_fifo : std_logic;
signal one_d_from_fifo : std_logic;
signal empty_out_r : std_logic;
signal full_out_r : std_logic;
signal clk_we_period_r : std_logic;
 
signal derived_clk : std_logic;
begin -- rtl
 
full_out <= full_out_r; --from_fifo;
data_out <= data_from_fifo;
empty_out <= empty_from_fifo;
 
regular_fifo : fifo
generic map (
data_width_g => data_width_g,
depth_g => depth_g)
port map (
clk => clk_re,
rst_n => rst_n,
data_in => data_to_fifo,
we_in => we_to_fifo,
full_out => full_from_fifo,
one_p_out => one_p_from_fifo,
re_in => re_in,
data_out => data_from_fifo,
empty_out => empty_from_fifo,
one_d_out => one_d_from_fifo
);
 
-----------------------------------------------------------------------------
-- RE CLK IS FASTER
process (clk_we, rst_n)
begin -- process wefaster
if rst_n = '0' then -- asynchronous reset (active low)
full_out_r <= '1';
data_between_r <= (others => '0');
we_between_r <= '0';
elsif clk_we'event and clk_we = '1' then -- rising clock edge
if full_between_r = '0' then
data_between_r <= data_in;
we_between_r <= we_in;
end if;
full_out_r <= full_between_r or one_p_between_r;
end if;
end process;
 
 
derived_clk <= (clk_ps_we nand clk_ps_re) and clk_we;
 
derclk : process (derived_clk, rst_n)
begin -- process derclk
if rst_n = '0' then -- asynchronous reset (active low)
data_to_fifo <= (others => '0');
we_local_r <= '0';
full_between_r <= '0';
one_p_between_r <= '0';
clk_we_period_r <= '0';
elsif derived_clk'event and derived_clk = '1' then -- rising clock edge
if full_from_fifo = '0' then
data_to_fifo <= data_between_r;
we_local_r <= we_between_r;
else
we_local_r <= '0';
end if;
full_between_r <= full_from_fifo;
one_p_between_r <= one_p_from_fifo;
clk_we_period_r <= not clk_we_period_r;
end if;
end process derclk;
 
we_to_fifo <= (clk_we_period_r xor clk_we_was_r) and we_local_r;
 
process (clk_re, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
clk_we_was_r <= '0';
elsif clk_re'event and clk_re = '1' then -- rising clock edge
clk_we_was_r <= clk_we_period_r;
end if;
end process;
 
end rtl;
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Vhdl/threeclk_fifo_v1.vhd
0,0 → 1,155
-------------------------------------------------------------------------------
-- Title : Multiclock FIFO
-- Project :
-------------------------------------------------------------------------------
-- File : multiclk_fifo.vhd
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 16.08.2006
-- Description: Synchronous multi-clock FIFO. Note that clock frequencies MUST
-- be related (synchronized) in order to avoid metastability.
-- Clocks that are asynchronous wrt. each other do not work.
--
-- Note! data must be ready in the data in wrt. faster clock when writing!
-- same applies for re and we
--
-- This one uses slow full and empty for the corresponding slower clock (i.e.
-- reader is slower -> empty is delayed). eg. empty transition from 1->0 is
-- delayed.
--
-- In this implementation we really utilize both clocks, whch can be a problem
-- in some systems (routing the another clock).
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity threeclk_fifo is
 
generic (
re_freq_g : integer := 1; -- integer multiple of clk_we
we_freq_g : integer := 1; -- or vice versa
tmp_freq_g : integer := 1; -- integer multiple of both clk_re and clk_we
depth_g : integer := 1;
data_width_g : integer := 1
);
port (
clk_re : in std_logic;
clk_we : in std_logic;
clk_tmp : in std_logic;
rst_n : in std_logic;
 
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
 
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic
);
end threeclk_fifo;
 
architecture structural of threeclk_fifo is
 
-- component multiclk_fifo
-- generic (
-- re_freq_g : integer := 0; -- integer multiple of clk_we
-- we_freq_g : integer := 0; -- or vice versa
-- depth_g : integer := 0;
-- data_width_g : integer := 0
-- );
-- port (
-- clk_re : in std_logic;
-- clk_we : in std_logic;
-- rst_n : in std_logic;
 
-- data_in : in std_logic_vector (data_width_g-1 downto 0);
-- we_in : in std_logic;
-- full_out : out std_logic;
-- one_p_out : out std_logic;
 
-- re_in : in std_logic;
-- data_out : out std_logic_vector (data_width_g-1 downto 0);
-- empty_out : out std_logic;
-- one_d_out : out std_logic
-- );
-- end component;
 
signal data_wef_ref : std_logic_vector (data_width_g-1 downto 0);
signal we_to_ref : std_logic;
signal full_from_ref : std_logic;
signal one_p_from_ref : std_logic;
signal re_to_wef : std_logic;
signal empty_from_wef : std_logic;
 
 
begin -- structural
 
 
 
we_fifo : entity work.multiclk_fifo
generic map (
re_freq_g => tmp_freq_g,
we_freq_g => we_freq_g,
data_width_g => data_width_g,
depth_g => depth_g
)
port map(
clk_we => clk_we,
clk_re => clk_tmp,
rst_n => rst_n,
 
data_in => data_in,
we_in => we_in,
full_out => full_out,
one_p_out => one_p_out,
 
data_out => data_wef_ref,
re_in => re_to_wef,
empty_out => empty_from_wef
--one_d_out
);
 
 
re_to_wef <= not full_from_ref;
we_to_ref <= not empty_from_wef;
 
re_fifo : entity work.multiclk_fifo
generic map (
re_freq_g => re_freq_g,
we_freq_g => tmp_freq_g,
data_width_g => data_width_g,
depth_g => depth_g/2
)
port map(
clk_we => clk_tmp,
clk_re => clk_re,
rst_n => rst_n,
 
data_in => data_wef_ref,
we_in => we_to_ref,
full_out => full_from_ref,
one_p_out => one_p_from_ref,
 
data_out => data_out,
re_in => re_in,
empty_out => empty_out,
one_d_out => one_d_out
);
 
 
 
 
end structural;
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Vhdl/mixed_clk_fifo_v3.vhd
0,0 → 1,207
-------------------------------------------------------------------------------
-- Title : Mixed clock FIFO
-- Project :
-------------------------------------------------------------------------------
-- File :
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 18.12.2006
-- Description: This aims to include possibility to have the
-- synchronization interface on both sides instead of fixed re faster scheme.
--
-- NOTE! one_p may be high when full is also high
-- one_d is high when empty is '0'.
-------------------------------------------------------------------------------
-- Copyright (c) 2005
-- Works in fpga testbench.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity mixed_clk_fifo is
generic (
re_faster_g : integer := 1; -- 0 we faster, 1 re faster.
depth_g : integer := 0;
data_width_g : integer := 0
);
port (
clk_re : in std_logic;
clk_ps_re : in std_logic; -- phase shifted pulse
clk_we : in std_logic;
clk_ps_we : in std_logic; -- phase shifted pulse
rst_n : in std_logic;
 
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
 
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic
);
end mixed_clk_fifo;
 
architecture rtl of mixed_clk_fifo is
 
component fifo
generic (
data_width_g : integer;
depth_g : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic);
end component;
 
component we_pulse_synchronizer
generic (
data_width_g : integer);
port (
clk_re : in std_logic;
clk_ps_re : in std_logic;
clk_we : in std_logic;
clk_ps_we : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
we_out : out std_logic;
full_in : in std_logic;
one_p_in : in std_logic);
end component;
 
component re_pulse_synchronizer
generic (
data_width_g : integer);
port (
clk_re : in std_logic;
clk_ps_re : in std_logic;
clk_we : in std_logic;
clk_ps_we : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector (data_width_g-1 downto 0);
empty_in : in std_logic;
re_out : out std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
re_in : in std_logic;
empty_out : out std_logic);
end component;
signal data_to_fifo : std_logic_vector (data_width_g-1 downto 0);
signal we_to_fifo : std_logic;
 
signal full_from_fifo : std_logic;
signal one_p_from_fifo : std_logic;
signal re_to_fifo : std_logic;
signal data_from_fifo : std_logic_vector (data_width_g-1 downto 0);
signal empty_from_fifo : std_logic;
signal one_d_from_fifo : std_logic;
 
signal full_out_from_synch : std_logic;
signal empty_out_from_synch : std_logic;
signal one_p_from_synch : std_logic;
 
signal clk_fifo : std_logic;
begin -- rtl
 
 
regular_fifo : fifo
generic map (
data_width_g => data_width_g,
depth_g => depth_g)
port map (
clk => clk_fifo,
rst_n => rst_n,
data_in => data_to_fifo,
we_in => we_to_fifo,
full_out => full_from_fifo,
one_p_out => one_p_from_fifo,
re_in => re_to_fifo,
data_out => data_from_fifo,
empty_out => empty_from_fifo,
one_d_out => one_d_from_fifo
);
refaster: if re_faster_g > 0 generate
we_pulse_synchronizer_1: we_pulse_synchronizer
generic map (
data_width_g => data_width_g)
port map (
clk_re => clk_re,
clk_ps_re => clk_ps_re,
clk_we => clk_we,
clk_ps_we => clk_ps_we,
rst_n => rst_n,
-- to/from we domain
data_in => data_in,
we_in => we_in,
full_out => full_out_from_synch,
one_p_out => one_p_from_synch,
-- to/from re domain
data_out => data_to_fifo,
we_out => we_to_fifo,
full_in => full_from_fifo,
one_p_in => one_p_from_fifo);
 
re_to_fifo <= re_in;
data_out <= data_from_fifo;
empty_out <= empty_from_fifo;
-- NOTE! this is for stupid HIBI which does not start when one_p is '1' and
-- addres is coming
one_p_out <= one_p_from_synch;--'0'; --not full_out_from_synch;
full_out <= full_out_from_synch;
one_d_out <= one_d_from_fifo;
 
clk_fifo <= clk_re;
end generate refaster;
 
wefaster: if re_faster_g = 0 generate
re_pulse_synchronizer_1: re_pulse_synchronizer
generic map (
data_width_g => data_width_g)
port map (
clk_re => clk_re,
clk_ps_re => clk_ps_re,
clk_we => clk_we,
clk_ps_we => clk_ps_we,
rst_n => rst_n,
data_in => data_from_fifo,
empty_in => empty_from_fifo,
re_out => re_to_fifo,
data_out => data_out,
re_in => re_in,
empty_out => empty_out_from_synch
);
 
we_to_fifo <= we_in;
full_out <= full_from_fifo;
one_p_out <= one_p_from_fifo;
data_to_fifo <= data_in;
empty_out <= empty_out_from_synch;
one_d_out <= not empty_out_from_synch;
clk_fifo <= clk_we;
end generate wefaster;
end rtl;
/trunk/TUT/ip.hwp.storage/fifos/multi_clk/Vhdl/re_pulse_synchronizer.vhd
0,0 → 1,170
-------------------------------------------------------------------------------
-- Title : Read pulse synchronizer for Mixed clock FIFO
-- WE faster than re
-- Project :
-------------------------------------------------------------------------------
-- File :
-- Author : kulmala3
-- Created : 16.12.2005
-- Last update: 15.12.2006
-- Description: An extra FIFO slot that synchronizes the data between different
-- clock domains
-------------------------------------------------------------------------------
-- Copyright (c) 2005
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 16.12.2005 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity re_pulse_synchronizer is
generic (
data_width_g : integer := 0
);
port (
clk_re : in std_logic; -- THIS IS ALWAYS THE SLOWER CLOCK!!!
clk_ps_re : in std_logic; -- phase shifted pulse
clk_we : in std_logic;
clk_ps_we : in std_logic; -- phase shifted pulse
rst_n : in std_logic;
 
-- from/to we domain
data_in : in std_logic_vector (data_width_g-1 downto 0);
empty_in : in std_logic;
re_out : out std_logic;
 
-- from/to re domain
data_out : out std_logic_vector (data_width_g-1 downto 0);
re_in : in std_logic;
empty_out : out std_logic
 
-- From clk_re domain FIFO
-- full_in : in std_logic;
-- one_p_in : in std_logic
 
 
 
);
end re_pulse_synchronizer;
 
architecture rtl of re_pulse_synchronizer is
 
signal clk_re_was_r : std_logic;
signal clk_re_period_r : std_logic;
 
signal derived_clk : std_logic;
 
signal re_to_fifo : std_logic;
-- signal re_between_r : std_logic;
 
-- signal data_between_r : std_logic_vector(data_width_g-1 downto 0);
signal data_out_r : std_logic_vector(data_width_g-1 downto 0);
signal valid_r : std_logic;
-- signal valid_between_r : std_logic;
signal clk_was_r : std_logic;
signal re_valid_r : std_logic;
signal re_was_r : std_logic;
begin -- rtl
 
derived_clk <= (clk_ps_re nand clk_ps_we) and clk_re;
 
-- read the fifo signals and read to the slot
derclk : process (derived_clk, rst_n)
begin -- process derclk
if rst_n = '0' then -- asynchronous reset (active low)
data_out_r <= (others => '0');
re_to_fifo <= '0';
valid_r <= '0';
clk_re_period_r <= '0';
elsif derived_clk'event and derived_clk = '1' then -- rising clock edge
if re_valid_r = '1' or (re_was_r = '1') then
-- by default, read invalidates data. next if will set again
-- if new one is read instead.
valid_r <= '0';
end if;
if empty_in = '0' and (valid_r = '0' or
(valid_r = '1' and
(re_valid_r = '1' or
(re_was_r = '1' and re_in = '1')))) then
-- read data to output from fifo
re_to_fifo <= '1';
data_out_r <= data_in;
valid_r <= '1';
else
re_to_fifo <= '0';
data_out_r <= data_out_r;
end if;
 
clk_re_period_r <= not clk_re_period_r;
end if;
end process derclk;
 
empty_out <= not valid_r;
data_out <= data_out_r;
re_out <= re_to_fifo and (clk_re_was_r xor clk_re_period_r);
 
re_valid_r <= (clk_was_r xnor clk_re_period_r) and re_in;
 
process (clk_re, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
clk_was_r <= '0';
re_was_r <= '0';
elsif clk_re'event and clk_re = '1' then -- rising clock edge
clk_was_r <= not clk_was_r;
re_was_r <= re_in;
 
end if;
end process;
 
-- refaster : process (clk_re, rst_n)
-- begin -- process refaster
-- if rst_n = '0' then -- asynchronous reset (active low)
-- re_between_r <= '0';
-- valid_r <= '0';
-- data_out_r <= (others => '0');
 
-- elsif clk_re'event and clk_re = '1' then -- rising clock edge
-- if re_in = '1' then
-- -- by default, read invalidates data. next if will set again
-- -- if new one is read instead.
-- valid_r <= '0';
-- end if;
-- if valid_between_r = '0' and (valid_r = '0' or
-- (valid_r = '1' and re_in = '1')) then
-- -- read data to output from fifo
-- re_between_r <= '1';
-- data_out_r <= data_in;
-- valid_r <= '1';
-- else
-- re_between_r <= '0';
-- data_out_r <= data_between_r;
-- end if;
-- end if;
-- end process refaster;
 
 
-- we faster, make the pulse length equal
process (clk_we, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
clk_re_was_r <= '0';
elsif clk_we'event and clk_we = '1' then -- rising clock edge
clk_re_was_r <= clk_re_period_r;
end if;
end process;
 
 
end rtl;
/trunk/TUT/ip.hwp.storage/fifos/fifo.vhd
0,0 → 1,310
-------------------------------------------------------------------------------
-- File : fifo.vhdl
-- Description : General fifo buffer
-- Author : Erno Salminen
-- e-mail : erno.salminen@tut.fi
-- Project :
-- Design :
-- Date : 29.04.2002
-- Modified : 30.04.2002 Vesa Lahtinen Optimized for synthesis
--
-- 15.12.04 ES: names changed
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This file is part of Transaction Generator.
--
-- Transaction Generator is free software: you can redistribute it and/or modify
-- it under the terms of the Lesser GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Transaction Generator is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- Lesser GNU General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with Transaction Generator. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity fifo is
 
generic (
data_width_g : integer := 32;
depth_g : integer := 5
);
port (
clk : in std_logic;
rst_n : in std_logic;
 
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
full_out : out std_logic;
one_p_out : out std_logic;
 
re_in : in std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
empty_out : out std_logic;
one_d_out : out std_logic
);
 
end fifo;
 
architecture behavioral of fifo is
 
 
-- Registers
signal full_r : std_logic;
signal empty_r : std_logic;
signal one_d_r : std_logic;
signal one_p_r : std_logic;
--signal data_amount_r : std_logic_vector (depth_g-1 downto 0);
signal data_amount_r : std_logic_vector (16-1 downto 0);
 
signal in_ptr_r : integer range 0 to depth_g-1;
signal out_ptr_r : integer range 0 to depth_g-1;
 
type data_arr_type is array (depth_g-1 downto 0) of std_logic_vector (data_width_g-1 downto 0);
signal fifo_buffer_r : data_arr_type;
 
 
begin -- behavioral
 
-- Continuous assignments
-- Assigns register values to outputs
full_out <= full_r;
empty_out <= empty_r;
one_d_out <= one_d_r;
one_p_out <= one_p_r;
data_out <= fifo_buffer_r (out_ptr_r); -- mux at output!
-- Note! There is some old value in data output when fifo is empty.
 
Main : process (clk, rst_n)
begin -- process Main
if rst_n = '0' then -- asynchronous reset (active low)
 
-- Reset all registers
-- Fifo is empty at first
full_r <= '0';
empty_r <= '1';
one_d_r <= '0';
in_ptr_r <= 0;
out_ptr_r <= 0;
data_amount_r <= (others => '0');
 
if depth_g =1 then -- 30.07
one_p_r <= '1';
else
one_p_r <= '0';
end if;
 
for i in 0 to depth_g-1 loop
fifo_buffer_r (i) <= (others => '0');
end loop; -- i
 
elsif clk'event and clk = '1' then -- rising clock edge
 
 
-- 1) Write data to fifo
if we_in = '1' and re_in = '0' then
 
if full_r = '0' then
empty_r <= '0';
if (in_ptr_r = (depth_g-1)) then
in_ptr_r <= 0;
else
in_ptr_r <= in_ptr_r + 1;
end if;
out_ptr_r <= out_ptr_r;
data_amount_r <= data_amount_r +1;
fifo_buffer_r (in_ptr_r) <= data_in;
 
-- Check if the fifo is getting full
if data_amount_r + 2 = depth_g then
full_r <= '0';
one_p_r <= '1';
elsif data_amount_r +1 = depth_g then
full_r <= '1';
one_p_r <= '0';
else
full_r <= '0';
one_p_r <= '0';
end if;
 
-- If fifo was empty, it has now one data
if empty_r = '1' then
one_d_r <= '1';
else
one_d_r <= '0';
end if;
 
else
-- in_ptr_r <= in_ptr_r;
-- out_ptr_r <= out_ptr_r;
-- full_r <= full_r;
-- empty_r <= empty_r;
-- fifo_buffer_r <= fifo_buffer_r;
-- data_amount_r <= data_amount_r;
-- one_d_r <= one_d_r;
-- one_p_r <= one_p_r;
end if;
 
-- 2) Read data from fifo
elsif we_in = '0' and re_in = '1' then
 
if empty_r = '0' then
in_ptr_r <= in_ptr_r;
if (out_ptr_r = (depth_g-1)) then
out_ptr_r <= 0;
else
out_ptr_r <= out_ptr_r + 1;
end if;
full_r <= '0';
data_amount_r <= data_amount_r -1;
 
-- Debug
-- fifo_buffer_r (out_ptr_r) <= (others => '1');
 
-- Check if the fifo is getting empty
if data_amount_r = 2 then
empty_r <= '0';
one_d_r <= '1';
elsif data_amount_r = 1 then
empty_r <= '1';
one_d_r <= '0';
else
empty_r <= '0';
one_d_r <= '0';
end if;
 
-- If fifo was full, it is no more
if full_r = '1' then
one_p_r <= '1';
else
one_p_r <= '0';
end if;
 
else
-- in_ptr_r <= in_ptr_r;
-- out_ptr_r <= out_ptr_r;
-- full_r <= full_r;
-- empty_r <= empty_r;
-- fifo_buffer_r <= fifo_buffer_r;
-- data_amount_r <= data_amount_r;
-- one_d_r <= one_d_r;
-- one_p_r <= one_p_r;
end if;
 
 
-- 3) Write and read at the same time
elsif we_in = '1' and re_in = '1' then
 
if full_r = '0' and empty_r = '0' then
if (in_ptr_r = (depth_g-1)) then
in_ptr_r <= 0;
else
in_ptr_r <= in_ptr_r + 1;
end if;
if (out_ptr_r = (depth_g-1)) then
out_ptr_r <= 0;
else
out_ptr_r <= out_ptr_r + 1;
end if;
full_r <= '0';
empty_r <= '0';
data_amount_r <= data_amount_r;
one_d_r <= one_d_r;
one_p_r <= one_p_r;
 
fifo_buffer_r (in_ptr_r) <= data_in;
-- fifo_buffer_r (out_ptr_r) <= (others => '1'); --debug
 
 
elsif full_r = '1' and empty_r = '0' then
-- Fifo is full, only reading is possible
in_ptr_r <= in_ptr_r;
if (out_ptr_r = (depth_g-1)) then
out_ptr_r <= 0;
else
out_ptr_r <= out_ptr_r + 1;
end if;
full_r <= '0';
one_p_r <= '1';
--fifo_buffer_r (out_ptr_r) <= (others => '1'); -- Debug
data_amount_r <= data_amount_r -1;
 
-- Check if the fifo is getting empty
if data_amount_r = 2 then
empty_r <= '0';
one_d_r <= '1';
elsif data_amount_r = 1 then
empty_r <= '1';
one_d_r <= '0';
else
empty_r <= '0';
one_d_r <= '0';
end if;
 
 
elsif full_r = '0' and empty_r = '1' then
-- Fifo is empty, only writing is possible
if (in_ptr_r = (depth_g-1)) then
in_ptr_r <= 0;
else
in_ptr_r <= in_ptr_r + 1;
end if;
out_ptr_r <= out_ptr_r;
empty_r <= '0';
one_d_r <= '1';
fifo_buffer_r (in_ptr_r) <= data_in;
data_amount_r <= data_amount_r +1;
 
-- Check if the fifo is getting full
if data_amount_r + 2 = depth_g then
full_r <= '0';
one_p_r <= '1';
elsif data_amount_r +1 = depth_g then
full_r <= '1';
one_p_r <= '0';
else
full_r <= '0';
one_p_r <= '0';
end if;
 
 
-- 4) Do nothing, fifo remains idle
else
 
-- in_ptr_r <= in_ptr_r;
-- out_ptr_r <= out_ptr_r;
-- full_r <= full_r;
-- empty_r <= empty_r;
-- fifo_buffer_r <= fifo_buffer_r;
-- data_amount_r <= data_amount_r;
-- one_d_r <= one_d_r;
-- one_p_r <= one_p_r;
end if;
 
else
-- Fifo is idle
-- in_ptr_r <= in_ptr_r;
-- out_ptr_r <= out_ptr_r;
-- full_r <= full_r;
-- empty_r <= empty_r;
-- fifo_buffer_r <= fifo_buffer_r;
-- data_amount_r <= data_amount_r;
-- one_d_r <= one_d_r;
-- one_p_r <= one_p_r;
end if;
 
end if;
end process Main;
 
end behavioral;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Testbench/tb_cdc_fifo_tester.vhd
0,0 → 1,113
-------------------------------------------------------------------------------
-- Title : Testbench for design "cdc_fifo_tester"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_cdc_fifo_tester.vhd
-- Author :
-- Created : 19.12.2006
-- Last update: 19.12.2006
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2006
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 19.12.2006 1.0 AK Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;use ieee.std_logic_1164.all;
 
-------------------------------------------------------------------------------
 
entity tb_cdc_fifo_tester is
 
end tb_cdc_fifo_tester;
 
-------------------------------------------------------------------------------
 
architecture struct of tb_cdc_fifo_tester is
 
component cdc_fifo_tester
generic (
depth_log2_g : integer;
dataw_g : integer);
port (
rd_clk, wr_clk : in std_logic;
rst_n : in std_logic;
pass_out, error_out : out std_logic;
pass_count_out : out std_logic_vector(31 downto 0));
end component;
 
-- component generics
constant depth_log2_g : integer := 3;
constant dataw_g : integer := 30;
 
-- component ports
signal Clk1, Clk2 : std_logic;
signal rst_n : std_logic;
signal pass_out, error_out : std_logic;
signal pass_count_out : std_logic_vector(31 downto 0);
 
-- clock and reset
constant Period1 : time := 100 ns;
constant Period2 : time := 10 ns;
 
begin -- struct
 
assertion: process (Clk1, rst_n)
begin -- process assertion
if rst_n = '0' then -- asynchronous reset (active low)
elsif Clk1'event and Clk1 = '1' then -- rising clock edge
assert error_out = '0' report "Error!" severity error;
end if;
end process assertion;
-- component instantiation
DUT: cdc_fifo_tester
generic map (
depth_log2_g => depth_log2_g,
dataw_g => dataw_g)
port map (
rd_clk => Clk1,
wr_clk => Clk2,
rst_n => rst_n,
pass_out => pass_out,
error_out => error_out,
pass_count_out => pass_count_out);
 
-- clock generation
-- PROC
CLOCK1: process -- generate clock signal for design
variable clktmp: std_logic := '0';
begin
wait for PERIOD1/2;
clktmp := not clktmp;
Clk1 <= clktmp;
end process CLOCK1;
 
-- clock generation
-- PROC
CLOCK2: process -- generate clock signal for design
variable clktmp: std_logic := '0';
begin
wait for PERIOD2/2;
clktmp := not clktmp;
Clk2 <= clktmp;
end process CLOCK2;
-- PROC
RESET: process
begin
Rst_n <= '0'; -- Reset the testsystem
wait for 6*PERIOD1; -- Wait
Rst_n <= '1'; -- de-assert reset
wait;
end process RESET;
 
end struct;
 
-------------------------------------------------------------------------------
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/cdc_fifo_ctrl.vhd
0,0 → 1,206
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.gray_code.all;
 
entity cdc_fifo_ctrl is
generic (
READ_AHEAD_g : integer := 0;
SYNC_CLOCKS_g : integer := 0;
depth_log2_g : integer := 0);
 
port (
rst_n : in std_logic;
 
rd_clk : in std_logic;
rd_en_in : in std_logic;
rd_empty_out : out std_logic;
rd_one_d_out : out std_logic;
rd_addr_out : out std_logic_vector (depth_log2_g-1 downto 0);
 
wr_clk : in std_logic;
wr_en_in : in std_logic;
wr_full_out : out std_logic;
wr_one_p_out : out std_logic;
wr_addr_out : out std_logic_vector (depth_log2_g-1 downto 0)
);
 
end entity cdc_fifo_ctrl;
 
architecture rtl of cdc_fifo_ctrl is
 
 
-- signal wr_counter_synchronized_r : unsigned (depth_log2_g-1 downto 0);
 
 
-- (rd_clk) registers
signal rd_counter_r : unsigned (depth_log2_g-1 downto 0);
signal rd_counter_gray_r : std_logic_vector(depth_log2_g-1 downto 0);
signal wr_counter_gray_sync1_r : std_logic_vector (depth_log2_g-1 downto 0);
signal wr_counter_gray_sync2_r : std_logic_vector (depth_log2_g-1 downto 0);
signal wr_counter_gray_sync3_r : std_logic_vector (depth_log2_g-1 downto 0);
signal rd_empty : std_logic;
-- (wr_clk) registers
signal wr_counter_r : unsigned (depth_log2_g-1 downto 0);
signal wr_counter_gray_r : std_logic_vector(depth_log2_g-1 downto 0);
signal rd_counter_gray_sync1_r : std_logic_vector (depth_log2_g-1 downto 0);
signal rd_counter_gray_sync2_r : std_logic_vector (depth_log2_g-1 downto 0);
signal rd_counter_gray_sync3_r : std_logic_vector (depth_log2_g-1 downto 0);
 
signal rd_counter_next : unsigned (depth_log2_g-1 downto 0);
signal wr_counter_next : unsigned (depth_log2_g-1 downto 0);
 
signal wr_counter_gray_syncd : std_logic_vector(depth_log2_g-1 downto 0);
signal rd_counter_gray_syncd : std_logic_vector(depth_log2_g-1 downto 0);
begin -- architecture rtl
 
-- concurrent assignments
wr_addr_out <= std_logic_vector(wr_counter_r);
 
--AK TESTE CAHNGED
-- data is available at the same clock cylce as the rd_en_in = '1'
readahead : if READ_AHEAD_g /= 0 generate
rd_addr_out <= std_logic_vector(rd_counter_next) when (rd_en_in = '1' and rd_empty = '0') else
std_logic_vector(rd_counter_r);
end generate readahead;
 
-- data is available at the next clock cycle
no_readahead : if READ_AHEAD_g = 0 generate
rd_addr_out <= std_logic_vector(rd_counter_r);
end generate no_readahead;
 
 
-- purpose: counter logic for write address (binary counter + gray counter)
-- type : sequential
-- inputs : wr_clk, rst_n
-- outputs:
wr_counter_next <= wr_counter_r + 1;
write_counter : process (rst_n, wr_clk) is
begin -- process write_counter
if (rst_n = '0') then -- asynchronous reset (active low)
wr_counter_r <= (others => '0');
wr_counter_gray_r <= (others => '0');
wr_counter_gray_sync1_r <= (others => '0');
elsif rising_edge(wr_clk) then -- rising clock edge
-- check also if becoming full
if (wr_en_in = '1') then
wr_counter_r <= wr_counter_next;
wr_counter_gray_r <= gray_encode(wr_counter_next);
end if;
wr_counter_gray_sync1_r <= wr_counter_gray_r;
end if;
end process write_counter;
 
-- purpose: counter logic for read address (binary counter & gray counter)
-- type : sequential
-- inputs : rd_clk, rst_n
-- outputs:
rd_counter_next <= rd_counter_r + 1;
read_counter : process (rd_clk, rst_n) is
begin -- process read_counter
if (rst_n = '0') then -- asynchronous reset (active low)
rd_counter_r <= (others => '0');
rd_counter_gray_r <= (others => '0');
elsif rising_edge(rd_clk) then -- rising clock edge
-- check also if becoming empty
if (rd_en_in = '1') then -- and (not rd_counter_gray_r = wr_counter_gray_syncd)
rd_counter_r <= rd_counter_next;
rd_counter_gray_r <= gray_encode(rd_counter_next);
end if;
end if;
end process read_counter;
 
 
syncd_clocks : if SYNC_CLOCKS_g /= 0 generate
-- use only 1 synchronization register
wr_counter_gray_syncd <= wr_counter_gray_sync1_r;
rd_counter_gray_syncd <= rd_counter_gray_sync1_r;
end generate syncd_clocks;
 
no_syncd_clocks : if SYNC_CLOCKS_g = 0 generate
-- use 2 synchronization registers
-- wr_counter_gray_syncd <= wr_counter_gray_sync2_r;
rd_counter_gray_syncd <= rd_counter_gray_sync2_r;
wr_counter_gray_syncd <= wr_counter_gray_sync3_r;
-- rd_counter_gray_syncd <= rd_counter_gray_sync3_r;
end generate no_syncd_clocks;
 
 
rd_empty_out <= rd_empty;
 
-- purpose: determines whether the fifo is empty or not
-- combinational inputs : rd_counter_r, wr_counter_sync2_r outputs:
-- empty
empty_logic : process (rd_counter_gray_r, wr_counter_gray_syncd,
rd_counter_r) is
begin -- process empty_logic
if (rd_counter_gray_r = wr_counter_gray_syncd) then
rd_empty <= '1';
else
rd_empty <= '0';
end if;
 
if (gray_encode(rd_counter_r+1) = wr_counter_gray_syncd) then
rd_one_d_out <= '1';
else
rd_one_d_out <= '0';
end if;
end process empty_logic;
 
 
 
full_logic : process (rd_counter_gray_syncd, wr_counter_next) is
begin -- process full_logic
if (rd_counter_gray_syncd = gray_encode(wr_counter_next)) then
wr_full_out <= '1';
else
wr_full_out <= '0';
end if;
 
if rd_counter_gray_syncd = gray_encode(wr_counter_next+1) then
wr_one_p_out <= '1';
else
wr_one_p_out <= '0';
end if;
end process full_logic;
 
-- purpose: Synchronizes write counter value to read -side clock domain.
-- type : sequential (avoids meta-stability)
-- inputs : rd_clk, rst_n
-- outputs:
rd_synchronizer : process (rd_clk, rst_n) is
begin -- process rd_synchronizer
if rst_n = '0' then -- asynchronous reset (active low)
-- wr_counter_gray_sync1_r <= (others => '0');
wr_counter_gray_sync2_r <= (others => '0');
wr_counter_gray_sync3_r <= (others => '0');
elsif rising_edge(rd_clk) then -- rising clock edge
-- wr_counter_gray_sync1_r <= wr_counter_gray_r;
wr_counter_gray_sync2_r <= wr_counter_gray_sync1_r;
wr_counter_gray_sync3_r <= wr_counter_gray_sync2_r;
end if;
end process rd_synchronizer;
 
-- purpose: Synchronizes read counter value to write -side clock domain.
-- type : sequential (avoids meta-stability)
-- inputs : wr_clk, rst_n
-- outputs:
wr_synchronizer : process (rst_n, wr_clk) is
begin -- process rd_synchronizer
if rst_n = '0' then -- asynchronous reset (active low)
rd_counter_gray_sync1_r <= (others => '0');
rd_counter_gray_sync2_r <= (others => '0');
rd_counter_gray_sync3_r <= (others => '0');
elsif rising_edge(wr_clk) then -- rising clock edge
rd_counter_gray_sync1_r <= rd_counter_gray_r;
rd_counter_gray_sync2_r <= rd_counter_gray_sync1_r;
rd_counter_gray_sync3_r <= rd_counter_gray_sync2_r;
end if;
end process wr_synchronizer;
 
end architecture rtl;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/async_dpram.vhd
0,0 → 1,18
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity async_dpram is
generic (
addrw_g : integer := 0;
dataw_g : integer := 0);
 
port (
rd_clk, wr_clk : in std_logic;
wr_en_in : in std_logic;
data_in : in std_logic_vector(dataw_g-1 downto 0);
data_out : out std_logic_vector(dataw_g-1 downto 0);
rd_addr_in, wr_addr_in : in std_logic_vector (addrw_g-1 downto 0));
 
end entity async_dpram;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/gray.vhd
0,0 → 1,39
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package gray_code is
 
function gray_encode (B : unsigned) -- binary input
return std_logic_vector; -- gray coded output
 
function gray_decode (G : std_logic_vector) -- gray coded input
return unsigned; -- binary output
 
end package gray_code;
 
package body gray_code is
 
function gray_encode (B : unsigned)
return std_logic_vector is
variable G : std_logic_vector(B'range);
begin
G(B'left) := B(B'left);
for i in B'left - 1 downto B'right loop
G(i) := B(i+1) xor B(i);
end loop; -- i
return G;
end gray_encode;
 
function gray_decode (G : std_logic_vector)
return unsigned is
variable B : unsigned(G'range);
begin
B(G'left) := G(G'left);
for i in G'left - 1 downto G'right loop
B(i) := B(i+1) xor G(i);
end loop; -- i
return B;
end gray_decode;
 
end package body gray_code;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/cdc_fifo_tester.vhd
0,0 → 1,165
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity cdc_fifo_tester is
 
generic (
depth_log2_g : integer := 2;
dataw_g : integer := 30
);
 
port (
rd_clk, wr_clk : in std_logic;
rst_n : in std_logic;
pass_out, error_out : out std_logic;
pass_count_out : out std_logic_vector(31 downto 0));
 
end entity cdc_fifo_tester;
 
architecture rtl of cdc_fifo_tester is
 
signal input_ctr_r : unsigned(dataw_g-1 downto 0);
signal expected_ctr_r : unsigned(dataw_g-1 downto 0);
signal check_r : std_logic;
signal wr_state : integer range 0 to 3 := 0;
 
constant READ_AHEAD_co : integer := 0;
 
signal wr_data_in : std_logic_vector(dataw_g-1 downto 0);
signal rd_data_out : std_logic_vector(dataw_g-1 downto 0);
signal rd_empty_out, wr_full_out : std_logic;
signal wr_en, rd_en : std_logic;
 
signal pass_count_r : unsigned(31 downto 0);
 
signal wr_empty_r : std_logic;
signal rd_full_r : std_logic;
signal wr_empty2_r : std_logic;
signal rd_full2_r : std_logic;
 
signal re_to_fifo : std_logic;
constant wr_wait_c : integer := 10;
signal wr_wait_r : integer range 0 to wr_wait_c-1;
signal we_wait_r : std_logic;
begin -- architecture rtl
 
cdc_fifo_inst : entity work.cdc_fifo
generic map (
READ_AHEAD_g => READ_AHEAD_co,
SYNC_CLOCKS_g => 0,
depth_log2_g => depth_log2_g,
dataw_g => dataw_g)
port map (
rst_n => rst_n,
rd_clk => rd_clk,
rd_en_in => re_to_fifo, --rd_en,
rd_empty_out => rd_empty_out,
rd_data_out => rd_data_out,
wr_clk => wr_clk,
wr_en_in => wr_en,
wr_full_out => wr_full_out,
wr_data_in => wr_data_in);
 
re_to_fifo <= '1';
wr_data_in <= std_logic_vector(input_ctr_r);
pass_count_out <= std_logic_vector(pass_count_r);
 
x : process (wr_state, wr_full_out, rd_empty_out)
begin
if (wr_state < 2) then
-- write inputs as fast as possible.
-- (i.e. write when fifo is not full)
-- read as fast as possible.
-- (i.e. read when fifo is not empty)
wr_en <= not wr_full_out;
rd_en <= not rd_empty_out;
elsif (wr_state = 2) then
-- write inputs "as slow as possible"!
-- (i.e. write only when fifo is empty)
-- read whne fifo is not empty.
-- wr_en <= wr_empty2_r;
-- wr_en <= not wr_full_out;
wr_en <= we_wait_r;
rd_en <= not rd_empty_out;
else
-- write inputs as fast as possible.
-- (i.e. write when fifo is not full)
-- read only when fifo is full
wr_en <= not wr_full_out;
rd_en <= not rd_empty_out;
--rd_en <= rd_full2_r;
end if;
end process x;
 
inproc : process (wr_clk, rst_n) is
begin -- process inproc
if rst_n = '0' then -- asynchronous reset (active low)
input_ctr_r <= (others => '0');
wr_state <= 0;
pass_out <= '0';
pass_count_r <= (others => '0');
wr_empty_r <= '0';
wr_empty2_r <= '0';
wr_wait_r <= 0;
we_wait_r <= '0';
elsif rising_edge(wr_clk) then -- rising clock edge
wr_empty_r <= rd_empty_out;
wr_empty2_r <= wr_empty_r;
 
if (wr_en = '1') then
input_ctr_r <= input_ctr_r + 1;
 
pass_out <= '0';
-- change state when pass/round done
if (input_ctr_r = 2**dataw_g - 1) then
wr_state <= (wr_state + 1) mod 4;
pass_out <= '1';
pass_count_r <= pass_count_r + 1;
input_ctr_r <= (others => '0');
end if;
end if;
 
if wr_state = 2 then
if wr_wait_r < wr_wait_c-1 then
wr_wait_r <= wr_wait_r+1;
we_wait_r <= '0';
else
we_wait_r <= '1' and (not wr_full_out);
end if;
else
wr_wait_r <= 0;
end if;
end if;
end process inproc;
 
 
 
outchecker : process (rd_clk, rst_n) is
begin -- process outcheker
if rst_n = '0' then -- asynchronous reset (active low)
expected_ctr_r <= (others => '0');
check_r <= '0';
error_out <= '0';
rd_full_r <= '0';
rd_full2_r <= '0';
elsif rising_edge(rd_clk) then -- rising clock edge
check_r <= rd_en;
rd_full_r <= wr_full_out;
rd_full2_r <= rd_full_r;
if ((check_r = '1' and READ_AHEAD_co = 0) or
(rd_en = '1' and READ_AHEAD_co /= 0)) then
if (std_logic_vector(expected_ctr_r) /= rd_data_out) then
assert (false) report "test failed!" severity failure;
error_out <= '1';
end if;
expected_ctr_r <= expected_ctr_r + 1;
end if;
end if;
end process outchecker;
 
end architecture rtl;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/Test_codes/async_dpram_generic_v2.vhd
0,0 → 1,34
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
architecture rtl of async_dpram is
 
type mem_t is array (0 to 2**addrw_g - 1) of std_logic_vector(dataw_g-1 downto 0);
 
signal memory : mem_t;
signal wr_addr, rd_addr : integer;
signal data_out_r : std_logic_vector(dataw_g-1 downto 0);
begin -- architecture rtl
 
wr_addr <= to_integer (unsigned(wr_addr_in));
rd_addr <= to_integer (unsigned(rd_addr_in));
data_out <= data_out_r;
 
wr : process (wr_en_in, data_in) is
begin -- process write
-- if rising_edge(wr_clk) then -- rising clock edge
if (wr_en_in = '1') then
memory(wr_addr) <= data_in;
end if;
-- end if;
end process wr;
-- data_out_r <= memory(rd_addr);
-- rd : process (rd_clk) is
-- begin -- process rd
-- if rising_edge(rd_clk) then
data_out_r <= memory(rd_addr);
-- end if;
-- end process rd;
 
end architecture rtl;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/Test_codes/async_dpram_altsyncram_v2.vhd
0,0 → 1,45
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
architecture rtl of async_dpram is
component ram2p_altsyncram_hh41
port (
address_a : in std_logic_vector (3 downto 0);
address_b : in std_logic_vector (3 downto 0) := (others => '1');
clock0 : in std_logic := '1';
clock1 : in std_logic := '1';
data_a : in std_logic_vector (35 downto 0) := (others => '1');
q_b : out std_logic_vector (35 downto 0);
wren_a : in std_logic := '0');
end component;
 
signal ONE : std_logic;
begin -- architecture rtl
ONE <= '1';
--
ram2p_altsyncram_hh41_1: ram2p_altsyncram_hh41
port map (
address_a => '0' & wr_addr_in,
address_b => '0' & rd_addr_in,
clock0 => wr_clk,
clock1 => rd_clk,
data_a => data_in,
q_b => data_out,
wren_a => wr_en_in
);
 
-- generic (
-- addrw_g : integer := 0;
-- dataw_g : integer := 0);
 
-- port (
-- rd_clk, wr_clk : in std_logic;
-- wr_en_in : in std_logic;
-- data_in : in std_logic_vector(dataw_g-1 downto 0);
-- data_out : out std_logic_vector(dataw_g-1 downto 0);
-- rd_addr_in, wr_addr_in : in std_logic_vector (addrw_g-1 downto 0));
 
end architecture rtl;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/Test_codes/cdc_fifo_ctrl_v2.vhd
0,0 → 1,202
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.gray_code.all;
 
entity cdc_fifo_ctrl is
generic (
READ_AHEAD_g : integer := 0;
SYNC_CLOCKS_g : integer := 0;
depth_log2_g : integer := 0);
 
port (
rst_n : in std_logic;
 
rd_clk : in std_logic;
rd_en_in : in std_logic;
rd_empty_out : out std_logic;
rd_one_d_out : out std_logic;
rd_addr_out : out std_logic_vector (depth_log2_g-1 downto 0);
 
wr_clk : in std_logic;
wr_en_in : in std_logic;
wr_full_out : out std_logic;
wr_one_p_out : out std_logic;
wr_addr_out : out std_logic_vector (depth_log2_g-1 downto 0)
);
 
end entity cdc_fifo_ctrl;
 
architecture rtl of cdc_fifo_ctrl is
 
 
-- signal wr_counter_synchronized_r : unsigned (depth_log2_g-1 downto 0);
 
 
-- (rd_clk) registers
signal rd_counter_r : unsigned (depth_log2_g-1 downto 0);
signal rd_counter_gray_r : std_logic_vector(depth_log2_g-1 downto 0);
signal wr_counter_gray_sync1_r : std_logic_vector (depth_log2_g-1 downto 0);
signal wr_counter_gray_sync2_r : std_logic_vector (depth_log2_g-1 downto 0);
signal wr_counter_gray_sync3_r : std_logic_vector (depth_log2_g-1 downto 0);
signal rd_empty : std_logic;
-- (wr_clk) registers
signal wr_counter_r : unsigned (depth_log2_g-1 downto 0);
signal wr_counter_gray_r : std_logic_vector(depth_log2_g-1 downto 0);
signal rd_counter_gray_sync1_r : std_logic_vector (depth_log2_g-1 downto 0);
signal rd_counter_gray_sync2_r : std_logic_vector (depth_log2_g-1 downto 0);
signal rd_counter_gray_sync3_r : std_logic_vector (depth_log2_g-1 downto 0);
 
signal rd_counter_next : unsigned (depth_log2_g-1 downto 0);
signal wr_counter_next : unsigned (depth_log2_g-1 downto 0);
 
signal wr_counter_gray_syncd : std_logic_vector(depth_log2_g-1 downto 0);
signal rd_counter_gray_syncd : std_logic_vector(depth_log2_g-1 downto 0);
begin -- architecture rtl
 
-- concurrent assignments
wr_addr_out <= std_logic_vector(wr_counter_r);
 
-- data is available at the same clock cylce as the rd_en_in = '1'
readahead : if READ_AHEAD_g /= 0 generate
rd_addr_out <= std_logic_vector(rd_counter_next) when (rd_en_in = '1' and rd_empty = '0') else
std_logic_vector(rd_counter_r);
end generate readahead;
 
-- data is available at the next clock cycle
no_readahead : if READ_AHEAD_g = 0 generate
rd_addr_out <= std_logic_vector(rd_counter_r);
end generate no_readahead;
 
 
-- purpose: counter logic for write address (binary counter + gray counter)
-- type : sequential
-- inputs : wr_clk, rst_n
-- outputs:
wr_counter_next <= wr_counter_r + 1;
write_counter : process (rst_n, wr_clk) is
begin -- process write_counter
if (rst_n = '0') then -- asynchronous reset (active low)
wr_counter_r <= (others => '0');
wr_counter_gray_r <= (others => '0');
elsif rising_edge(wr_clk) then -- rising clock edge
-- check also if becoming full
if (wr_en_in = '1') then
wr_counter_r <= wr_counter_next;
wr_counter_gray_r <= gray_encode(wr_counter_next);
end if;
end if;
end process write_counter;
 
-- purpose: counter logic for read address (binary counter & gray counter)
-- type : sequential
-- inputs : rd_clk, rst_n
-- outputs:
rd_counter_next <= rd_counter_r + 1;
read_counter : process (rd_clk, rst_n) is
begin -- process read_counter
if (rst_n = '0') then -- asynchronous reset (active low)
rd_counter_r <= (others => '0');
rd_counter_gray_r <= (others => '0');
elsif rising_edge(rd_clk) then -- rising clock edge
-- check also if becoming empty
if (rd_en_in = '1') then -- and (not rd_counter_gray_r = wr_counter_gray_syncd)
rd_counter_r <= rd_counter_next;
rd_counter_gray_r <= gray_encode(rd_counter_next);
end if;
end if;
end process read_counter;
 
 
syncd_clocks : if SYNC_CLOCKS_g /= 0 generate
-- use only 1 synchronization register
wr_counter_gray_syncd <= wr_counter_gray_sync1_r;
rd_counter_gray_syncd <= rd_counter_gray_sync1_r;
end generate syncd_clocks;
 
no_syncd_clocks : if SYNC_CLOCKS_g = 0 generate
-- use 2 synchronization registers
---- wr_counter_gray_syncd <= wr_counter_gray_sync2_r;
rd_counter_gray_syncd <= rd_counter_gray_sync2_r;
wr_counter_gray_syncd <= wr_counter_gray_sync3_r;
-- rd_counter_gray_syncd <= rd_counter_gray_sync3_r;
end generate no_syncd_clocks;
 
 
rd_empty_out <= rd_empty;
 
-- purpose: determines whether the fifo is empty or not
-- combinational inputs : rd_counter_r, wr_counter_sync2_r outputs:
-- empty
empty_logic : process (rd_counter_gray_r, wr_counter_gray_syncd) is
begin -- process empty_logic
if (rd_counter_gray_r = wr_counter_gray_syncd) then
rd_empty <= '1';
else
rd_empty <= '0';
end if;
 
if (gray_encode(rd_counter_r+1) = wr_counter_gray_syncd) then
rd_one_d_out <= '1';
else
rd_one_d_out <= '0';
end if;
end process empty_logic;
 
 
 
full_logic : process (rd_counter_gray_syncd, wr_counter_next) is
begin -- process full_logic
if (rd_counter_gray_syncd = gray_encode(wr_counter_next)) then
wr_full_out <= '1';
else
wr_full_out <= '0';
end if;
 
if rd_counter_gray_syncd = gray_encode(wr_counter_next+1) then
wr_one_p_out <= '1';
else
wr_one_p_out <= '0';
end if;
end process full_logic;
 
-- purpose: Synchronizes write counter value to read -side clock domain.
-- type : sequential (avoids meta-stability)
-- inputs : rd_clk, rst_n
-- outputs:
rd_synchronizer : process (rd_clk, rst_n) is
begin -- process rd_synchronizer
if rst_n = '0' then -- asynchronous reset (active low)
wr_counter_gray_sync1_r <= (others => '0');
wr_counter_gray_sync2_r <= (others => '0');
wr_counter_gray_sync3_r <= (others => '0');
elsif rising_edge(rd_clk) then -- rising clock edge
wr_counter_gray_sync1_r <= wr_counter_gray_r;
wr_counter_gray_sync2_r <= wr_counter_gray_sync1_r;
wr_counter_gray_sync3_r <= wr_counter_gray_sync2_r;
end if;
end process rd_synchronizer;
 
-- purpose: Synchronizes read counter value to write -side clock domain.
-- type : sequential (avoids meta-stability)
-- inputs : wr_clk, rst_n
-- outputs:
wr_synchronizer : process (rst_n, wr_clk) is
begin -- process rd_synchronizer
if rst_n = '0' then -- asynchronous reset (active low)
rd_counter_gray_sync1_r <= (others => '0');
rd_counter_gray_sync2_r <= (others => '0');
rd_counter_gray_sync3_r <= (others => '0');
elsif rising_edge(wr_clk) then -- rising clock edge
rd_counter_gray_sync1_r <= rd_counter_gray_r;
rd_counter_gray_sync2_r <= rd_counter_gray_sync1_r;
rd_counter_gray_sync3_r <= rd_counter_gray_sync2_r;
end if;
end process wr_synchronizer;
 
end architecture rtl;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/Test_codes/async_dpram_altsyncram.vhd
0,0 → 1,177
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
architecture rtl of async_dpram is
component altsyncram
generic
(
ADDRESS_ACLR_A : string := "UNUSED";
ADDRESS_ACLR_B : string := "NONE";
ADDRESS_REG_B : string := "CLOCK1";
BYTE_SIZE : natural := 8;
BYTEENA_ACLR_A : string := "UNUSED";
BYTEENA_ACLR_B : string := "NONE";
BYTEENA_REG_B : string := "CLOCK1";
CLOCK_ENABLE_INPUT_A : string := "NORMAL";
CLOCK_ENABLE_INPUT_B : string := "NORMAL";
CLOCK_ENABLE_OUTPUT_A : string := "NORMAL";
CLOCK_ENABLE_OUTPUT_B : string := "NORMAL";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
IMPLEMENT_IN_LES : string := "OFF";
INDATA_ACLR_A : string := "UNUSED";
INDATA_ACLR_B : string := "NONE";
INDATA_REG_B : string := "CLOCK1";
INIT_FILE : string := "UNUSED";
INIT_FILE_LAYOUT : string := "PORT_A";
MAXIMUM_DEPTH : natural := 0;
NUMWORDS_A : natural := 0;
NUMWORDS_B : natural := 0;
OPERATION_MODE : string := "BIDIR_DUAL_PORT";
OUTDATA_ACLR_A : string := "NONE";
OUTDATA_ACLR_B : string := "NONE";
OUTDATA_REG_A : string := "UNREGISTERED";
OUTDATA_REG_B : string := "UNREGISTERED";
RAM_BLOCK_TYPE : string := "AUTO";
RDCONTROL_ACLR_B : string := "NONE";
RDCONTROL_REG_B : string := "CLOCK1";
READ_DURING_WRITE_MODE_MIXED_PORTS : string := "DONT_CARE";
WIDTH_A : natural;
WIDTH_B : natural := 1;
WIDTH_BYTEENA_A : natural := 1;
WIDTH_BYTEENA_B : natural := 1;
WIDTHAD_A : natural;
WIDTHAD_B : natural := 1;
WRCONTROL_ACLR_A : string := "UNUSED";
WRCONTROL_ACLR_B : string := "NONE";
WRCONTROL_WRADDRESS_REG_B : string := "CLOCK1";
LPM_HINT : string := "UNUSED";
LPM_TYPE : string := "ALTSYNCRAM"
);
 
port (
wren_a : in std_logic;
address_a : in std_logic_vector(WIDTHAD_A-1 downto 0);
address_b : in std_logic_vector(WIDTHAD_B-1 downto 0);
clock0, clock1, rden_b : in std_logic;
data_a : in std_logic_vector(WIDTH_A-1 downto 0);
data_b : in std_logic_vector(WIDTH_B-1 downto 0);
q_a : out std_logic_vector(WIDTH_A-1 downto 0);
q_b : out std_logic_vector(WIDTH_B-1 downto 0)
);
 
end component;
constant ADDRESS_ACLR_A : STRING := "UNUSED";
constant ADDRESS_ACLR_B : STRING := "NONE";
constant ADDRESS_REG_B : STRING := "CLOCK1";
constant BYTE_SIZE : NATURAL := 8;
constant BYTEENA_ACLR_A : STRING := "UNUSED";
constant BYTEENA_ACLR_B : STRING := "NONE";
constant BYTEENA_REG_B : STRING := "CLOCK1";
constant CLOCK_ENABLE_INPUT_A : STRING := "NORMAL"; -- normal...
constant CLOCK_ENABLE_INPUT_B : STRING := "NORMAL";
constant CLOCK_ENABLE_OUTPUT_A : STRING := "NORMAL";
constant CLOCK_ENABLE_OUTPUT_B : STRING := "NORMAL";
constant INTENDED_DEVICE_FAMILY : STRING := "UNUSED";
constant IMPLEMENT_IN_LES : STRING := "OFF";
constant INDATA_ACLR_A : STRING := "UNUSED";
constant INDATA_ACLR_B : STRING := "NONE";
constant INDATA_REG_B : STRING := "CLOCK1";
constant INIT_FILE : STRING := "UNUSED";
constant INIT_FILE_LAYOUT : STRING := "PORT_A";
constant MAXIMUM_DEPTH : NATURAL := 0;
constant NUMWORDS_A : NATURAL := 2**addrw_g;
constant NUMWORDS_B : NATURAL := 2**addrw_g;
constant OPERATION_MODE : STRING := "DUAL_PORT";
constant OUTDATA_ACLR_A : STRING := "NONE";
constant OUTDATA_ACLR_B : STRING := "NONE";
constant OUTDATA_REG_A : STRING := "UNREGISTERED";
constant OUTDATA_REG_B : STRING := "UNREGISTERED";
constant RAM_BLOCK_TYPE : STRING := "AUTO";
constant RDCONTROL_ACLR_B : STRING := "NONE";
constant RDCONTROL_REG_B : STRING := "CLOCK1";
constant READ_DURING_WRITE_MODE_MIXED_PORTS : STRING := "DONT_CARE";
constant WIDTH_A : NATURAL := dataw_g;
constant WIDTH_B : NATURAL := dataw_g;
constant WIDTH_BYTEENA_A : NATURAL := 1;
constant WIDTH_BYTEENA_B : NATURAL := 1;
constant WIDTHAD_A : NATURAL := addrw_g;
constant WIDTHAD_B : NATURAL := addrw_g;
constant WRCONTROL_ACLR_A : STRING := "UNUSED";
constant WRCONTROL_ACLR_B : STRING := "NONE";
constant WRCONTROL_WRADDRESS_REG_B : STRING := "CLOCK1";
constant LPM_HINT : STRING := "UNUSED";
constant LPM_TYPE : STRING := "ALTSYNCRAM";
 
signal ONE : std_logic;
begin -- architecture rtl
ONE <= '1';
 
altsyncram_1 : altsyncram
generic map (
ADDRESS_ACLR_A => ADDRESS_ACLR_A,
ADDRESS_ACLR_B => ADDRESS_ACLR_B,
ADDRESS_REG_B => ADDRESS_REG_B,
BYTE_SIZE => BYTE_SIZE,
BYTEENA_ACLR_A => BYTEENA_ACLR_A,
BYTEENA_ACLR_B => BYTEENA_ACLR_B,
BYTEENA_REG_B => BYTEENA_REG_B,
CLOCK_ENABLE_INPUT_A => CLOCK_ENABLE_INPUT_A,
CLOCK_ENABLE_INPUT_B => CLOCK_ENABLE_INPUT_B,
CLOCK_ENABLE_OUTPUT_A => CLOCK_ENABLE_OUTPUT_A,
CLOCK_ENABLE_OUTPUT_B => CLOCK_ENABLE_OUTPUT_B,
INTENDED_DEVICE_FAMILY => INTENDED_DEVICE_FAMILY,
IMPLEMENT_IN_LES => IMPLEMENT_IN_LES,
INDATA_ACLR_A => INDATA_ACLR_A,
INDATA_ACLR_B => INDATA_ACLR_B,
INDATA_REG_B => INDATA_REG_B,
INIT_FILE => INIT_FILE,
INIT_FILE_LAYOUT => INIT_FILE_LAYOUT,
MAXIMUM_DEPTH => MAXIMUM_DEPTH,
NUMWORDS_A => NUMWORDS_A,
NUMWORDS_B => NUMWORDS_B,
OPERATION_MODE => OPERATION_MODE,
OUTDATA_ACLR_A => OUTDATA_ACLR_A,
OUTDATA_ACLR_B => OUTDATA_ACLR_B,
OUTDATA_REG_A => OUTDATA_REG_A,
OUTDATA_REG_B => OUTDATA_REG_B,
RAM_BLOCK_TYPE => RAM_BLOCK_TYPE,
RDCONTROL_ACLR_B => RDCONTROL_ACLR_B,
RDCONTROL_REG_B => RDCONTROL_REG_B,
READ_DURING_WRITE_MODE_MIXED_PORTS => READ_DURING_WRITE_MODE_MIXED_PORTS,
WIDTH_A => WIDTH_A,
WIDTH_B => WIDTH_B,
WIDTH_BYTEENA_A => WIDTH_BYTEENA_A,
WIDTH_BYTEENA_B => WIDTH_BYTEENA_B,
WIDTHAD_A => WIDTHAD_A,
WIDTHAD_B => WIDTHAD_B,
WRCONTROL_ACLR_A => WRCONTROL_ACLR_A,
WRCONTROL_ACLR_B => WRCONTROL_ACLR_B,
WRCONTROL_WRADDRESS_REG_B => WRCONTROL_WRADDRESS_REG_B,
LPM_HINT => LPM_HINT,
LPM_TYPE => LPM_TYPE)
port map (
wren_a => wr_en_in,
address_a => wr_addr_in,
address_b => rd_addr_in,
clock0 => wr_clk,
clock1 => rd_clk,
rden_b => ONE,
data_a => data_in,
q_b => data_out
);
 
--
-- generic (
-- addrw_g : integer := 0;
-- dataw_g : integer := 0);
 
-- port (
-- rd_clk, wr_clk : in std_logic;
-- wr_en_in : in std_logic;
-- data_in : in std_logic_vector(dataw_g-1 downto 0);
-- data_out : out std_logic_vector(dataw_g-1 downto 0);
-- rd_addr_in, wr_addr_in : in std_logic_vector (addrw_g-1 downto 0));
 
end architecture rtl;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/cdc_fifo.vhd
0,0 → 1,100
-------------------------------------------------------------------------------
-- Title : Gray counter based mixed clock FIFO
-- Project :
-------------------------------------------------------------------------------
-- File : cdc_fifo.vhd
-- Author :
-- Created : 19.12.2006
-- Last update: 19.12.2006
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2006
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2006 1.0 Timo Alho Created
-- 19.12.2006 Ari Kulmala Comments. header. one p and one d
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity cdc_fifo is
generic (
READ_AHEAD_g : integer := 0;
SYNC_CLOCKS_g : integer := 0; -- 0 two flop synch, otherwise 1 flop synch
depth_log2_g : integer := 5;
dataw_g : integer := 32);
 
port (
rst_n : in std_logic;
rd_clk : in std_logic;
rd_en_in : in std_logic;
rd_empty_out : out std_logic;
rd_one_d_out : out std_logic;
rd_data_out : out std_logic_vector(dataw_g-1 downto 0);
 
wr_clk : in std_logic;
wr_en_in : in std_logic;
wr_full_out : out std_logic;
wr_one_p_out : out std_logic;
wr_data_in : in std_logic_vector(dataw_g-1 downto 0)
);
 
end entity cdc_fifo;
 
architecture rtl of cdc_fifo is
 
signal wr_en, rd_en : std_logic;
signal rd_addr, wr_addr : std_logic_vector(depth_log2_g-1 downto 0);
 
signal wr_full, rd_empty : std_logic;
begin -- architecture rtl
 
wr_full_out <= wr_full;
rd_empty_out <= rd_empty;
-- write cannot be '1' when full,
wr_en <= wr_en_in and (not wr_full);
-- read cannot be asserted wen empty
rd_en <= rd_en_in and (not rd_empty);
 
fifo_ram_storage : entity work.async_dpram
generic map (
addrw_g => depth_log2_g,
dataw_g => dataw_g)
port map (
rd_clk => rd_clk,
wr_clk => wr_clk,
wr_en_in => wr_en,
data_in => wr_data_in,
data_out => rd_data_out,
rd_addr_in => rd_addr,
wr_addr_in => wr_addr);
 
cdc_fifo_ctrl_2 : entity work.cdc_fifo_ctrl
generic map (
READ_AHEAD_g => READ_AHEAD_g,
SYNC_CLOCKS_g => SYNC_CLOCKS_g,
depth_log2_g => depth_log2_g)
port map (
rst_n => rst_n,
rd_clk => rd_clk,
rd_en_in => rd_en,
rd_empty_out => rd_empty,
rd_addr_out => rd_addr,
rd_one_d_out => rd_one_d_out,
wr_clk => wr_clk,
wr_en_in => wr_en,
wr_full_out => wr_full,
wr_one_p_out => wr_one_p_out,
wr_addr_out => wr_addr
);
 
end architecture rtl;
/trunk/TUT/ip.hwp.storage/fifos/gray_fifo/Vhdl/async_dpram_generic.vhd
0,0 → 1,34
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
architecture rtl of async_dpram is
 
type mem_t is array (0 to 2**addrw_g - 1) of std_logic_vector(dataw_g-1 downto 0);
 
signal memory : mem_t;
signal wr_addr, rd_addr : integer;
signal data_out_r : std_logic_vector(dataw_g-1 downto 0);
begin -- architecture rtl
 
wr_addr <= to_integer (unsigned(wr_addr_in));
rd_addr <= to_integer (unsigned(rd_addr_in));
data_out <= data_out_r;
 
wr : process (wr_clk) is
begin -- process write
if rising_edge(wr_clk) then -- rising clock edge
if (wr_en_in = '1') then
memory(wr_addr) <= data_in;
end if;
end if;
end process wr;
-- data_out_r <= memory(rd_addr);
rd : process (rd_clk) is
begin -- process rd
if rising_edge(rd_clk) then
data_out_r <= memory(rd_addr);
end if;
end process rd;
 
end architecture rtl;
/trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Testbench/tb_fifo1.vhdl
0,0 → 1,316
-------------------------------------------------------------------------------
-- File : tb_fifo1.vhdl
-- Description : Test bench for Fifo buffer, fifo length = 1!
-- Author : Erno Salminen
-- Date : 29.04.2002
-- Modified : 02.05.2002 Vesa Lahtinen Tests added
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity tb_fifo1 is
end tb_fifo1;
 
architecture behavioral of tb_fifo1 is
 
 
component fifo
 
generic (
width : integer := 0;
depth : integer := 0
);
 
port (
Clk : in std_logic;
Rst_n : std_logic;
Data_In : in std_logic_vector (width-1 downto 0);
Write_Enable : in std_logic;
One_Place_Left : out std_logic;
Full : out std_logic;
Data_Out : out std_logic_vector (width-1 downto 0);
Read_Enable : in std_logic;
Empty : out std_logic;
One_Data_Left : out std_logic
);
end component;
 
constant width : integer := 16;
constant depth : integer := 1; -- !!!
constant PERIOD : time := 10 ns;
 
signal Clk : std_logic;
signal Rst_n : std_logic;
signal Data_In : std_logic_vector (width-1 downto 0);
signal Data_Out : std_logic_vector (width-1 downto 0);
signal Write_Enable : std_logic;
signal Read_Enable : std_logic;
signal Full : std_logic;
signal One_Place_Left : std_logic;
signal Empty : std_logic;
signal One_Data_Left : std_logic;
 
signal Read_Data : std_logic_vector (width-1 downto 0);
 
signal Test_Phase : integer range 0 to 20;
 
begin -- behavioral
 
 
DUT : fifo
generic map (
width => width,
depth => depth)
port map (
Clk => Clk,
Rst_n => Rst_n,
Data_In => Data_In,
Write_Enable => Write_Enable,
Full => Full,
One_Place_Left => One_Place_Left,
Data_Out => Data_Out,
Read_Enable => Read_Enable,
Empty => Empty,
One_Data_Left => One_Data_Left );
 
Generate_input : process
 
-----------------------------------------------------------------------------
-- Two procedures for writing to and for reading the fifo
-----------------------------------------------------------------------------
procedure WriteToFifo (
Data_To_Fifo : in integer;
wait_time : in integer) is
begin --procedure
Read_Enable <= '0'; -- 24.05 es
Data_In <= conv_std_logic_vector (Data_To_Fifo, width);
Write_Enable <= '1';
if Full = '1' then
assert false report "Fifo full. Cannot write" severity note;
end if;
wait for PERIOD;
Write_Enable <= '0';
Data_In <= (others => 'Z');
wait for (wait_time)* PERIOD;
end WriteToFifo;
 
 
procedure ReadFifo (
wait_time : in integer) is
begin --procedure
Write_Enable <= '0'; -- 24.05 es
Read_Enable <= '1';
if Empty = '1' then
assert false report "Fifo empty. Cannot read." severity note;
end if;
wait for PERIOD;
Read_Enable <= '0';
wait for (wait_time)* PERIOD;
 
end ReadFifo;
 
procedure WriteAndReadFifo (
Data_To_Fifo : in integer;
wait_time : in integer) is
begin --procedure
Read_Enable <= '1';
if Empty = '1' then
assert false report "Fifo empty. Cannot read. Writing possible." severity note;
end if;
Data_In <= conv_std_logic_vector (Data_To_Fifo, width);
Write_Enable <= '1';
if Full = '1' then
assert false report "Fifo full. Cannot write. Reading possible." severity note;
end if;
 
 
wait for PERIOD;
Read_Enable <= '0';
Write_Enable <= '0';
Data_In <= (others => 'Z'); -- 24.05 es
wait for (wait_time)* PERIOD;
 
end WriteAndReadFifo;
-----------------------------------------------------------------------------
 
 
 
begin -- process Generate_input
-- test sequence
-- 0 wait for reset
-- 1 write to empty fifo and read so that it is empty again
-- 2 write to fifo until there is only one place left
-- 3 write to fifo so that it becomes full
-- 4 read from full fifo and continue until there is only one data left
-- 5 read the last data
-- write and read the empty fifo at the same time, only write is succesful!
-- 6 write to fifo, write and read at the same time, both should be succesful!
-- 7 write until fifo is full
-- 8 write and read full fifo, only reading succesful!
-- read until fifo is empty
-- 9 make sure fifo is empty
 
 
-- 0 Wait for reset
Write_Enable <= '0';
Read_Enable <= '0';
Data_In <= (others => 'Z');
Test_Phase <= 0;
wait for (6+2)*PERIOD;
wait for PERIOD/2;
wait for PERIOD/3;
 
 
-- At the beginning
-- Full = 0
-- Empty = 1
-- One_Place_Left = 1
-- One_Data_Left = 0
-- NOTE! Empty = One_Place_Left and Full = One_Data_Left
assert Full = '0' report "0: Full not correct" severity error;
assert Empty = '1' report "0: Empty not correct" severity error;
assert One_Data_Left = '0' report "0: One_Data_Left not correct" severity error;
assert One_Place_Left = '1' report "0: One_Place_Left not correct" severity error;
 
-- 1) Write to empty fifo
Test_Phase <= Test_Phase +1;
WriteToFifo (5, 1);
assert Full = '1' report "1: Full not correct" severity error;
assert Empty = '0' report "1: Empty not correct" severity error;
assert One_Data_Left = '1' report "1: One_Data_Left not correct" severity error;
assert One_Place_Left = '0' report "1: One_Place_Left not correct" severity error;
assert Data_Out = conv_std_logic_vector (5, width) report "1: data not stored correctly" severity error;
 
-- 2 )write to full fifo
Test_Phase <=Test_Phase +1;
WriteToFifo (10, 1);
WriteToFifo (11, 1);
WriteToFifo (12, 1);
WriteToFifo (13, 1);
assert Full = '1' report "2: Full not correct" severity error;
assert Empty = '0' report "2: Empty not correct" severity error;
assert One_Data_Left = '1' report "2: One_Data_Left not correct" severity error;
assert One_Place_Left = '0' report "2: One_Place_Left not correct" severity error;
assert Data_Out = conv_std_logic_vector (5, width) report "2: data not stored correctly" severity error;
-- 3) write and read full fifo
-- only read succesful
Test_Phase <= Test_Phase +1;
WriteAndReadFifo (14,2);
assert Full = '0' report "3: Full not correct" severity error;
assert Empty = '1' report "3: Empty not correct" severity error;
assert One_Data_Left = '0' report "3: One_Data_Left not correct" severity error;
assert One_Place_Left = '1' report "3: One_Place_Left not correct" severity error;
 
 
-- 4 read empty fifo
Test_Phase <= Test_Phase +1;
ReadFifo (1);
ReadFifo (1);
ReadFifo (1);
assert Full = '0' report "4: Full not correct" severity error;
assert Empty = '1' report "4: Empty not correct" severity error;
assert One_Data_Left = '0' report "4: One_Data_Left not correct" severity error;
assert One_Place_Left = '1' report "4: One_Place_Left not correct" severity error;
-- 5 write and read empty fifo
Test_Phase <= Test_Phase +1;
WriteAndReadFifo (15,2);
assert Full = '1' report "5: Full not correct" severity error;
assert Empty = '0' report "5: Empty not correct" severity error;
assert One_Data_Left = '1' report "5: One_Data_Left not correct" severity error;
assert One_Place_Left = '0' report "5: One_Place_Left not correct" severity error;
assert Data_Out = conv_std_logic_vector (15, width) report "5: data not stored correctly" severity error;
-- 6 read full fifo
Test_Phase <= Test_Phase +1;
ReadFifo (2);
assert Full = '0' report "6: Full not correct" severity error;
assert Empty = '1' report "6: Empty not correct" severity error;
assert One_Data_Left = '0' report "6: One_Data_Left not correct" severity error;
assert One_Place_Left = '1' report "6: One_Place_Left not correct" severity error;
 
-- 7 other shit
-- ReadFifo (2);
-- WriteToFifo (52, 1);
-- ReadFifo (2);
 
-- WriteToFifo (14, 1);
-- WriteToFifo (15, 1);
-- WriteToFifo (16, 1);
 
-- WriteToFifo (17, 1);
-- ReadFifo (1);
-- ReadFifo (1);
-- ReadFifo (4);
 
-- WriteAndReadFifo (67,2);
-- wait for 5*PERIOD;
-- ReadFifo (1);
-- Test completed
Test_Phase <= 0;
wait;
end process Generate_input;
 
 
 
Read_Data_from_fifo : process (Clk, Rst_n)
begin -- process Read_Data_from_fifo
if Rst_n = '0' then -- asynchronous reset (active low)
Read_Data <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if Read_Enable = '1' then
Read_Data <= Data_Out;
else
Read_Data <= Read_Data;
end if;
end if;
end process Read_Data_from_fifo;
 
 
CLOCK1: process -- generate clock signal for design
variable clktmp: std_logic := '0';
begin
wait for PERIOD/2;
clktmp := not clktmp;
Clk <= clktmp;
end process CLOCK1;
 
RESET: process
begin
Rst_n <= '0'; -- Reset the testsystem
wait for 6*PERIOD; -- Wait
Rst_n <= '1'; -- de-assert reset
wait;
end process RESET;
 
 
end behavioral;
 
 
 
 
 
configuration basic_cfg of tb_fifo1 is
for behavioral
for all : fifo
--use entity work.fifo (inout_mux);
use entity work.fifo (in_mux);
--use entity work.fifo (shift_reg);
end for;
 
end for;
 
 
end basic_cfg;
/trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Testbench/tb_fifo_stratix.vhd
0,0 → 1,188
-------------------------------------------------------------------------------
-- title : tb_fifo_stratix
-- project :
-------------------------------------------------------------------------------
-- file : tb_fifo_stratix.vhdl
-- author : kulmala3
-- created : 08.09.2004
-- last update: 31.05.2005
-- description: tests that fifo_stratix works in fpga. synthesizable test bench
-------------------------------------------------------------------------------
-- revisions :
-- date version author description
-- 08.09.2004 1.0 ak created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity tb_fifo_stratix is
port (
clk : in std_logic;
rst_n : in std_logic;
led_state_out : out std_logic_vector(3 downto 0);
led_error_out : out std_logic_vector(3 downto 0)
);
 
end tb_fifo_stratix;
 
architecture rtl of tb_fifo_stratix is
 
component fifo
generic (
data_width_g : integer;
depth_g : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector (data_width_g-1 downto 0);
we_in : in std_logic;
one_p_out : out std_logic;
full_out : out std_logic;
data_out : out std_logic_vector (data_width_g-1 downto 0);
re_in : in std_logic;
empty_out : out std_logic;
one_d_out : out std_logic);
end component;
 
type ctrl_state is (initial, write_fifo, read_fifo);
 
signal control_r : ctrl_state;
signal write_counter_r : integer range 0 to 2**16-1;
signal read_counter_r : integer range 0 to 2**16-1;
signal read_data_r : integer range 0 to 2**16-1;
signal error_counter_r : integer range 0 to 2**16-1;
 
constant initial_c : std_logic_vector := "0001";
constant write_c : std_logic_vector := "0010";
constant read_c : std_logic_vector := "0100";
 
 
constant width : integer := 16;
constant depth : integer := 5;
 
signal data_to_fifo : std_logic_vector (width-1 downto 0);
signal write_enable : std_logic;
signal one_place_left_r : std_logic;
signal full_r : std_logic;
signal data_from_fifo : std_logic_vector (width-1 downto 0);
signal read_enable : std_logic;
signal empty_r : std_logic;
signal one_data_left_r : std_logic;
 
signal ef_r : std_logic_vector(1 downto 0);
signal temp : std_logic;
begin -- rtl
 
data_to_fifo <= conv_std_logic_vector(write_counter_r, width);
read_data_r <= conv_integer(data_from_fifo);
ef_r <= empty_r & full_r;
led_error_out <= conv_std_logic_vector(error_counter_r, 4);
temp <= one_data_left_r and one_place_left_r;
 
fifo_1 : fifo
generic map (
data_width_g => width,
depth_g => depth)
port map (
clk => clk,
rst_n => rst_n,
data_in => data_to_fifo,
we_in => write_enable,
one_p_out => one_place_left_r,
full_out => full_r,
data_out => data_from_fifo,
re_in => read_enable,
empty_out => empty_r,
one_d_out => one_data_left_r);
 
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
control_r <= initial;
write_enable <= '0';
read_enable <= '0';
write_counter_r <= 0;
read_counter_r <= 1;
-- just to use one_data_left_r and one_place_left_r
led_state_out <= temp & temp & temp & temp;
error_counter_r <= 0;
elsif clk'event and clk = '1' then -- rising clock edge
 
case control_r is
when initial =>
case ef_r is
when "00" | "01" => -- not empty, not full or full-> read
control_r <= read_fifo;
write_enable <= '0';
read_enable <= '0';
when "10" => -- empty, write
control_r <= write_fifo;
write_enable <= '0';
read_enable <= '0';
when others => null; --empty and full, not possible...
end case;
led_state_out <= initial_c;
when write_fifo =>
read_enable <= '0';
if full_r = '0' then -- not yet full
write_enable <= '1';
write_counter_r <= write_counter_r+1;
control_r <= write_fifo;
else
-- fifo full
write_enable <= '0';
-- write_counter_r+1 always written, so we do -1 here.
write_counter_r <= write_counter_r-1;
control_r <= read_fifo;
end if;
led_state_out <= write_c;
when read_fifo =>
write_enable <= '0';
if empty_r = '0' then
read_enable <= '1';
if read_enable = '1' then
if read_data_r /= read_counter_r then
-- error!
assert false report "fifo read error, wrong data" severity error;
if error_counter_r >= 2**4-1 then
error_counter_r <= 0;
else
error_counter_r <= error_counter_r +1;
end if;
-- if something was missing, start from the new data value
read_counter_r <= read_data_r+1;
else
error_counter_r <= error_counter_r;
read_counter_r <= read_counter_r+1;
end if;
control_r <= read_fifo;
end if;
else
-- empty
read_enable <= '0';
read_counter_r <= read_counter_r;
error_counter_r <= error_counter_r;
control_r <= initial;
end if;
 
led_state_out <= read_c;
 
when others => null;
 
end case;
 
end if;
end process;
 
end rtl;
/trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Testbench/tb_fifo2.vhdl
0,0 → 1,338
-------------------------------------------------------------------------------
-- File : tb_fifo2.vhdl
-- Description : Testbench for a Fifo buffer
-- Author : Erno Salminen
-- Date : 29.04.2002
-- Modified : 02.05.2002 Vesa Lahtinen More tests added
-- 18.06.2003 AK - direction for Rst_n signal
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity tb_fifo2 is
end tb_fifo2;
 
architecture behavioral of tb_fifo2 is
 
component fifo
 
generic (
width : integer := 0;
depth : integer := 0
);
 
port (
Clk : in std_logic;
Rst_n : in std_logic;
Data_In : in std_logic_vector (width-1 downto 0);
Write_Enable : in std_logic;
One_Place_Left : out std_logic;
Full : out std_logic;
Data_Out : out std_logic_vector (width-1 downto 0);
Read_Enable : in std_logic;
Empty : out std_logic;
One_Data_Left : out std_logic
);
 
 
end component;
 
 
constant width : integer := 16;
constant depth : integer := 5;
constant PERIOD : time := 10 ns;
 
signal Clk : std_logic;
signal Rst_n : std_logic;
signal Data_In : std_logic_vector (width-1 downto 0);
signal Data_Out : std_logic_vector (width-1 downto 0);
signal Write_Enable : std_logic;
signal Read_Enable : std_logic;
signal Full : std_logic;
signal One_Place_Left : std_logic;
signal Empty : std_logic;
signal One_Data_Left : std_logic;
 
signal Read_Data : std_logic_vector (width-1 downto 0);
signal Test_Phase : integer range 0 to 20;
 
begin -- behavioral
 
 
DUT : fifo
generic map (
width => width,
depth => depth)
port map (
Clk => Clk,
Rst_n => Rst_n,
Data_In => Data_In,
Write_Enable => Write_Enable,
Full => Full,
One_Place_Left => One_Place_Left,
Data_Out => Data_Out,
Read_Enable => Read_Enable,
Empty => Empty,
One_Data_Left => One_Data_Left );
 
Generate_input : process
 
-----------------------------------------------------------------------------
-- Two procedures for writing to and for reading the fifo
-----------------------------------------------------------------------------
procedure WriteToFifo (
Data_To_Fifo : in integer;
wait_time : in integer) is
begin --procedure
Data_In <= conv_std_logic_vector (Data_To_Fifo, width);
Write_Enable <= '1';
if Full = '1' then
--assert false report "Fifo full. Cannot write" severity note;
end if;
wait for PERIOD;
--if wait_time > 0 then
Write_Enable <= '0';
Data_In <= (others => 'Z');
wait for (wait_time)* PERIOD;
--end if;
 
end WriteToFifo;
 
 
procedure ReadFifo (
wait_time : in integer) is
begin --procedure
Read_Enable <= '1';
if Empty = '1' then
--assert false report "Fifo empty. Cannot read" severity note;
end if;
wait for PERIOD;
--if wait_time > 0 then
Read_Enable <= '0';
wait for (wait_time)* PERIOD;
--end if;
 
 
end ReadFifo;
 
procedure WriteAndReadFifo (
Data_To_Fifo : in integer;
wait_time : in integer) is
begin --procedure
Read_Enable <= '1';
if Empty = '1' then
--assert false report "Fifo empty. Cannot read" severity note;
end if;
Data_In <= conv_std_logic_vector (Data_To_Fifo, width);
Write_Enable <= '1';
if Full = '0' then
--assert false report "Fifo full. Cannot write" severity note;
end if;
 
 
wait for PERIOD;
--if wait_time > 0 then
Read_Enable <= '0';
Write_Enable <= '0';
Data_In <= (others => 'Z');
wait for (wait_time)* PERIOD;
--end if;
 
 
end WriteAndReadFifo;
-----------------------------------------------------------------------------
 
 
 
begin -- process Generate_input
 
-- test sequence
-- 0 wait for reset
-- 1 write to empty fifo and read so that it is empty again
-- 2 write to fifo until there is only one place left
-- 3 write to fifo so that it becomes full
-- 4 read from full fifo and continue until there is only one data left
-- 5 read the last data
-- write and read the empty fifo at the same time, only write is succesful!
-- 6 write to fifo, write and read at the same time, both should be succesful!
-- 7 write until fifo is full
-- 8 write and read full fifo, only reading succesful!
-- read until fifo is empty
-- 9 make sure fifo is empty
 
-- Wait for reset
Write_Enable <= '0';
Read_Enable <= '0';
Data_In <= (others => 'Z');
Test_Phase <= 0;
wait for (6+2)*PERIOD;
wait for PERIOD/2;
wait for PERIOD/3;
 
-- 0) At the beginning
-- One_Place_Left = 0
-- Empty = 1
-- Full = 0
-- One_Data_Left = 0
assert One_Data_Left = '0' report "0: One_Place_Left does not work" severity error;
assert Empty = '1' report "0: Empty does not work" severity error;
assert Full = '0' report "0: Full does not work" severity error;
assert One_Data_Left = '0' report "0: One_Place_Left does not work" severity error;
 
-- 1) Write one data to empty fifo
-- Data_Out = 5
-- One_Data_Left = 1
-- Empty = 0
Test_Phase <= Test_Phase +1;
WriteToFifo (5, 1);
assert Data_Out = conv_std_logic_vector (5, width) report "1: data not stored correctly" severity error;
assert One_Data_Left = '1' report "1: One_Place_Left does not work" severity error;
assert Empty = '0' report "1: Empty does not work" severity error;
 
ReadFifo (2);
WriteToFifo (52, 1);
ReadFifo (2);
 
-- 2) Fill up the empty fifo until there is only one place left
-- One_Place_Left = 1
-- Full = 0
Test_Phase <= Test_Phase +1;
WriteToFifo (10, 1); --to empty fifo
assert Data_Out = conv_std_logic_vector (10, width) report "2: data not stored correctly" severity error;
WriteToFifo (11, 0);
WriteToFifo (12, 0);
WriteToFifo (13, 0);
assert One_Place_Left = '1' report "2: One_Place_Left does not work" severity error;
assert Full = '0' report "2: Full does not work" severity error;
 
--3) One data more => fifo becomes full
-- Try to write two data (15 & 16) to full fifo
-- One_Place_Left = 0
-- Full = 1
Test_Phase <= Test_Phase +1;
WriteToFifo (14, 0);
assert One_Place_Left = '0' report "3: One_Place_Left does not work" severity error;
assert Full = '1' report "3: Full does not work" severity error;
 
WriteToFifo (15, 0);
WriteToFifo (16, 0);
Write_Enable <= '0';
Data_In <= (others => 'Z');
 
-- 4) Read one data from full fifo
Test_Phase <= Test_Phase +1;
ReadFifo (1); -- fifo out: 10 => 11
assert One_Place_Left = '1' report "4: One_Place_Left does not work" severity error;
assert Full = '0' report "4: Full does not work" severity error;
assert Data_Out = conv_std_logic_vector (11, width) report "4: data not stored correctly" severity error;
ReadFifo (1); -- fifo out: 11 => 12
ReadFifo (1); -- fifo out: 12 => 13
WriteToFifo (17, 1);
ReadFifo (1); -- fifo out: 13 => 14
ReadFifo (1); -- fifo out: 14 => 17
 
-- 5) Read the last data
-- write one to empty fifo and read empty fifo at the same time
Test_Phase <= Test_Phase +1;
assert Data_Out = conv_std_logic_vector (17, width) report "5: data not stored correctly" severity error;
ReadFifo (4); -- fifo out: 14 => empty (11)
WriteAndReadFifo (67,2);
wait for 5*PERIOD;
ReadFifo (1);-- fifo out: 67 => empty
 
-- 6) Fill up the fifo with two (1 & 2) data
-- Start reading fifo at the same as the latter data (2) is written
Test_Phase <= Test_Phase +1;
WriteToFifo (1, 0);
WriteAndReadFifo (2,0);
assert Data_Out = conv_std_logic_vector (2, width) report "6: data not stored correctly" severity error;
 
-- 7) Fill up the fifo
Test_Phase <= Test_Phase +1;
WriteToFifo (3, 0);
WriteToFifo (4, 0);
WriteToFifo (5, 0);
WriteToFifo (6, 0);
Write_Enable <= '0';
Data_In <= (others => 'Z');
-- Fifo now full
assert Full = '1' report "8: Full does not work" severity error;
-- 8) Empty the fifo
-- At first try to write one data (88) to full fifo and read fifo at the same
-- time. Data 88 should not go to fifo
Test_Phase <= Test_Phase +1;
WriteAndReadFifo(88,0);
ReadFifo(0);
ReadFifo(0);
ReadFifo(0);
ReadFifo(0);
assert Data_Out /= conv_std_logic_vector (88, width) report "8: data not stored correctly" severity error;
 
-- 9) Fifo should be empty
Test_Phase <= 9;
assert Empty = '1' report "9: Empty does not work" severity error;
 
-- Test completd
Test_Phase <= 0;
wait;
end process Generate_input;
 
 
 
Read_Data_from_fifo : process (Clk, Rst_n)
begin -- process Read_Data_from_fifo
if Rst_n = '0' then -- asynchronous reset (active low)
Read_Data <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if Read_Enable = '1' and Empty = '0'then
Read_Data <= Data_Out;
else
Read_Data <= Read_Data;
end if;
end if;
end process Read_Data_from_fifo;
 
 
 
 
 
CLOCK1: process -- generate clock signal for design
variable clktmp: std_logic := '0';
begin
wait for PERIOD/2;
clktmp := not clktmp;
Clk <= clktmp;
end process CLOCK1;
 
 
 
RESET: process
begin
Rst_n <= '0'; -- Reset the testsystem
wait for 6*PERIOD; -- Wait
Rst_n <= '1'; -- de-assert reset
wait;
end process RESET;
 
 
end behavioral;
 
 
configuration basic_cfg of tb_fifo2 is
for behavioral
for all : fifo
--use entity work.fifo (inout_mux);
--use entity work.fifo (in_mux);
use entity work.fifo (shift_reg);
end for;
 
end for;
 
end basic_cfg;
/trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Testbench/tb_fifo_mixed_clocks2.vhdl
0,0 → 1,354
-------------------------------------------------------------------------------
-- File : tb_fifo_mixed_clocks2.vhdl
-- Description : Testbench for a mixed clock Fifo buffer
-- Author : Ari Kulmala
-- Date : 19.06.2003
-- Modified :
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity tb_fifo_mixed_clocks2 is
end tb_fifo_mixed_clocks2;
 
architecture behavioral of tb_fifo_mixed_clocks2 is
 
component mixed_clocks_fifo
 
generic (
width : integer := 0;
depth : integer := 0);
 
port (
Clk_In : in std_logic;
Clk_Out : in std_logic;
Rst_n : in std_logic; -- Active low
Data_In : in std_logic_vector (width-1 downto 0);
Write_Enable : in std_logic;
-- One_Place_Left : out std_logic;
Full : out std_logic;
Data_Out : out std_logic_vector (width-1 downto 0);
Read_Enable : in std_logic;
Empty : out std_logic
-- One_Data_Left : out std_logic
);
 
end component;
 
 
constant width : integer := 16;
constant depth : integer := 5;
constant PERIOD_IN : time := 10 ns;
constant PERIOD_OUT : time := 4 ns;
 
signal Clk_In : std_logic;
signal Clk_Out : std_logic;
signal Rst_n : std_logic;
signal Data_In : std_logic_vector (width-1 downto 0);
signal Data_Out : std_logic_vector (width-1 downto 0);
signal Write_Enable : std_logic;
signal Read_Enable : std_logic;
signal Full : std_logic;
--signal One_Place_Left : std_logic;
signal Empty : std_logic;
--signal One_Data_Left : std_logic;
 
signal Read_Data : std_logic_vector (width-1 downto 0);
signal Test_Phase : integer range 0 to 20;
 
begin -- behavioral
 
 
DUT : mixed_clocks_fifo
generic map (
width => width,
depth => depth)
port map (
Clk_In => Clk_In,
Clk_Out => Clk_Out,
Rst_n => Rst_n,
Data_In => Data_In,
Write_Enable => Write_Enable,
Full => Full,
-- One_Place_Left => One_Place_Left,
Data_Out => Data_Out,
Read_Enable => Read_Enable,
Empty => Empty);
-- One_Data_Left => One_Data_Left );
 
Generate_input : process
 
-----------------------------------------------------------------------------
-- Two procedures for writing to and for reading the fifo
-----------------------------------------------------------------------------
procedure WriteToFifo (
Data_To_Fifo : in integer;
wait_time : in integer) is
begin --procedure
Data_In <= conv_std_logic_vector (Data_To_Fifo, width);
Write_Enable <= '1';
if Full = '1' then
--assert false report "Fifo full. Cannot write" severity note;
end if;
wait for PERIOD_IN;
--if wait_time > 0 then
Write_Enable <= '0';
Data_In <= (others => 'Z');
wait for (wait_time)* PERIOD_IN;
--end if;
 
end WriteToFifo;
 
 
procedure ReadFifo (
wait_time : in integer) is
begin --procedure
Read_Enable <= '1';
if Empty = '1' then
--assert false report "Fifo empty. Cannot read" severity note;
end if;
wait for PERIOD_OUT+1ns;
--if wait_time > 0 then
Read_Enable <= '0';
wait for (wait_time)* PERIOD_OUT;
--end if;
 
 
end ReadFifo;
 
 
procedure WriteAndReadFifo (
Data_To_Fifo : in integer;
wait_time : in integer) is
begin --procedure
Read_Enable <= '1';
if Empty = '1' then
--assert false report "Fifo empty. Cannot read" severity note;
end if;
Data_In <= conv_std_logic_vector (Data_To_Fifo, width);
Write_Enable <= '1';
if Full = '0' then
--assert false report "Fifo full. Cannot write" severity note;
end if;
 
 
wait for PERIOD_IN;
--if wait_time > 0 then
Read_Enable <= '0';
Write_Enable <= '0';
Data_In <= (others => 'Z');
wait for (wait_time)* (PERIOD_IN);
--end if;
 
 
end WriteAndReadFifo;
-----------------------------------------------------------------------------
 
 
 
begin -- process Generate_input
 
-- test sequence
-- 0 wait for reset
-- 1 write to empty fifo and read so that it is empty again
-- 2 write to fifo until there is only one place left
-- 3 write to fifo so that it becomes full
-- 4 read from full fifo and continue until there is only one data left
-- 5 read the last data
-- write and read the empty fifo at the same time, only write is succesful!
-- 6 write to fifo, write and read at the same time, both should be succesful!
-- 7 write until fifo is full
-- 8 write and read full fifo, only reading succesful!
-- read until fifo is empty
-- 9 make sure fifo is empty
 
-- Wait for reset
Write_Enable <= '0';
Read_Enable <= '0';
Data_In <= (others => 'Z');
Test_Phase <= 0;
wait for (6+2)*PERIOD_IN;
wait for PERIOD_IN/2;
wait for PERIOD_IN/3;
 
-- 0) At the beginning
-- One_Place_Left = 0
-- Empty = 1
-- Full = 0
-- One_Data_Left = 0
-- assert One_Data_Left = '0' report "0: One_Place_Left does not work" severity error;
assert Empty = '1' report "0 : Empty does not work" severity error;
assert Full = '0' report "0 : Full does not work" severity error;
-- assert One_Data_Left = '0' report "0: One_Place_Left does not work" severity error;
 
-- 1) Write one data to empty fifo
-- Data_Out = 5
-- One_Data_Left = 1
-- Empty = 0
Test_Phase <= Test_Phase +1;
WriteToFifo (5, 1);
assert Data_Out = conv_std_logic_vector (5, width) report "1 : data not stored correctly" severity error;
-- assert One_Data_Left = '1' report "1: One_Place_Left does not work" severity error;
assert Empty = '0' report "1 : Empty does not work" severity error;
 
ReadFifo (2);
WriteToFifo (52, 1);
ReadFifo (2);
 
-- 2) Fill up the empty fifo until there is only one place left
-- One_Place_Left = 1
-- Full = 0
Test_Phase <= Test_Phase +1;
WriteToFifo (10, 1); --to empty fifo
assert Data_Out = conv_std_logic_vector (10, width) report "2 : data not stored correctly" severity error;
WriteToFifo (11, 0);
WriteToFifo (12, 0);
WriteToFifo (13, 0);
-- assert One_Place_Left = '1' report "2: One_Place_Left does not work" severity error;
assert Full = '0' report "2 : Full does not work" severity error;
 
--3) One data more => fifo becomes full
-- Try to write two data (15 & 16) to full fifo
-- One_Place_Left = 0
-- Full = 1
Test_Phase <= Test_Phase +1;
WriteToFifo (14, 0);
-- assert One_Place_Left = '0' report "3: One_Place_Left does not work" severity error;
assert Full = '1' report "3 : Full does not work" severity error;
 
WriteToFifo (15, 0);
WriteToFifo (16, 0);
Write_Enable <= '0';
Data_In <= (others => 'Z');
 
-- 4) Read one data from full fifo
Test_Phase <= Test_Phase +1;
ReadFifo (1); -- fifo out: 10 => 11
-- assert One_Place_Left = '1' report "4: One_Place_Left does not work" severity error;
assert Full = '0' report "4 : Full does not work" severity error;
assert Data_Out = conv_std_logic_vector (11, width) report "4 : data not stored correctly" severity error;
 
ReadFifo (1); -- fifo out: 11 => 12
ReadFifo (1); -- fifo out: 12 => 13
WriteToFifo (17, 1);
ReadFifo (1); -- fifo out: 13 => 14
ReadFifo (1); -- fifo out: 14 => 17
 
-- 5) Read the last data
-- write one to empty fifo and read empty fifo at the same time
Test_Phase <= Test_Phase +1;
assert Data_Out = conv_std_logic_vector (17, width) report "5 : data not stored correctly" severity error;
ReadFifo (4); -- fifo out: 14 => empty (11)
WriteAndReadFifo (67, 2);
wait for 5*PERIOD_IN;
ReadFifo (1); -- fifo out: 67 => empty
 
-- 6) Fill up the fifo with two (1 & 2) data
-- Start reading fifo at the same as the latter data (2) is written
Test_Phase <= Test_Phase +1;
WriteToFifo (1, 0);
WriteAndReadFifo (2, 0);
assert Data_Out = conv_std_logic_vector (2, width) report "6 : data not stored correctly" severity error;
 
-- 7) Fill up the fifo
Test_Phase <= Test_Phase +1;
WriteToFifo (3, 0);
WriteToFifo (4, 0);
WriteToFifo (5, 0);
WriteToFifo (6, 0);
Write_Enable <= '0';
Data_In <= (others => 'Z');
-- Fifo now full
assert Full = '1' report "8 : Full does not work" severity error;
 
-- 8) Empty the fifo
-- At first try to write one data (88) to full fifo and read fifo at the same
-- time. Data 88 should not go to fifo
Test_Phase <= Test_Phase +1;
WriteAndReadFifo(88, 0);
ReadFifo(0);
ReadFifo(0);
ReadFifo(0);
ReadFifo(0);
assert Data_Out /= conv_std_logic_vector (88, width) report "8 : data not stored correctly" severity error;
 
-- 9) Fifo should be empty
Test_Phase <= 9;
assert Empty = '1' report "9 : Empty does not work" severity error;
 
-- Test completed
Test_Phase <= 0;
wait;
end process Generate_input;
 
 
 
Read_Data_from_fifo : process (Clk_In, Rst_n)
begin -- process Read_Data_from_fifo
if Rst_n = '0' then -- asynchronous reset (active low)
Read_Data <= (others => '0');
elsif Clk_In'event and Clk_In = '1' then -- rising clock edge
if Read_Enable = '1' and Empty = '0'then
Read_Data <= Data_Out;
else
Read_Data <= Read_Data;
end if;
end if;
end process Read_Data_from_fifo;
 
 
 
 
 
CLOCK_IN : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
wait for PERIOD_IN/2;
clktmp := not clktmp;
Clk_In <= clktmp;
end process CLOCK_IN;
 
CLOCK_OUT : process -- generate clock signal for design
variable clktmp : std_logic := '0';
begin
wait for PERIOD_OUT/2;
clktmp := not clktmp;
Clk_Out <= clktmp;
end process CLOCK_OUT;
 
 
 
RESET : process
begin
Rst_n <= '0'; -- Reset the testsystem
wait for 6*(PERIOD_IN); -- Wait
Rst_n <= '1'; -- de-assert reset
wait;
end process RESET;
 
 
 
end behavioral;
 
 
configuration basic_cfg of tb_fifo_mixed_clocks2 is
 
for behavioral
for all : mixed_clocks_fifo
--use entity work.fifo (inout_mux);
--use entity work.fifo (in_mux);
--use entity work.fifo (shift_reg);
use entity work.mixed_clocks_fifo (mixed_clocks);
end for;
 
end for;
 
end basic_cfg;
 
 
 
 
 
/trunk/TUT/ip.hwp.storage/fifos/synch_fifos/mixed_fifos_wave.do
0,0 → 1,29
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/clk_in
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/clk_out
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/rst_n
add wave -noupdate -format Literal -radix decimal /tb_fifo_mixed_clocks2/dut/data_in
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/write_enable
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/full
add wave -noupdate -format Literal -radix decimal /tb_fifo_mixed_clocks2/dut/data_out
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/read_enable
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/empty
add wave -noupdate -format Literal -radix decimal /tb_fifo_mixed_clocks2/dut/input_buffer
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/full_reg
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/empty_reg
add wave -noupdate -format Literal -radix decimal /tb_fifo_mixed_clocks2/dut/write_token
add wave -noupdate -format Literal -radix decimal /tb_fifo_mixed_clocks2/dut/read_token
add wave -noupdate -format Logic -radix decimal /tb_fifo_mixed_clocks2/dut/write_turned
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {92 ns}
WaveRestoreZoom {0 ns} {257 ns}
configure wave -namecolwidth 211
configure wave -valuecolwidth 39
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
run 700
/trunk/TUT/ip.hwp.storage/fifos/synch_fifos/create_makefile
0,0 → 1,51
#
# Skripti kaantaa kaikki vhdl-tiedostot ja tekee niista makefilen
# Ymparistomuuttjat
# CODEC_DATA_DIR kertoo mihin hakemistoon kaannetyt fiilut laitetaan.
# CODEC_WORK_DIR kertoo tyohakemiston (mm. Makefile.vhdl on siella)
#
 
clear
#Poistetaan vanha codelib ja tehdaan ja mapataan uusi
echo "Removing old vhdl library"
rm -rf $CODEC_DATA_DIR/codelib
echo; echo "Creating a new library at"
echo $CODEC_DATA_DIR; echo
 
vlib $CODEC_DATA_DIR/codelib
vmap work $CODEC_DATA_DIR/codelib
 
# Hibi-koodit v2
echo; echo "Compiling vhdl codes"; echo
 
vcom Vhdl/shift_slot.vhdl
 
vcom Vhdl/fifo_iom.vhdl
vcom Vhdl/fifo_im.vhdl
vcom Vhdl/fifo_shift.vhdl
vcom Vhdl/fifo_shift_slotted.vhdl
#vcom Vhdl/fifo_casev3.vhdl
#vcom Vhdl/fifo_im_case.vhdl
vcom Vhdl/fifo_casev5.vhdl
vcom Vhdl/fifo_casev4.vhdl
vcom Vhdl/fifo_mixed_clocks.vhdl
 
# Testipenkit
echo; echo "Compiling vhdl testbenches";echo
 
vcom Testbench/tb_fifo1.vhdl
vcom Testbench/tb_fifo2.vhdl
vcom Testbench/tb_fifo_mixed_clocks2.vhdl
 
 
 
 
# Poistetaan vanha makefile ja tehdaan uusi
echo;echo "Creating a new makefile"
rm -f $CODEC_WORK_DIR/Makefile.vhdl
vmake $CODEC_DATA_DIR/codelib > $CODEC_WORK_DIR/Makefile
 
echo " --------Create_Makefile done-------------"
 
 
 
/trunk/TUT/ip.hwp.storage/fifos/synch_fifos/wave.do
0,0 → 1,26
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_fifo2/clk
add wave -noupdate -format Logic /tb_fifo2/rst_n
add wave -noupdate -format Literal -radix unsigned /tb_fifo2/data_in
add wave -noupdate -format Literal -radix unsigned /tb_fifo2/data_out
add wave -noupdate -format Logic /tb_fifo2/write_enable
add wave -noupdate -format Logic /tb_fifo2/read_enable
add wave -noupdate -format Logic /tb_fifo2/full
add wave -noupdate -format Logic /tb_fifo2/one_place_left
add wave -noupdate -format Logic /tb_fifo2/empty
add wave -noupdate -format Logic /tb_fifo2/one_data_left
add wave -noupdate -format Literal -radix unsigned /tb_fifo2/read_data
add wave -noupdate -format Literal /tb_fifo2/test_phase
add wave -noupdate -format Literal -radix unsigned /tb_fifo2/dut/fifo_buffer
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {0 ns}
WaveRestoreZoom {0 ns} {1 us}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
/trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/fifo_Comparison.ppt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/fifo_Comparison.ppt
trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/fifo_Comparison.ppt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison_fpga.m =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison_fpga.m (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison_fpga.m (revision 18) @@ -0,0 +1,91 @@ +% SYNTHESIS FOR FPGA +% used Mentor Graphics Precision RTL Synthesis 2003a.29 +% Synthesized for Altera Excalibur ARM, frequency 20 MHz +% +% Uses double_fifo_muxed_read components +% which include two FIFOs and a read multiplexer +% FIFOs are 3b wide + +close all +clear all + +% Vertailussa kaytetyt fifojen pituudet +length = [3 30 80] + + +% Max clock frequency +% (library set up time 0.17 ns is left out of these results) +delay_casev3 = [113.3 62.4 46.3] +delay_casev4 = [113.3 59.0 40.7] +delay_im_case = [ 88.0 81.1 71.0] +delay_im = [ 84.4 71.2 59.7] + +% Areas [IOs] +%io_casev3 = [ 32 32 32] +%io_casev4 = [ 32 32 32] +%io_im_case = [ 32 32 32] + +% Areas [LCs] +area_casev3 = [ 90 858 2370] +area_casev4 = [ 90 864 2394] +area_im_case = [ 94 1098 2744] +area_im = [ 126 1090 2730] + +% Areas total +%area_casev3 = io_casev3 +lc_casev3 +%area_casev4 = io_casev4 +lc_casev4 +%area_im_case = io_im_case +lc_im_case + + + +% Plot figures +% Delay figure +%figure +%plot ( length, delay_im, 'r-o') +%hold on +%plot ( length, delay_iom, '-<') +%hold on +%plot ( length, delay_shift, 'k-*') +%hold on +%plot ( length, delay_slotted_shift, 'bo-') +%hold on +plot ( length, delay_casev3, 'k-o') +hold on +plot ( length, delay_casev4, 'r-*') +hold on +plot ( length, delay_im_case, '-<') +hold on +plot ( length, delay_im, '-*') +hold on + +legend ('casev3', 'casev4', 'in-mux-case', 'in-mux', 0) +title (['Max frequency (MHz) of 3-bit double-FIFO']) +xlabel ('Depth of FIFOs') +ylabel ('Max Frequency [MHz]') +axis ([0 82 0 120]) + +% Area figure +figure +%plot ( length, area_im, 'r-o') +%hold on +%plot ( length, area_iom, '-<') +%hold on +%plot ( length, area_shift, 'k-*') +%hold on +%plot ( length, area_slotted_shift, 'bs-') +%hold on +plot ( length, area_casev3, 'k-o') +hold on +plot ( length, area_casev4, 'r-*') +hold on +plot ( length, area_im_case, '-<') +hold on +plot ( length, area_im_case, '-*') +hold on +legend ('casev3', 'casev4', 'in-mux-case', 'in-mux', 0) + +title (['Area (LC) of 3-bit double-FIFO']) +xlabel ('Depth of FIFOs') +ylabel ('Area [LC]') +axis ([0 82 0 3000]) + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison.m =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison.m (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison.m (revision 18) @@ -0,0 +1,108 @@ +% Prints the synthesis results of FIFO comparison @ 0.18 um +% Uses double_fifo_muxed_read components +% which include two FIFOs and a read multiplexer +% FIFOs are 3b wide +% _im = in-mux (triagle in figures) +% _iom = inout-mux (circle in figures) +% shift = shift register (star in figures) + +close all +clear all + +% Vertailussa kaytetyt fifojen pituudet +length = [3 30 80] + + +% Delay [ns] = data arrival time +% (library set up time 0.17 ns is left out of these results) +delay_im = [1.99 3.06 3.82] +delay_iom = [2.25 3.63 4.62] +delay_shift = [1.33 2.15 2.81] +delay_slotted_shift = [1.56 1.99 1.81] +% delay_casev3 = [1.05 2.16 3.43] +delay_casev4 = [1.48 2.36 3.64] +delay_casev4a = [1.69 2.52 3.34] +delay_casev5 = [1.72 2.52 3.75] +delay_casev6 = [1.86 2.66 3.55] +delay_im_case = [1.57 2.54 3.92] + + +% Areas [um2] +area_im = [11214 55672 161906] +area_iom = [12955 62296 140750] +area_slotted_shift = [ 7688 43724 110645] +area_shift = [ 7696 45350 114765] +% area_casev3 = [ 6602 50802 129232] +area_casev4 = [10014 54546 133443] +area_casev4a = [11051 63721 159215] +area_casev5 = [10264 55255 132984] +area_casev6 = [10088 64253 158724] +area_im_case = [ 8978 53493 160079] + +% Plot figures +% Delay figure +figure +%plot ( length, delay_shift, 'k-*') +%hold on +%plot ( length, delay_slotted_shift, 'bo-') +%hold on +plot ( length, delay_im, 'k-o') +hold on +plot ( length, delay_iom, '-<') +hold on +plot ( length, delay_casev4, 'r-o') +hold on +plot ( length, delay_casev4a, 'r-*') +hold on +plot ( length, delay_casev5, 'r-+') +hold on +plot ( length, delay_casev6, 'c-+') +hold on +plot ( length, delay_im_case, 'k-<') +hold on + +%title (['Delay of 3-bit double-FIFO (blue triangle=inout-mux, red' ... +% ' o= in-mux, black *=shift, black square= slotted shift, red * = +%casev4, red triangle = im-case, black o= casev3)']) + +title ('Delay of 3-bit double-FIFO') +legend('in-mux', 'inout-mux', 'casev4', 'casev4a','casev5','casev6', 'in-mux-case',0) + +xlabel ('Depth of FIFOs') +ylabel ('Delay [ns]') +axis ([0 82 0 5]) + +% Area figure +figure +%plot ( length, area_shift, 'k-*') +%hold on +%plot ( length, area_slotted_shift, 'bs-') +%hold on +plot ( length, area_im, 'k-o') +hold on +plot ( length, area_iom, '-<') +hold on +plot ( length, area_casev4, 'r-o') +hold on +plot ( length, area_casev4a, 'r-*') +hold on +plot ( length, area_casev5, 'r-+') +hold on +plot ( length, area_casev6, 'c-+') +hold on +plot ( length, area_im_case, 'k-<') +hold on + + +%title (['Area of 3-bit double-FIFO (blue triangle=inout-mux, red' ... +% ' o= in-mux, black *=shift, black square= slotted shift, red * = +%casev4, red triangle = im-case, black o = casev3)']) + +title ('Area of 3-bit double-FIFO') +legend('in-mux', 'inout-mux', 'casev4', 'casev4a', 'casev5','casev6','in-mux-case',0) + +xlabel ('Depth of FIFOs') +ylabel ('Area [um2]') +axis ([0 82 0 18e4]) + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/fifo_Comparison.pdf =================================================================== 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+/Author (ege) +/Creator (PScript5.dll Version 5.2) +/Title (Microsoft PowerPoint - fifo_Comparison.ppt) +>> +endobj +32 0 obj +<< /Type /Metadata /Subtype /XML /Length 1098 >> +stream + +Microsoft PowerPoint - fifo_Comparison.ppt + + +endstream +endobj +xref +0 33 +0000000000 65535 f +0000063513 00000 n +0000063664 00000 n +0000063822 00000 n +0000066188 00000 n +0000066339 00000 n +0000066473 00000 n +0000068166 00000 n +0000068317 00000 n +0000068463 00000 n +0000072477 00000 n +0000072631 00000 n +0000072778 00000 n +0000075405 00000 n +0000075559 00000 n +0000075779 00000 n +0000080237 00000 n +0000080498 00000 n +0000080652 00000 n +0000080835 00000 n +0000081223 00000 n +0000153071 00000 n +0000216698 00000 n +0000216914 00000 n +0000217315 00000 n +0000217528 00000 n +0000227848 00000 n +0000228068 00000 n +0000241495 00000 n +0000241526 00000 n +0000241570 00000 n +0000241675 00000 n +0000241922 00000 n +trailer +<< +/Size 33 +/ID[<5ab2ce6d23797f07660c2e8ad696cfc3><5b35cbeb57638c642f899e30b20e117a>] +>> +startxref +173 +%%EOF Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/fifojen_erot.txt =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/fifojen_erot.txt (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/fifojen_erot.txt (revision 18) @@ -0,0 +1,30 @@ + +Fifo_case (global): +- input and output-register is always the same. +- after the first data the following data is stored to + a shift register +- see the fifo_case.ppt for more info + +differencies between fifo_case's: +v3 - bug discovered - don't use +v4 - uses a variable rather than a signal to update control signals + (Empty, Full, etc.). +v4a - doesn't reset to zero any register. only control + data_amount +v5 - code-level registered output (concurrent assignments), v3 doesn't have. + - signal is used to update control signals. +v6 - different from v5 : doesn't reset to zero any register. only control + + data_amount + + +fifo_im: uses mux in the input +fifo_iom: uses mux in the input and output +fifo_im_case: implemented as fifo_im except that uses "case" instead of "if". + (makes it concurrent rather than sequential) + +there is a problem with fifo_im (both) when trying to write data even though +fifo is full. + + +Fifo_cases: +tested: doesn't set the output to '0's when last data is read. +Result: doesn't have a significant impact on anything Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison.xls =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison.xls =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison.xls (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison.xls (revision 18)
trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/plot_comparison.xls Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/emulation_status.txt =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/emulation_status.txt (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Doc/emulation_status.txt (revision 18) @@ -0,0 +1,4 @@ +fifo_im_case - ok +fifo_casev4 - toimii, data_outissa heittoa verrattuna in-muxiin, kun fifo +tyhja (tama kun tyhjentaa, in-mux ei) +fifo_casev5 - kuten v4. Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/environment.cshrc =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/environment.cshrc (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/environment.cshrc (revision 18) @@ -0,0 +1,35 @@ + +# source /opt/modeltech-5.5d/modeltech.cshrc +# source /opt/modeltech-5.6b/modeltech.cshrc + source /opt/modeltech-5.7a/modeltech.cshrc + + +# Synopsys-hommat pitaa sourcettaa vastaa Mentorin +# juttujen jalkeen, koska paskat Mentorin softat ei muuten +# toimi. Tulee maailman informatiivisin +# virheilmoitus "printenv: Undefined variable." + +source /opt/synopsys/syn-2000.11/synopsys.cshrc + + + + + + +setenv USER_HOME $HOME + + +setenv CODEC_DATA_DIR /tmp/${USER}/Fifo_comparison +setenv CODEC_WORK_DIR ${PWD} + +echo "###########" +echo Directory settings for fifo_comparison +echo Data_dir = $CODEC_DATA_DIR +echo Work_dir = $CODEC_WORK_DIR +echo "###########" + + + + + +echo; echo " Environment is set" Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/shifter.do =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/shifter.do (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/shifter.do (revision 18) @@ -0,0 +1,31 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_fifo2/clk +add wave -noupdate -format Logic /tb_fifo2/rst_n +add wave -noupdate -format Literal -radix unsigned /tb_fifo2/data_in +add wave -noupdate -format Literal -radix unsigned /tb_fifo2/data_out +add wave -noupdate -format Logic /tb_fifo2/write_enable +add wave -noupdate -format Logic /tb_fifo2/read_enable +add wave -noupdate -format Logic /tb_fifo2/full +add wave -noupdate -format Logic /tb_fifo2/one_place_left +add wave -noupdate -format Logic /tb_fifo2/empty +add wave -noupdate -format Logic /tb_fifo2/one_data_left +add wave -noupdate -format Literal -radix unsigned /tb_fifo2/read_data +add wave -noupdate -format Literal /tb_fifo2/test_phase +add wave -noupdate -format Literal -radix unsigned /tb_fifo2/dut/intermediate_signal +add wave -noupdate -format Literal -radix unsigned /tb_fifo2/dut/first_slot/data_reg +add wave -noupdate -format Literal -radix unsigned /tb_fifo2/dut/map_slots__3/gen_slot_i/data_reg +add wave -noupdate -format Literal -radix unsigned /tb_fifo2/dut/map_slots__2/gen_slot_i/data_reg +add wave -noupdate -format Literal -radix unsigned /tb_fifo2/dut/map_slots__1/gen_slot_i/data_reg +add wave -noupdate -format Literal -radix unsigned /tb_fifo2/dut/map_slots__0/gen_slot_i/data_reg +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {102 ns} +WaveRestoreZoom {0 ns} {442 ns} +configure wave -namecolwidth 220 +configure wave -valuecolwidth 110 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/modelsim.ini =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/modelsim.ini (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/modelsim.ini (revision 18) @@ -0,0 +1,293 @@ +[Library] +others = $MODEL_TECH/../modelsim.ini + +work = /tmp/kulmala3/Fifo_comparison/codelib +[vcom] +; Turn on VHDL-1993 as the default. Default is off (VHDL-1987). +; VHDL93 = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explict enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = false + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that don't involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Perform range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; RangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after an assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +AssertionFormat = "** %S: %R Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. For VHDL, PathSeparator = / +; for Verilog, PathSeparator = . +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, or deposit +; or in other terms, fixed, wired, or charged. +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control number of VHDL files open concurrently +; This number should always be less than the +; current ulimit setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Controls the number of hierarchical regions displayed as +; part of a signal name shown in the waveform window. The default +; value or a value of zero tells VSIM to display the full name. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of a generate statement label. Don't quote it. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is to be compressed. +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1; compress WLF file. +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in WLF file +; or only regions containing logged signals (0). +; The default is 0; log only regions with logged signals. +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0; no limit. Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0; no limit. +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0; don't delete WLF file when simulation ends. +; WLFDeleteOnQuit = 1 + +[lmc] +; ModelSim's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so + +; ModelSim's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_slotted_2.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_slotted_2.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_slotted_2.vhd (revision 18) @@ -0,0 +1,147 @@ +------------------------------------------------------------------------------- +-- Title : fifo +-- Project : +------------------------------------------------------------------------------- +-- File : fifo_slotted_2.vhd +-- Author : +-- Company : +-- Created : 2005-05-23 +-- Last update: 2005/12/15 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2005-05-23 1.0 penttin5 Created +-- 2005-05-31 1.1 penttin5 Added comments +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity fifo is + + generic ( + data_width_g : integer := 0; + depth_g : integer := 0 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + data_in : in std_logic_vector (data_width_g-1 downto 0); + we_in : in std_logic; + one_p_out : out std_logic; + full_out : out std_logic; + data_out : out std_logic_vector (data_width_g-1 downto 0); + re_in : in std_logic; + empty_out : out std_logic; + one_d_out : out std_logic + ); + +end fifo; + +architecture rtl of fifo is + + component fifo_reg + generic ( + width_g : integer := 0); + + port ( + clk : in std_logic; + rst_n : in std_logic; + load_in : in std_logic; + data1_in : in std_logic_vector(width_g - 1 downto 0); + data2_in : in std_logic_vector(width_g - 1 downto 0); + data_sel_in : in std_logic; + data_out : out std_logic_vector(width_g - 1 downto 0)); + end component; -- fifo_reg + + signal fifo_state_r : std_logic_vector(depth_g downto 0); + type reg_data_type is array (0 to depth_g) of std_logic_vector(data_width_g - 1 downto 0); + type reg_load_type is array (0 to depth_g - 1) of std_logic; + signal reg_data_out : reg_data_type; + signal reg_load : reg_load_type; + signal reg_data_sel : std_logic_vector(depth_g - 1 downto 0); + +begin -- rtl + + empty_out <= fifo_state_r(0); + full_out <= fifo_state_r(depth_g); + one_d_out <= fifo_state_r(1); + one_p_out <= fifo_state_r(depth_g - 1); + data_out <= reg_data_out(0); + + reg_data_out(depth_g) <= (others => '0'); + + -- load new value if (write and this is the next free register) or read + reg_load_assign : for i in 0 to depth_g - 1 generate + reg_load(i) <= (fifo_state_r(i) and we_in) or re_in; + end generate reg_load_assign; + + + -- sel = 0 <=> load from data_in, + -- sel = 1 <=> load from register i+1 + -- Data in from the next register (i+1) if: + -- 1 not read or not write or this is not the first free register + -- AND + -- 1.1 read and fifo full or + -- 1.2 read and write and this is not the last free register + reg_data_sel_assign : for i in 0 to depth_g - 1 generate + reg_data_sel(i) <= ((re_in and (not(we_in) or fifo_state_r(depth_g))) or (re_in and we_in and not (fifo_state_r (i + 1)))) + and (not(re_in and we_in and fifo_state_r(i))); + end generate reg_data_sel_assign; + + map_registers : for i in 0 to depth_g - 1 generate + gen_reg_i : fifo_reg + generic map ( + width_g => data_width_g + ) + port map ( + clk => clk, + rst_n => rst_n, + load_in => reg_load(i), + data1_in => data_in, + data2_in => reg_data_out(i + 1), + data_sel_in => reg_data_sel(i), + data_out => reg_data_out(i) + ); + end generate map_registers; + + ----------------------------------------------------------------------------- + -- Update fifo_state_r + ----------------------------------------------------------------------------- + fifo_state_r_update : process (clk, rst_n) + begin -- process fifo + if rst_n = '0' then -- asynchronous reset (active low) + + -- after reset the first register is the first free register + fifo_state_r (depth_g downto 1) <= (others => '0'); + fifo_state_r (0) <= '1'; + + elsif clk'event and clk = '1' then -- rising clock edge + + -- free the last full register if: + -- read and fifo isn't empty or simultaneus read and write and fifo is full + if (re_in = '1' and ((we_in = '0' and fifo_state_r(0) = '0') or + (we_in = '1' and fifo_state_r(depth_g) = '1'))) + then + fifo_state_r <= '0' & fifo_state_r(depth_g downto 1); + + -- fill the first free register if: + -- write and fifo isn't full or simultaneus read and write and fifo is empty + -- write and ( (no read and fifo not full) or (read and empty) ) + elsif (we_in = '1' and ((re_in = '0' and fifo_state_r(depth_g) = '0') or + (re_in = '1' and fifo_state_r(0) = '1'))) then + fifo_state_r <= fifo_state_r(depth_g - 1 downto 0) & '0'; + else + fifo_state_r <= fifo_state_r; + end if; + end if; + end process fifo_state_r_update; +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_iom.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_iom.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_iom.vhdl (revision 18) @@ -0,0 +1,299 @@ +------------------------------------------------------------------------------- +-- File : fifo_iom.vhdl +-- Description : Fifo buffer for hibi interface. +-- Uses pointers and muxes for input and output. +-- +-- Author : Erno Salminen +-- Date : 29.04.2002 +-- Modified : 30.04.2002 Vesa Lahtinen Optimized for synthesis +-- +-- 02.06 ES: default assignment Fifo_Buffer <= Fifo_Buffer +-- Effect on synthesis is uncertain : +-- small fifos seem to gets smaller and faster, but big fifos +-- get bigger and slower. Strange. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity fifo is + + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + +architecture inout_mux of fifo is + + type data_array is array (depth-1 downto 0) of std_logic_vector (width-1 downto 0); + signal Fifo_Buffer : data_array; + + signal in_ptr : integer range 0 to depth-1; + signal out_ptr : integer range 0 to depth-1; + + -- Registers + signal Full_reg : std_logic; + signal Empty_reg : std_logic; + signal One_Data_Left_reg : std_logic; + signal One_Place_Left_reg : std_logic; + --signal Data_Amount : std_logic_vector (depth-1 downto 0); + signal Data_Amount : integer range 0 to depth-1; + + +begin -- inout_mux + + -- Continuous assignments + -- Assigns register values to outputs + Full <= Full_reg; + Empty <= Empty_reg; + One_Data_Left <= One_Data_Left_reg; + One_Place_Left <= One_Place_Left_reg; + Data_Out <= Fifo_Buffer (out_ptr); + -- Note! There is some old value in data output when fifo is empty. + + +Main : process (Clk, Rst_n) +begin -- process Main + if Rst_n = '0' then -- asynchronous reset (active low) + + -- Reset all registers + -- Fifo is empty at first + Full_reg <= '0'; + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + in_ptr <= 0; + out_ptr <= 0; + Data_Amount <= 0; --(others => '0'); + + if depth =1 then -- 30.07 + One_Place_Left_reg <= '1'; + else + One_Place_Left_reg <= '0'; + end if; + + for i in 0 to depth-1 loop + Fifo_Buffer (i) <= (others => '0'); + end loop; -- i + + elsif Clk'event and Clk = '1' then -- rising clock edge + + + -- 1) Write data to fifo + if Write_Enable = '1' and Read_Enable = '0' then + + if Full_reg = '0' then + Empty_reg <= '0'; + if (in_ptr = (depth-1)) then + in_ptr <= 0; + else + in_ptr <= in_ptr + 1; + end if; + out_ptr <= out_ptr; + Data_Amount <= Data_Amount +1; + Fifo_Buffer <= Fifo_Buffer; --02.06 + Fifo_Buffer (in_ptr) <= Data_In; + + -- Check if the fifo is getting full + if Data_Amount + 2 = depth then + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + elsif Data_Amount +1 = depth then + Full_reg <= '1'; + One_Place_Left_reg <= '0'; + else + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + end if; + + -- If fifo was empty, it has now one data + if Empty_reg = '1' then + One_Data_Left_reg <= '1'; + else + One_Data_Left_reg <= '0'; + end if; + + else + in_ptr <= in_ptr; + out_ptr <= out_ptr; + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + + -- 2) Read data from fifo + elsif Write_Enable = '0' and Read_Enable = '1' then + + if Empty_reg = '0' then + in_ptr <= in_ptr; + if (out_ptr = (depth-1)) then + out_ptr <= 0; + else + out_ptr <= out_ptr + 1; + end if; + Full_reg <= '0'; + Data_Amount <= Data_Amount -1; + Fifo_Buffer <= Fifo_Buffer; --02.06 + + -- Debug + -- Fifo_Buffer (out_ptr) <= (others => '1'); + + -- Check if the fifo is getting empty + if Data_Amount = 2 then + Empty_reg <= '0'; + One_data_Left_reg <= '1'; + elsif Data_Amount = 1 then + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + else + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + end if; + + -- If fifo was full, it is no more + if Full_reg = '1' then + One_Place_Left_reg <= '1'; + else + One_Place_Left_reg <= '0'; + end if; + + else + in_ptr <= in_ptr; + out_ptr <= out_ptr; + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + + -- 3) Write and read at the same time + elsif Write_Enable = '1' and Read_Enable = '1' then + + + if Full_reg = '0' and Empty_reg = '0' then + if (in_ptr = (depth-1)) then + in_ptr <= 0; + else + in_ptr <= in_ptr + 1; + end if; + if (out_ptr = (depth-1)) then + out_ptr <= 0; + else + out_ptr <= out_ptr + 1; + end if; + Full_reg <= '0'; + Empty_reg <= '0'; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + + Fifo_Buffer <= Fifo_Buffer; --02.06 + Fifo_Buffer (in_ptr) <= Data_In; + -- Fifo_Buffer (out_ptr) <= (others => '1'); --debug + + + elsif Full_reg = '1' and Empty_reg = '0' then + -- Fifo is full, only reading is possible + in_ptr <= in_ptr; + if (out_ptr = (depth-1)) then + out_ptr <= 0; + else + out_ptr <= out_ptr + 1; + end if; + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + Fifo_Buffer <= Fifo_Buffer; --02.06 + --Fifo_Buffer (out_ptr) <= (others => '1'); -- Debug + Data_Amount <= Data_Amount -1; + + -- Check if the fifo is getting empty + if Data_Amount = 2 then + Empty_reg <= '0'; + One_data_Left_reg <= '1'; + elsif Data_Amount = 1 then + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + else + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + end if; + + + elsif Full_reg = '0' and Empty_reg = '1' then + -- Fifo is empty, only writing is possible + if (in_ptr = (depth-1)) then + in_ptr <= 0; + else + in_ptr <= in_ptr + 1; + end if; + out_ptr <= out_ptr; + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + Fifo_Buffer <= Fifo_Buffer; --02.06 + Fifo_Buffer (in_ptr) <= Data_In; + Data_Amount <= Data_Amount +1; + + -- Check if the fifo is getting full + if Data_Amount + 2 = depth then + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + elsif Data_Amount +1 = depth then + Full_reg <= '1'; + One_Place_Left_reg <= '0'; + else + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + end if; + + + -- 4) Do nothing, fifo remains idle + else + + in_ptr <= in_ptr; + out_ptr <= out_ptr; + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + else + -- Fifo is idle + in_ptr <= in_ptr; + out_ptr <= out_ptr; + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + end if; +end process Main; + +end inout_mux; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/lifo_slotted.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/lifo_slotted.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/lifo_slotted.vhdl (revision 18) @@ -0,0 +1,204 @@ +------------------------------------------------------------------------------- +-- File : lifo_shift.vhdl +-- Description : Lifo buffer for hibi interface +-- +-- Author : Erno Salminen +-- Date : 29.05.2003 +-- Modified : +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity lifo is + + generic ( + width : integer := 3; + depth : integer := 30); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end lifo; + + + +architecture slotted_lifo_reg of lifo is + + component fifo_slot + generic ( + width : integer := 0); + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Right_Valid_In : in std_logic; + Right_Enable_In : in std_logic; + Right_Data_In : in std_logic_vector ( width-1 downto 0); + + Left_Data_In : in std_logic_vector ( width-1 downto 0); + Left_Valid_In : in std_logic; + Left_Enable : in std_logic; + Valid_Out : out std_logic; + Data_Out : out std_logic_vector ( width-1 downto 0) + ); + + end component; -- fifo_slot; + + + + type Fifo_slot_type is record + Valid : std_logic; + Data : std_logic_vector ( width-1 downto 0); + end record; + type slot_signal_array is array (depth downto -1) of Fifo_slot_type; + signal intermediate_signal : slot_signal_array; + signal we : std_logic_vector ( depth-1 downto 0); + signal re : std_logic_vector ( depth-1 downto 0); + +begin -- slotted_lifo_reg + + + ----------------------------------------------------------------------------- + -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + -- LIFO! + -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + ------------------------------------------------------------------------------ + + -- Continuous assignments + -- Assigns register values to outputs + assert depth > 1 report "Lifo depth must be more than one!" severity WARNING; + Full <= intermediate_signal (depth-1).Valid; -- ylin paikka varattu + Empty <= not (intermediate_signal (0).Valid ); -- alin paikka tyhja + + -- Yksi data=alin taynna, toiseksi alin tyhja + One_Data_Left <= not (intermediate_signal (1).Valid) and intermediate_signal (0).Valid; + + -- Yksi paikka=ylin tyhja, toiseksi ylin taynna + One_Place_Left <= not (intermediate_signal (depth-1).Valid) and intermediate_signal (depth-2).Valid; + + Data_Out <= intermediate_signal (0).Data; --alin data ulostuloon + -- Note! There is some old value in data output when lifo is empty. + + + map_slots : for i in 0 to depth-1 generate + gen_slot_i : fifo_slot + generic map ( + width => width) + port map ( + Clk => Clk, + Rst_n => Rst_n, + Right_Valid_In => intermediate_signal (i-1).Valid, + Right_Data_In => intermediate_signal (i-1).Data, + Right_Enable_In => we(i), + Left_Valid_In => intermediate_signal (i+1).Valid, + Left_Data_In => intermediate_signal (i+1).Data, + Left_Enable => re(i), + Valid_Out => intermediate_signal (i).Valid, + Data_Out => intermediate_signal (i).Data + ); + end generate map_slots; + + intermediate_signal (depth).Data <= (others => '0'); --'Z'); + intermediate_signal (depth).Valid <= '0'; + + intermediate_signal (-1).Data <= Data_In; + intermediate_signal (-1).Valid <= '1'; + + + + async_first_slot: process (intermediate_signal, Data_In, Write_Enable, Read_Enable) + begin -- process async_first_slot + -- Ohjataan ensimmaisen we-signaalia + + if Write_Enable = '1' and Read_Enable = '0' then + -- Kirjoitus pelkästään + + re <= (others => '0'); + + if intermediate_signal (depth-1).Valid = '1' then + -- Ylin paikka taynna + we <= (others => '0'); + else + -- Kirjoitetaan uusi data + we <= (others => '1'); + end if; + + + elsif Write_Enable = '0' and Read_Enable = '1' then + -- Luku pelkästään + we <= (others => '0'); + re <= (others => '1'); + + + + elsif Write_Enable = '1' and Read_Enable = '1' then + --Luku ja kirjoitus yhta aikaa + + if intermediate_signal (depth-1).Valid = '1' then + -- Ylin paikka taynna + we <= (others => '0'); + re <= (others => '1'); + + else + -- Kirjoitetaan uusi data alinmpaan slottiiin + -- muut pitväät vanahan arvonsa + we <= (others => '0'); + we(0) <= '1'; + re <= (others => '0'); + + end if; + + + + else + -- Ei tehda mitaan + we <= (others => '0'); --'Z'); + re <= (others => '0'); --'Z'); + + + end if; + + + end process async_first_slot; + + + ----------------------------------------------------------------------------- + -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + -- LIFO! + -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + ------------------------------------------------------------------------------ + + + check_we: process (we) + variable one_bits : integer := 0; + begin -- process check_we + one_bits := 0; + + for i in 0 to depth-1 loop + if we(i)= '1' then + one_bits := one_bits +1; + end if; + end loop; -- i + + +-- assert one_bits < 2 report "Too many write enables" severity WARNING; + end process check_we; + + + + + + +end slotted_lifo_reg; --architecture Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev3.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev3.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev3.vhdl (revision 18) @@ -0,0 +1,237 @@ + +-- !NOTE! output control signals ain't working right in all cases!! + +-- use v5 or v6. + +------------------------------------------------------------------------------- +-- File : fifo_casev3.vhdl +-- Description : Fifo buffer for hibi interface +-- Author : Ari Kulmala +-- Date : 10.06.2003 +-- Modified : 18.06.2003 - Re-wrote the way output control signals are +-- assigned +-- +-- +-- Detailed description: +-- -Input and Output always from the same register +-- -> input-buffer is shifted whenever write occurs +-- -> when read, a mux chooses which value to load to the output next +-- (the oldest) +-- +-- !NOTE! isn't tested as one-length FIFO. doesn't probably work. (vector +-- length (1 downto 2) ... +-- +-- !NOTE! +-- * Output is zero when empty. +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + + +entity fifo is + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; -- Active low + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + +architecture behavioral of fifo is + + type reg is array (depth downto 2) of std_logic_vector + (width-1 downto 0); + signal input_buffer : reg; + +-- signal output : std_logic_vector (width-1 downto 0); + signal Data_amount : integer range 0 to depth; + + + signal WR : std_logic_vector ( 1 downto 0); + +begin -- behavioral + + -- Concurrent assignment + WR <= Write_Enable & Read_Enable; + + + +process (Clk, rst_n) +begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + for i in depth downto 2 loop + input_buffer(i) <= (others => '0'); + end loop; -- i + + Data_out <= (others => '0'); + Data_Amount <= 0; + Empty <= '1'; + One_Data_Left <= '0'; + One_Place_Left <= '0'; + Full <= '0'; + + elsif Clk'event and Clk = '1' then -- rising clock edge + +case WR is + when "01" => -- Read data + if Data_amount = 0 then + Data_amount <= Data_amount; + elsif Data_amount = 1 then + Data_out <= (others => '0'); + Data_amount <= Data_amount-1; + else + Data_out <= input_buffer(Data_amount); + Data_amount <= Data_amount-1; + end if; + + + when "10" => -- Write Data + + if Data_amount = 0 then + Data_out <= Data_In; + Data_amount <= Data_amount+1; + elsif Data_amount = depth then + input_buffer <= input_buffer; + else + for i in depth-1 downto 2 loop + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + Data_amount <= Data_amount+1; + end if; + + when "11" => -- Read and Write concurrently + + if Data_amount = 0 then + Data_out <= Data_in; + elsif Data_amount = 1 then + Data_out <= Data_In; + elsif Data_amount = depth then -- cannot write if full + Data_out <= input_buffer (Data_amount); + Data_amount <= Data_amount-1; + else + Data_out <= input_buffer (Data_amount); + for i in depth-1 downto 2 loop + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + end if; + + when others => -- Do nothing + input_buffer <= input_buffer; + Data_amount <= Data_amount; + +end case; + + if Data_amount = 0 then + if Write_Enable = '1' then + Empty <= '0'; + One_Data_Left <= '1'; + else + Empty <= '1'; + One_Place_Left <= '0'; + end if; + + One_Data_Left <= '0'; + Full <= '0'; + + elsif Data_amount = 1 then + if Read_Enable = '1' then + Empty <= '1'; + One_Data_Left <= '0'; + else + Empty <= '0'; + One_Data_Left <= '1'; + end if; + if Write_Enable = '1' then + One_Data_Left <= '0'; + end if; + + One_Place_Left <= '0'; + Full <= '0'; + + elsif Data_amount = 2 then + if Read_Enable = '1' then + One_Data_Left <= '1'; + else + One_Data_Left <= '0'; + end if; + Empty <= '0'; + One_Place_Left <= '0'; + Full <= '0'; + + + elsif Data_amount = (depth-2) then + Empty <= '0'; + if Write_Enable = '1' then + One_Place_Left <= '1'; + else + One_Place_Left <= '0'; + end if; + + One_Data_Left <= '0'; + Full <= '0'; + elsif Data_amount = (depth-1) then + Empty <= '0'; + if Read_Enable = '1' or Write_Enable = '1' then + One_Place_Left <= '0'; + else + One_Place_Left <= '1'; + end if; + One_Data_Left <= '0'; + if Write_Enable = '1' then + Full <= '1'; + else + Full <= '0'; + end if; + + elsif Data_Amount = depth then + if Read_Enable = '1' then + full <= '0'; + One_Data_Left <= '1'; + else + full <= '1'; + One_Data_Left <= '0'; + end if; + Empty <= '0'; + One_Place_Left <= '0'; + + else + Empty <= '0'; + One_Place_Left <= '0'; + One_Data_Left <= '0'; + Full <= '0'; + end if; + + end if; --synchronous + + end process; + +end behavioral; + + + + + + + + + + + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev4.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev4.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev4.vhdl (revision 18) @@ -0,0 +1,188 @@ +------------------------------------------------------------------------------- +-- File : fifo_casev4.vhdl +-- Description : Fifo buffer for hibi interface +-- Author : Ari Kulmala +-- Date : 12.06.2003 +-- Modified : +-- +-- +-- Detailed description: +-- -Uses variable to handle Data-amount and Full, Empty etc. signals +-- -Input and Output always from the same register +-- -> input-buffer is shifted whenever write occurs +-- -> when read, a mux chooses which value to load to the output next +-- (the oldest) +-- +-- Fifo with case version 4: +-- different from v3: +-- - using variable data_amount in order to update it right away, +-- rather than wait util the process ends. +-- +-- !NOTE! isn't tested as one-length FIFO. doesn't probably work. (vector +-- length (1 downto 2) ... +-- +-- !NOTE! +-- * Output is zero when empty. (doesn't speed this up if otherwise). +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + + +entity fifo is + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; -- Active low + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + +architecture behavioral of fifo is + +-- range is this so that one can use data_amount directly to indexing + type reg is array (depth downto 2) of std_logic_vector + (width-1 downto 0); + signal input_buffer : reg; + +-- tie them together so that use of case is simpler + signal WR : std_logic_vector ( 1 downto 0); + +begin -- behavioral + + -- Concurrent assignment + WR <= Write_Enable & Read_Enable; + + + +process (Clk, rst_n) + variable Data_amount : integer range 0 to depth; +begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + for i in depth downto 2 loop + input_buffer(i) <= (others => '0'); + end loop; -- i + + Data_out <= (others => '0'); + Data_Amount := 0; + Empty <= '1'; + One_Data_Left <= '0'; + One_Place_Left <= '0'; + Full <= '0'; + + elsif Clk'event and Clk = '1' then -- rising clock edge + +case WR is + when "01" => -- Read data + if Data_amount = 0 then + Data_amount := Data_amount; + elsif Data_amount = 1 then + Data_out <= (others => '0'); + Data_amount := Data_amount-1; + else + Data_out <= input_buffer(Data_amount); + Data_amount := Data_amount-1; + end if; + + + when "10" => -- Write Data + + if Data_amount = 0 then + Data_out <= Data_In; + Data_amount := Data_amount+1; + elsif Data_amount = depth then + input_buffer <= input_buffer; + else + for i in depth-1 downto 2 loop -- Shifting + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + Data_amount := Data_amount+1; + end if; + + when "11" => -- Read and Write concurrently + + if Data_amount = 0 then -- cannot read if empty + Data_out <= Data_in; + Data_Amount := Data_Amount +1; + elsif Data_amount = 1 then + Data_out <= Data_In; + elsif Data_amount = depth then -- cannot write if full + Data_out <= input_buffer (Data_amount); + Data_amount := Data_amount-1; + else + Data_out <= input_buffer (Data_amount); + for i in depth-1 downto 2 loop -- Shifting + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + end if; + + when others => -- Do nothing, Both 0. + input_buffer <= input_buffer; + Data_amount := Data_amount; + +end case; + +-- because Data_amount is a variable, it's updated right-away. + + if Data_amount = 0 then -- Empty + Empty <= '1'; + One_Place_Left <= '0'; + One_Data_Left <= '0'; + Full <= '0'; + + elsif Data_amount = 1 then -- One_Data_Left + + Empty <= '0'; + One_Data_Left <= '1'; + One_Place_Left <= '0'; + Full <= '0'; + elsif Data_amount = depth-1 then --one_place_left + Empty <= '0'; + One_Place_Left <= '1'; + One_Data_Left <= '0'; + Full <= '0'; + elsif Data_amount = depth then --full + Empty <= '0'; + One_Place_Left <= '0'; + One_Data_Left <= '0'; + Full <= '1'; + else -- Otherwise every signal is low + Empty <= '0'; + One_Place_Left <= '0'; + One_Data_Left <= '0'; + Full <= '0'; + end if; + + end if; --synchronous + + end process; + +end behavioral; + + + + + + + + + + + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev5.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev5.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev5.vhdl (revision 18) @@ -0,0 +1,242 @@ +------------------------------------------------------------------------------- +-- File : fifo_casev5.vhdl +-- Description : Fifo buffer for hibi interface +-- Author : Ari Kulmala +-- Date : 10.06.2003 +-- Modified : 18.06.2003 - Re-wrote the way output control signals are +-- assigned +-- +-- +-- Detailed description: +-- -Input and Output always from the same register +-- -> input-buffer is shifted whenever write occurs +-- -> when read, a mux chooses which value to load to the output next +-- (the oldest) +-- +-- !NOTE! isn't tested as one-length FIFO. doesn't probably work. (vector +-- length (1 downto 2) ... +-- +-- !NOTE! +-- * Output is zero when empty. +------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + + +entity fifo is + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; -- Active low + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + + +architecture behavioral of fifo is + + -- range is this so that one can use data_amount directly to indexing + type reg is array (depth downto 2) of std_logic_vector + (width-1 downto 0); + signal input_buffer : reg; + -- Registers + signal Full_reg : std_logic; + signal Empty_reg : std_logic; + signal One_Data_Left_reg : std_logic; + signal One_Place_Left_reg : std_logic; + signal Data_amount : integer range 0 to depth; + + + signal WR : std_logic_vector ( 1 downto 0); + +begin -- behavioral + + -- Continuous assignments + -- Assigns register values to outputs + Full <= Full_reg; + Empty <= Empty_reg; + One_Data_Left <= One_Data_Left_reg; + One_Place_Left <= One_Place_Left_reg; + -- Concurrent assignment + WR <= Write_Enable & Read_Enable; + + + + process (Clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + for i in depth downto 2 loop + input_buffer(i) <= (others => '0'); + end loop; -- i + Data_out <= (others => '0'); + + Data_Amount <= 0; + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + One_Place_Left_reg <= '0'; + Full_reg <= '0'; + + elsif Clk'event and Clk = '1' then -- rising clock edge + + case WR is + when "01" => + -- Read data + if Data_amount = 0 then + -- empty + Data_amount <= Data_amount; + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + elsif Data_amount = 1 then + -- 1 data + Data_out <= (others => '0'); + Data_amount <= Data_amount-1; + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + elsif Data_amount = 2 then + Data_out <= input_buffer(Data_amount); + Data_amount <= Data_amount-1; + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + else + Data_out <= input_buffer(Data_amount); + Data_amount <= Data_amount-1; + One_Data_Left_reg <= '0'; + Empty_reg <= '0'; + end if; + + -- Fifo's getting emptier + if Data_amount = depth-1 then + One_Place_Left_reg <= '0'; + Full_reg <= '0'; + elsif Data_amount = depth then + One_Place_Left_reg <= '1'; + Full_reg <= '0'; + else + One_Place_Left_reg <= '0'; + Full_reg <= '0'; + end if; + + + when "10" => + -- Write Data + if Data_amount = 0 then + Data_out <= Data_In; + Data_amount <= Data_amount+1; + elsif Data_amount = depth then + input_buffer <= input_buffer; + else + for i in depth-1 downto 2 loop + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + Data_amount <= Data_amount+1; + end if; + + -- define the values for output control signals + if Data_amount = 0 then + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + elsif Data_amount = 1 then + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + elsif Data_amount = depth-2 then + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + elsif Data_amount = depth-1 then + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + Full_reg <= '1'; + One_Place_Left_reg <= '0'; + else + Empty_reg <= Empty_reg; + One_Data_Left_reg <= One_Data_Left_reg; + Full_reg <= Full_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + when "11" => + -- Read and Write concurrently + + if Data_amount = 0 then + -- can only write + Data_out <= Data_in; + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + Data_amount <= Data_amount+1; + + elsif Data_amount = 1 then + Data_out <= Data_In; + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + + elsif Data_amount = depth then + -- cannot write if full, just read + Data_out <= input_buffer (Data_amount); + Data_amount <= Data_amount-1; + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + else + Data_out <= input_buffer (Data_amount); + for i in depth-1 downto 2 loop + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + Empty_reg <= Empty_reg; + One_Data_Left_reg <= One_Data_Left_reg; + Full_reg <= Full_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + when others => + -- Do nothing, write and read low + input_buffer <= input_buffer; + Data_amount <= Data_amount; + Empty_reg <= Empty_reg; + One_Data_Left_reg <= One_Data_Left_reg; + Full_reg <= Full_reg; + One_Place_Left_reg <= One_Place_Left_reg; + + end case; + end if; --synchronous + end process; + +end behavioral; + + + + + + + + + + + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev4a.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev4a.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev4a.vhdl (revision 18) @@ -0,0 +1,173 @@ +-- Fifo with case version 4: +-- different from v3: +-- - using variable data_amount in order to update it right away, +-- rather than wait util the process ends. +-- +-- Designer : Ari Kulmala +-- +-- Variable Data_amount will infer register synthesis! Scary stuff, es 07.11.2003 + + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + + +entity fifo is + + generic ( + width : integer := 0; + depth : integer := 0 + ); + port ( + Clk : in std_logic; + Rst_n : in std_logic; -- Active low + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + +architecture behavioral of fifo is + + type reg is array (depth downto 2) of std_logic_vector + (width-1 downto 0); + signal input_buffer : reg; + + signal WR : std_logic_vector ( 1 downto 0); + +begin -- behavioral + + -- Concurrent assignment + WR <= Write_Enable & Read_Enable; + + + + process (Clk, rst_n) + variable Data_amount : integer range 0 to depth; + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + -- for i in depth downto 2 loop + -- input_buffer(i) <= (others => '0'); + -- end loop; -- i + -- Data_out <= (others => '0'); + + Data_Amount := 0; + Empty <= '1'; + One_Data_Left <= '0'; + One_Place_Left <= '0'; + Full <= '0'; + + elsif Clk'event and Clk = '1' then -- rising clock edge + + case WR is + when "01" => + -- Read data + if Data_amount = 0 then + Data_amount := Data_amount; + elsif Data_amount = 1 then + -- Data_out <= (others => '0'); + Data_amount := Data_amount-1; + else + Data_out <= input_buffer(Data_amount); + Data_amount := Data_amount-1; + end if; + + + when "10" => + -- Write Data + if Data_amount = 0 then + Data_out <= Data_In; + Data_amount := Data_amount+1; + elsif Data_amount = depth then + input_buffer <= input_buffer; + else + for i in depth-1 downto 2 loop + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + Data_amount := Data_amount+1; + end if; + + when "11" => + -- Read and Write concurrently + if Data_amount = 0 then + -- cannot read if empty + Data_out <= Data_in; + Data_Amount := Data_Amount +1; + elsif Data_amount = 1 then + Data_out <= Data_In; + elsif Data_amount = depth then + -- cannot write if full + Data_out <= input_buffer (Data_amount); + Data_amount := Data_amount-1; + else + Data_out <= input_buffer (Data_amount); + for i in depth-1 downto 2 loop + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + end if; + + when others => -- Do nothing + input_buffer <= input_buffer; + Data_amount := Data_amount; + + end case; + + if Data_amount = 0 then + Empty <= '1'; + One_Place_Left <= '0'; + One_Data_Left <= '0'; + Full <= '0'; + + elsif Data_amount = 1 then + + Empty <= '0'; + One_Data_Left <= '1'; + One_Place_Left <= '0'; + Full <= '0'; + elsif Data_amount = depth-1 then --one place left + Empty <= '0'; + + One_Place_Left <= '1'; + One_Data_Left <= '0'; + Full <= '0'; + elsif Data_amount = depth then --full + Empty <= '0'; + One_Place_Left <= '0'; + One_Data_Left <= '0'; + Full <= '1'; + + + else + Empty <= '0'; + One_Place_Left <= '0'; + One_Data_Left <= '0'; + Full <= '0'; + end if; + + end if; --synchronous + + end process; + +end behavioral; + + + + + + + + + + + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev6.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev6.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_casev6.vhdl (revision 18) @@ -0,0 +1,248 @@ +------------------------------------------------------------------------------- +-- File : fifo_casev6.vhdl +-- Description : Fifo buffer for hibi interface +-- Author : Ari Kulmala +-- Date : 10.06.2003 +-- Modified : 18.06.2003 - Re-wrote the way output control signals are +-- assigned +-- - output value is not zero when empty +-- +-- Detailed description: +-- -Input and Output always from the same register +-- -> input-buffer is shifted whenever write occurs +-- -> when read, a mux chooses which value to load to the output next +-- (the oldest) +-- +-- !NOTE! isn't tested as one-length FIFO. doesn't probably work. (vector +-- length (1 downto 2) ... +-- +-- !NOTE! +-- * Output stays in the old value when empty. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- To do: as in fifo_casev4: fifojen nollaus olisi syyta ehka poistaa myos +-- resetin yhteydesta, jos sita ei nollata myoskaan luettaessa viimeinen +-- samaten input_bufferin nollaus. +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + + +entity fifo is + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; -- Active low + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + +architecture behavioral of fifo is + + -- range is this so that one can use data_amount directly to indexing + type reg is array (depth downto 2) of std_logic_vector + (width-1 downto 0); + signal input_buffer : reg; + -- Registers + signal Full_reg : std_logic; + signal Empty_reg : std_logic; + signal One_Data_Left_reg : std_logic; + signal One_Place_Left_reg : std_logic; + + signal Data_amount : integer range 0 to depth; + + + signal WR : std_logic_vector ( 1 downto 0); + +begin -- behavioral + + -- Continuous assignments + -- Assigns register values to outputs + Full <= Full_reg; + Empty <= Empty_reg; + One_Data_Left <= One_Data_Left_reg; + One_Place_Left <= One_Place_Left_reg; + -- Concurrent assignment + WR <= Write_Enable & Read_Enable; + + + +process (Clk, rst_n) +begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + -- for i in depth downto 2 loop + -- input_buffer(i) <= (others => '0'); + -- end loop; -- i + -- Data_out <= (others => '0'); + Data_Amount <= 0; + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + One_Place_Left_reg <= '0'; + Full_reg <= '0'; + + elsif Clk'event and Clk = '1' then -- rising clock edge + + case WR is + when "01" => + -- Read data + if Data_amount = 0 then + -- empty + Data_amount <= Data_amount; + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + elsif Data_amount = 1 then -- 1 data + -- Data_out <= (others => '0'); + Data_amount <= Data_amount-1; + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + elsif Data_amount = 2 then + Data_out <= input_buffer(Data_amount); + Data_amount <= Data_amount-1; + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + else + Data_out <= input_buffer(Data_amount); + Data_amount <= Data_amount-1; + One_Data_Left_reg <= '0'; + Empty_reg <= '0'; + end if; + + if Data_amount = depth-1 then + One_Place_Left_reg <= '0'; + Full_reg <= '0'; + elsif Data_amount = depth then + One_Place_Left_reg <= '1'; + Full_reg <= '0'; + else + One_Place_Left_reg <= '0'; + Full_reg <= '0'; + end if; + + + when "10" => + -- Write Data + if Data_amount = 0 then + Data_out <= Data_In; + Data_amount <= Data_amount+1; + elsif Data_amount = depth then + input_buffer <= input_buffer; + else + for i in depth-1 downto 2 loop + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + Data_amount <= Data_amount+1; + end if; + + -- Define the control signals here + + if Data_amount = 0 then + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + elsif Data_amount = 1 then + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + elsif Data_amount = depth-2 then + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + elsif Data_amount = depth-1 then + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + Full_reg <= '1'; + One_Place_Left_reg <= '0'; + else + Empty_reg <= Empty_reg; + One_Data_Left_reg <= One_Data_Left_reg; + Full_reg <= Full_reg; + One_Place_Left_reg <= One_Place_Left_reg; + + end if; + + when "11" => + -- Read and Write concurrently + + if Data_amount = 0 then + -- can only write + Data_out <= Data_in; + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + Data_amount <= Data_amount+1; + + elsif Data_amount = 1 then + Data_out <= Data_In; + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + + elsif Data_amount = depth then + -- cannot write if full, just read + Data_out <= input_buffer (Data_amount); + Data_amount <= Data_amount-1; + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + else + Data_out <= input_buffer (Data_amount); + for i in depth-1 downto 2 loop + input_buffer(i+1) <= input_buffer(i); + end loop; -- i + input_buffer(2) <= Data_In; + Empty_reg <= Empty_reg; + One_Data_Left_reg <= One_Data_Left_reg; + Full_reg <= Full_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + when others => + -- Do nothing + input_buffer <= input_buffer; + Data_amount <= Data_amount; + Empty_reg <= Empty_reg; + One_Data_Left_reg <= One_Data_Left_reg; + Full_reg <= Full_reg; + One_Place_Left_reg <= One_Place_Left_reg; + + end case; + + end if; --synchronous + + end process; + +end behavioral; + + + + + + + + + + + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/dual_ram_async_read.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/dual_ram_async_read.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/dual_ram_async_read.vhd (revision 18) @@ -0,0 +1,74 @@ +------------------------------------------------------------------------------- +-- Title : Dual port RAM +-- Project : +------------------------------------------------------------------------------- +-- File : dual_ram.vhd +-- Author : +-- Company : +-- Created : 2005-05-26 +-- Last update: 2005-05-31 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: dual port RAM with asynchronous read for QuartusII +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2005-05-26 1.0 penttin5 Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dual_ram_async_read is + + generic ( + ram_width : integer := 0; + ram_depth : integer := 0); + port + ( + clock1 : in std_logic; + clock2 : in std_logic; + data : in std_logic_vector(0 to ram_width - 1); + write_address : in integer range 0 to ram_depth - 1; + read_address : in integer range 0 to ram_depth - 1; + we : in std_logic; + q : out std_logic_vector(0 to ram_width - 1) + ); + + type word is array(0 to ram_width - 1) of std_logic; + type ram is array(0 to ram_depth - 1) of std_logic_vector(0 to ram_width - 1); + subtype address_vector is integer range 0 to ram_depth - 1; + +-- signal read_address_reg : address_vector; + +end dual_ram_async_read; + +architecture rtl of dual_ram_async_read is + + signal ram_block : RAM; +begin + + process (clock1) + begin + if (clock1'event and clock1 = '1') then + if (we = '1') then + ram_block(write_address) <= data; + end if; + end if; + end process; + + + process (clock2) + begin + if (clock2'event and clock2 = '1') then + --q <= ram_block(read_address); + -- read_address_reg <= read_address; + end if; + end process; + + q <= ram_block (read_address); + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/double_fifo_demuxed_write.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/double_fifo_demuxed_write.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/double_fifo_demuxed_write.vhdl (revision 18) @@ -0,0 +1,272 @@ +------------------------------------------------------------------------------- +-- File : double_fifo_demuxed_write.vhdl +-- Description : Double_Fifo_Demuxed_Write buffer for hibi v.2 interface +-- Includes two fifos and a special demultiplexer +-- so that the writer sees only one fifo. Demultiplexer +-- directs addr+data to correct fifo (0 = for messages) +-- Author : Vesa Lahtinen +-- Date : 08.04.2003 +-- Modified : +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + + +entity double_fifo_demuxed_write is + + generic ( + Data_Width : integer := 0; + Depth_0 : integer := 0; + Depth_1 : integer := 0; + Comm_Width : integer := 0 + ); + port ( + Clk : in std_logic; + Rst_n : in std_logic; + + Data_In : in std_logic_vector ( Data_Width-1 downto 0); + Comm_In : in std_logic_vector ( Comm_Width-1 downto 0); + Addr_Valid_In : in std_logic; + Write_Enable_In : in std_logic; + One_Place_Left_Out : out std_logic; + Full_Out : out std_logic; + + Read_Enable_In_0 : in std_logic; + Data_Out_0 : out std_logic_vector ( Data_Width-1 downto 0); + Comm_Out_0 : out std_logic_vector ( Comm_Width-1 downto 0); + Addr_Valid_Out_0 : out std_logic; + Empty_Out_0 : out std_logic; + One_Data_Left_Out_0 : out std_logic; + + Read_Enable_In_1 : in std_logic; + Data_Out_1 : out std_logic_vector ( Data_Width-1 downto 0); + Comm_Out_1 : out std_logic_vector ( Comm_Width-1 downto 0); + Addr_Valid_Out_1 : out std_logic; + Empty_Out_1 : out std_logic; + One_Data_Left_Out_1 : out std_logic + ); +end double_fifo_demuxed_write; + + + +architecture structural of double_fifo_demuxed_write is + + + + + component fifo + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + + Read_Enable : in std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Empty : out std_logic; + One_Data_Left : out std_logic + ); + end component; --fifo; + + + component fifo_demux_write + generic ( + Data_Width : integer := 0; + Comm_Width : integer := 0); + + port ( + -- 13.04 Clk : in std_logic; + -- 13.04 Rst_n : in std_logic; + Data_In : in std_logic_vector (Data_Width-1 downto 0); + Addr_Valid_In : in std_logic; + Comm_In : in std_logic_vector (Comm_Width-1 downto 0); + WE_In : in std_logic; + One_Place_Left_Out : out std_logic; + Full_Out : out std_logic; + + -- Data/Comm/AV conencted to both fifos + -- Distinction made with WE! + Data_Out : out std_logic_vector (Data_Width-1 downto 0); + Comm_Out : out std_logic_vector (Comm_Width-1 downto 0); + Addr_Valid_Out : out std_logic; + WE_0_Out : out std_logic; + WE_1_Out : out std_logic; + Full_0_In : in std_logic; + Full_1_In : in std_logic; + One_Place_Left_0_In : in std_logic; + One_Place_Left_1_In : in std_logic + ); + end component; + + signal Data_AV_Comm_Out_0 : std_logic_vector ( 1 + Comm_Width + Data_Width-1 downto 0); + signal Data_AV_Comm_Out_1 : std_logic_vector ( 1 + Comm_Width + Data_Width-1 downto 0); + + signal Data_AV_Comm_From_Demux : std_logic_vector ( 1 + Comm_Width + Data_Width-1 downto 0); + + signal Data_Demux_To_fifo : std_logic_vector(Data_Width-1 downto 0); + signal Comm_Demux_To_fifo : std_logic_vector(Comm_Width-1 downto 0); + signal Addr_Valid_Demux_To_fifo : std_logic; + + signal Write_Enable_0 : std_logic; + signal Full_0 : std_logic; + signal One_Place_Left_0 : std_logic; + + signal Write_Enable_1 : std_logic; + signal Full_1 : std_logic; + signal One_Place_Left_1 : std_logic; + + signal Tie_High : std_logic; + signal Tie_Low : std_logic; + + +begin -- structural + -- Check generics + assert (Depth_0 + Depth_1 > 0) report "Both fifo depths zero!" severity warning; + + -- Concurrent assignments + Tie_High <= '1'; + Tie_Low <= '0'; + -- Combine fifo inputs + -- Data_AV_Comm_From_Demux <= Addr_Valid_Demux_To_fifo & Comm_Demux_To_fifo & Data_Demux_To_fifo; + + -- Splitting the data + Addr_Valid_Out_0 <= Data_AV_Comm_Out_0(Comm_Width+Data_Width); + Comm_Out_0 <= Data_AV_Comm_Out_0(Comm_Width+Data_Width-1 downto Data_Width); + Data_Out_0 <= Data_AV_Comm_Out_0(Data_Width-1 downto 0); + Addr_Valid_Out_1 <= Data_AV_Comm_Out_1(Comm_Width+Data_Width); + Comm_Out_1 <= Data_AV_Comm_Out_1(Comm_Width+Data_Width-1 downto Data_Width); + Data_Out_1 <= Data_AV_Comm_Out_1(Data_Width-1 downto 0); + + Map_Fifo_0 : if Depth_0 > 0 generate + Fifo_0 : fifo + generic map( + width => 1 + Comm_Width + Data_Width, + depth => Depth_0 + ) + port map( + Clk => Clk, + Rst_n => Rst_n, + + Data_In => Data_AV_Comm_From_Demux, + Write_Enable => Write_Enable_0, + One_Place_Left => One_Place_Left_0, + Full => Full_0, + + Read_Enable => Read_Enable_In_0, + Data_Out => Data_AV_Comm_Out_0, + Empty => Empty_Out_0, + One_Data_Left => One_Data_Left_Out_0 + ); + end generate Map_Fifo_0; + + Not_Map_Fifo_0 : if Depth_0 = 0 generate + -- Fifo #0 and demux does not exist! + Data_AV_Comm_Out_0 <= (others => '0'); + Empty_Out_0 <= Tie_High; + One_Data_Left_Out_0 <= Tie_Low; + Full_0 <= Tie_High; + One_Place_Left_0 <= Tie_Low; + Write_Enable_0 <= Tie_Low; + + -- Connect the other fifo (#1) straight to the outputs (FSM) + Write_Enable_1 <= Write_Enable_In; + One_Place_Left_Out <= One_Place_Left_1; + Full_Out <= Full_1; + Data_AV_Comm_From_Demux(Data_Width-1 downto 0) <= Data_In; + Data_AV_Comm_From_Demux(Comm_Width+Data_Width-1 downto Data_Width) <= Comm_In; + Data_AV_Comm_From_Demux(Comm_Width+Data_Width) <= Addr_Valid_In; + + end generate Not_Map_Fifo_0; + + + + + Map_Fifo_1 : if Depth_1 > 0 generate + Fifo_1 : fifo + generic map( + width => 1 + Comm_Width + Data_Width, + depth => Depth_1 + ) + port map( + Clk => Clk, + Rst_n => Rst_n, + + Data_In => Data_AV_Comm_From_Demux, + Write_Enable => Write_Enable_1, + One_Place_Left => One_Place_Left_1, + Full => Full_1, + + Read_Enable => Read_Enable_In_1, + Data_Out => Data_AV_Comm_Out_1, + Empty => Empty_Out_1, + One_Data_Left => One_Data_Left_Out_1 + ); + end generate Map_Fifo_1; + + Not_Map_Fifo_1 : if Depth_1 = 0 generate + -- Fifo #1 and demux does not exist! + Data_AV_Comm_Out_1 <= (others => '0'); + Empty_Out_1 <= Tie_High; + One_Data_Left_Out_1 <= Tie_Low; + Full_1 <= Tie_High; + One_Place_Left_1 <= Tie_Low; + Write_Enable_1 <= Tie_Low; + + -- Connect the other fifo (#0) straight to the outputs (FSM) + Write_Enable_0 <= Write_Enable_In; + One_Place_Left_Out <= One_Place_Left_0; + Full_Out <= Full_0; + Data_AV_Comm_From_Demux(Data_Width-1 downto 0) <= Data_In; + Data_AV_Comm_From_Demux(Comm_Width+Data_Width-1 downto Data_Width) <= Comm_In; + Data_AV_Comm_From_Demux(Comm_Width+Data_Width) <= Addr_Valid_In; + + end generate Not_Map_Fifo_1; + + + Map_Demux : if Depth_0 > 0 and Depth_1 > 0 generate + -- Demultiplexer is needed only if two fifos are used + DEMUX_01 : fifo_demux_write + generic map( + Data_Width => Data_Width, + Comm_Width => Comm_Width + ) + port map( + -- 13.04 + -- Clk => Clk, + -- Rst_n => Rst_n, + Data_In => Data_In, + Comm_In => Comm_In, + Addr_Valid_In => Addr_Valid_In, + WE_In => Write_Enable_In, + + One_Place_Left_Out => One_Place_Left_Out, + Full_Out => Full_Out, + Data_Out => Data_AV_Comm_From_Demux(Data_Width-1 downto 0), + Comm_Out => Data_AV_Comm_From_Demux(Comm_Width+Data_Width-1 downto Data_Width), + Addr_Valid_Out => Data_AV_Comm_From_Demux(Comm_Width+Data_Width), + WE_0_Out => Write_Enable_0, + WE_1_Out => Write_Enable_1, + + Full_0_In => Full_0, + Full_1_In => Full_1, + One_Place_Left_0_In => One_Place_Left_0, + One_Place_Left_1_In => One_Place_Left_1 + ); + end generate Map_Demux; + + +end structural; + + + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_im_case.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_im_case.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_im_case.vhdl (revision 18) @@ -0,0 +1,287 @@ +------------------------------------------------------------------------------- +-- File : fifo_im_case.vhdl +-- Description : Fifo buffer for hibi interface +-- Author : Erno Salminen +-- Date : 29.04.2002 +-- Modified : 30.04.2002 Vesa Lahtinen Optimized for synthesis +-- +-- 02.06 ES: default assignment Fifo_Buffer <= Fifo_Buffer +-- smaller and faster implementation +-- Effect on synthesis is uncertain : +-- small fifos seem to gets smaller and faster, but big fifos +-- get bigger and slower. Strange. +-- +-- ?.06.03 AK - uses "case" instead of "if" in main process. +-- (makes it concurrent rather than sequential) +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity fifo is + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + +architecture behavioral of fifo is + + type data_array is array (depth-1 downto 0) of std_logic_vector (width-1 downto 0); + signal Fifo_Buffer : data_array; + + -- Registers + signal Full_reg : std_logic; + signal Empty_reg : std_logic; + signal One_Data_Left_reg : std_logic; + signal One_Place_Left_reg : std_logic; + --signal Data_Amount : std_logic_vector (depth-1 downto 0); + signal Data_Amount : integer range 0 to depth-1; + signal WR : std_logic_vector ( 1 downto 0); + + +begin -- in_mux + + -- Continuous assignments + -- Assigns register values to outputs + Full <= Full_reg; + Empty <= Empty_reg; + One_Data_Left <= One_Data_Left_reg; + One_Place_Left <= One_Place_Left_reg; + Data_Out <= Fifo_Buffer (0); + -- Note! There is some old value in data output when fifo is empty. + + WR <= Write_Enable & Read_Enable; + + +Main : process (Clk, Rst_n) +begin -- process Main + if Rst_n = '0' then -- asynchronous reset (active low) + + -- Reset all registers + -- Fifo is empty at first + Full_reg <= '0'; + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + Data_Amount <= 0; + + if depth =1 then -- 30.07 + One_Place_Left_reg <= '1'; + else + One_Place_Left_reg <= '0'; + end if; + + for i in 0 to depth-1 loop + Fifo_Buffer (i) <= (others => '0'); + end loop; -- i + + elsif Clk'event and Clk = '1' then -- rising clock edge + + + -- 1) Write data to fifo +-- if Write_Enable = '1' and Read_Enable = '0' then + + case WR is + when "10" => + + if Full_reg = '0' then + Empty_reg <= '0'; + Data_Amount <= Data_Amount +1; + + Fifo_Buffer <= Fifo_Buffer; --02.06 + Fifo_Buffer (Data_Amount) <= Data_In; + + -- Check if the fifo is getting full + if Data_Amount + 2 = depth then + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + elsif Data_Amount +1 = depth then + Full_reg <= '1'; + One_Place_Left_reg <= '0'; + else + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + end if; + + + -- If fifo was empty, it has now one data + if Empty_reg = '1' then + One_Data_Left_reg <= '1'; + else + One_Data_Left_reg <= '0'; + end if; + + else + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + + -- 2) Read data from fifo +-- elsif Write_Enable = '0' and Read_Enable = '1' then + + when "01" => + if Empty_reg = '0' then + + -- Shiftaus + Fifo_Buffer <= Fifo_Buffer; --02.06 + for i in 0 to depth-2 loop + Fifo_Buffer (i) <= Fifo_Buffer (i+1); + end loop; -- i + + Full_reg <= '0'; + Data_Amount <= Data_Amount -1; + + -- Debug + -- Fifo_Buffer (out_ptr) <= (others => '1'); + + + + + -- Check if the fifo is getting empty + if Data_Amount = 2 then + Empty_reg <= '0'; + One_data_Left_reg <= '1'; + elsif Data_Amount = 1 then + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + else + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + end if; + + -- If fifo was full, it is no more + if Full_reg = '1' then + One_Place_Left_reg <= '1'; + else + One_Place_Left_reg <= '0'; + end if; + + else + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + + -- 3) Write and read at the same time +-- elsif Write_Enable = '1' and Read_Enable = '1' then + + when "11" => + + if Full_reg = '0' and Empty_reg = '0' then + Full_reg <= '0'; + Empty_reg <= '0'; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + + Fifo_Buffer <= Fifo_Buffer; --02.06 + -- Shiftaus + for i in 0 to depth-2 loop + Fifo_Buffer (i) <= Fifo_Buffer (i+1); + end loop; -- i + Fifo_Buffer (Data_Amount-1) <= Data_In; --vai amount-1 ?? koska pitaa + --shiftata samalla + + -- Fifo_Buffer (out_ptr) <= (others => '1'); --debug + + + elsif Full_reg = '1' and Empty_reg = '0' then + -- Fifo is full, only reading is possible + + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + --Fifo_Buffer (out_ptr) <= (others => '1'); -- Debug + Data_Amount <= Data_Amount -1; + + Fifo_Buffer <= Fifo_Buffer; --02.06 + -- Shiftaus + for i in 0 to depth-2 loop + Fifo_Buffer (i) <= Fifo_Buffer (i+1); + end loop; -- i + + -- Check if the fifo is getting empty + if Data_Amount = 2 then + Empty_reg <= '0'; + One_data_Left_reg <= '1'; + elsif Data_Amount = 1 then + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + else + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + end if; + + + elsif Full_reg = '0' and Empty_reg = '1' then + -- Fifo is empty, only writing is possible + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + Fifo_Buffer <= Fifo_Buffer; --02.06 + Fifo_Buffer (Data_Amount) <= Data_In; --Data_Amount =0 + Data_Amount <= Data_Amount +1; + + -- Check if the fifo is getting full + if Data_Amount + 2 = depth then + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + elsif Data_Amount +1 = depth then + Full_reg <= '1'; + One_Place_Left_reg <= '0'; + else + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + end if; + + + else + -- Fifo is full and empty at the same time => impossible + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; --Full_reg & Empty_reg + + + -- 4) Do nothing, fifo remains idle +-- else + + when others => + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end case; + + end if; +end process Main; + +end behavioral; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_muxes.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_muxes.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_muxes.vhdl (revision 18) @@ -0,0 +1,771 @@ +------------------------------------------------------------------------------- +-- File : fifo_muxes.vhdl +-- Description : Makes two fifos look like a single fifo. +-- Two components : one for writing and one for reading fifo. +-- Write_demux: +-- Input : data, addr valid and command +-- Out : data, addr valid and command to two fifos +-- +-- Read_mux : +-- Input : data, addr valid and command from two fifos +-- Out : data, addr valid and command +-- +-- NOTE: +-- 1) +-- Read_mux does not fully support One_Data_Left_Out! +-- +-- It works when writing to fifo. However, when something +-- is written to empty fifo, One_Data_Left_Out remains 0 +-- even if Empty goes from 1 to 0! Be careful out there. +-- +-- Case when new addr is written to fifo 0 and there is a gap before +-- corresponding data. At the same time there is some data in fifo +-- #1. It is not wise to wait for data#0, because it blocks the data#1. +-- In such, case transfer from fifo#0 is interrupted (Empty goes high). +-- At the moment, One_Data_Left_Out does not work in such case. +-- (Probably it could be repaired with fifo_bookkeeper component?) +-- 2) +-- +-- Author : Erno Salminen +-- Date : 05.02.2003 +-- Modified : +-- +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + + + + +-- Write_Mux checks the incoming addr. Same addr is not +-- written to fifo more than once! Written fifo is selected +-- according to incoming command +entity fifo_demux_write is + + generic ( + Data_Width : integer := 0; + Comm_Width : integer := 0 + ); + port ( + -- 13.04 Fully asynchronous! + --Clk : in std_logic; + --Rst_n : in std_logic; + + Data_In : in std_logic_vector (Data_Width-1 downto 0); + Addr_Valid_In : in std_logic; + Comm_In : in std_logic_vector (Comm_Width-1 downto 0); + WE_In : in std_logic; + One_Place_Left_Out : out std_logic; + Full_Out : out std_logic; + + -- Data/Comm/AV conencted to both fifos + -- Distinction made with WE! + Data_Out : out std_logic_vector (Data_Width-1 downto 0); + Comm_Out : out std_logic_vector (Comm_Width-1 downto 0); + Addr_Valid_Out : out std_logic; + WE_0_Out : out std_logic; + WE_1_Out : out std_logic; + Full_0_In : in std_logic; + Full_1_In : in std_logic; + One_Place_Left_0_In : in std_logic; + One_Place_Left_1_In : in std_logic + ); + +end fifo_demux_write; + + + + + + +-- constant Idle : std_logic_vector ( Comm_Width-1 downto 0) := "000"; -- 0 +-- constant Write_Config_Data : std_logic_vector ( Comm_Width-1 downto 0) := "001"; -- 1 +-- constant Write_Data : std_logic_vector ( Comm_Width-1 downto 0) := "010"; -- 2 +-- constant Write_Message : std_logic_vector ( Comm_Width-1 downto 0) := "011"; -- 3 + +-- constant Read_RQ : std_logic_vector ( Comm_Width-1 downto 0) := "100"; -- 4 +-- constant Read_Config : std_logic_vector ( Comm_Width-1 downto 0) := "101"; -- 5 +-- constant Multicast_Data : std_logic_vector ( Comm_Width-1 downto 0) := "110"; -- 6 +-- constant Multicast_Message : std_logic_vector ( Comm_Width-1 downto 0) := "111"; -- 7 + +architecture rtl of fifo_demux_write is + +begin -- rtl + + + -- Concurrent assignments + Data_Out <= Data_In; + Addr_Valid_Out <= Addr_Valid_In; + Comm_Out <= Comm_In; + + + -- PROCESSES + -- Fully combinational + Demultiplex_data : process (Data_In, Addr_Valid_In, Comm_In, WE_In, + One_Place_Left_0_In, One_Place_Left_1_In, + Full_0_In, Full_1_In) + begin -- process Demultiplex_data + + if Comm_In = conv_std_logic_vector (3, Comm_Width) + or Comm_In = conv_std_logic_vector (7, Comm_Width) then + -- MESSAGE + + WE_0_Out <= WE_In; + WE_1_Out <= '0'; + Full_Out <= Full_0_In; + One_Place_Left_Out <= One_Place_Left_0_In; + + + elsif Comm_In = conv_std_logic_vector (2, Comm_Width) + or Comm_In = conv_std_logic_vector (4, Comm_Width) + or Comm_In = conv_std_logic_vector (6, Comm_Width) then + -- DATA + WE_0_Out <= '0'; + WE_1_Out <= WE_In; + Full_Out <= Full_1_In; + One_Place_Left_Out <= One_Place_Left_1_In; + + + elsif Comm_In = conv_std_logic_vector (1, Comm_Width) + or Comm_In = conv_std_logic_vector (5, Comm_Width) then + -- CONFIG + assert false report "Config comm to fifo_demux_write" severity warning; + WE_0_Out <= '0'; + WE_1_Out <= '0'; + Full_Out <= '0'; + One_Place_Left_Out <= '0'; + + + else + --IDLE + WE_0_Out <= '0'; + WE_1_Out <= '0'; + Full_Out <= '0'; + One_Place_Left_Out <= '0'; + end if; --Comm_In + + + end process Demultiplex_data; + + + +end rtl; --fifo_demux_write + + + + + + +------------------------------------------------------------------------------- +--entity fifo_mux_read kaytetaan lukemaan kahdesta fifosta osoite ja data perakkain +-- fifolla 0 on suurempi prioritetti. Jos ollaan lukemassa fifoa 1, ei ruveta +-- lukemaan fifoa 0 ennekuin on siirretty ainakin yksi data fifosta 1. +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + + + + +entity fifo_mux_read is + + generic ( + Data_Width : integer := 0; + Comm_Width : integer := 0 + ); + port ( + Clk : in std_logic; + Rst_n : in std_logic; + + Data_0_In : in std_logic_vector (Data_Width-1 downto 0); + Comm_0_In : in std_logic_vector (Comm_Width-1 downto 0); + Addr_Valid_0_In : in std_logic; + One_Data_Left_0_In : in std_logic; + Empty_0_In : in std_logic; + RE_0_Out : out std_logic; + + Data_1_In : in std_logic_vector (Data_Width-1 downto 0); + Comm_1_In : in std_logic_vector (Comm_Width-1 downto 0); + Addr_Valid_1_In : in std_logic; + One_Data_Left_1_In : in std_logic; + Empty_1_In : in std_logic; + RE_1_Out : out std_logic; + + Read_Enable_In : in std_logic; + Data_Out : out std_logic_vector (Data_Width-1 downto 0); + Comm_Out : out std_logic_vector (Comm_Width-1 downto 0); + Addr_Valid_Out : out std_logic; + One_Data_Left_Out : out std_logic; + Empty_Out : out std_logic + ); + +end fifo_mux_read; + + +architecture rtl of fifo_mux_read is + signal Last_Addr_Reg_0 : std_logic_vector ( Comm_Width+Data_Width-1 downto 0); + signal Last_Addr_Reg_1 : std_logic_vector ( Comm_Width+Data_Width-1 downto 0); + + signal State_Reg : integer range 0 to 5; + -- Transferred_Reg - siirron tila + -- 00) Ei ole siirretty viela mitaan + -- 01) Osoite fifossa 0 + -- 02) Data fifossa 0 + -- 03) Osoite fifosta 1 + -- 04) Data fifosta 1 + -- 05) mol tyhjia + + -- Tilasiirtymat + -- 00 -> 01, 03 + -- 01 -> 02 + -- 02 -> 01, 02, 03 + -- 03 -> 04 + -- 04 -> 01, 04, 05 + -- 05 -> 01, 03 + +begin -- rtl + + + + -- PROC + Assign_Outputs : process (State_Reg, Data_1_In, Data_0_In, Addr_Valid_1_In, Addr_Valid_0_In, + Comm_0_In, Comm_1_In, Empty_0_In, Empty_1_In, + One_Data_Left_0_In, One_Data_Left_1_In, + Last_Addr_Reg_0, Last_Addr_Reg_1, Read_Enable_In) + begin -- process Assign_Outputs + + case State_Reg is + + when 0 => + -- Ei ole tehty mitaan + Data_Out <= (others => '0'); -- 'Z'); -- '0'); + Comm_Out <= (others => '0'); -- 'Z'); -- '0'); + Addr_Valid_Out <= '0'; + Empty_Out <= '1'; + RE_0_Out <= '0'; + RE_1_Out <= '0'; + + + + when 1 => + -- Siirretaan osoite 0 + + -- joko rekisterista (sama osoite kuin viimeksikin) + -- tai suoraan fifosta (uusi osoite, otetaan se myos talteen) + if Addr_Valid_0_In = '1' then + -- Uusi osoite + Data_Out <= Data_0_In; + Comm_Out <= Comm_0_In; + RE_0_Out <= Read_Enable_In; + else + Data_Out <= Last_Addr_Reg_0 (Data_Width-1 downto 0); + Comm_Out <= Last_Addr_Reg_0 ( Comm_Width+Data_Width-1 downto Data_Width); + RE_0_Out <= '0'; + + end if; + Addr_Valid_Out <= '1'; + Empty_Out <= '0'; + RE_1_Out <= '0'; + + + + when 2 => + -- Siirretaan data fifosta 0 + + if Addr_Valid_0_In = '1' and One_Data_Left_0_In = '1' then + -- Fifossa 0 pelkka osoite + + if Empty_1_In = '1' + or (Addr_Valid_1_In = '1' and One_Data_Left_1_In = '1') then + -- Fifo 1 tyhja tai siella pelkka osoite + RE_0_Out <= '0'; + RE_1_Out <= '0'; + Data_Out <= (others => '0'); -- 'X'); + Comm_Out <= (others => '0'); -- 'X'); + Addr_Valid_Out <= '0'; + Empty_Out <= '1'; + else + -- Fifossa 1 olisi jotain, otetaan varman paalle + RE_0_Out <= '0'; + RE_1_Out <= '0'; + Data_Out <= (others => '0'); -- '-'); + Comm_Out <= (others => '0'); -- '-'); + Addr_Valid_Out <= '0'; + Empty_Out <= '1'; + end if; --e_1 || (av1&1left1) + else + -- Fifossa 0 osoite+jotain tai dataa + RE_0_Out <= Read_Enable_In; + RE_1_Out <= '0'; + + Data_Out <= Data_0_In; + Comm_Out <= Comm_0_In; + Addr_Valid_Out <= Addr_Valid_0_In; + Empty_Out <= Empty_0_In; + end if; --av_1 + + + + + when 3 => + -- Siirretaan osoite 1 + + if Addr_Valid_1_In = '1' then + -- Uusi osoite + Data_Out <= Data_1_In; + Comm_Out <= Comm_1_In; + RE_1_Out <= Read_Enable_In; + else + Data_Out <= Last_Addr_Reg_1 (Data_Width-1 downto 0); + Comm_Out <= Last_Addr_Reg_1 ( Comm_Width+Data_Width-1 downto Data_Width); + RE_1_Out <= '0'; + end if; + RE_0_Out <= '0'; + Addr_Valid_Out <= '1'; + Empty_Out <= '0'; + + + + + when 4 => + -- Siirretaan fifosta 1 + + + if Addr_Valid_1_In = '1' and One_Data_Left_1_In = '1' then + -- Fifossa 1 pelkka osoite + + if Empty_0_In = '1' + or (Addr_Valid_0_In = '1' and One_Data_Left_0_In = '1') then + -- Fifo 0 tyhja tai siella pelkka osoite + RE_0_Out <= '0'; + RE_1_Out <= '0'; + Data_Out <= (others => '0'); -- 'X'); + Comm_Out <= (others => '0'); -- 'X'); + Addr_Valid_Out <= '0'; + Empty_Out <= '1'; + else + -- Fifossa 0 olisi jotain, otetaan varman paalle + RE_0_Out <= '0'; + RE_1_Out <= '0'; + Data_Out <= (others => '0'); -- '-'); + Comm_Out <= (others => '0'); -- '-'); + Addr_Valid_Out <= '0'; + Empty_Out <= '1'; + end if; --e_0 || (av0&1left0) + else + -- Fifossa 1 osoite+jotain tai dataa + RE_0_Out <= '0'; + RE_1_Out <= Read_Enable_In; + + Data_Out <= Data_1_In; + Comm_Out <= Comm_1_In; + Addr_Valid_Out <= Addr_Valid_1_In; + Empty_Out <= Empty_1_In; + end if; --av_1 + + + + when 5 => + -- Molemmat fifot tyhjia + RE_0_Out <= '0'; + RE_1_Out <= '0'; + Data_Out <= (others => '0'); -- 'Z'); -- '0'); + Comm_Out <= (others => '0'); -- 'Z'); -- '0'); + Addr_Valid_Out <= '0'; + Empty_Out <= '1'; + + when others => + RE_0_Out <= '0'; + RE_1_Out <= '0'; + Data_Out <= (others => '0'); -- 'Z'); -- '0'); + Comm_Out <= (others => '0'); -- 'Z'); -- '0'); + Addr_Valid_Out <= '0'; + Empty_Out <= '1'; + assert false report "Illegal state in fifo_mux_read" severity warning; + end case; + + end process Assign_Outputs; + + + + + -- PROC + Reg_proc : process (Clk, Rst_n) + begin -- process Reg_proc + if Rst_n = '0' then -- asynchronous reset (active low) + State_Reg <= 5; + Last_Addr_Reg_0 <= (others => '0'); -- '0'); + Last_Addr_Reg_1 <= (others => '0'); -- 'Z'); -- '0'); + + elsif Clk'event and Clk = '1' then -- rising clock edge + case State_Reg is + + when 0 => +-- -- Ei ole tehty mitaan + + + + + when 1 => + -- Siirretaan osoite 0 + -- joko rekisterista (sama osoite kuin viimeksikin) + -- tai suoraan fifosta (uusi osoite, otetaan se myos talteen) + if Read_Enable_In = '1' then + State_Reg <= 2; + else + State_Reg <= 1; + end if; + + if Addr_Valid_0_In = '1' then + -- Uusi osoite + Last_Addr_Reg_0 <= Comm_0_In & Data_0_In; + else + Last_Addr_Reg_0 <= Last_Addr_Reg_0; + end if; + + + + when 2 => + -- Siirretaan fifosta 0 + + if Read_Enable_In = '1' then + -- Luetaan fifosta 0 + + if One_Data_Left_0_In = '1' then + -- Oli viim data fifossa 0 + if Empty_1_In = '1' + or (Addr_Valid_1_In = '1' and One_Data_Left_1_In = '1') then + -- Myos fifo 1 tyhja tai siella pelkka osoite + State_Reg <= 5; + else + -- Siirretaan osoite 1 (fifosta tai rekisterista) + State_Reg <= 3; + end if; --Empty_1_In + Last_Addr_Reg_0 <= Last_Addr_Reg_0; + Last_Addr_Reg_1 <= Last_Addr_Reg_1; + + else + -- Fifossa 0 lukemisen jalkeenkin viela jotain + State_Reg <= 2; + Last_Addr_Reg_1 <= Last_Addr_Reg_1; + + if Addr_Valid_0_In = '1' then + -- fifosta 0 luettiin osoite + Last_Addr_Reg_0 <= Comm_0_In & Data_0_In; + else + -- Fifosta 0 luettiin dataa + Last_Addr_Reg_0 <= Last_Addr_Reg_0; + end if; --Addr_Valid_0_In + end if; --Empty_0_In + + + + + else + -- Odotellaan etta data luetaan + State_Reg <= 2; + Last_Addr_Reg_0 <= Last_Addr_Reg_0; + Last_Addr_Reg_1 <= Last_Addr_Reg_1; + end if; --Read_Enable_In + + + + + + + + when 3 => + -- Siirretaan osoite 1 + if Read_Enable_In = '1' then + State_Reg <= 4; + else + -- Odotellaan lukua + State_Reg <= 3; + end if; + + if Addr_Valid_1_In = '1' then + -- Uusi osoite + Last_Addr_Reg_1 <= Comm_1_In & Data_1_In; + else + Last_Addr_Reg_1 <= Last_Addr_Reg_1; + end if; + + + + when 4 => + -- Siirretaan fifosta 1 + + if Read_Enable_In = '1' then + -- Luetaan fifoa 1 + + if Addr_Valid_1_In = '1' then + -- Luetaan osoite fifosta 1 + Last_Addr_Reg_0 <= Last_Addr_Reg_0; + Last_Addr_Reg_1 <= Comm_1_In & Data_1_In; + + if One_Data_Left_1_In = '1' then + -- fifossa oli pelkka osoite + -- puolittainen VIRHE? + assert false report "Was? 1" severity note; + State_Reg <= 5; + else + -- Fifossa 1 on myos dataa, luetaan se + -- ennen (mahdollista) siirtymista + -- fifon 1 lukemiseen + State_Reg <= 4; + end if; --One_Data_Left_1_In + + else + -- Luetaan data fifosta 1 + + if Empty_0_In = '1' + or (Addr_Valid_0_In = '1' and One_Data_Left_0_In = '1') then + -- Fifo 0 tyhja tai siella pelkka osoite + + if One_Data_Left_1_In = '0' then + -- Onneksi fifossa 1 on viela jotain + State_Reg <= 4; + else + -- Ei ole siis kummassakaan fifossa mit'n + State_Reg <= 5; + end if; -- One_Data_Left_1_In + + + else + -- fifossa 0 luettavaa + -- siirretann siis osoite 1 seuraavaksi (fifosta/rekisterista) + State_Reg <= 1; + Last_Addr_Reg_0 <= Last_Addr_Reg_0; + Last_Addr_Reg_1 <= Last_Addr_Reg_1; + end if; --Empty_0_In or (av0 & 1left_0) + end if; --Addr_Valid_0_In + + + else + -- Odotetaan etta luetaan fifoa 1 + --State_Reg <= 4; + Last_Addr_Reg_0 <= Last_Addr_Reg_0; + Last_Addr_Reg_1 <= Last_Addr_Reg_1; + + if Addr_Valid_1_In = '1' and One_Data_Left_1_In ='1' then + -- Ei olekaan kuin pelkka osoite fifossa #1! + if Empty_0_In = '1' + or (Addr_Valid_0_In = '1' and One_Data_Left_0_In ='1') then + -- Ei ole fifossa 0 :kaan mitaan jarkevaa + State_Reg <= 5; + else + -- Voidaan siirtaa osoite 0 seuraavaksi + State_Reg <= 1; + end if; + else + -- fifossa 1 on myos dataa, odotellaan lukemista + State_Reg <= 4; + end if; + + + + end if; --Read_Enable_In + + + + + when 5 => + -- Ei voitu lukea kummastakaan fifosta + + Last_Addr_Reg_0 <= Last_Addr_Reg_0; + Last_Addr_Reg_1 <= Last_Addr_Reg_1; + + + if Empty_0_In = '1' or ( Addr_Valid_0_In = '1' and One_Data_Left_0_In ='1') then + -- Fifo 0 tyhja tai siella pelkka osoite + if Empty_1_In = '1' or ( Addr_Valid_1_In = '1' and One_Data_Left_1_In ='1') then + -- Fifo 1 tyhja tai siella pelkka osoite + -- => KUmmastakaan ei voi lukea + State_Reg <= 5; + else + -- Fifossa 1 jotain + -- siirretann siis osoite 1 seuraavaksi (fifosta/rekisterista) + State_Reg <= 3; + end if;--Empty_0_In or (av0 & 1left_0) + + else + -- Fifossa 0 jotain + -- siirretann siis osoite 0 seuraavaksi (fifosta/rekisterista) + State_Reg <= 1; + end if; --Empty_0_In or (av0 & 1left_0) + + + + + + + + when others => + assert false report "Illegal state in fifo_mux_read" severity warning; + end case; + + + end if; + end process Reg_proc; + + + -- One_Data_Left_Out on sen verta vaikea, etta tehdaan se omassa prosessissaan + Assign_1_D_Left_Out : process (State_Reg, + Data_0_In, Data_1_In, + Comm_0_In, Comm_1_In, + Empty_0_In, Empty_1_In, + Addr_Valid_0_In, Addr_Valid_1_In, + One_Data_Left_0_In,One_Data_Left_1_In, + Last_Addr_Reg_0, Last_Addr_Reg_1, + Read_Enable_In) + begin -- process Assign_1_D_Left_Out + case State_Reg is + + when 0 => + -- Ei ole tehty mitaan + One_Data_Left_Out <= '0'; + + when 1 => + -- Siirretaan osoite 0 + -- ellei ihmeita tapahdu, One_Data_Left_Out pitaisi olla 0! + + if Addr_Valid_0_In = '1' then + --Olisi syyta olla dataakin fifossa 0, toivotaan + One_Data_Left_Out <= '0'; + else + -- Sama osoite kuin viimeksi (rekisterista) + if Empty_0_In = '1' then + -- Fifossa 0 tyhja + assert false report + "Retrsnferring addr#0, but fifo#0 is empty. ERROR?" severity warning; + + + if Empty_1_In = '1' + or (Addr_Valid_1_In = '1' and One_Data_Left_1_In = '1') then + -- ja fifo 1:kin on tyhja, tai siina on pelkka osoite + One_Data_Left_Out <= '1'; + else + -- Voidaan siirtya lukemaan fifoa 1 + One_Data_Left_Out <= '0'; + end if; -- Empty_1_In || (av1 &1d_Left1) + else + One_Data_Left_Out <= '0'; + end if; -- Empty_0_In + + end if; -- Addr_Valid_0 + + + + + when 2 => + -- Siirretaan data fifosta 0 + + if One_Data_Left_0_In = '1' then + -- Fifo 0 tyhjenee + + if Empty_1_In = '1' then + -- ja fifo 1:kin on tyhja + One_Data_Left_Out <= '1'; + else + if Addr_Valid_1_In = '1' and One_Data_Left_1_In = '1' then + -- Fifossa 1 pelkka osoite + One_Data_Left_Out <= '1'; + else + -- Voidaan siirtya lukemaan fifoa 1 + One_Data_Left_Out <= '0'; + end if; --AV1 & 1D_Left1 + end if; -- Empty_1_In + else + -- Fifoon 0 jaa jotain + One_Data_Left_Out <= '0'; + end if; --One_Data_Left_0_In + + + + when 3 => + -- Siirretaan osoite 1 + -- ellei ihmeita tapahdu, One_Data_Left_Out pitaisi olla 0! + + if Addr_Valid_1_In = '1' then + --Olisi syyta olla dataakin fifossa 1, toivotaan + One_Data_Left_Out <= '0'; + else + -- Sama osoite kuin viimeksi (rekisterista) + + if Empty_1_In = '1' then + -- Fifo 1 on tyhja + assert false report + "Retrsnferring addr#1, but fifo#1 is empty. ERROR?" severity warning; + + if Empty_0_In = '1' + or (Addr_Valid_0_In = '1' and One_Data_Left_0_In = '1' )then + -- ja fifo 0:kin on tyhja + One_Data_Left_Out <= '1'; + else + -- Voidaan siirtya lukemaan fifoa 0 + One_Data_Left_Out <= '0'; + end if; -- Empty_1_In & (AV1 & 1D_Left1) + -- + else + One_Data_Left_Out <= '0'; + end if; --Empty_Left_1_In + end if; -- Addr_Valid_1 + + + + + + + when 4 => + -- Siirretaan data 1 + + if One_Data_Left_1_In = '1' then + -- fifo 1 tyhjenee + + if Empty_0_In = '1' + or (Addr_Valid_0_In = '1' and One_Data_Left_0_In = '1') then + -- Fifo 0:kin on tyhja tai siella pelkka osoite + One_Data_Left_Out <= '1'; + else + -- Voidaan siirtya lukemaan fifoa 0 + One_Data_Left_Out <= '0'; + end if; --Empty_0_In & (av0 & 1_D_Left0) + + else + -- Fifoon 1 jaa jotain + One_Data_Left_Out <= '0'; + end if; --One_Data_Left_1_In + + + + when 5 => + -- Molemmat fifot tyhjia + One_Data_Left_Out <= '0'; + + + when others => + One_Data_Left_Out <= '0'; + assert false report "Illegal state in fifo_mux_read" severity warning; + end case; + end process Assign_1_D_Left_Out; + + + + + + +end rtl; + + + + + + + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_reg.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_reg.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_reg.vhd (revision 18) @@ -0,0 +1,80 @@ +------------------------------------------------------------------------------- +-- Title : fifo_reg +-- Project : +------------------------------------------------------------------------------- +-- File : fifo_reg.vhd +-- Author : +-- Company : +-- Created : 2005-05-23 +-- Last update: 31.05.2005 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2005-05-23 1.0 penttin5 Created +-- 31.5.2005 AK Naming scheme according to coding rules +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity fifo_reg is + + generic ( + width_g : integer := 0 + ); + + port ( + clk : in std_logic; + rst_n : in std_logic; + load_in : in std_logic; + data1_in : in std_logic_vector(width_g - 1 downto 0); + data2_in : in std_logic_vector(width_g - 1 downto 0); + data_sel_in : in std_logic; + data_out : out std_logic_vector(width_g - 1 downto 0) + ); + +end fifo_reg; + +architecture RTL of fifo_reg is + + signal data_r : std_logic_vector(width_g - 1 downto 0); + signal load_and_sel : std_logic_vector(1 downto 0); + +begin -- RTL + + load_and_sel <= load_in & data_sel_in; + data_out <= data_r; + + fifo_reg : process (clk, rst_n) + begin -- process fifo_reg + if rst_n = '0' then -- asynchronous reset (active low) + data_r <= (others => '0'); + + elsif clk'event and clk = '1' then -- rising clock edge + case load_and_sel is + when "10" => + data_r <= data1_in; + when "11" => + data_r <= data2_in; + when others => + data_r <= data_r; + end case; +-- if load = '1' then +-- if data_sel = '0' then +-- data_r <= data1_in; +-- elsif data_sel = '1' then +-- data_r <= data2_in; +-- end if; +-- end if; + end if; + end process fifo_reg; + +end RTL; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_slotted.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_slotted.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_slotted.vhd (revision 18) @@ -0,0 +1,231 @@ +------------------------------------------------------------------------------- +-- File : fifo_shift.vhdl +-- Description : Fifo buffer for hibi interface +-- +-- Author : Erno Salminen +-- Date : 29.10.2004 +-- Modified : +-- 20.01.2005 ES Names changed +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity fifo is + + generic ( + data_width_g : integer := 32; + depth_g : integer := 5 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + data_in : in std_logic_vector (data_width_g-1 downto 0); + we_in : in std_logic; + one_p_out : out std_logic; + full_out : out std_logic; + data_out : out std_logic_vector (data_width_g-1 downto 0); + re_in : in std_logic; + empty_out : out std_logic; + one_d_out : out std_logic + ); + +end fifo; + + + +architecture slotted_fifo_reg of fifo is + + component fifo_slot + generic ( + width : integer := 0); + port ( + clk : in std_logic; + rst_n : in std_logic; + Right_Valid_In : in std_logic; + Right_Enable_In : in std_logic; + Right_data_in : in std_logic_vector ( width-1 downto 0); + + Left_data_in : in std_logic_vector ( width-1 downto 0); + Left_Valid_In : in std_logic; + Left_Enable : in std_logic; + Valid_Out : out std_logic; + data_out : out std_logic_vector ( width-1 downto 0) + ); + + end component; -- fifo_slot; + + + + type Fifo_slot_type is record + Valid : std_logic; + Data : std_logic_vector ( data_width_g-1 downto 0); + end record; + type slot_signal_array is array (depth_g downto 0) of Fifo_slot_type; + signal intermediate_signal : slot_signal_array; + signal we : std_logic_vector ( depth_g-1 downto 0); + signal re : std_logic_vector ( depth_g-1 downto 0); + + signal tie_high : std_logic; + + +begin -- slotted_fifo_reg + + + + -- Continuous assignments + -- Assigns register values to outputs + tie_high <= '1'; + assert depth_g > 1 report "Fifo depth_g must be more than one!" severity WARNING; + full_out <= intermediate_signal (depth_g-1).Valid; -- ylin paikka varattu + empty_out <= not (intermediate_signal (0).Valid ); -- alin paikka tyhja + + + + -- Yksi data=alin taynna, toiseksi alin tyhja + one_d_out <= not (intermediate_signal (1).Valid) and intermediate_signal (0).Valid; + + -- Yksi paikka=ylin tyhja, toiseksi ylin taynna + one_p_out <= not (intermediate_signal (depth_g-1).Valid) and intermediate_signal (depth_g-2).Valid; + + data_out <= intermediate_signal (0).Data; --alin data ulostuloon + -- Note! There is some old value in data output when fifo is empty. + + + + map_slots : for i in 0 to depth_g-1 generate + gen_slot_i : fifo_slot + generic map ( + width => data_width_g + ) + port map ( + clk => clk, + rst_n => rst_n, + Right_data_in => data_in, + Right_Valid_In => tie_high, + Right_Enable_In => we (i), + Left_Valid_In => intermediate_signal (i+1).Valid, + Left_data_in => intermediate_signal (i+1).Data, + Left_Enable => re (i), + Valid_Out => intermediate_signal (i).Valid, + data_out => intermediate_signal (i).Data + ); + end generate map_slots; + + intermediate_signal (depth_g).Data <= (others => '0'); --'Z'); + intermediate_signal (depth_g).Valid <= '0'; + + async_first_slot: process (intermediate_signal, we_in, re_in) + begin -- process async_first_slot + -- Ohjataan ensimmaisen we-signaalia + + if we_in = '1' and re_in = '0' then + -- Kirjoitus pelkästään + re <= (others => '0'); + + + if intermediate_signal (depth_g-1).Valid = '1' then + -- Ylin paikka taynna + we <= (others => '0'); + + + else + -- Kirjoitetaan uusi data + we <= (others => '0'); + + if intermediate_signal(0).Valid = '0' then + -- tyhjä + we(0) <= '1'; + else + + + for i in 1 to depth_g-1 loop + if intermediate_signal(i-1).Valid = '1' + and intermediate_signal(i).Valid = '0' + then + we(i) <= '1'; + end if; + end loop; -- (i + end if; + end if; + + + elsif we_in = '0' and re_in = '1' then + -- Luku pelkästään + we <= (others => '0'); + re <= (others => '1'); + + + + elsif we_in = '1' and re_in = '1' then + --Luku ja kirjoitus yhta aikaa + + if intermediate_signal (depth_g-1).Valid = '1' then + -- Ylin paikka taynna + we <= (others => '0'); + re <= (others => '1'); + + else + -- Kirjoitetaan uusi data ja shiftataaan vanhoja + we <= (others => '0'); + re <= (others => '1'); + + + if intermediate_signal(0).Valid = '0' then + -- tyhjä, ei shifatata + we(0) <= '1'; + re <= (others => '0'); + + else + + for i in 1 to depth_g-1 loop + if intermediate_signal(i-1).Valid = '1' + and intermediate_signal(i).Valid = '0' + then + -- kirjoiteteaan juuri tyhjenevään paikkaan + we (i-1) <= '1'; + re (i-1) <= '0'; + + end if; + end loop; -- (i + + end if; + end if; + + + + else + -- Ei tehda mitaan + we <= (others => '0'); --'Z'); + re <= (others => '0'); -- 'Z'); + + + end if; + + + end process async_first_slot; + + + + check_we: process (we) + variable one_bits : integer := 0; + begin -- process check_we + one_bits := 0; + + for i in 0 to depth_g-1 loop + if we(i)= '1' then + one_bits := one_bits +1; + end if; + end loop; -- i + + + -- assert one_bits < 2 report "Too many write enables" severity WARNING; + end process check_we; + + + + + + +end slotted_fifo_reg; --architecture Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_ram.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_ram.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_ram.vhd (revision 18) @@ -0,0 +1,174 @@ +------------------------------------------------------------------------------- +-- Title : fifo +-- Project : +------------------------------------------------------------------------------- +-- File : fifo_ram.vhd +-- Author : +-- Company : +-- Created : 2005-05-26 +-- Last update: 2005-05-31 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: fifo implemented with dual port RAM with asynchronous read +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2005-05-26 1.0 penttin5 Created +------------------------------------------------------------------------------- +-- +-- NOTE! Precision RTL synthesisis 2004c.45 doesn't infer the RAM with +-- asynchronous read for Stratix 1 S40F780C5. +-- Quartus II 4.2 infers RAM with asynchronic read but gives old RAM value +-- when reading and writing simultaneusly to/from same address. +-- That doesn't matter because FIFO doesn't read and write in the same +-- address at the same time. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity fifo is + + generic ( + data_width_g : integer := 0; + depth_g : integer := 0 + ); + + port ( + clk : in std_logic; + rst_n : in std_logic; + data_in : in std_logic_vector (data_width_g-1 downto 0); + we_in : in std_logic; + one_p_out : out std_logic; + full_out : out std_logic; + data_out : out std_logic_vector (data_width_g-1 downto 0); + re_in : in std_logic; + empty_out : out std_logic; + one_d_out : out std_logic + ); + +end fifo; + +architecture rtl of fifo is + + component dual_ram_async_read + generic ( + ram_width : integer := 0; + ram_depth : integer := 0); + port + ( + clock1 : in std_logic; + clock2 : in std_logic; + data : in std_logic_vector(0 to ram_width - 1); + write_address : in integer range 0 to ram_depth - 1; + read_address : in integer range 0 to ram_depth - 1; + we : in std_logic; + q : out std_logic_vector(0 to ram_width - 1) + ); + end component; -- dual_ram_async_read + + signal write_address_r : integer range 0 to depth_g - 1; + signal read_address_r : integer range 0 to depth_g - 1; + signal write_read_count_r : integer range 0 to depth_g; + signal ram_data_out_i : std_logic_vector(0 to data_width_g - 1); + signal we_ram : std_logic; + attribute dont_touch : boolean; + attribute dont_touch of gen_dual_ram: label is true; +begin -- rtl + + gen_dual_ram : dual_ram_async_read + generic map ( + ram_width => data_width_g, + ram_depth => depth_g + ) + port map ( + clock1 => clk, + clock2 => clk, + data => data_in, + write_address => write_address_r, + read_address => read_address_r, + we => we_ram, + q => ram_data_out_i + ); + + -- write to fifo when write enabled and fifo not full + we_ram <= we_in when write_read_count_r /= depth_g + else '0'; + + data_out <= ram_data_out_i; + + one_d_out <= '1' when write_read_count_r = 1 else + '0'; + one_p_out <= '1' when write_read_count_r = depth_g - 1 else + '0'; + empty_out <= '1' when write_read_count_r = 0 else + '0'; + full_out <= '1' when write_read_count_r = depth_g else + '0'; + + ----------------------------------------------------------------------------- + -- Update read and write addresses + ----------------------------------------------------------------------------- + fifo_read_and_write : process (clk, rst_n) + + begin -- process fifo_read_and_write + + if rst_n = '0' then -- asynchronous reset (active low) + write_read_count_r <= 0; + read_address_r <= 0; + write_address_r <= 0; + elsif clk'event and clk = '1' then -- rising clock edge + + -- read if re_in = '1' and fifo not empty or + -- simultaneus read and write and fifo full + if re_in = '1' and ((we_in = '0' and write_read_count_r /= 0) + or (we_in = '1' and write_read_count_r = depth_g)) then + write_read_count_r <= write_read_count_r - 1; + if read_address_r = depth_g - 1 then + read_address_r <= 0; + else + read_address_r <= read_address_r + 1; + end if; + write_address_r <= write_address_r; + + -- write if we_in = '1' and fifo not full or + -- simultaneus read and write and fifo empty + elsif we_in = '1' and ((re_in = '0' and write_read_count_r /= depth_g) + or (re_in = '1' and write_read_count_r = 0)) then + write_read_count_r <= write_read_count_r + 1; + read_address_r <= read_address_r; + if write_address_r = depth_g - 1 then + write_address_r <= 0; + else + write_address_r <= write_address_r + 1; + end if; + + -- write and read at the same time if re_in = '1' and we_in = '1' and + -- fifo not empty or full + elsif re_in = '1' and we_in = '1' and write_read_count_r /= depth_g and write_read_count_r /= 0 then + write_read_count_r <= write_read_count_r; + if read_address_r = depth_g - 1 then + read_address_r <= 0; + else + read_address_r <= read_address_r + 1; + end if; + if write_address_r = depth_g - 1 then + write_address_r <= 0; + else + write_address_r <= write_address_r + 1; + end if; + else + write_read_count_r <= write_read_count_r; + read_address_r <= read_address_r; + write_address_r <= write_address_r; + end if; + end if; + end process fifo_read_and_write; + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_mixed_clocks.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_mixed_clocks.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_mixed_clocks.vhdl (revision 18) @@ -0,0 +1,280 @@ +------------------------------------------------------------------------------- +-- File : fifo_mixed_clocks.vhdl +-- Description : Mixed Clocks fifo buffer for hibi interface +-- Author : Ari Kulmala +-- Date : 19.06.2003 +-- Modified : +-- +-- _almost_ works. Empty signal isn't behaving as expected when +-- concurrent read and write occurs. It's probably just a little +-- human err somewhere. Also has to check that full really works, even though +-- testbench says it does. +-- +-- +-- !NOTE! +-- * Output is rubbish when empty. (doesn't speed this up if otherwise). +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + + +entity mixed_clocks_fifo is + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk_In : in std_logic; + Clk_Out : in std_logic; + Rst_n : in std_logic; -- Active low + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; +-- One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic +-- One_Data_Left : out std_logic + ); + +end mixed_clocks_fifo; + +architecture behavioral of mixed_clocks_fifo is + type reg is array (depth-1 downto 0) of std_logic_vector + (width-1 downto 0); + signal Input_Buffer : reg; + signal Full_reg : std_logic; + signal Empty_reg : std_logic; +-- signal Full_register : std_logic register; +-- signal Empty_register : std_logic register; + signal Write_token : integer range 0 to depth-1; + signal Read_token : integer range 0 to depth-1; + -- if write catches read (full) + signal Write_Turned : std_logic; + signal Read_got : std_logic; + +begin -- behavioral + + -- Continious assignments + Full <= Full_reg; + Empty <= Empty_reg; + Data_Out <= Input_Buffer(Read_token); + + -- purpose: Read from the FIFO + Read : process (Clk_Out, Rst_n) + begin -- process Read + if Rst_n = '0' then -- asynchronous reset (active low) + Read_token <= 0; +-- Empty_reg <= '1'; + + elsif Clk_Out'event and Clk_Out = '1' then -- rising clock edge + if Read_Enable = '1' then + + if Empty_reg = '0' then + -- Full_reg <= '0'; + if Read_token = depth-1 then + Read_token <= 0; + else + Read_token <= Read_token+1; + end if; + +-- if Read_token = Write_token then +-- Empty_reg = '1'; +-- else +-- Empty_reg = '0'; +-- end if; + + else + Read_token <= Read_token; + end if; + end if; + + else + Read_token <= Read_token; + end if; + end process Read; + + -- purpose: Write to the FIFO + -- type : sequential + Write : process (Clk_In, Rst_n) + begin -- process Write + if Rst_n = '0' then -- asynchronous reset (active low) + Write_token <= 0; +-- Full_reg <= '0'; + + elsif Clk_In'event and Clk_In = '1' then -- rising clock edge + if Write_Enable = '1' then + + if Full_reg = '0' then + Input_Buffer(Write_token) <= Data_In; -- Write_token < depth +-- Empty_reg <= '0'; + if Write_token = depth-1 then + Write_token <= 0; + else + Write_token <= Write_token+1; + end if; + +-- if Write_token = Read_token then +-- -- Full_reg <= '1' +-- Write_Turned <= '1'; +-- else +-- -- Full_reg <= '0': +-- Write_Turned <= '0'; +-- end if; + else +-- Write_Turned <= Write_Turned; + Input_Buffer <= Input_Buffer; + Write_token <= Write_token; + end if; + end if; + + else +-- Write_Turned <= Write_Turned; + Input_Buffer <= Input_Buffer; + Write_token <= Write_token; + end if; + + end process Write; + +RESET: process (Clk_In, Clk_Out, Rst_n) + + -- ONLY READ CAN PUT EMPTY HIGH +begin -- process RESET + if Rst_n = '0' then -- asynchronous reset (active low) + Full_reg <= '0'; + Empty_reg <= '1'; + Write_Turned <= '0'; + elsif Clk_Out'event and Clk_Out = '1' then -- rising clock edge + +-- READ + + if Write_token = Read_token then + if Read_Enable = '1' and Write_Enable = '1' then + if Full_reg = '1' then + Full_reg <= '0'; + Write_Turned <= '0'; + -- Empty_reg <= '0'; +-- elsif Empty_reg = '1' then +-- Full_reg <= '0'; +-- Empty_reg <= '0'; + else + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + end if; + +-- elsif Write_Enable = '1' and Write_Turned = '0' then +-- Empty_reg <= '0'; +-- Full_reg <= '0'; + elsif Read_Enable = '1' and Write_Turned = '1' then +-- Empty_reg <= '0'; + Full_reg <= '0'; + Write_Turned <= '0'; + else + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Write_Turned <= Write_Turned; + + end if; + -- getting empty + elsif (Write_token - Read_token = 1 or Write_token - Read_token = -depth+1) + and Read_Enable = '1' then + Full_reg <= '0'; + Empty_reg <= '1'; +-- elsif (Write_token - Read_token = -1 or Write_token - Read_token = depth-1) and Write_Enable = '1' then +-- Full_reg <= '1'; +-- Empty_reg <= '0'; +-- Write_Turned <= '1'; + + else + +-- Full_reg <= '0'; + Empty_reg <= '0'; + end if; + +-- ONLY WRITE CAN PUT FULL HIGH + + elsif Clk_In'event and Clk_In = '1' then -- rising clock edge + + if Write_token = Read_token then + if Read_Enable = '1' and Write_Enable = '1' then + if Full_reg = '1' then + Full_reg <= Full_reg; +-- Empty_reg <= '0'; + -- elsif Empty_reg = '1' then + -- Full_reg <= '0'; + -- Empty_reg <= '0'; + else + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + end if; + + elsif Write_Enable = '1' and Write_Turned = '0' then + Empty_reg <= '0'; + Full_reg <= '0'; + -- elsif Read_Enable = '1' and Write_Turned = '1' then + -- Empty_reg <= '0'; + -- Full_reg <= '0'; + -- Write_Turned <= '0'; + else + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Write_Turned <= Write_Turned; + end if; + +-- elsif (Write_token - Read_token = 1 or Write_token - Read_token = -depth+1) +-- and Read_Enable = '1' then + -- Full_reg <= '0'; +-- Empty_reg <= '1'; + elsif (Write_token - Read_token = -1 or Write_token - Read_token = depth-1) and Write_Enable = '1' then + Full_reg <= '1'; +-- Empty_reg <= '0'; + Write_Turned <= '1'; + + else + + Full_reg <= '0'; + Empty_reg <= '0'; + end if; + + +-- if Write_token = Read_token then +-- if Write_Turned = '1' then +-- Full_reg <= '1'; +-- Empty_reg <= '0'; +-- else + + +-- Full_reg <= '0'; +-- Empty_reg <= '1'; +-- end if; + +-- else + +-- Full_reg <= '0'; +-- Empty_reg <= '0'; +-- end if; + + end if; +end process RESET; + + + + +-- if Rst_n = '0' then +-- Full_reg <= '0'; +-- Empty_reg <= '1'; +-- else +-- Full_reg <= Full_reg; +-- Empty_reg <= Empty_reg; +-- end if; +-- end process Reset; + +-- end process FULL_AND_EMPTY; + +end behavioral; + + + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/conf_ram.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/conf_ram.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/conf_ram.vhd (revision 18) @@ -0,0 +1,194 @@ +-- megafunction wizard: %ALTSYNCRAM% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: conf_ram.vhd +-- Megafunction Name(s): +-- altsyncram +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 5.0 Build 168 06/22/2005 SP 1.04 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2005 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY conf_ram IS + PORT + ( + address : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END conf_ram; + + +ARCHITECTURE SYN OF conf_ram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + operation_mode : STRING; + width_a : NATURAL; + widthad_a : NATURAL; + numwords_a : NATURAL; + lpm_type : STRING; + width_byteena_a : NATURAL; + outdata_reg_a : STRING; + outdata_aclr_a : STRING; + address_aclr_a : STRING; + read_during_write_mode_mixed_ports : STRING; + power_up_uninitialized : STRING; + init_file : STRING; + lpm_hint : STRING; + intended_device_family : STRING + ); + PORT ( + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + operation_mode => "ROM", + width_a => 8, + widthad_a => 4, + numwords_a => 16, + lpm_type => "altsyncram", + width_byteena_a => 1, + outdata_reg_a => "CLOCK0", + outdata_aclr_a => "NONE", + address_aclr_a => "NONE", + read_during_write_mode_mixed_ports => "DONT_CARE", + power_up_uninitialized => "FALSE", + init_file => "conf_ram.mif", + lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CONF", + intended_device_family => "Stratix" + ) + PORT MAP ( + clock0 => clock, + address_a => address, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "128" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "conf_ram.mif" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" +-- Retrieval info: PRIVATE: JTAG_ID STRING "CONF" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: INIT_FILE STRING "conf_ram.mif" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CONF" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL address[3..0] +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram_inst.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram_wave*.jpg FALSE Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_slot.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_slot.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_slot.vhd (revision 18) @@ -0,0 +1,93 @@ +------------------------------------------------------------------------------- +-- File : fifo_slot.vhdl +-- Description : One slot for fifo register +-- Basically a Register(valid bit+data) and mux +-- Author : Erno Salminen +-- Date : 29.05.2003 +-- Modified : +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity fifo_slot is + + generic ( + width : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Right_Valid_In : in std_logic; + Right_Enable_In : in std_logic; + Right_Data_In : in std_logic_vector ( width-1 downto 0); + + Left_Data_In : in std_logic_vector ( width-1 downto 0); + Left_Valid_in : in std_logic; + Left_Enable : in std_logic; + Valid_Out : out std_logic; + Data_Out : out std_logic_vector ( width-1 downto 0) + ); + +end fifo_slot; + + + +architecture rtl of fifo_slot is + + type Fifo_slot_type is record + Valid : std_logic; + Data : std_logic_vector ( width-1 downto 0); + end record; + + signal Data_reg : Fifo_slot_type; + + +begin -- rtl + + + -- CONC + Data_Out <= Data_reg.Data; + Valid_Out <= Data_reg.Valid; + + -- PROC + Sync : process (Clk, Rst_n) + begin -- process Sync + if Rst_n = '0' then -- asynchronous reset (active low) + Data_reg.Data <= (others => '0'); + Data_reg.Valid <= '0'; + + elsif Clk'event and Clk = '1' then -- rising clock edge + + if Right_Enable_In = '1' and Left_Enable = '1' then + -- ctrl = "11" = 3 + -- keep old values + Data_reg.Data <= Data_reg.Data; + Data_reg.Valid <= Data_reg.Valid; + assert false report "Simultaneous read+write" severity note; + + + elsif Right_Enable_In = '1' and Left_Enable = '0' then + -- ctrl = "10" = 2 + Data_reg.Data <= Right_Data_In; + Data_reg.Valid <= Right_Valid_In; --'1'; + + elsif Right_Enable_In = '0' and Left_Enable = '1'then + -- ctrl = "01" = 1 + Data_reg.Data <= Left_Data_In; + Data_reg.Valid <= Left_Valid_in; + + else + -- ctrl = "00" = 0 + Data_reg.Data <= Data_reg.Data; + Data_reg.Valid <= Data_reg.Valid; + end if; + + + end if; + end process Sync; + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_im.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_im.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_im.vhdl (revision 18) @@ -0,0 +1,274 @@ +------------------------------------------------------------------------------- +-- File : fifo_im.vhdl +-- Description : Fifo buffer for hibi interface +-- Author : Erno Salminen +-- Date : 29.04.2002 +-- Modified : 30.04.2002 Vesa Lahtinen Optimized for synthesis +-- +-- 02.06 ES: default assignment Fifo_Buffer <= Fifo_Buffer +-- smaller and faster implementation +-- Effect on synthesis is uncertain : +-- small fifos seem to gets smaller and faster, but big fifos +-- get bigger and slower. Strange. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity fifo is + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + +architecture in_mux of fifo is + + type data_array is array (depth-1 downto 0) of std_logic_vector (width-1 downto 0); + signal Fifo_Buffer : data_array; + + -- Registers + signal Full_reg : std_logic; + signal Empty_reg : std_logic; + signal One_Data_Left_reg : std_logic; + signal One_Place_Left_reg : std_logic; + --signal Data_Amount : std_logic_vector (depth-1 downto 0); + signal Data_Amount : integer range 0 to depth-1; + + +begin -- in_mux + + -- Continuous assignments + -- Assigns register values to outputs + Full <= Full_reg; + Empty <= Empty_reg; + One_Data_Left <= One_Data_Left_reg; + One_Place_Left <= One_Place_Left_reg; + Data_Out <= Fifo_Buffer (0); + -- Note! There is some old value in data output when fifo is empty. + + +Main : process (Clk, Rst_n) +begin -- process Main + if Rst_n = '0' then -- asynchronous reset (active low) + + -- Reset all registers + -- Fifo is empty at first + Full_reg <= '0'; + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + Data_Amount <= 0; + + if depth =1 then -- 30.07 + One_Place_Left_reg <= '1'; + else + One_Place_Left_reg <= '0'; + end if; + + for i in 0 to depth-1 loop + Fifo_Buffer (i) <= (others => '0'); + end loop; -- i + + elsif Clk'event and Clk = '1' then -- rising clock edge + + + -- 1) Write data to fifo + if Write_Enable = '1' and Read_Enable = '0' then + + if Full_reg = '0' then + Empty_reg <= '0'; + Data_Amount <= Data_Amount +1; + + Fifo_Buffer <= Fifo_Buffer; --02.06 + Fifo_Buffer (Data_Amount) <= Data_In; + + -- Check if the fifo is getting full + if Data_Amount + 2 = depth then + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + elsif Data_Amount +1 = depth then + Full_reg <= '1'; + One_Place_Left_reg <= '0'; + else + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + end if; + + + -- If fifo was empty, it has now one data + if Empty_reg = '1' then + One_Data_Left_reg <= '1'; + else + One_Data_Left_reg <= '0'; + end if; + + else + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + + -- 2) Read data from fifo + elsif Write_Enable = '0' and Read_Enable = '1' then + + if Empty_reg = '0' then + + -- Shiftaus + Fifo_Buffer <= Fifo_Buffer; --02.06 + for i in 0 to depth-2 loop + Fifo_Buffer (i) <= Fifo_Buffer (i+1); + end loop; -- i + + Full_reg <= '0'; + Data_Amount <= Data_Amount -1; + + -- Debug + -- Fifo_Buffer (out_ptr) <= (others => '1'); + + + + + -- Check if the fifo is getting empty + if Data_Amount = 2 then + Empty_reg <= '0'; + One_data_Left_reg <= '1'; + elsif Data_Amount = 1 then + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + else + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + end if; + + -- If fifo was full, it is no more + if Full_reg = '1' then + One_Place_Left_reg <= '1'; + else + One_Place_Left_reg <= '0'; + end if; + + else + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + + -- 3) Write and read at the same time + elsif Write_Enable = '1' and Read_Enable = '1' then + + + if Full_reg = '0' and Empty_reg = '0' then + Full_reg <= '0'; + Empty_reg <= '0'; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + + Fifo_Buffer <= Fifo_Buffer; --02.06 + -- Shiftaus + for i in 0 to depth-2 loop + Fifo_Buffer (i) <= Fifo_Buffer (i+1); + end loop; -- i + Fifo_Buffer (Data_Amount-1) <= Data_In; --vai amount-1 ?? koska pitaa + --shiftata samalla + + -- Fifo_Buffer (out_ptr) <= (others => '1'); --debug + + + elsif Full_reg = '1' and Empty_reg = '0' then + -- Fifo is full, only reading is possible + + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + --Fifo_Buffer (out_ptr) <= (others => '1'); -- Debug + Data_Amount <= Data_Amount -1; + + Fifo_Buffer <= Fifo_Buffer; --02.06 + -- Shiftaus + for i in 0 to depth-2 loop + Fifo_Buffer (i) <= Fifo_Buffer (i+1); + end loop; -- i + + -- Check if the fifo is getting empty + if Data_Amount = 2 then + Empty_reg <= '0'; + One_data_Left_reg <= '1'; + elsif Data_Amount = 1 then + Empty_reg <= '1'; + One_Data_Left_reg <= '0'; + else + Empty_reg <= '0'; + One_Data_Left_reg <= '0'; + end if; + + + elsif Full_reg = '0' and Empty_reg = '1' then + -- Fifo is empty, only writing is possible + Empty_reg <= '0'; + One_Data_Left_reg <= '1'; + Fifo_Buffer <= Fifo_Buffer; --02.06 + Fifo_Buffer (Data_Amount) <= Data_In; --Data_Amount =0 + Data_Amount <= Data_Amount +1; + + -- Check if the fifo is getting full + if Data_Amount + 2 = depth then + Full_reg <= '0'; + One_Place_Left_reg <= '1'; + elsif Data_Amount +1 = depth then + Full_reg <= '1'; + One_Place_Left_reg <= '0'; + else + Full_reg <= '0'; + One_Place_Left_reg <= '0'; + end if; + + + else + -- Fifo is full and empty at the same time => impossible + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; --Full_reg & Empty_reg + + + -- 4) Do nothing, fifo remains idle + else + + Full_reg <= Full_reg; + Empty_reg <= Empty_reg; + Fifo_Buffer <= Fifo_Buffer; + Data_Amount <= Data_Amount; + One_Data_Left_reg <= One_Data_Left_reg; + One_Place_Left_reg <= One_Place_Left_reg; + end if; + + end if; +end process Main; + +end in_mux; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/double_fifo_muxed_read.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/double_fifo_muxed_read.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/double_fifo_muxed_read.vhdl (revision 18) @@ -0,0 +1,301 @@ +------------------------------------------------------------------------------- +-- File : double_fifo_muxed_read.vhdl +-- Description : Double_Fifo_Muxed_Read buffer for hibi v.2 interface +-- Includes two fifos and a special multiplexer +-- so that the reader sees only one fifo. Multiplexer +-- selects addr+data first from fifo 0 (i.e. it has a higher priority) +-- Author : Erno Salminen +-- Date : 07.02.2003 +-- Modified : +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + + +entity double_fifo_muxed_read is + + generic ( + Data_Width : integer := 0; + Depth_0 : integer := 0; + Depth_1 : integer := 0; + Comm_Width : integer := 0 + ); + port ( + Clk : in std_logic; + Rst_n : in std_logic; + + Data_In_0 : in std_logic_vector ( Data_Width-1 downto 0); + Comm_In_0 : in std_logic_vector ( Comm_Width-1 downto 0); + Addr_Valid_In_0 : in std_logic; + Write_Enable_In_0 : in std_logic; + One_Place_Left_Out_0 : out std_logic; + Full_Out_0 : out std_logic; + + Data_In_1 : in std_logic_vector ( Data_Width-1 downto 0); + Comm_In_1 : in std_logic_vector ( Comm_Width-1 downto 0); + Addr_Valid_In_1 : in std_logic; + Write_Enable_In_1 : in std_logic; + One_Place_Left_Out_1 : out std_logic; + Full_Out_1 : out std_logic; + + Read_Enable_In : in std_logic; + Data_Out : out std_logic_vector ( Data_Width-1 downto 0); + Comm_Out : out std_logic_vector ( Comm_Width-1 downto 0); + Addr_Valid_Out : out std_logic; + Empty_Out : out std_logic; + One_Data_Left_Out : out std_logic + ); +end double_fifo_muxed_read; + + + +architecture structural of double_fifo_muxed_read is + + + + + component fifo + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + + Read_Enable : in std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Empty : out std_logic; + One_Data_Left : out std_logic + ); + end component; --fifo; + + + component fifo_mux_read + generic ( + Data_Width : integer := 0; + Comm_Width : integer := 0 + ); + port ( + Clk : in std_logic; + Rst_n : in std_logic; + + Data_0_In : in std_logic_vector (Data_Width-1 downto 0); + Comm_0_In : in std_logic_vector (Comm_Width-1 downto 0); + Addr_Valid_0_In : in std_logic; + One_Data_Left_0_In : in std_logic; + Empty_0_In : in std_logic; + RE_0_Out : out std_logic; + + Data_1_In : in std_logic_vector (Data_Width-1 downto 0); + Comm_1_In : in std_logic_vector (Comm_Width-1 downto 0); + Addr_Valid_1_In : in std_logic; + One_Data_Left_1_In : in std_logic; + Empty_1_In : in std_logic; + RE_1_Out : out std_logic; + + Read_Enable_In : in std_logic; + Data_Out : out std_logic_vector (Data_Width-1 downto 0); + Comm_Out : out std_logic_vector (Comm_Width-1 downto 0); + Addr_Valid_Out : out std_logic; + One_Data_Left_Out : out std_logic; + Empty_Out : out std_logic + ); + end component; --fifo_mux_read; + + + signal Data_AV_Comm_In_0 : std_logic_vector ( 1 + Comm_Width + Data_Width-1 downto 0); + signal Data_AV_Comm_In_1 : std_logic_vector ( 1 + Comm_Width + Data_Width-1 downto 0); + + signal Data_AV_Comm_0_Mux : std_logic_vector ( 1 + Comm_Width + Data_Width-1 downto 0); + signal Data_0_Mux : std_logic_vector ( Data_Width-1 downto 0); + signal Comm_0_Mux : std_logic_vector ( Comm_Width-1 downto 0); + signal AV_0_Mux : std_logic; + + signal Data_AV_Comm_1_Mux : std_logic_vector ( 1 + Comm_Width + Data_Width-1 downto 0); + signal Data_1_Mux : std_logic_vector ( Data_Width-1 downto 0); + signal Comm_1_Mux : std_logic_vector ( Comm_Width-1 downto 0); + signal AV_1_Mux : std_logic; + + signal Read_Enable_Mux_0 : std_logic; + signal Empty_0_Mux : std_logic; + signal One_Data_Left_0_Mux : std_logic; + + signal Read_Enable_Mux_1 : std_logic; + signal Empty_1_Mux : std_logic; + signal One_Data_Left_1_Mux : std_logic; + + + signal Tie_High : std_logic; + signal Tie_Low : std_logic; + + +begin -- structural + -- Check generics + assert (Depth_0 + Depth_1 > 0) report "Both fifo depths zero!" severity warning; + + -- Concurrent assignments + Tie_High <= '1'; + Tie_Low <= '0'; + -- Combine fifo inputs + Data_AV_Comm_In_0 <= Addr_Valid_In_0 & Comm_In_0 & Data_In_0; + Data_AV_Comm_In_1 <= Addr_Valid_In_1 & Comm_In_1 & Data_In_1; + + + -- Split fifooutput + AV_0_Mux <= Data_AV_Comm_0_Mux ( 1+Comm_Width + Data_Width-1); + Comm_0_Mux <= Data_AV_Comm_0_Mux ( Comm_Width + Data_Width-1 downto Data_Width); + Data_0_Mux <= Data_AV_Comm_0_Mux ( Data_Width-1 downto 0); + AV_1_Mux <= Data_AV_Comm_1_Mux ( 1+Comm_Width + Data_Width-1); + Comm_1_Mux <= Data_AV_Comm_1_Mux ( Comm_Width + Data_Width-1 downto Data_Width); + Data_1_Mux <= Data_AV_Comm_1_Mux ( Data_Width-1 downto 0); + + + Map_Fifo_0 : if Depth_0 > 0 generate + Fifo_0 : fifo + generic map( + width => 1 + Comm_Width + Data_Width, + depth => Depth_0 + ) + port map( + Clk => Clk, + Rst_n => Rst_n, + + Data_In => Data_AV_Comm_In_0, + Write_Enable => Write_Enable_In_0, + One_Place_Left => One_Place_Left_Out_0, + Full => Full_Out_0, + + Read_Enable => Read_Enable_Mux_0, + Data_Out => Data_AV_Comm_0_Mux, + Empty => Empty_0_Mux, + One_Data_Left => One_Data_Left_0_Mux + ); + end generate Map_Fifo_0; + + + Not_Map_Fifo_0 : if Depth_0 = 0 generate + -- Fifo #0 does not exist! + Data_AV_Comm_0_Mux <= (others => '0'); + Empty_0_Mux <= Tie_High; + One_Data_Left_0_Mux <= Tie_Low; + Full_Out_0 <= Tie_High; + One_Place_Left_Out_0 <= Tie_Low; + + -- Connect the other fifo (#1)straight to the outputs ( => FSM) + Data_Out <= Data_1_Mux; + Comm_Out <= Comm_1_Mux; + Addr_Valid_Out <= AV_1_Mux; + One_Data_Left_Out <= One_Data_Left_1_Mux; + Empty_Out <= Empty_1_Mux; + + Read_Enable_Mux_1 <= Read_Enable_In; --15.05 + + end generate Not_Map_Fifo_0; + + + + + Map_Fifo_1 : if Depth_1 > 0 generate + Fifo_1 : fifo + generic map( + width => 1 + Comm_Width + Data_Width, + depth => Depth_1 + ) + port map( + Clk => Clk, + Rst_n => Rst_n, + + Data_In => Data_AV_Comm_In_1, + Write_Enable => Write_Enable_In_1, + One_Place_Left => One_Place_Left_Out_1, + Full => Full_Out_1, + + Read_Enable => Read_Enable_Mux_1, + Data_Out => Data_AV_Comm_1_Mux, + Empty => Empty_1_Mux, + One_Data_Left => One_Data_Left_1_Mux + ); + end generate Map_Fifo_1; + + + Not_Map_Fifo_1 : if Depth_1 = 0 generate + -- Fifo #1 does not exist! + + -- Signals fifo#1=> IP + -- Full_Out_1 <= Tie_High; + -- One_Place_Left_Out_1 <= Tie_Low; + + -- Signals fifo#1=> FSM + Data_AV_Comm_1_Mux <= (others => '0'); + Empty_1_Mux <= Tie_High; + One_Data_Left_1_Mux <= Tie_Low; + + -- Connect the other fifo (#0)straight to the outputs ( => FSM) + Data_Out <= Data_0_Mux; + Comm_Out <= Comm_0_Mux; + Addr_Valid_Out <= AV_0_Mux; + One_Data_Left_Out <= One_Data_Left_0_Mux; + Empty_Out <= Empty_0_Mux; + + Read_Enable_Mux_0 <= Read_Enable_In; --15.05 + + end generate Not_Map_Fifo_1; + + + Map_Mux : if Depth_0 > 0 and Depth_1 > 0 generate + -- Only one fifo used + -- Multiplexer is needed only if two fifos are used + MUX_01: fifo_mux_read + generic map( + Data_Width => Data_Width, + Comm_Width => Comm_Width + ) + port map( + Clk => Clk, + Rst_n => Rst_n, + + Data_0_In => Data_0_Mux, + Comm_0_In => Comm_0_Mux, + Addr_Valid_0_In => AV_0_Mux, + One_Data_Left_0_In => One_Data_Left_0_Mux, + Empty_0_In => Empty_0_Mux, + RE_0_Out => Read_Enable_Mux_0, + + Data_1_In => Data_1_Mux, + Comm_1_In => Comm_1_Mux, + Addr_Valid_1_In => AV_1_Mux, + One_Data_Left_1_In => One_Data_Left_1_Mux, + Empty_1_In => Empty_1_Mux, + RE_1_Out => Read_Enable_Mux_1, + + Read_Enable_In => Read_Enable_In, + Data_Out => Data_Out, + Comm_Out => Comm_Out, + Addr_Valid_Out => Addr_Valid_Out, + One_Data_Left_Out => One_Data_Left_Out, + Empty_Out => Empty_Out + ); + end generate Map_Mux; + + + + + + + + + + +end structural; + + + Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_ram_dynamic.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_ram_dynamic.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_ram_dynamic.vhd (revision 18) @@ -0,0 +1,284 @@ +------------------------------------------------------------------------------- +-- Title : fifo +-- Project : +------------------------------------------------------------------------------- +-- File : fifo_ram_dynamic.vhd +-- Author : +-- Company : +-- Created : 2005-05-26 +-- Last update: 2006-03-02 +-- Platform : +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: Fifo w/dynamic depth implemented with dual port RAM +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2005-05-26 1.0 penttin5 Created +------------------------------------------------------------------------------- +-- +-- NOTE! generic depth_g is the maximum depth of fifo +-- NOTE! Precision RTL synthesisis 2004c.45 doesn't infer the RAM with +-- asynchronous read for Stratix 1 S40F780C5. +-- Quartus II 4.2 infers RAM with asynchronic read but gives old RAM +-- value when reading and writing simultaneusly to/from same address. +-- That doesn't matter because FIFO doesn't read and write in the same +-- address at the same time. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity fifo is + + generic ( + data_width_g : integer := 32; + depth_g : integer := 10 -- this is the maximum depth of fifo! + ); + + port ( + clk : in std_logic; + rst_n : in std_logic; + data_in : in std_logic_vector (data_width_g-1 downto 0); + we_in : in std_logic; + one_p_out : out std_logic; + full_out : out std_logic; + data_out : out std_logic_vector (data_width_g-1 downto 0); + re_in : in std_logic; + empty_out : out std_logic; + one_d_out : out std_logic + ); + +end fifo; + +architecture rtl of fifo is + + -- this is the configuration RAM which holds the + -- dynamic depth value at address 0 + component conf_ram + port ( + address : in std_logic_vector(3 downto 0); + clock : in std_logic; + q : out std_logic_vector(7 downto 0) + ); + end component; + + component dual_ram_async_read + generic ( + ram_width : integer := 0; + ram_depth : integer := 0); + port + ( + clock1 : in std_logic; + clock2 : in std_logic; + data : in std_logic_vector(0 to ram_width - 1); + write_address : in integer range 0 to ram_depth - 1; + read_address : in integer range 0 to ram_depth - 1; + we : in std_logic; + q : out std_logic_vector(0 to ram_width - 1) + ); + end component; -- dual_ram_async_read + + signal write_address_r : integer range 0 to depth_g - 1; + signal read_address_r : integer range 0 to depth_g - 1; + signal write_read_count_r : integer range 0 to depth_g; + signal ram_data_out_i : std_logic_vector(0 to data_width_g - 1); + signal we_ram : std_logic; + + signal conf_ram_addr : std_logic_vector(3 downto 0); + signal depth_from_conf_ram : std_logic_vector(7 downto 0); + signal dynamic_depth_r : integer range 0 to depth_g; + signal full_out_r : std_logic; + +begin -- rtl + + conf_ram_inst : conf_ram + port map ( + address => (others => '0'), + clock => clk, + q => depth_from_conf_ram + ); + + gen_dual_ram : dual_ram_async_read + generic map ( + ram_width => data_width_g, + ram_depth => depth_g + ) + port map ( + clock1 => clk, + clock2 => clk, + data => data_in, + write_address => write_address_r, + read_address => read_address_r, + we => we_ram, + q => ram_data_out_i + ); + + full_out <= full_out_r; + -- write to fifo when write enabled and fifo not full + we_ram <= we_in when full_out_r = '0'--write_read_count_r < dynamic_depth_r + else '0'; + + data_out <= ram_data_out_i; + +-- one_d_out <= '1' when write_read_count_r = 1 else +-- '0'; +-- one_p_out <= '1' when write_read_count_r = dynamic_depth_r - 1 else +-- '0'; +-- empty_out <= '1' when write_read_count_r = 0 else +-- '0'; +-- full_out <= '1' when write_read_count_r >= dynamic_depth_r else +-- '0'; + + update_flags: process (clk, rst_n) + begin -- process update_flags + if rst_n = '0' then -- asynchronous reset (active low) + one_d_out <= '0'; + one_p_out <= '0'; + empty_out <= '1'; + full_out_r <= '0'; + elsif clk'event and clk = '1' then -- rising clock edge + + if (we_in = '0' and re_in = '0' and write_read_count_r = 1) or + (we_in = '1' and re_in = '1' and write_read_count_r = 1) or + (we_in = '1' and re_in = '0' and write_read_count_r = 0) or + (we_in = '0' and re_in = '1' and write_read_count_r = 2) then + one_d_out <= '1'; + else + one_d_out <= '0'; + end if; + + if (we_in = '0' and re_in = '0' and write_read_count_r = dynamic_depth_r - 1) or + (we_in = '1' and re_in = '1' and write_read_count_r = dynamic_depth_r - 1) or + (we_in = '1' and re_in = '0' and write_read_count_r = dynamic_depth_r - 2) or + (we_in = '0' and re_in = '1' and write_read_count_r = dynamic_depth_r) then + + one_p_out <= '1'; + else + one_p_out <= '0'; + end if; + + if (we_in = '0' and re_in = '0' and write_read_count_r = 0) or + (we_in = '0' and re_in = '1' and write_read_count_r = 0) or + (we_in = '0' and re_in = '1' and write_read_count_r = 1) then + + empty_out <= '1'; + else + empty_out <= '0'; + end if; + + if (we_in = '0' and re_in = '0' and write_read_count_r = dynamic_depth_r) or + (we_in = '1' and re_in = '0' and write_read_count_r = dynamic_depth_r) or + (we_in = '1' and re_in = '0' and write_read_count_r = dynamic_depth_r - 1) or + (write_read_count_r > dynamic_depth_r) then + + full_out_r <= '1'; + else + full_out_r <= '0'; + end if; + + end if; + end process update_flags; + + ----------------------------------------------------------------------------- + -- Update dynamic depth + ----------------------------------------------------------------------------- + update_dynamic_depth_r : process (clk, rst_n) + begin -- process update_dynamic_depth_r + if rst_n = '0' then -- asynchronous reset (active low) + dynamic_depth_r <= depth_g; + conf_ram_addr <= (others => '0'); + + elsif clk'event and clk = '1' then -- rising clock edge + conf_ram_addr <= (others => '0'); + + if conv_integer(depth_from_conf_ram) > depth_g + or depth_from_conf_ram = + + -- dynamic depth is bigger than maximum depth or + -- it's not defined(zero) => Use the maximum depth + conv_std_logic_vector(0, depth_from_conf_ram'length) then + dynamic_depth_r <= depth_g; + + else + + -- update dynamic depth + dynamic_depth_r <= + conv_integer(depth_from_conf_ram); + end if; + + end if; + end process update_dynamic_depth_r; + + ----------------------------------------------------------------------------- + -- Update read and write addresses + ----------------------------------------------------------------------------- + fifo_read_and_write : process (clk, rst_n) + + begin -- process fifo_read_and_write + + if rst_n = '0' then -- asynchronous reset (active low) + write_read_count_r <= 0; + read_address_r <= 0; + write_address_r <= 0; + + elsif clk'event and clk = '1' then -- rising clock edge + + -- read if re_in = '1' and fifo not empty or + -- simultaneus read and write and fifo full + if re_in = '1' and ((we_in = '0' and write_read_count_r /= 0) + or (we_in = '1' + and write_read_count_r = dynamic_depth_r)) then + + write_read_count_r <= write_read_count_r - 1; + + if read_address_r = dynamic_depth_r - 1 then + read_address_r <= 0; + else + read_address_r <= read_address_r + 1; + end if; + write_address_r <= write_address_r; + + -- write if we_in = '1' and fifo not full or + -- simultaneus read and write and fifo empty + elsif we_in = '1' and ((re_in = '0' and + write_read_count_r /= dynamic_depth_r) + or (re_in = '1' and write_read_count_r = 0)) then + write_read_count_r <= write_read_count_r + 1; + read_address_r <= read_address_r; + if write_address_r = dynamic_depth_r - 1 then + write_address_r <= 0; + else + write_address_r <= write_address_r + 1; + end if; + + -- write and read at the same time if re_in = '1' and we_in = '1' and + -- fifo not empty or full + elsif re_in = '1' and we_in = '1' + and write_read_count_r /= dynamic_depth_r + and write_read_count_r /= 0 then + write_read_count_r <= write_read_count_r; + if read_address_r = dynamic_depth_r - 1 then + read_address_r <= 0; + else + read_address_r <= read_address_r + 1; + end if; + if write_address_r = dynamic_depth_r - 1 then + write_address_r <= 0; + else + write_address_r <= write_address_r + 1; + end if; + else + write_read_count_r <= write_read_count_r; + read_address_r <= read_address_r; + write_address_r <= write_address_r; + end if; + end if; + end process fifo_read_and_write; + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/shift_slot.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/shift_slot.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/shift_slot.vhdl (revision 18) @@ -0,0 +1,73 @@ +------------------------------------------------------------------------------- +-- File : shift_slot.vhdl +-- Description : One slot for shift register +-- Basically a Register(valid bit+data) and mux +-- Author : Erno Salminen +-- Date : 29.05.2003 +-- Modified : +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity shift_slot is + + generic ( + width : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Valid_In : in std_logic; + Data_In : in std_logic_vector ( width-1 downto 0); + Shift_Enable : in std_logic; + Valid_Out : out std_logic; + Data_Out : out std_logic_vector ( width-1 downto 0) + ); + +end shift_slot; + + + +architecture rtl of shift_slot is + + type Shift_slot_type is record + Valid : std_logic; + Data : std_logic_vector ( width-1 downto 0); + end record; + + signal Data_reg : Shift_slot_type; + + +begin -- rtl + + + -- CONC + Data_Out <= Data_reg.Data; + Valid_Out <= Data_reg.Valid; + + -- PROC + Sync : process (Clk, Rst_n) + begin -- process Sync + if Rst_n = '0' then -- asynchronous reset (active low) + Data_reg.Data <= (others => '0'); + Data_reg.Valid <= '0'; + + elsif Clk'event and Clk = '1' then -- rising clock edge + + if Shift_Enable = '1' then + Data_reg.Data <= Data_In; + Data_reg.Valid <= Valid_In; + else + Data_reg.Data <= Data_reg.Data; + Data_reg.Valid <= Data_reg.Valid; + end if; + + + end if; + end process Sync; + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_shift_slotted.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_shift_slotted.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_shift_slotted.vhdl (revision 18) @@ -0,0 +1,174 @@ +------------------------------------------------------------------------------- +-- File : fifo_shift.vhdl +-- Description : Fifo buffer for hibi interface +-- +-- Author : Erno Salminen +-- Date : 29.05.2003 +-- Modified : +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity fifo is + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + + + +architecture slotted_shift_reg of fifo is + + component shift_slot + generic ( + width : integer := 0); + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Valid_In : in std_logic; + Data_In : in std_logic_vector ( width-1 downto 0); + Shift_Enable : in std_logic; + Valid_Out : out std_logic; + Data_Out : out std_logic_vector ( width-1 downto 0) + ); + + end component; -- shift_slot; + + + + type Fifo_slot_type is record + Valid : std_logic; + Data : std_logic_vector ( width-1 downto 0); + end record; + type slot_signal_array is array (depth downto 0) of Fifo_slot_type; + signal intermediate_signal : slot_signal_array; + signal Top_Slot_Write_Enable : std_logic; + +begin -- slotted_shift_reg + + + + -- Continuous assignments + -- Assigns register values to outputs + assert depth > 1 report "Fifo depth must be more than one!" severity WARNING; + Full <= intermediate_signal (depth-1).Valid; -- ylin paikka varattu + Empty <= not (intermediate_signal (0).Valid ); -- alin paikka tyhja + + -- Yksi data=alin taynna, toiseksi alin tyhja + One_Data_Left <= not (intermediate_signal (1).Valid) and intermediate_signal (0).Valid; + + -- Yksi paikka=ylin tyhja, toiseksi ylin taynna + One_Place_Left <= not (intermediate_signal (depth-1).Valid) and intermediate_signal (depth-2).Valid; + + Data_Out <= intermediate_signal (0).Data; --alin data ulostuloon + -- Note! There is some old value in data output when fifo is empty. + + + + top_slot : shift_slot + generic map ( + width => width) + port map ( + Clk => Clk, + Rst_n => Rst_n, + Valid_In => intermediate_signal (depth).Valid, + Data_In => intermediate_signal (depth).Data, + Shift_Enable => Top_Slot_Write_Enable, + Valid_Out => intermediate_signal(depth-1).Valid, + Data_Out => intermediate_signal(depth-1).Data + ); + + map_slots : for i in 0 to depth-2 generate + gen_slot_i : shift_slot + generic map ( + width => width) + port map ( + Clk => Clk, + Rst_n => Rst_n, + Valid_In => intermediate_signal (i+1).Valid, + Data_In => intermediate_signal (i+1).Data, + Shift_Enable => Read_Enable, + Valid_Out => intermediate_signal (i).Valid, + Data_Out => intermediate_signal (i).Data + ); + end generate map_slots; + + + async_first_slot: process (intermediate_signal, Data_In, Write_Enable, Read_Enable) + begin -- process async_first_slot + -- Ohjataan ensimmaisen (=kirjoitus-) paikan sisaanmenoja + + if Write_Enable = '1' and Read_Enable = '0' then + -- Kirjoitus + + if intermediate_signal (depth-1).Valid = '1' then + -- Ylin paikka taynna + Top_Slot_Write_Enable <= '0'; + intermediate_signal (depth).Data <= (others => '0'); --'Z'); + intermediate_signal (depth).Valid <= '0'; + + else + -- Kirjoitetaan uusi data ylimpaan + Top_Slot_Write_Enable <= '1'; + intermediate_signal (depth).Data <= Data_In; + intermediate_signal (depth).Valid <= '1'; + end if; + + + elsif Write_Enable = '0' and Read_Enable = '1' then + -- Luku + --Nollataan ylin paikka + Top_Slot_Write_Enable <= '1'; + intermediate_signal (depth).Data <= (others => '0'); -- 'Z'); + intermediate_signal (depth).Valid <= '0'; + + + elsif Write_Enable = '1' and Read_Enable = '1' then + --Luku ja kirjoitus yhta aikaa + if intermediate_signal (depth-1).Valid = '1' then + -- Ylin paikka taynna + Top_Slot_Write_Enable <= '0'; + intermediate_signal (depth).Data <= (others => '0'); --'Z'); + intermediate_signal (depth).Valid <= '0'; + + else + -- Kirjoitetaan uusi data ylimpaan + Top_Slot_Write_Enable <= '1'; + intermediate_signal (depth).Data <= Data_In; + intermediate_signal (depth).Valid <= '1'; + end if; + + + + else + -- Ei tehda mitaan + -- Ylin paikka taynna + Top_Slot_Write_Enable <= '0'; + intermediate_signal (depth).Data <= (others => '0'); --'Z'); + intermediate_signal (depth).Valid <= '0'; + + + end if; + + + end process async_first_slot; + +end slotted_shift_reg; --architecture Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_shift.vhdl =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_shift.vhdl (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Vhdl/fifo_shift.vhdl (revision 18) @@ -0,0 +1,154 @@ +------------------------------------------------------------------------------- +-- File : fifo_shift.vhdl +-- Description : Fifo buffer for hibi interface +-- +-- Author : Erno Salminen +-- Date : 29.05.2003 +-- Modified : +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity fifo is + + generic ( + width : integer := 0; + depth : integer := 0); + + port ( + Clk : in std_logic; + Rst_n : in std_logic; + Data_In : in std_logic_vector (width-1 downto 0); + Write_Enable : in std_logic; + One_Place_Left : out std_logic; + Full : out std_logic; + Data_Out : out std_logic_vector (width-1 downto 0); + Read_Enable : in std_logic; + Empty : out std_logic; + One_Data_Left : out std_logic + ); + +end fifo; + + + +architecture shift_reg of fifo is + + type Fifo_slot_type is record + Valid : std_logic; + Data : std_logic_vector ( width-1 downto 0); + end record; + + type data_array is array (depth-1 downto 0) of Fifo_slot_type; + signal Fifo_Buffer : data_array; + + -- Registers + --signal Data_Amount : integer range 0 to depth-1; + + signal WE_RE : std_logic_vector ( 1 downto 0); + +begin -- shift_reg + + + + -- Continuous assignments + -- Assigns register values to outputs + WE_RE <= Write_Enable & Read_Enable; -- yhdistetaan case-lausetta varten + + assert depth > 1 report "Fifo depth must be more than one!" severity WARNING; + Full <= Fifo_Buffer (depth-1).Valid; -- ylin paikka varattu + Empty <= not (Fifo_Buffer (0).Valid); -- alin paikka tyhja + + -- Yksi data=alin taynna, toiseksi alin tyhja + One_Data_Left <= not (Fifo_Buffer (1).Valid) and Fifo_Buffer (0).Valid; + + -- Yksi paikka=ylin tyhja, toiseksi ylin taynna + One_Place_Left <= not (Fifo_Buffer (depth-1).Valid) and Fifo_Buffer (depth-2).Valid; + + Data_Out <= Fifo_Buffer (0).Data; --alin data ulostuloon + -- Note! There is some old value in data output when fifo is empty. + + + + + + + Sync: process (Clk, Rst_n) + begin -- process Sync + if Rst_n = '0' then -- asynchronous reset (active low) + + -- Reset all registers + --Data_Amount <= 0; + for i in 0 to depth-1 loop + Fifo_Buffer (i).Data <= (others => '0'); --'Z'); + Fifo_Buffer (i).Valid <= '0'; + end loop; -- i + + + elsif Clk'event and Clk = '1' then -- rising clock edge + + -- Vaihdetaan if-elsif-else case-lauseeksi + case WE_RE is + + when "10" => + -- Kirjoitus + if Fifo_Buffer (depth-1).Valid = '1' then + -- Fifo taynna, kirjoitus ei onnistu + Fifo_Buffer <= Fifo_Buffer; + assert false report "Cannot write to full fifo" severity note; + + else + -- Fifossa tilaa + --30.05 + -- !!! Huom jos tassa ei sijoita muihin paikkoihin vanhoja + -- arvoja, max. viive kasvaa!! + -- Esim. 50x1b (ilman sijoitusta) 1.5ns + -- 50x1b (sijoituksen kanssa) 0.88ns + -- be careful out there! + Fifo_Buffer <= Fifo_Buffer; --30.05 + Fifo_Buffer (depth-1).Valid <= '1'; --paikka kaytossa + Fifo_Buffer (depth-1).Data <= Data_In; + end if; + + + when "01" => + -- Luku + -- Shiftaus (isoista indekseista kohti indeksia nolla) + for i in 0 to depth-2 loop + Fifo_Buffer (i) <= Fifo_Buffer (i+1); + end loop; -- i + --ylin paikka tyhjenee + Fifo_Buffer (depth-1).Valid <= '0'; + Fifo_Buffer (depth-1).Data <= (others => '0'); --'Z'); + + + when "11" => + -- Seka kirjoitus etta luku + + if Fifo_Buffer (depth-1).Valid = '1' then + -- Fifo taynna, kirjoitus ei onnistu mutta luku onnistuu + -- Ylin (sisaantulo)paikka tyhjenee + Fifo_Buffer (depth-1).Data <= (others => '0'); --'Z'; + Fifo_Buffer (depth-1).Valid <= '0'; + else + -- Seka luku etta kirjoitus onnistuvat + Fifo_Buffer (depth-1).Valid <= '1'; --paikka kaytossa + Fifo_Buffer (depth-1).Data <= Data_In; + end if; + + -- Shiftataan joka tapauksessa (isoista indekseista kohti indeksia nolla) + for i in 0 to depth-2 loop + Fifo_Buffer (i) <= Fifo_Buffer (i+1); + end loop; -- i + + when others => + -- Ei tehda mitaan + Fifo_Buffer <= Fifo_Buffer; + end case; + end if; --rst/clk + end process Sync; + +end shift_reg; Index: trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Makefile =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Makefile (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synch_fifos/Makefile (revision 18) @@ -0,0 +1,118 @@ +# Generated by vmake version 2.0 + +# Define path to each library +LIB_IEEE = /opt/modeltech-5.7a/hppa64/../ieee +LIB_WORK = /tmp/kulmala3/Fifo_comparison/codelib +LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB = /tmp/kulmala3/Fifo_comparison/codelib + +# Define path to each design unit +IEEE-std_logic_unsigned = $(LIB_IEEE)/std_logic_unsigned/_primary.dat +IEEE-std_logic_1164 = $(LIB_IEEE)/std_logic_1164/_primary.dat +IEEE-std_logic_arith = $(LIB_IEEE)/std_logic_arith/_primary.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo_mixed_clocks2-behavioral = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/tb_fifo_mixed_clocks2/behavioral.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo_mixed_clocks2 = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/tb_fifo_mixed_clocks2/_primary.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo2-behavioral = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/tb_fifo2/behavioral.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo2 = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/tb_fifo2/_primary.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo1-behavioral = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/tb_fifo1/behavioral.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo1 = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/tb_fifo1/_primary.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-shift_slot-rtl = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/shift_slot/rtl.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-shift_slot = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/shift_slot/_primary.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-mixed_clocks_fifo-behavioral = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/mixed_clocks_fifo/behavioral.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-mixed_clocks_fifo = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/mixed_clocks_fifo/_primary.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-inout_mux = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/fifo/inout_mux.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-in_mux = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/fifo/in_mux.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-shift_reg = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/fifo/shift_reg.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-slotted_shift_reg = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/fifo/slotted_shift_reg.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-behavioral = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/fifo/behavioral.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/fifo/_primary.dat +/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-basic_cfg = $(LIB_/TMP/KULMALA3/FIFO_COMPARISON/CODELIB)/basic_cfg/_primary.dat +VCOM = vcom +VLOG = vlog + +whole_library : $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo_mixed_clocks2-behavioral) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo_mixed_clocks2) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo2-behavioral) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo2) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo1-behavioral) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo1) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-shift_slot-rtl) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-shift_slot) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-mixed_clocks_fifo-behavioral) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-mixed_clocks_fifo) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-inout_mux) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-in_mux) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-shift_reg) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-slotted_shift_reg) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-behavioral) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-basic_cfg) + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo) \ +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-behavioral) : Vhdl/fifo_casev4.vhdl \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Vhdl/fifo_casev4.vhdl + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-slotted_shift_reg) : Vhdl/fifo_shift_slotted.vhdl \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-shift_slot) \ + $(IEEE-std_logic_unsigned) \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Vhdl/fifo_shift_slotted.vhdl + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-shift_reg) : Vhdl/fifo_shift.vhdl \ + $(IEEE-std_logic_unsigned) \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Vhdl/fifo_shift.vhdl + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-in_mux) : Vhdl/fifo_im.vhdl \ + $(IEEE-std_logic_unsigned) \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Vhdl/fifo_im.vhdl + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo-inout_mux) : Vhdl/fifo_iom.vhdl \ + $(IEEE-std_logic_unsigned) \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Vhdl/fifo_iom.vhdl + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-mixed_clocks_fifo) \ +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-mixed_clocks_fifo-behavioral) : Vhdl/fifo_mixed_clocks.vhdl \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Vhdl/fifo_mixed_clocks.vhdl + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-shift_slot) \ +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-shift_slot-rtl) : Vhdl/shift_slot.vhdl \ + $(IEEE-std_logic_unsigned) \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Vhdl/shift_slot.vhdl + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo1) \ +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo1-behavioral) : Testbench/tb_fifo1.vhdl \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo) \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Testbench/tb_fifo1.vhdl + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo2) \ +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo2-behavioral) : Testbench/tb_fifo2.vhdl \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-fifo) \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Testbench/tb_fifo2.vhdl + +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-basic_cfg) \ +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo_mixed_clocks2) \ +$(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-tb_fifo_mixed_clocks2-behavioral) : Testbench/tb_fifo_mixed_clocks2.vhdl \ + $(/TMP/KULMALA3/FIFO_COMPARISON/CODELIB-mixed_clocks_fifo) \ + $(IEEE-std_logic_arith) \ + $(IEEE-std_logic_1164) + $(VCOM) -work /tmp/kulmala3/Fifo_comparison/codelib Testbench/tb_fifo_mixed_clocks2.vhdl Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_in_burst.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_in_burst.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_in_burst.vhd (revision 18) @@ -0,0 +1,193 @@ +------------------------------------------------------------------------------- +-- Title : +-- Project : +------------------------------------------------------------------------------- +-- File : aif_read_in_burst +-- Author : kulmala3 +-- Created : 01.07.2005 +-- Last update: 28.07.2006 +-- Description: Input: regular fifo IF: output asynchronous ack/nack IF +-- +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 01.07.2005 1.0 AK Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity aif_read_in_burst is + generic ( + parity_g : integer := 0; -- do we send parity or no + burst_width_g : integer := 6; -- length = data_w/burst_w + data_width_g : integer := 36 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + empty_in : in std_logic; + re_out : out std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(burst_width_g-1 downto 0); + a_we_out : out std_logic; + burst_out : out std_logic; + nack_in : in std_logic; + ack_in : in std_logic + + ); +end aif_read_in_burst; + +architecture rtl of aif_read_in_burst is + constant stages_c : integer := 2; -- only works with 2 now + signal ack_r : std_logic_vector(stages_c-1 downto 0); + signal nack_r : std_logic_vector(stages_c-1 downto 0); + + constant b_length_c : integer := data_width_g / burst_width_g; + + signal slow_cnt_r : integer range 0 to 15; -- slowdown counter + signal slow_value_r : integer range 0 to 15; -- slowdown counter + signal fail_cnt_r : integer range 0 to 1; -- two times we try to send per speed + signal a_we_l : std_logic; +-- signal full_r : std_logic; + + type data_vec_type is array (0 to b_length_c-1) of std_logic_vector(burst_width_g-1 downto 0); + signal data_slice : std_logic_vector(burst_width_g-1 downto 0); +-- signal datavec : data_vec_type; + signal slice_cnt_r : integer range 0 to b_length_c-1; + + signal ack_receiveid_r : std_logic; + signal nack_receiveid_r : std_logic; + + type send_state is (wait_data, send_burst, wait_ack, read_fifo); + signal ctrl_r : send_state; + + signal burst_r : std_logic; + +begin + + a_we_out <= a_we_l; + + data_out <= data_slice; + + burst_out <= burst_r; + + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_l <= '0'; + re_out <= '0'; + ack_r <= (others => '0'); + nack_r <= (others => '0'); + slow_cnt_r <= 1; + slice_cnt_r <= 0; + fail_cnt_r <= 0; + ctrl_r <= wait_data; + slow_value_r <= 1; + ack_receiveid_r <= '0'; + nack_receiveid_r <= '0'; + burst_r <= '0'; + + elsif clk'event and clk = '1' then -- rising clock edge + for i in 0 to stages_c-2 loop + ack_r(i+1) <= ack_r(i); + nack_r(i+1) <= nack_r(i); + end loop; -- i + ack_r(0) <= ack_in; + nack_r(0) <= nack_in; + + ack_receiveid_r <= ack_receiveid_r or ((ack_r(stages_c-1) xor ack_r(stages_c-2))); + nack_receiveid_r <= nack_receiveid_r or ((nack_r(stages_c-1) xor nack_r(stages_c-2))); + + case ctrl_r is + when wait_data => + if empty_in = '1' then + ctrl_r <= wait_data; + else + -- data in HIBI FIFO, send it + a_we_l <= not a_we_l; + slow_cnt_r <= slow_value_r; + slice_cnt_r <= 0; + ctrl_r <= send_burst; + end if; + + when send_burst => +-- if slow_cnt_r = 1 then +-- slow_cnt_r <= slow_cnt_r-1; +-- if slice_cnt_r = b_length_c-1 then +-- ctrl_r <= wait_ack; +-- burst_r <= not burst_r; +-- slice_cnt_r <= 0; -- last one +-- else +-- slice_cnt_r <= slice_cnt_r+1; +-- end if; +-- elsif slow_cnt_r = 0 then +-- a_we_l <= not a_we_l; +-- slow_cnt_r <= slow_value_r; +-- else +-- slow_cnt_r <= slow_cnt_r-1; +-- end if; + + if slow_cnt_r = 0 then + a_we_l <= not a_we_l; + slow_cnt_r <= slow_value_r; + elsif slow_cnt_r = 1 then --slow_value_r then + + if slice_cnt_r = b_length_c-1 then + ctrl_r <= wait_ack; + burst_r <= not burst_r; + slice_cnt_r <= 0; -- last one + else + slice_cnt_r <= slice_cnt_r+1; + end if; + slow_cnt_r <= slow_cnt_r-1; + else + slow_cnt_r <= slow_cnt_r-1; + + end if; + + when wait_ack => + if ack_receiveid_r = '1' then + ack_receiveid_r <= '0'; + ctrl_r <= read_fifo; + re_out <= '1'; + end if; + + if nack_receiveid_r = '1' then + nack_receiveid_r <= '0'; + slow_value_r <= slow_value_r+1; + slow_cnt_r <= slow_value_r+1; + a_we_l <= not a_we_l; + ctrl_r <= send_burst; + slice_cnt_r <= 0; -- ha´s been for a while now + end if; + + when read_fifo => + re_out <= '0'; + ctrl_r <= wait_data; + + when others => null; + end case; + + + end if; + end process; + + + datamux : process (data_in, slice_cnt_r) + variable datavec : data_vec_type; + + begin -- process datamux + datavec(0) := data_in(burst_width_g-1 downto 0); + for i in 2 to b_length_c loop + datavec(i-1) := data_in(burst_width_g*(i)-1 downto burst_width_g*(i-1)); + end loop; -- i + data_slice <= datavec(slice_cnt_r); + end process datamux; + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/synch_fifo_pulse.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/synch_fifo_pulse.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/synch_fifo_pulse.vhd (revision 18) @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- Title : Synchronizes two clock domains to a single clock FIFO +-- Project : +------------------------------------------------------------------------------- +-- File : synch_fifo_pulse.vhd +-- Author : kulmala3 +-- Created : 01.07.2005 +-- Last update: 01.07.2005 +-- Description: Generates a narrower pulse from a broader one, to read only one +-- data from a faster FIFO. +-- Should work at least when clk_fast is at least 2x clk_slow +-- tested on FPGA with clk_slow 50 and clk_fast 200 MHz +-- ASYNCHRONOUS INPUT/OUTPUT SIGNALS! +-- clk_slow: ____----____----____---- +-- clk_fast: -_-_-_-_-_-_-_-_-_-_-_-_ +-- re_in: __--------------------- +-- re_out: ____--________--______-- +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 01.07.2005 1.0 AK Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity synch_fifo_pulse is + + port ( + clk_slow : in std_logic; + clk_fast : in std_logic; + rst_n : in std_logic; + re_in : in std_logic; + re_out : out std_logic); + +end synch_fifo_pulse; + +architecture rtl of synch_fifo_pulse is + signal pulse_slow_r : std_logic; + signal pulse_fast_r : std_logic; + +begin -- rtl + + process (clk_slow, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + pulse_slow_r <= '0'; + + elsif clk_slow'event and clk_slow = '1' then -- rising clock edge + pulse_slow_r <= not pulse_slow_r; + end if; + end process; + + process (clk_fast, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + pulse_fast_r <= '0'; + + elsif clk_fast'event and clk_fast = '1' then -- rising clock edge + pulse_fast_r <= pulse_slow_r; + end if; + end process; + + re_out <= (pulse_fast_r xor pulse_slow_r) and re_in; + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/re_feeder.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/re_feeder.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/re_feeder.vhd (revision 18) @@ -0,0 +1,46 @@ +-- Simple block to test Synchronizer, no real testbench included. +-- tested on FPGA. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity re_feeder is + generic ( + pulse_width_g : integer := 8 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + re_out : out std_logic + ); + +end re_feeder; + +architecture rtl of re_feeder is + signal counter_r : integer range 0 to pulse_width_g-1 ; + signal re_r : std_logic; +begin -- rtl + + re_out <= re_r; + + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + counter_r <= 0; + re_r <= '0'; + + elsif clk'event and clk = '1' then -- rising clock edge + if counter_r = pulse_width_g-1 then + re_r <= not re_r; + counter_r <= 0; + else + re_r <= re_r; + counter_r <= counter_r+1; + end if; + end if; + end process; + + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_out_burst.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_out_burst.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_out_burst.vhd (revision 18) @@ -0,0 +1,145 @@ +------------------------------------------------------------------------------- +-- Title : +-- Project : +------------------------------------------------------------------------------- +-- File : aif_read_out_burst +-- Author : kulmala3 +-- Created : 01.07.2005 +-- Last update: 05.01.2006 +-- Description: OUT: regular fifo IN: output asynchronous ack/nack IF +-- +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 01.07.2005 1.0 AK Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity aif_read_out_burst is + generic ( + parity_g : integer := 0; -- do we send parity or no + burst_width_g : integer := 6; -- length = data_w/burst_w + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + a_we_in : in std_logic; + ack_out : out std_logic; + nack_out : out std_logic; + empty_out : out std_logic; + re_in : in std_logic; + burst_in : in std_logic; + data_in : in std_logic_vector(burst_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0) + + ); +end aif_read_out_burst; + +architecture rtl of aif_read_out_burst is + + constant stages_c : integer := 3; + constant ctrl_stages_c : integer := 2; -- burst + + constant b_length_c : integer := data_width_g / burst_width_g; + + signal ack_r : std_logic; + signal nack_r : std_logic; + -- synchronizer, last two are xorred + signal a_we_r : std_logic_vector(stages_c-1 downto 0); + + type in_data_type is array (0 to stages_c-1) of std_logic_vector(burst_width_g-1 downto 0); + signal in_data_r : in_data_type; + + signal data_r : std_logic_vector(data_width_g-1 downto 0); + + type data_vec_type is array (0 to b_length_c-1) of std_logic_vector(burst_width_g-1 downto 0); +-- signal data_slice : std_logic_vector(burst_width_g-1 downto 0); +-- signal datavec : data_vec_type; + signal slice_cnt_r : integer range 0 to b_length_c-1; + signal burst_r : std_logic_vector(stages_c-1 downto 0); + signal empty_r : std_logic; + signal data_ok_r : std_logic; + +begin + data_out <= data_r; + ack_out <= ack_r; + nack_out <= nack_r; + empty_out <= empty_r; + + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_r <= (others => '0'); + ack_r <= '0'; + empty_r <= '1'; + slice_cnt_r <= 0; + nack_r <= '0'; + empty_r <= '1'; + for i in 0 to stages_c-1 loop + in_data_r(i) <= (others => '0'); + end loop; -- i + burst_r <= (others => '0'); + data_ok_r <= '0'; + + elsif clk'event and clk = '1' then -- rising clock edge + ack_r <= ack_r; + + for i in 0 to stages_c-2 loop + a_we_r(i+1) <= a_we_r(i); + in_data_r(i+1) <= in_data_r(i); + burst_r(i+1) <= burst_r(i); + end loop; -- i + + burst_r(0) <= burst_in; + a_we_r(0) <= a_we_in; + in_data_r(0) <= data_in; + + if (a_we_r(stages_c-1) xor a_we_r(stages_c-2)) = '1' then + -- slice cnt testaus! + + for i in 0 to b_length_c-1 loop + if i = slice_cnt_r then + data_r((i+1)*burst_width_g-1 downto burst_width_g*(i)) <= in_data_r(stages_c-2); + end if; + end loop; -- i + + if slice_cnt_r = b_length_c-1 then + empty_r <= '0'; + slice_cnt_r <= 0; + data_ok_r <= '1'; + else + empty_r <= '1'; + slice_cnt_r <= slice_cnt_r+1; + end if; + + end if; + + if (burst_r(stages_c-1) xor burst_r(stages_c-2)) = '1' then + if data_ok_r = '0' then + nack_r <= not nack_r; + empty_r <= '1'; + slice_cnt_r <= 0; + else + data_ok_r <= '0'; + end if; + end if; + + if re_in = '1' and empty_r = '0' then + -- acknowledge, stop writing + ack_r <= not ack_r; + empty_r <= '1'; + end if; + + + end if; + end process; + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_we_in.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_we_in.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_we_in.vhd (revision 18) @@ -0,0 +1,82 @@ +------------------------------------------------------------------------------- +-- Title : +-- Project : +------------------------------------------------------------------------------- +-- File : +-- Author : kulmala3 +-- Created : 01.07.2005 +-- Last update: 10.01.2006 +-- Description: Input: regular fifo IF: output asynchronous ack/nack IF +-- +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 01.07.2005 1.0 AK Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity aif_we_in is + generic ( + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + we_in : in std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + full_out : out std_logic; + a_we_out : out std_logic; -- must arrive after data! + ack_in : in std_logic -- actually, one clock cycle + ); -- more for data in rx +end aif_we_in; + +architecture rtl of aif_we_in is + constant stages_c : integer := 2; -- only works with 2 now + signal ack_r : std_logic_vector(stages_c-1 downto 0); + + signal a_we_l : std_logic; + signal data_r : std_logic_vector(data_width_g-1 downto 0); + signal full_r : std_logic; +begin + + a_we_out <= a_we_l; + + data_out <= data_r; + + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_l <= '0'; + ack_r <= (others => '0'); + full_r <= '0'; +-- first_full_r <= '1'; +-- data_r <= (others => '0'); + + elsif clk'event and clk = '1' then -- rising clock edge + for i in 0 to stages_c-2 loop + ack_r(i+1) <= ack_r(i); + end loop; -- i + + ack_r(0) <= ack_in; + full_r <= (a_we_l xor ack_r(stages_c-1)); + if we_in = '1' and full_r = '0' then + a_we_l <= not a_we_l; + data_r <= data_in; + full_r <= '1'; -- react immediatelly + else + a_we_l <= a_we_l; + end if; + + end if; + end process; + + full_out <= full_r; +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_in.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_in.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_in.vhd (revision 18) @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------- +-- Title : +-- Project : +------------------------------------------------------------------------------- +-- File : latch synch +-- Author : kulmala3 +-- Created : 01.07.2005 +-- Last update: 17.02.2006 +-- Description: Input: regular fifo IF: output asynchronous ack/nack IF +-- +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 01.07.2005 1.0 AK Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity aif_read_in is + generic ( + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + empty_in : in std_logic; + re_out : out std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + a_we_out : out std_logic; + ack_in : in std_logic + ); +end aif_read_in; + +architecture rtl of aif_read_in is + constant stages_c : integer := 2; -- only works with 2 now + signal ack_r : std_logic_vector(stages_c-1 downto 0); + + + signal a_we_l : std_logic; + signal data_r : std_logic_vector(data_width_g-1 downto 0); + signal full_r : std_logic; +begin + + a_we_out <= a_we_l; + + data_out <= data_r; + + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_l <= '0'; + re_out <= '0'; + ack_r <= (others => '0'); + full_r <= '0'; + + elsif clk'event and clk = '1' then -- rising clock edge + for i in 0 to stages_c-2 loop + ack_r(i+1) <= ack_r(i); + end loop; -- i + ack_r(0) <= ack_in; + full_r <= (a_we_l xor ack_r(stages_c-1)); + + if empty_in = '0' and full_r = '0' then + a_we_l <= not a_we_l; + re_out <= '1'; + data_r <= data_in; + full_r <= '1'; + else + re_out <= '0'; + a_we_l <= a_we_l; + end if; + + end if; + end process; + +-- full_r <= (a_we_l xor ack_in); +-- full_out <= full; +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_we_out.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_we_out.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_we_out.vhd (revision 18) @@ -0,0 +1,95 @@ +------------------------------------------------------------------------------- +-- Title : +-- Project : +------------------------------------------------------------------------------- +-- File : latch synch +-- Author : kulmala3 +-- Created : 01.07.2005 +-- Last update: 05.01.2006 +-- Description: OUT: regular fifo IN: output asynchronous ack/nack IF +-- +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 01.07.2005 1.0 AK Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity aif_we_out is + generic ( + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + a_we_in : in std_logic; + ack_out : out std_logic; + we_out : out std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + + full_in : in std_logic + ); +end aif_we_out; + +architecture rtl of aif_we_out is + + constant stages_c : integer := 3; + + signal ack_r : std_logic; + signal received_data_r : std_logic; + -- synchronizer, last two are xorred + signal a_we_r : std_logic_vector(stages_c-1 downto 0); + signal data_r : std_logic_vector(data_width_g-1 downto 0); + +begin + data_out <= data_r; +-- ack_out <= ack_r; + + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_r <= (others => '0'); + ack_r <= '0'; + ack_out <= '0'; + we_out <= '0'; + received_data_r <= '0'; + + elsif clk'event and clk = '1' then -- rising clock edge + + for i in 0 to stages_c-2 loop + a_we_r(i+1) <= a_we_r(i); + end loop; -- i + + a_we_r(0) <= a_we_in; + + -- now wait until we can write it to fifo + + if (a_we_r(stages_c-1) xor a_we_r(stages_c-2)) = '1' then + ack_r <= not ack_r; + received_data_r <= '1'; + we_out <= '1'; + data_r <= data_in; + else + ack_r <= ack_r; + end if; + + if full_in = '0' and received_data_r = '1' then + -- acknowledge, stop writing + ack_out <= ack_r; + we_out <= '0'; + received_data_r <= '0'; + end if; + + + end if; + end process; + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_out.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_out.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_out.vhd (revision 18) @@ -0,0 +1,94 @@ +------------------------------------------------------------------------------- +-- Title : +-- Project : +------------------------------------------------------------------------------- +-- File : latch synch +-- Author : kulmala3 +-- Created : 01.07.2005 +-- Last update: 05.01.2006 +-- Description: OUT: regular fifo IN: output asynchronous ack/nack IF +-- +------------------------------------------------------------------------------- +-- Copyright (c) 2005 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 01.07.2005 1.0 AK Created +------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity aif_read_out is + generic ( + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + a_we_in : in std_logic; + ack_out : out std_logic; + empty_out : out std_logic; + re_in : in std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0) + + ); +end aif_read_out; + +architecture rtl of aif_read_out is + + constant stages_c : integer := 3; + + signal ack_r : std_logic; + signal received_data_r : std_logic; + -- synchronizer, last two are xorred + signal a_we_r : std_logic_vector(stages_c-1 downto 0); + signal data_r : std_logic_vector(data_width_g-1 downto 0); +begin + data_out <= data_r; +-- ack_out <= ack_r; + + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_r <= (others => '0'); + ack_r <= '0'; + ack_out <= '0'; + received_data_r <= '0'; + empty_out <= '1'; + + elsif clk'event and clk = '1' then -- rising clock edge + + for i in 0 to stages_c-2 loop + a_we_r(i+1) <= a_we_r(i); + end loop; -- i + + a_we_r(0) <= a_we_in; + + -- now wait until we can write it to fifo + + if (a_we_r(stages_c-1) xor a_we_r(stages_c-2)) = '1' then + ack_r <= not ack_r; + received_data_r <= '1'; + data_r <= data_in; + empty_out <= '0'; + else + ack_r <= ack_r; + end if; + + if re_in = '1' and received_data_r = '1' then + -- acknowledge, stop writing + ack_out <= ack_r; + empty_out <= '1'; + received_data_r <= '0'; + end if; + + + end if; + end process; + +end rtl; Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/asyn_re_fifo.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/asyn_re_fifo.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/asyn_re_fifo.vhd (revision 18) @@ -0,0 +1,127 @@ +------------------------------------------------------------------------------- +-- Title : asyn re fifo +-- Project : +------------------------------------------------------------------------------- +-- File : asyn_re_fifo.vhd +-- Author : kulmala3 +-- Created : 13.06.2006 +-- Last update: 13.06.2006 +-- Description: A FIFO with synchronous write interface and asynchronous +-- signaling for RX +------------------------------------------------------------------------------- +-- Copyright (c) 2006 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 13.06.2006 1.0 AK Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +entity asyn_re_fifo is + generic ( + depth_g : integer := 5; + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + -- regular fifo + data_in : in std_logic_vector (data_width_g-1 downto 0); + we_in : in std_logic; + full_out : out std_logic; + -- asyn IF + data_out : out std_logic_vector (data_width_g-1 downto 0); + ack_in : in std_logic; + a_we_out : out std_logic + + ); +end asyn_re_fifo; + + +architecture structural of asyn_re_fifo is + + component aif_read_in + generic ( + data_width_g : integer); + port ( + clk : in std_logic; + rst_n : in std_logic; + empty_in : in std_logic; + re_out : out std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + a_we_out : out std_logic; + ack_in : in std_logic); + end component; + + signal empty_to_read_in : std_logic; + signal re_from_read_in : std_logic; + signal data_to_read_in : std_logic_vector(data_width_g-1 downto 0); + signal data_from_read_in : std_logic_vector(data_width_g-1 downto 0); + signal a_we_from_read_in : std_logic; + signal ack_to_read_in : std_logic; + + component fifo + generic ( + data_width_g : integer; + depth_g : integer); + port ( + clk : in std_logic; + rst_n : in std_logic; + data_in : in std_logic_vector (data_width_g-1 downto 0); + we_in : in std_logic; + full_out : out std_logic; + one_p_out : out std_logic; + re_in : in std_logic; + data_out : out std_logic_vector (data_width_g-1 downto 0); + empty_out : out std_logic; + one_d_out : out std_logic); + end component; + + + +begin + + aif_read_in_1 : aif_read_in + generic map ( + data_width_g => data_width_g) + port map ( + clk => clk, + rst_n => rst_n, + + empty_in => empty_to_read_in, + re_out => re_from_read_in, + data_in => data_to_read_in, + + data_out => data_out, + a_we_out => a_we_out, + ack_in => ack_in + ); + + fifo_1 : fifo + generic map ( + data_width_g => data_width_g, + depth_g => depth_g) + port map ( + clk => clk, + rst_n => rst_n, + + data_in => data_in, + we_in => we_in, + full_out => full_out, + +-- one_p_out => one_p_out, +-- one_d_out => one_d_out, + + re_in => re_from_read_in, + data_out => data_to_read_in, + empty_out => empty_to_read_in + ); + + +end structural; Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/ext_data_synch_v2.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/ext_data_synch_v2.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/ext_data_synch_v2.vhd (revision 18) @@ -0,0 +1,227 @@ +------------------------------------------------------------------------------- +-- Title : Off-chip data bus for same clock frequencies at different phase +-- Project : +------------------------------------------------------------------------------- +-- File : ext_data_synch.vhd +-- Author : +-- Created : 11.08.2006 +-- Last update: 07.08.2007 +-- Description: REQUIRES THE SAME CLOCK FREQUENCIES FROM BOTH ENDS! +-- Possible hazard in empty: not synchronized. maybe change it later if errors +-- occure. +------------------------------------------------------------------------------- +-- Copyright (c) 2006 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 11.08.2006 1.0 AK Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity ext_data_synch is + + generic ( + sync_freq_g : integer := 1; + bus_freq_g : integer := 1; + data_width_g : integer := 4; + depth_g : integer := 10 -- FIFO size & max transfer size + ); + + port ( + + clk_re : in std_logic; + clk_we : in std_logic; + rst_n : in std_logic; + + tx_data_in : in std_logic_vector(data_width_g-1 downto 0); + tx_empty_in : in std_logic; + tx_re_out : out std_logic; + + rx_re_in : in std_logic; + rx_data_out : out std_logic_vector(data_width_g-1 downto 0); + rx_empty_out : out std_logic; + + a_empty_in : in std_logic; + a_empty_out : out std_logic; + a_we_out : out std_logic; + a_we_in : in std_logic; + a_data_out : out std_logic_vector(data_width_g-1 downto 0); + a_data_in : in std_logic_vector(data_width_g-1 downto 0) + ); + +end ext_data_synch; + +architecture rtl of ext_data_synch is + constant stable_period_c : integer := 3; -- stable for n clock cycles. + -- works with 3 in FPGA. + constant n_data_on_lines_c : integer := 10; -- amount of data packets that may be + -- travelling currently to the other side. used to approximate the rquired + -- FIFO depth (depth_g+n_data_on_lines_c = fifo depth) + + -- tx signals + signal a_we_out_r : std_logic; + signal data_cnt_r : integer range depth_g downto 0; + signal stable_cnt_r : integer range stable_period_c-1 downto 0; + signal a_data_out_r : std_logic_vector(data_width_g-1 downto 0); + signal a_empty_in_r : std_logic_vector(1 downto 0); + --rx signals + signal a_we_in_r : std_logic_vector(1 downto 0); + signal read_in : std_logic; + + signal rx_fifo_data_in : std_logic_vector (data_width_g-1 downto 0); + signal rx_fifo_we_in : std_logic; + signal rx_fifo_full_out : std_logic; +-- signal rx_fifo_re_in : std_logic; +-- signal rx_fifo_data_out : std_logic_vector (data_width_g-1 downto 0); + signal rx_fifo_empty_out : std_logic; + + -- receiving FIFO + component multiclk_fifo + generic ( + re_freq_g : integer; + we_freq_g : integer; + depth_g : integer; + data_width_g : integer); + port ( + clk_re : in std_logic; + clk_we : in std_logic; + rst_n : in std_logic; + data_in : in std_logic_vector (data_width_g-1 downto 0); + we_in : in std_logic; + full_out : out std_logic; + one_p_out : out std_logic; + re_in : in std_logic; + data_out : out std_logic_vector (data_width_g-1 downto 0); + empty_out : out std_logic; + one_d_out : out std_logic); + end component; + +-- component fifo +-- generic ( +-- data_width_g : integer; +-- depth_g : integer); +-- port ( +-- clk : in std_logic; +-- rst_n : in std_logic; +-- data_in : in std_logic_vector (data_width_g-1 downto 0); +-- we_in : in std_logic; +-- full_out : out std_logic; +-- one_p_out : out std_logic; +-- re_in : in std_logic; +-- data_out : out std_logic_vector (data_width_g-1 downto 0); +-- empty_out : out std_logic; +-- one_d_out : out std_logic); +-- end component; + + type tx_states is (send, keep_stable); + signal tx_ctrl_r : tx_states; + +begin -- rtl + + -- purpose: tx side of the block + a_data_out <= a_data_out_r; + a_we_out <= a_we_out_r; + + process (clk_we, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_out_r <= '0'; + data_cnt_r <= 0; -- could also be depth_g + tx_ctrl_r <= send; + stable_cnt_r <= 0; + a_data_out_r <= (others => '0'); + tx_re_out <= '0'; + a_empty_in_r <= (others => '0'); + + elsif clk_we'event and clk_we = '1' then -- rising clock edge + a_empty_in_r(0) <= a_empty_in; + a_empty_in_r(1) <= a_empty_in_r(0); + case tx_ctrl_r is + when send => + if tx_empty_in = '0' and (a_empty_in_r(1) = '1' or data_cnt_r /= 0) then + a_data_out_r <= tx_data_in; + tx_re_out <= '1'; + a_we_out_r <= not a_we_out_r; + tx_ctrl_r <= keep_stable; + stable_cnt_r <= stable_period_c-1; + if a_empty_in_r(1) = '1' then + data_cnt_r <= depth_g; + else + data_cnt_r <= data_cnt_r-1; + end if; + + else + tx_re_out <= '0'; + end if; + + when keep_stable => + a_data_out_r <= a_data_out_r; + a_we_out_r <= a_we_out_r; + tx_re_out <= '0'; + if stable_cnt_r /= 0 then + stable_cnt_r <= stable_cnt_r-1; + else + tx_ctrl_r <= send; + stable_cnt_r <= stable_period_c-1; + end if; + + end case; + + end if; + end process; + + + read_in <= a_we_in_r(1) xor a_we_in_r(0); + -- purpose: rx side of the block + process (clk_we, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_in_r <= (others => '0'); + rx_fifo_we_in <= '0'; + + elsif clk_we'event and clk_we = '1' then -- rising clock edge + -- if FIFO is full, we are anyway screwed, no reason to check it... + a_we_in_r(0) <= a_we_in; + a_we_in_r(1) <= a_we_in_r(0); + if read_in = '1' then + rx_fifo_data_in <= a_data_in; + rx_fifo_we_in <= '1'; + assert rx_fifo_full_out = '0' report "Writing to full FIFO!!" severity error; + else + rx_fifo_we_in <= '0'; + end if; + end if; + end process; + + fifo_1 : multiclk_fifo + generic map ( + re_freq_g => sync_freq_g, + we_freq_g => sync_freq_g, + data_width_g => data_width_g, + depth_g => depth_g+n_data_on_lines_c) + port map ( + + clk_we => clk_we, + clk_re => clk_we, + rst_n => rst_n, + + data_in => rx_fifo_data_in, + we_in => rx_fifo_we_in, + full_out => rx_fifo_full_out, + +-- one_p_out => one_p_out, + re_in => rx_re_in, + data_out => rx_data_out, + empty_out => rx_fifo_empty_out +-- one_d_out => one_d_out + ); + + rx_empty_out <= rx_fifo_empty_out; + a_empty_out <= rx_fifo_empty_out; + +end rtl; + Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_we_top.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_we_top.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_we_top.vhd (revision 18) @@ -0,0 +1,122 @@ +------------------------------------------------------------------------------- +-- Title : +-- Project : +------------------------------------------------------------------------------- +-- File : +-- Author : +-- Created : 04.01.2006 +-- Last update: 24.02.2006 +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2006 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 04.01.2006 1.0 AK Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +------------------------------------------------------------------------------- + +entity aif_we_top is + generic ( + data_width_g : integer := 32 + ); + port ( + tx_clk : in std_logic; + tx_rst_n : in std_logic; + tx_we_in : in std_logic; + tx_data_in : in std_logic_vector(data_width_g-1 downto 0); + tx_full_out : out std_logic; + + rx_clk : in std_logic; + rx_rst_n : in std_logic; + rx_full_in : in std_logic; + rx_we_out : out std_logic; + rx_data_out : out std_logic_vector(data_width_g-1 downto 0) + + ); + +end aif_we_top; + +------------------------------------------------------------------------------- + +architecture structural of aif_we_top is + + component aif_we_out + generic ( + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + a_we_in : in std_logic; + ack_out : out std_logic; + we_out : out std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + full_in : in std_logic); + end component; + + -- component ports + signal ack_from_rx : std_logic; +-- signal we_from_rx : std_logic; +-- signal data_from_rx : std_logic_vector(data_width_g-1 downto 0); + + component aif_we_in + generic ( + data_width_g : integer); + port ( + clk : in std_logic; + rst_n : in std_logic; + we_in : in std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + full_out : out std_logic; + a_we_out : out std_logic; + ack_in : in std_logic + ); + end component; + + signal data_from_tx : std_logic_vector(data_width_g-1 downto 0); +-- signal full_from_tx : std_logic; + signal a_we_from_tx : std_logic; + +begin -- structural + + -- component instantiation + DUT : aif_we_out + generic map ( + data_width_g => data_width_g) + port map ( + clk => rx_clk, + rst_n => rx_rst_n, + a_we_in => a_we_from_tx, + ack_out => ack_from_rx, + data_in => data_from_tx, + data_out => rx_data_out, + we_out => rx_we_out, + full_in => rx_full_in + ); + + asynch_if_tx_1 : aif_we_in + generic map ( + data_width_g => data_width_g) + port map ( + clk => tx_clk, + rst_n => tx_rst_n, + we_in => tx_we_in, + data_in => tx_data_in, + data_out => data_from_tx, + full_out => tx_full_out, + a_we_out => a_we_from_tx, + ack_in => ack_from_rx + ); + + +end structural; + +------------------------------------------------------------------------------- Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_top.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_top.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/aif_read_top.vhd (revision 18) @@ -0,0 +1,124 @@ +------------------------------------------------------------------------------- +-- Title : +-- Project : +------------------------------------------------------------------------------- +-- File : +-- Author : +-- Created : 04.01.2006 +-- Last update: 04.01.2006 +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2006 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 04.01.2006 1.0 AK Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +------------------------------------------------------------------------------- + +entity aif_read_top is + generic ( + data_width_g : integer := 32 + ); + port ( + tx_clk : in std_logic; + tx_rst_n : in std_logic; + tx_data_in : in std_logic_vector(data_width_g-1 downto 0); + tx_empty_in : in std_logic; + tx_re_out : out std_logic; + + rx_clk : in std_logic; + rx_rst_n : in std_logic; + rx_empty_out : out std_logic; + rx_re_in : in std_logic; + + rx_data_out : out std_logic_vector(data_width_g-1 downto 0) + + ); + +end aif_read_top; + +------------------------------------------------------------------------------- + +architecture structural of aif_read_top is + + component aif_read_out + generic ( + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + a_we_in : in std_logic; + ack_out : out std_logic; + empty_out : out std_logic; + re_in : in std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0) + ); + end component; + + -- component ports + signal ack_from_rx : std_logic; +-- signal we_from_rx : std_logic; +-- signal data_from_rx : std_logic_vector(data_width_g-1 downto 0); + + component aif_read_in + generic ( + data_width_g : integer); + port ( + clk : in std_logic; + rst_n : in std_logic; + empty_in : in std_logic; + re_out : out std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + a_we_out : out std_logic; + ack_in : in std_logic + ); + end component; + + signal data_from_tx : std_logic_vector(data_width_g-1 downto 0); + signal full_from_tx : std_logic; + signal a_we_from_tx : std_logic; + +begin -- structural + + -- component instantiation + DUT : aif_read_out + generic map ( + data_width_g => data_width_g) + port map ( + clk => rx_clk, + rst_n => rx_rst_n, + a_we_in => a_we_from_tx, + ack_out => ack_from_rx, + data_in => data_from_tx, + data_out => rx_data_out, + empty_out => rx_empty_out, + re_in => rx_re_in + ); + + aif_read_in_1 : aif_read_in + generic map ( + data_width_g => data_width_g) + port map ( + clk => tx_clk, + rst_n => tx_rst_n, + empty_in => tx_empty_in, + data_in => tx_data_in, + data_out => data_from_tx, + re_out => tx_re_out, + a_we_out => a_we_from_tx, + ack_in => ack_from_rx + ); + + +end structural; + +------------------------------------------------------------------------------- Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/ext_data_synch.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/ext_data_synch.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Vhd/ext_data_synch.vhd (revision 18) @@ -0,0 +1,199 @@ +------------------------------------------------------------------------------- +-- Title : Off-chip data bus for same clock frequencies at different phase +-- Project : +------------------------------------------------------------------------------- +-- File : ext_data_synch.vhd +-- Author : +-- Created : 11.08.2006 +-- Last update: 15.08.2006 +-- Description: REQUIRES THE SAME CLOCK FREQUENCIES FROM BOTH ENDS! +-- Possible hazard in empty: not synchronized. maybe change it later if errors +-- occure. +------------------------------------------------------------------------------- +-- Copyright (c) 2006 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 11.08.2006 1.0 AK Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity ext_data_synch is + + generic ( + data_width_g : integer := 4; + depth_g : integer := 10 -- FIFO size & max transfer size + ); + + port ( + clk : in std_logic; + rst_n : in std_logic; + + tx_data_in : in std_logic_vector(data_width_g-1 downto 0); + tx_empty_in : in std_logic; + tx_re_out : out std_logic; + + rx_re_in : in std_logic; + rx_data_out : out std_logic_vector(data_width_g-1 downto 0); + rx_empty_out : out std_logic; + + a_empty_in : in std_logic; + a_empty_out : out std_logic; + a_we_out : out std_logic; + a_we_in : in std_logic; + a_data_out : out std_logic_vector(data_width_g-1 downto 0); + a_data_in : in std_logic_vector(data_width_g-1 downto 0) + ); + +end ext_data_synch; + +architecture rtl of ext_data_synch is + constant stable_period_c : integer := 3; -- stable for n clock cycles. + -- works with 3 in FPGA. + constant n_data_on_lines_c : integer := 10; -- amount of data packets that may be + -- travelling currently to the other side. used to approximate the rquired + -- FIFO depth (depth_g+n_data_on_lines_c = fifo depth) + + -- tx signals + signal a_we_out_r : std_logic; + signal data_cnt_r : integer range depth_g downto 0; + signal stable_cnt_r : integer range stable_period_c-1 downto 0; + signal a_data_out_r : std_logic_vector(data_width_g-1 downto 0); + signal a_empty_in_r : std_logic_vector(1 downto 0); + --rx signals + signal a_we_in_r : std_logic_vector(1 downto 0); + signal read_in : std_logic; + + signal rx_fifo_data_in : std_logic_vector (data_width_g-1 downto 0); + signal rx_fifo_we_in : std_logic; + signal rx_fifo_full_out : std_logic; +-- signal rx_fifo_re_in : std_logic; +-- signal rx_fifo_data_out : std_logic_vector (data_width_g-1 downto 0); + signal rx_fifo_empty_out : std_logic; + + -- receiving FIFO + component fifo + generic ( + data_width_g : integer; + depth_g : integer); + port ( + clk : in std_logic; + rst_n : in std_logic; + data_in : in std_logic_vector (data_width_g-1 downto 0); + we_in : in std_logic; + full_out : out std_logic; + one_p_out : out std_logic; + re_in : in std_logic; + data_out : out std_logic_vector (data_width_g-1 downto 0); + empty_out : out std_logic; + one_d_out : out std_logic); + end component; + + type tx_states is (send, keep_stable); + signal tx_ctrl_r : tx_states; + +begin -- rtl + + -- purpose: tx side of the block + a_data_out <= a_data_out_r; + a_we_out <= a_we_out_r; + + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_out_r <= '0'; + data_cnt_r <= 0; -- could also be depth_g + tx_ctrl_r <= send; + stable_cnt_r <= 0; + a_data_out_r <= (others => '0'); + tx_re_out <= '0'; + a_empty_in_r <= (others => '0'); + + elsif clk'event and clk = '1' then -- rising clock edge + a_empty_in_r(0) <= a_empty_in; + a_empty_in_r(1) <= a_empty_in_r(0); + case tx_ctrl_r is + when send => + if tx_empty_in = '0' and (a_empty_in_r(1) = '1' or data_cnt_r /= 0) then + a_data_out_r <= tx_data_in; + tx_re_out <= '1'; + a_we_out_r <= not a_we_out_r; + tx_ctrl_r <= keep_stable; + stable_cnt_r <= stable_period_c-1; + if a_empty_in_r(1) = '1' then + data_cnt_r <= depth_g; + else + data_cnt_r <= data_cnt_r-1; + end if; + + else + tx_re_out <= '0'; + end if; + + when keep_stable => + a_data_out_r <= a_data_out_r; + a_we_out_r <= a_we_out_r; + tx_re_out <= '0'; + if stable_cnt_r /= 0 then + stable_cnt_r <= stable_cnt_r-1; + else + tx_ctrl_r <= send; + stable_cnt_r <= stable_period_c-1; + end if; + + end case; + + end if; + end process; + + + read_in <= a_we_in_r(1) xor a_we_in_r(0); + -- purpose: rx side of the block + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + a_we_in_r <= (others => '0'); + rx_fifo_we_in <= '0'; + + elsif clk'event and clk = '1' then -- rising clock edge + -- if FIFO is full, we are anyway screwed, no reason to check it... + a_we_in_r(0) <= a_we_in; + a_we_in_r(1) <= a_we_in_r(0); + if read_in = '1' then + rx_fifo_data_in <= a_data_in; + rx_fifo_we_in <= '1'; + assert rx_fifo_full_out = '0' report "Writing to full FIFO!!" severity error; + else + rx_fifo_we_in <= '0'; + end if; + end if; + end process; + + fifo_1 : fifo + generic map ( + data_width_g => data_width_g, + depth_g => depth_g+n_data_on_lines_c) + port map ( + clk => clk, + rst_n => rst_n, + + data_in => rx_fifo_data_in, + we_in => rx_fifo_we_in, + full_out => rx_fifo_full_out, + +-- one_p_out => one_p_out, + re_in => rx_re_in, + data_out => rx_data_out, + empty_out => rx_fifo_empty_out +-- one_d_out => one_d_out + ); + + rx_empty_out <= rx_fifo_empty_out; + a_empty_out <= rx_fifo_empty_out; + +end rtl; + Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_aif_we_top.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_aif_we_top.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_aif_we_top.vhd (revision 18) @@ -0,0 +1,214 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "aif_we_top_s" +-- Project : +------------------------------------------------------------------------------- +-- File : tb_aif_we_top_send.vhd +-- Author : +-- Created : 04.01.2006 +-- Last update: 17.02.2006 +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2006 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 04.01.2006 1.0 AK Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use work.txt_util.all; +------------------------------------------------------------------------------- + +entity tb_aif_we_top is + +end tb_aif_we_top; + +------------------------------------------------------------------------------- + +architecture rtl of tb_aif_we_top is + + component aif_we_out + generic ( + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + a_we_in : in std_logic; + ack_out : out std_logic; + we_out : out std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + full_in : in std_logic); + end component; + + constant data_width_g : integer := 32; + + -- component ports + signal clk : std_logic; + signal rst_n : std_logic; + signal ack_from_rx : std_logic; + signal we_from_rx : std_logic; + signal data_from_rx : std_logic_vector(data_width_g-1 downto 0); + signal full_to_rx : std_logic; + + -- clock and reset + constant Period : time := 100 ns; + constant Period2 : time := 10 ns; + + component aif_we_in + generic ( + data_width_g : integer); + port ( + clk : in std_logic; + rst_n : in std_logic; + we_in : in std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + full_out : out std_logic; + a_we_out : out std_logic; + ack_in : in std_logic + ); + end component; + + signal we_to_tx : std_logic; + signal data_to_tx : std_logic_vector(data_width_g-1 downto 0); + signal data_from_tx : std_logic_vector(data_width_g-1 downto 0); + signal full_from_tx : std_logic; + signal a_we_from_tx : std_logic; + + signal clk2 : std_logic; +-- constant clk2_scaler : integer := 3; + + signal cnt_tx_data_r : std_logic_vector(data_width_g-1 downto 0); + signal cnt_rx_data_r : std_logic_vector(data_width_g-1 downto 0); + signal rx_full_cnt_r : integer; + signal tx_we_cnt_r : integer; + + constant full_after_we_c : integer := 3; -- after n data issue full + constant full_length_c : integer := 10; -- cc full is asserted + constant time_before_we_c : integer := 100; -- delay after sending + constant start_value_c : integer := 3; + +begin -- rtl + + -- component instantiation + DUT : aif_we_out + generic map ( + data_width_g => data_width_g) + port map ( + clk => clk, + rst_n => rst_n, + a_we_in => a_we_from_tx, + ack_out => ack_from_rx, + data_in => data_from_tx, + data_out => data_from_rx, + we_out => we_from_rx, + full_in => full_to_rx + ); + + aif_we_in_1 : aif_we_in + generic map ( + data_width_g => data_width_g) + port map ( + clk => clk2, + rst_n => rst_n, + we_in => we_to_tx, + data_in => data_to_tx, + data_out => data_from_tx, + full_out => full_from_tx, + a_we_out => a_we_from_tx, + ack_in => ack_from_rx + ); + + + -- receiving, use clk + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + cnt_rx_data_r <= conv_std_logic_vector(start_value_c, data_width_g); + full_to_rx <= '0'; + rx_full_cnt_r <= 0; + + elsif clk'event and clk = '1' then -- rising clock edge + if we_from_rx = '1' and full_to_rx = '0' then + assert cnt_rx_data_r = data_from_rx report "Error: rx data wrong wait: " & + str(conv_integer(cnt_rx_data_r)) & "got: " & + str(conv_integer(data_from_rx)) + severity error; + cnt_rx_data_r <= cnt_rx_data_r+1; + rx_full_cnt_r <= rx_full_cnt_r + 1; + end if; + + if rx_full_cnt_r > full_after_we_c + full_length_c -1 then + full_to_rx <= '0'; + rx_full_cnt_r <= 0; + elsif rx_full_cnt_r > full_after_we_c-1 then + full_to_rx <= '1'; + rx_full_cnt_r <= rx_full_cnt_r+1; + end if; + + end if; + + end process; + + -- transmit, use different clock. + tx : process (clk2, rst_n) + begin -- process tx + if rst_n = '0' then -- asynchronous reset (active low) + tx_we_cnt_r <= 0; + data_to_tx <= conv_std_logic_vector(start_value_c, data_width_g); + cnt_tx_data_r <= conv_std_logic_vector(start_value_c, data_width_g); + we_to_tx <= '0'; + + elsif clk2'event and clk2 = '1' then -- rising clock edge + if tx_we_cnt_r > 0 then + tx_we_cnt_r <= tx_we_cnt_r-1; + we_to_tx <= '0'; + end if; + if full_from_tx = '0' then + if tx_we_cnt_r = 0 then + we_to_tx <= '1'; + data_to_tx <= cnt_tx_data_r; + cnt_tx_data_r <= cnt_tx_data_r+1; + tx_we_cnt_r <= time_before_we_c; + end if; + end if; + end if; + end process tx; + + -- clock generation + -- PROC + CLOCK1 : process -- generate clock signal for design + variable clktmp : std_logic := '0'; + begin + wait for PERIOD/2; + clktmp := not clktmp; + Clk <= clktmp; + end process CLOCK1; + + CLOCK2 : process -- generate clock signal for design + variable clktmp : std_logic := '0'; + begin + wait for PERIOD2/2; + clktmp := not clktmp; + Clk2 <= clktmp; + end process CLOCK2; + + -- PROC + RESET : process + begin + Rst_n <= '0'; -- Reset the testsystem + wait for 6*PERIOD; -- Wait + Rst_n <= '1'; -- de-assert reset + wait; + end process RESET; + + + +end rtl; + +------------------------------------------------------------------------------- Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_asynch_if_fpga.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_asynch_if_fpga.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_asynch_if_fpga.vhd (revision 18) @@ -0,0 +1,189 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "asynch_if_s" +-- Project : +------------------------------------------------------------------------------- +-- File : tb_asynch_if_fpga.vhd +-- Author : +-- Created : 04.01.2006 +-- Last update: 04.01.2006 +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2006 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 04.01.2006 1.0 AK Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +--use work.txt_util.all; +------------------------------------------------------------------------------- + +entity tb_asynch_if_fpga is + port ( + clk : in std_logic; + clk2 : in std_logic; + rst_n : in std_logic; + error_out : out std_logic + ); +end tb_asynch_if_fpga; + +------------------------------------------------------------------------------- + +architecture rtl of tb_asynch_if_fpga is + + component asynch_if_rx + generic ( + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + a_we_in : in std_logic; + ack_out : out std_logic; + we_out : out std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + full_in : in std_logic); + end component; + + constant data_width_g : integer := 32; + + -- component ports + signal ack_from_rx : std_logic; + signal we_from_rx : std_logic; + signal data_from_rx : std_logic_vector(data_width_g-1 downto 0); + signal full_to_rx : std_logic; + + -- clock and reset + component asynch_if_tx + generic ( + data_width_g : integer); + port ( + clk : in std_logic; + rst_n : in std_logic; + we_in : in std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + full_out : out std_logic; + a_we_out : out std_logic; + ack_in : in std_logic + ); + end component; + + signal we_to_tx : std_logic; + signal data_to_tx : std_logic_vector(data_width_g-1 downto 0); + signal data_from_tx : std_logic_vector(data_width_g-1 downto 0); + signal full_from_tx : std_logic; + signal a_we_from_tx : std_logic; + + signal cnt_tx_data_r : std_logic_vector(data_width_g-1 downto 0); + signal cnt_rx_data_r : std_logic_vector(data_width_g-1 downto 0); + signal rx_full_cnt_r : integer; + signal tx_we_cnt_r : integer; + + constant full_after_we_c : integer := 3; -- after n data issue full + constant full_length_c : integer := 10; -- cc full is asserted + constant time_before_we_c : integer := 0; -- delay after sending + constant start_value_c : integer := 3; + +begin -- rtl + + -- component instantiation + DUT : asynch_if_rx + generic map ( + data_width_g => data_width_g) + port map ( + clk => clk, + rst_n => rst_n, + a_we_in => a_we_from_tx, + ack_out => ack_from_rx, + data_in => data_from_tx, + data_out => data_from_rx, + we_out => we_from_rx, + full_in => full_to_rx + ); + + asynch_if_tx_1 : asynch_if_tx + generic map ( + data_width_g => data_width_g) + port map ( + clk => clk2, + rst_n => rst_n, + we_in => we_to_tx, + data_in => data_to_tx, + data_out => data_from_tx, + full_out => full_from_tx, + a_we_out => a_we_from_tx, + ack_in => ack_from_rx + ); + + + -- receiving, use clk + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + cnt_rx_data_r <= conv_std_logic_vector(start_value_c, data_width_g); + full_to_rx <= '0'; + rx_full_cnt_r <= 0; + error_out <= '0'; + + elsif clk'event and clk = '1' then -- rising clock edge + if we_from_rx = '1' and full_to_rx = '0' then + if cnt_rx_data_r /= data_from_rx then + error_out <= '1'; + else + error_out <= '0'; + end if; +-- assert cnt_rx_data_r = data_from_rx report "Error: rx data wrong wait: " & +-- str(conv_integer(cnt_rx_data_r)) & "got: " & +-- str(conv_integer(data_from_rx)) +-- severity error; + cnt_rx_data_r <= cnt_rx_data_r+1; + rx_full_cnt_r <= rx_full_cnt_r + 1; + end if; + + if rx_full_cnt_r > full_after_we_c + full_after_we_c -1 then + full_to_rx <= '0'; + rx_full_cnt_r <= 0; + elsif rx_full_cnt_r > full_after_we_c-1 then + full_to_rx <= '1'; + rx_full_cnt_r <= rx_full_cnt_r+1; + end if; + + end if; + + end process; + + -- transmit, use different clock. + tx : process (clk2, rst_n) + begin -- process tx + if rst_n = '0' then -- asynchronous reset (active low) + tx_we_cnt_r <= 0; + data_to_tx <= conv_std_logic_vector(start_value_c, data_width_g); + cnt_tx_data_r <= conv_std_logic_vector(start_value_c, data_width_g); + we_to_tx <= '0'; + + elsif clk2'event and clk2 = '1' then -- rising clock edge + if tx_we_cnt_r > 0 then + tx_we_cnt_r <= tx_we_cnt_r-1; + we_to_tx <= '0'; + end if; + if full_from_tx = '0' then + if tx_we_cnt_r = 0 then + we_to_tx <= '1'; + data_to_tx <= cnt_tx_data_r; + cnt_tx_data_r <= cnt_tx_data_r+1; + tx_we_cnt_r <= time_before_we_c; + end if; + end if; + end if; + end process tx; + + +end rtl; + +------------------------------------------------------------------------------- Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_aif_top.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_aif_top.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_aif_top.vhd (revision 18) @@ -0,0 +1,196 @@ +------------------------------------------------------------------------------- +-- Title : Testbench for design "asynch_if_s" +-- Project : +------------------------------------------------------------------------------- +-- File : tb_asynch_if_send.vhd +-- Author : +-- Created : 04.01.2006 +-- Last update: 02.03.2006 +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2006 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 04.01.2006 1.0 AK Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use work.txt_util.all; +------------------------------------------------------------------------------- + +entity tb_aif_top is + +end tb_aif_top; + +------------------------------------------------------------------------------- + +architecture rtl of tb_aif_top is + + constant data_width_g : integer := 32; + + -- component ports + signal clk : std_logic; + signal rst_n : std_logic; + + -- clock and reset + constant Period : time := 10 ns; + constant Period2 : time := 100 ns; + + component aif_read_top + generic ( + data_width_g : integer); + port ( + tx_clk : in std_logic; + tx_rst_n : in std_logic; + tx_data_in : in std_logic_vector(data_width_g-1 downto 0); + tx_empty_in : in std_logic; + tx_re_out : out std_logic; + rx_clk : in std_logic; + rx_rst_n : in std_logic; + rx_empty_out : out std_logic; + rx_re_in : in std_logic; + rx_data_out : out std_logic_vector(data_width_g-1 downto 0)); + end component; + + signal tx_data_to : std_logic_vector(data_width_g-1 downto 0); + signal tx_empty_to : std_logic; + signal tx_re_from : std_logic; + signal rx_empty_from : std_logic; + signal rx_re_to : std_logic; + signal rx_data_from : std_logic_vector(data_width_g-1 downto 0); + + signal clk2 : std_logic; + constant clk_scaler : integer := 1; + constant clk2_scaler : integer := 1; + + signal cnt_tx_data_r : std_logic_vector(data_width_g-1 downto 0); + signal cnt_rx_data_r : std_logic_vector(data_width_g-1 downto 0); + signal rx_full_cnt_r : integer; + signal tx_we_cnt_r : integer; + + constant full_after_we_c : integer := 3; -- after n data issue full + constant full_length_c : integer := 10; -- cc full is asserted + constant time_before_we_c : integer := 10; -- delay after sending + constant start_value_c : integer := 3; + +begin -- rtl + + + aif_read_top_1 : aif_read_top + generic map ( + data_width_g => data_width_g) + port map ( + tx_clk => clk2, + tx_rst_n => rst_n, + tx_data_in => tx_data_to, + tx_empty_in => tx_empty_to, + tx_re_out => tx_re_from, + rx_clk => clk, + rx_rst_n => rst_n, + rx_empty_out => rx_empty_from, + rx_re_in => rx_re_to, + rx_data_out => rx_data_from + ); + + + -- use clk + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + cnt_rx_data_r <= conv_std_logic_vector(start_value_c, data_width_g); + rx_re_to <= '0'; + rx_full_cnt_r <= 0; + + elsif clk'event and clk = '1' then -- rising clock edge + if rx_empty_from = '0' and rx_re_to = '1' then + cnt_rx_data_r <= cnt_rx_data_r+1; + assert cnt_rx_data_r = rx_data_from report "Error: rx data wrong wait: " & + str(conv_integer(cnt_rx_data_r)) & "got: " & + str(conv_integer(rx_data_from)) + severity error; + + end if; + if rx_empty_from = '0' then + + if rx_full_cnt_r > full_after_we_c + full_after_we_c -1 then + rx_re_to <= '1'; + rx_full_cnt_r <= 0; + elsif rx_full_cnt_r > full_after_we_c-1 then + rx_re_to <= '0'; + rx_full_cnt_r <= rx_full_cnt_r+1; + else + rx_re_to <= '1'; + rx_full_cnt_r <= rx_full_cnt_r+1; + end if; + + else + rx_re_to <= '0'; + end if; + -- rx re to always '1', resemble n2h2 behavior + -- rx_re_to <= '1'; + end if; + + end process; + + + -- transmit, use different clock. + tx : process (clk2, rst_n) + begin -- process tx + if rst_n = '0' then -- asynchronous reset (active low) + tx_we_cnt_r <= 0; + tx_data_to <= conv_std_logic_vector(start_value_c, data_width_g); + cnt_tx_data_r <= conv_std_logic_vector(start_value_c+1, data_width_g); + tx_empty_to <= '1'; + + elsif clk2'event and clk2 = '1' then -- rising clock edge + if tx_we_cnt_r > 0 then + tx_we_cnt_r <= tx_we_cnt_r-1; + tx_empty_to <= '1'; + else + tx_empty_to <= '0'; + if tx_re_from = '1' then + tx_data_to <= cnt_tx_data_r; + cnt_tx_data_r <= cnt_tx_data_r+1; + tx_we_cnt_r <= time_before_we_c; + end if; + + end if; + end if; + end process tx; + + -- clock generation + -- PROC + CLOCK1 : process -- generate clock signal for design + variable clktmp : std_logic := '0'; + begin + wait for PERIOD/2; + clktmp := not clktmp; + Clk <= clktmp; + end process CLOCK1; + + CLOCK2 : process -- generate clock signal for design + variable clktmp : std_logic := '0'; + begin + wait for PERIOD2/2; + clktmp := not clktmp; + Clk2 <= clktmp; + end process CLOCK2; + + -- PROC + RESET : process + begin + Rst_n <= '0'; -- Reset the testsystem + wait for 6*PERIOD; -- Wait + Rst_n <= '1'; -- de-assert reset + wait; + end process RESET; + + + +end rtl; + +------------------------------------------------------------------------------- Index: trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_asynch_if.vhd =================================================================== --- trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_asynch_if.vhd (nonexistent) +++ trunk/TUT/ip.hwp.storage/fifos/synchronizer/Tb/tb_asynch_if.vhd (revision 18) @@ -0,0 +1,214 @@ + +------------------------------------------------------------------------------- +-- Title : Testbench for design "asynch_if_s" +-- Project : +------------------------------------------------------------------------------- +-- File : tb_asynch_if_send.vhd +-- Author : +-- Created : 04.01.2006 +-- Last update: 05.01.2006 +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2006 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 04.01.2006 1.0 AK Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use work.txt_util.all; +------------------------------------------------------------------------------- + +entity tb_asynch_if is + +end tb_asynch_if; + +------------------------------------------------------------------------------- + +architecture rtl of tb_asynch_if is + + component asynch_if_rx + generic ( + data_width_g : integer := 32 + ); + port ( + clk : in std_logic; + rst_n : in std_logic; + a_we_in : in std_logic; + ack_out : out std_logic; + we_out : out std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + full_in : in std_logic); + end component; + + constant data_width_g : integer := 32; + + -- component ports + signal clk : std_logic; + signal rst_n : std_logic; + signal ack_from_rx : std_logic; + signal we_from_rx : std_logic; + signal data_from_rx : std_logic_vector(data_width_g-1 downto 0); + signal full_to_rx : std_logic; + + -- clock and reset + constant Period : time := 10 ns; + + component asynch_if_tx + generic ( + data_width_g : integer); + port ( + clk : in std_logic; + rst_n : in std_logic; + we_in : in std_logic; + data_in : in std_logic_vector(data_width_g-1 downto 0); + data_out : out std_logic_vector(data_width_g-1 downto 0); + full_out : out std_logic; + a_we_out : out std_logic; + ack_in : in std_logic + ); + end component; + + signal we_to_tx : std_logic; + signal data_to_tx : std_logic_vector(data_width_g-1 downto 0); + signal data_from_tx : std_logic_vector(data_width_g-1 downto 0); + signal full_from_tx : std_logic; + signal a_we_from_tx : std_logic; + + signal clk2 : std_logic; + constant clk2_scaler : integer := 3; + + signal cnt_tx_data_r : std_logic_vector(data_width_g-1 downto 0); + signal cnt_rx_data_r : std_logic_vector(data_width_g-1 downto 0); + signal rx_full_cnt_r : integer; + signal tx_we_cnt_r : integer; + + constant full_after_we_c : integer := 3; -- after n data issue full + constant full_length_c : integer := 10; -- cc full is asserted + constant time_before_we_c : integer := 0; -- delay after sending + constant start_value_c : integer := 3; + +begin -- rtl + + -- component instantiation + DUT : asynch_if_rx + generic map ( + data_width_g => data_width_g) + port map ( + clk => clk, + rst_n => rst_n, + a_we_in => a_we_from_tx, + ack_out => ack_from_rx, + data_in => data_from_tx, + data_out => data_from_rx, + we_out => we_from_rx, + full_in => full_to_rx + ); + + asynch_if_tx_1 : asynch_if_tx + generic map ( + data_width_g => data_width_g) + port map ( + clk => clk2, + rst_n => rst_n, + we_in => we_to_tx, + data_in => data_to_tx, + data_out => data_from_tx, + full_out => full_from_tx, + a_we_out => a_we_from_tx, + ack_in => ack_from_rx + ); + + + -- receiving, use clk + process (clk, rst_n) + begin -- process + if rst_n = '0' then -- asynchronous reset (active low) + cnt_rx_data_r <= conv_std_logic_vector(start_value_c, data_width_g); + full_to_rx <= '0'; + rx_full_cnt_r <= 0; + + elsif clk'event and clk = '1' then -- rising clock edge + if we_from_rx = '1' and full_to_rx = '0' then + assert cnt_rx_data_r = data_from_rx report "Error: rx data wrong wait: " & + str(conv_integer(cnt_rx_data_r)) & "got: " & + str(conv_integer(data_from_rx)) + severity error; + cnt_rx_data_r <= cnt_rx_data_r+1; + rx_full_cnt_r <= rx_full_cnt_r + 1; + end if; + + if rx_full_cnt_r > full_after_we_c + full_after_we_c -1 then + full_to_rx <= '0'; + rx_full_cnt_r <= 0; + elsif rx_full_cnt_r > full_after_we_c-1 then + full_to_rx <= '1'; + rx_full_cnt_r <= rx_full_cnt_r+1; + end if; + + end if; + + end process; + + -- transmit, use different clock. + tx : process (clk2, rst_n) + begin -- process tx + if rst_n = '0' then -- asynchronous reset (active low) + tx_we_cnt_r <= 0; + data_to_tx <= conv_std_logic_vector(start_value_c, data_width_g); + cnt_tx_data_r <= conv_std_logic_vector(start_value_c, data_width_g); + we_to_tx <= '0'; + + elsif clk2'event and clk2 = '1' then -- rising clock edge + if tx_we_cnt_r > 0 then + tx_we_cnt_r <= tx_we_cnt_r-1; + we_to_tx <= '0'; + end if; + if full_from_tx = '0' then + if tx_we_cnt_r = 0 then + we_to_tx <= '1'; + data_to_tx <= cnt_tx_data_r; + cnt_tx_data_r <= cnt_tx_data_r+1; + tx_we_cnt_r <= time_before_we_c; + end if; + end if; + end if; + end process tx; + + -- clock generation + -- PROC + CLOCK1 : process -- generate clock signal for design + variable clktmp : std_logic := '0'; + begin + wait for PERIOD/2; + clktmp := not clktmp; + Clk <= clktmp; + end process CLOCK1; + + CLOCK2 : process -- generate clock signal for design + variable clktmp : std_logic := '0'; + begin + wait for PERIOD/clk2_scaler; + clktmp := not clktmp; + Clk2 <= clktmp; + end process CLOCK2; + + -- PROC + RESET : process + begin + Rst_n <= '0'; -- Reset the testsystem + wait for 6*PERIOD; -- Wait + Rst_n <= '1'; -- de-assert reset + wait; + end process RESET; + + + +end rtl; + +-------------------------------------------------------------------------------

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