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URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

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Rev 44 → Rev 45

/trunk/TUT/ip.hwp.interface/switch_pkt_codec_mk2/1.0/vhd/switch_pkt_codec_mk2.vhd
0,0 → 1,103
-------------------------------------------------------------------------------
-- Title : Switch reader for ase_mesh1
-- Project :
-------------------------------------------------------------------------------
-- File : switch_pkt_codec_mk2.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-11-09
-- Last update: 2011-11-09
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-11-09 1.0 lehton87 Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity switch_pkt_codec_mk2 is
 
generic (
target_id_g : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
cmd_in : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(31 downto 0);
stall_out : out std_logic;
cmd_out : out std_logic_vector(1 downto 0);
data_out : out std_logic_vector(31 downto 0);
stall_in : in std_logic;
switch_in : in std_logic);
 
end switch_pkt_codec_mk2;
 
 
architecture rtl of switch_pkt_codec_mk2 is
 
signal switch1_r : std_logic;
signal switch2_r : std_logic;
signal switch3_r : std_logic;
 
type fsm_type is (idle, cmd, data);
signal state_r : fsm_type;
begin -- rtl
stall_out <= '0';
 
 
main_p : process (clk, rst_n)
begin -- process main_p
if rst_n = '0' then -- asynchronous reset (active low)
 
switch1_r <= '0';
switch2_r <= '0';
state_r <= idle;
elsif clk'event and clk = '1' then -- rising clock edge
 
switch1_r <= switch_in;
switch2_r <= switch1_r;
switch3_r <= switch2_r;
case state_r is
when idle =>
if stall_in = '0' then
cmd_out <= "00";
data_out <= (others => '0');
if switch3_r /= switch2_r then
state_r <= cmd;
end if;
end if;
 
when cmd =>
if stall_in = '0' then
data_out <= std_logic_vector(to_unsigned(target_id_g, 32));
cmd_out <= "01";
state_r <= data;
end if;
 
when data =>
if stall_in = '0' then
data_out <= std_logic_vector(to_unsigned(42, 32));
cmd_out <= "10";
state_r <= idle;
end if;
when others => null;
end case;
end if;
end process main_p;
 
end rtl;
/trunk/TUT/ip.hwp.interface/switch_pkt_codec_mk2/1.0/switch_pkt_codec_mk2.1.0.xml
0,0 → 1,368
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 19:50:42 ke marras 9 2011-->
<spirit:component>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.interface</spirit:library>
<spirit:name>switch_pkt_codec_mk2</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clock</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pkt_codec_mk2</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2.absDef" spirit:version="1.0"/>
<spirit:mirroredMaster/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_IN</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall_out</spirit:name>
<spirit:vector>
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<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_OUT</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>data_in</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_OUT</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_in</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_OUT</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_IN</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>data_out</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_IN</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd_out</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>reset</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RESETn</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>rst_n</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>switch</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.0"/>
<spirit:mirroredMaster/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>switch_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
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</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>cmd_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>cmd_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>data_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>data_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>rst_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>stall_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>stall_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>switch_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter spirit:dataType="integer" spirit:usageType="typed">
<spirit:name>target_id_g</spirit:name>
<spirit:description>target_id in the noc</spirit:description>
<spirit:value>0</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>HDLsourced</spirit:name>
<spirit:file>
<spirit:name>vhd/switch_pkt_codec_mk2.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:buildCommand>
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
</spirit:buildCommand>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>IP</kactus2:kts_productHier>
<kactus2:kts_implementation>HW</kactus2:kts_implementation>
<kactus2:kts_firmness>Fixed</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>
/trunk/TUT/ip.hwp.interface/led_pkt_codec_mk2/1.0/vhd/led_pkt_codec_mk2.vhd
0,0 → 1,76
-------------------------------------------------------------------------------
-- Title : Led blinker for ase_mesh1
-- Project :
-------------------------------------------------------------------------------
-- File : led_pkt_codec_mk2.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-11-09
-- Last update: 2011-11-09
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-11-09 1.0 lehton87 Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity led_pkt_codec_mk2 is
port (
clk : in std_logic;
rst_n : in std_logic;
cmd_in : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(31 downto 0);
stall_out : out std_logic;
cmd_out : out std_logic_vector(1 downto 0);
data_out : out std_logic_vector(31 downto 0);
stall_in : in std_logic;
led_out : out std_logic);
 
end led_pkt_codec_mk2;
 
 
architecture rtl of led_pkt_codec_mk2 is
 
signal led_r : std_logic;
begin -- rtl
 
data_out <= (others => '0');
cmd_out <= (others => '0');
stall_out <= '0';
led_out <= led_r;
 
main_p : process (clk, rst_n)
begin -- process main_p
if rst_n = '0' then -- asynchronous reset (active low)
 
led_r <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
 
if cmd_in = "00" then
-- no data coming in
elsif cmd_in = "01" then
-- address coming in
elsif cmd_in = "10" then
-- data coming in
led_r <= not led_r;
else
-- not defined
end if;
end if;
end process main_p;
 
 
end rtl;
/trunk/TUT/ip.hwp.interface/led_pkt_codec_mk2/1.0/led_pkt_codec_mk2.1.0.xml
0,0 → 1,358
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 19:49:44 ke marras 9 2011-->
<spirit:component>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.interface</spirit:library>
<spirit:name>led_pkt_codec_mk2</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>led</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>led_out</spirit:name>
<spirit:vector>
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</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
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<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2.absDef" spirit:version="1.0"/>
<spirit:mirroredMaster/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_IN</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
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<spirit:right>0</spirit:right>
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</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_OUT</spirit:name>
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<spirit:physicalPort>
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<spirit:portMap>
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<spirit:physicalPort>
<spirit:name>cmd_in</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_OUT</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall_in</spirit:name>
<spirit:vector>
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<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
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<spirit:name>DATA_IN</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
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<spirit:physicalPort>
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<spirit:right>0</spirit:right>
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<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>reset</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RESETn</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>rst_n</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>cmd_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>cmd_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>data_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>data_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic_vector</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>led_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>rst_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>stall_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>stall_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>HDLsources</spirit:name>
<spirit:file>
<spirit:name>vhd/led_pkt_codec_mk2.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:buildCommand>
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
</spirit:buildCommand>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Inverts led for evey data word received.</spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>IP</kactus2:kts_productHier>
<kactus2:kts_implementation>HW</kactus2:kts_implementation>
<kactus2:kts_firmness>Fixed</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>
/trunk/TUT/soc/led_ase_mesh1_example/1.0/led_ase_mesh1_example.1.0.xml
0,0 → 1,251
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 19:50:55 ke marras 9 2011-->
<spirit:component>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
<spirit:name>led_ase_mesh1_example</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk_CLK</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>led</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>led_gpio_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>led_1</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>led_1_gpio_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>reset</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RESETn</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset_RESETn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>switch</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.0"/>
<spirit:mirroredMaster/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>switch_gpio_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>switch_1</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="gpio_1bit.absDef" spirit:version="1.0"/>
<spirit:mirroredMaster/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gpio_out</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>switch_1_gpio_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>structural</spirit:name>
<spirit:envIdentifier></spirit:envIdentifier>
<spirit:hierarchyRef spirit:vendor="TUT" spirit:library="soc" spirit:name="led_ase_mesh1_example.designcfg" spirit:version="1.0"/>
<spirit:vendorExtensions>
<kactus2:topLevelViewRef>rtl</kactus2:topLevelViewRef>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>VHDL::</spirit:envIdentifier>
<spirit:language spirit:strict="false">vhdl</spirit:language>
<spirit:modelName>led_ase_mesh1_example(top_level)</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>vhdlSource</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk_CLK</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>led_1_gpio_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>led_gpio_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>reset_RESETn</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>switch_1_gpio_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>switch_gpio_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName spirit:constrained="false">std_logic</spirit:typeName>
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef></spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>vhdlSource</spirit:name>
<spirit:group>sourceFiles</spirit:group>
<spirit:file>
<spirit:name>led_ase_mesh1_example.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">true</spirit:isIncludeFile>
<spirit:logicalName spirit:default="false">soc</spirit:logicalName>
<spirit:buildCommand>
<spirit:command>vcom</spirit:command>
<spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
<spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
</spirit:buildCommand>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>IP</kactus2:kts_productHier>
<kactus2:kts_implementation>HW</kactus2:kts_implementation>
<kactus2:kts_firmness>Fixed</kactus2:kts_firmness>
</kactus2:kts_attributes>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>
/trunk/TUT/soc/led_ase_mesh1_example/1.0/led_ase_mesh1_example.design.1.0.xml
0,0 → 1,391
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 19:14:40 ke marras 9 2011-->
<spirit:design>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
<spirit:name>led_ase_mesh1_example.design</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>switch_pkt_codec_mk2_1</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="switch_pkt_codec_mk2" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="target_id_g">0</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<kactus2:position x="770" y="60"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="clock">
<kactus2:position x="-80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="pkt_codec_mk2">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="reset">
<kactus2:position x="-80" y="70"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="switch">
<kactus2:position x="80" y="70"/>
</kactus2:portPosition>
</kactus2:portPositions>
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>switch_pkt_codec_mk2_2</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="switch_pkt_codec_mk2" spirit:version="1.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="target_id_g">1</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<kactus2:position x="770" y="180"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="clock">
<kactus2:position x="-80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="pkt_codec_mk2">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="reset">
<kactus2:position x="-80" y="70"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="switch">
<kactus2:position x="80" y="70"/>
</kactus2:portPosition>
</kactus2:portPositions>
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>ase_mesh1_top4_1</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="ase_mesh1_top4" spirit:version="1.0"/>
<spirit:configurableElementValues/>
<spirit:vendorExtensions>
<kactus2:position x="510" y="60"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="clock">
<kactus2:position x="-80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="port0">
<kactus2:position x="-80" y="120"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="port1">
<kactus2:position x="-80" y="90"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="port2">
<kactus2:position x="80" y="80"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="port3">
<kactus2:position x="80" y="110"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="reset">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
</kactus2:portPositions>
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>led_pkt_codec_mk2_1</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="led_pkt_codec_mk2" spirit:version="1.0"/>
<spirit:configurableElementValues/>
<spirit:vendorExtensions>
<kactus2:position x="250" y="60"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="clk">
<kactus2:position x="-80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="led">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="pkt_codec_mk2">
<kactus2:position x="-80" y="80"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="reset">
<kactus2:position x="80" y="70"/>
</kactus2:portPosition>
</kactus2:portPositions>
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>led_pkt_codec_mk2_2</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="led_pkt_codec_mk2" spirit:version="1.0"/>
<spirit:configurableElementValues/>
<spirit:vendorExtensions>
<kactus2:position x="250" y="190"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="clk">
<kactus2:position x="-80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="led">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="pkt_codec_mk2">
<kactus2:position x="-80" y="70"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="reset">
<kactus2:position x="80" y="70"/>
</kactus2:portPosition>
</kactus2:portPositions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
<spirit:interconnections>
<spirit:interconnection>
<spirit:name>switch_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port3</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="switch_pkt_codec_mk2_2" spirit:busRef="pkt_codec_mk2"/>
<spirit:activeInterface spirit:componentRef="ase_mesh1_top4_1" spirit:busRef="port3"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>switch_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port2</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="switch_pkt_codec_mk2_1" spirit:busRef="pkt_codec_mk2"/>
<spirit:activeInterface spirit:componentRef="ase_mesh1_top4_1" spirit:busRef="port2"/>
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<spirit:interconnection>
<spirit:name>led_pkt_codec_mk2_2_pkt_codec_mk2_to_ase_mesh1_top4_1_port1</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="led_pkt_codec_mk2_2" spirit:busRef="pkt_codec_mk2"/>
<spirit:activeInterface spirit:componentRef="ase_mesh1_top4_1" spirit:busRef="port1"/>
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<spirit:interconnection>
<spirit:name>led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0</spirit:name>
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<spirit:description></spirit:description>
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<spirit:hierConnection spirit:interfaceRef="clk">
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<spirit:hierConnection spirit:interfaceRef="reset">
<spirit:interface spirit:componentRef="led_pkt_codec_mk2_1" spirit:busRef="reset"/>
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<kactus2:position x="60" y="130"/>
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<spirit:hierConnection spirit:interfaceRef="clk">
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<spirit:hierConnection spirit:interfaceRef="clk">
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<spirit:vendorExtensions>
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<spirit:hierConnection spirit:interfaceRef="clk">
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<spirit:vendorExtensions>
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<spirit:hierConnection spirit:interfaceRef="reset">
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<spirit:vendorExtensions>
<kactus2:columnLayout>
<kactus2:column name="IO" contentType="0" allowedItems="1"/>
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<kactus2:column name="Components" contentType="2" allowedItems="2"/>
<kactus2:column name="IO" contentType="0" allowedItems="1"/>
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<kactus2:routes>
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<kactus2:route kactus2:connRef="led_pkt_codec_mk2_1_pkt_codec_mk2_to_ase_mesh1_top4_1_port0">
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</spirit:vendorExtensions>
</spirit:design>
/trunk/TUT/soc/led_ase_mesh1_example/1.0/led_ase_mesh1_example.designcfg.1.0.xml
0,0 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 19:14:40 ke marras 9 2011-->
<spirit:designConfiguration>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
<spirit:name>led_ase_mesh1_example.designcfg</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:designRef spirit:vendor="TUT" spirit:library="soc" spirit:name="led_ase_mesh1_example.design" spirit:version="1.0"/>
</spirit:designConfiguration>
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/pkt_codec_mk2.1.0.xml
0,0 → 1,10
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 18:01:52 ke marras 9 2011-->
<spirit:busDefinition>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.communication</spirit:library>
<spirit:name>pkt_codec_mk2</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:directConnection>true</spirit:directConnection>
<spirit:isAddressable>true</spirit:isAddressable>
</spirit:busDefinition>
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_gen.vhd
0,0 → 1,179
-------------------------------------------------------------------------------
-- Title : Address generator for pkt_codec
-- Project :
-------------------------------------------------------------------------------
-- File : addr_gen.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-10-12
-- Last update: 2011-10-25
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-- Handles address flit repeating when data comes slowly from IP and
-- prevents sending only address flits without at least on data flit.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-10-12 1.0 lehton87 Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
 
entity addr_gen is
generic (
cmd_width_g : positive;
data_width_g : positive;
addr_flit_en_g : natural);
 
port (
clk : in std_logic;
rst_n : in std_logic;
-- from IP side
ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0);
ip_data_in : in std_logic_vector(data_width_g-1 downto 0);
ip_stall_out : out std_logic;
orig_addr_in : in std_logic_vector(data_width_g-1 downto 0);
-- to NET
net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0);
net_data_out : out std_logic_vector(data_width_g-1 downto 0);
net_stall_in : in std_logic);
 
end addr_gen;
 
architecture rtl of addr_gen is
 
signal cmd_r : std_logic_vector(cmd_width_g-1 downto 0);
signal data_r : std_logic_vector(data_width_g-1 downto 0);
signal addr_r : std_logic_vector(data_width_g-1 downto 0);
signal stall_r : std_logic;
signal first_data_r : std_logic;
 
type state_type is (idle, addr, orig, data);
signal state_r : state_type;
begin -- rtl
 
ip_stall_out <= net_stall_in or stall_r;
 
fsm_p : process (clk, rst_n)
begin -- process fsm_p
if rst_n = '0' then -- asynchronous reset (active low)
state_r <= idle;
cmd_r <= (others => '0');
data_r <= (others => '0');
addr_r <= (others => '0');
stall_r <= '0';
first_data_r <= '0';
net_cmd_out <= (others => '0');
net_data_out <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
 
-- default
if net_stall_in = '0' then
stall_r <= '0';
end if;
 
case state_r is
-----------------------------------------------------------------------
-- IDLE
-----------------------------------------------------------------------
when idle =>
if net_stall_in = '0' then
if ip_cmd_in = "00" then
net_cmd_out <= "00";
first_data_r <= '0';
elsif ip_cmd_in = "01" then
net_cmd_out <= "00";
first_data_r <= '1';
addr_r <= ip_data_in;
state_r <= addr;
else
first_data_r <= '1';
data_r <= ip_data_in;
net_cmd_out <= "01";
net_data_out <= addr_r;
state_r <= data;
end if;
end if;
 
---------------------------------------------------------------------
-- ADDR
---------------------------------------------------------------------
when addr =>
if net_stall_in = '0' then
if ip_cmd_in = "00" then
state_r <= idle;
net_cmd_out <= "00";
first_data_r <= '0';
elsif ip_cmd_in = "01" then
addr_r <= ip_data_in;
state_r <= addr;
net_cmd_out <= "00";
first_data_r <= '1';
else
net_cmd_out <= "01";
net_data_out <= addr_r;
data_r <= ip_data_in;
state_r <= data;
end if;
end if;
 
---------------------------------------------------------------------
-- DATA
---------------------------------------------------------------------
when data =>
if net_stall_in = '0' then
if ip_cmd_in = "00" then
if first_data_r = '1' and addr_flit_en_g = 1 then
stall_r <= '1';
net_cmd_out <= "10";
net_data_out <= orig_addr_in;
first_data_r <= '0';
else
net_data_out <= data_r;
net_cmd_out <= "10";
state_r <= idle;
end if;
elsif ip_cmd_in = "01" then
if first_data_r = '1' and addr_flit_en_g = 1 then
stall_r <= '1';
net_cmd_out <= "10";
net_data_out <= orig_addr_in;
first_data_r <= '0';
else
net_data_out <= data_r;
net_cmd_out <= "10";
addr_r <= ip_data_in;
state_r <= addr;
first_data_r <= '1'; -- ase 25-10-2011
end if;
else
if first_data_r = '1' and addr_flit_en_g = 1 then
stall_r <= '1';
net_cmd_out <= "10";
net_data_out <= orig_addr_in;
first_data_r <= '0';
else
net_data_out <= data_r;
net_cmd_out <= "10";
data_r <= ip_data_in;
end if;
end if;
end if;
when others => null;
end case;
 
end if;
end process fsm_p;
 
end rtl;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/log2_pkg.vhd
0,0 → 1,62
-------------------------------------------------------------------------------
-- Title : log2_ceil function
-- Project :
-------------------------------------------------------------------------------
-- File : log2_pkg.vhdl
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2010-06-16
-- Last update: 2011-10-07
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-16 1.0 ase Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
 
-------------------------------------------------------------------------------
-- PACKAGE DECLARATION
-------------------------------------------------------------------------------
 
package log2_pkg is
 
-----------------------------------------------------------------------------
-- HELPER FUNCTIONS
-----------------------------------------------------------------------------
 
-- purpose: Return ceiling log 2 of n
function log2_ceil (
constant n : positive)
return positive;
 
end package log2_pkg;
 
 
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
 
package body log2_pkg is
 
-- purpose: Return ceiling log 2 of n
function log2_ceil (
constant n : positive)
return positive is
variable retval : positive := 1;
begin -- function log2_ceil
while 2**retval < n loop
retval := retval + 1;
end loop;
return retval;
end function log2_ceil;
 
end package body log2_pkg;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/pkt_codec_mk2.vhd
0,0 → 1,215
-------------------------------------------------------------------------------
-- Title : Packet Codec MK2
-- Project :
-------------------------------------------------------------------------------
-- File : pkt_codec_mk2.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-01-12
-- Last update: 2011-10-24
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- Generics
--
-- address_mode_g 0 : IP gives raw network address
-- address_mode_g 1 : IP gives integer ID numbers as target address
-- address_mode_g 2 : IP gives memory mapped addresses
--
-- clock_mode_g 0 : Use one clock for both ip and the net
-- (clk_ip must be same as clk_net)
-- clock_mode_g 1 : Use two asynchronous clocks
--
-- noc_type_g 0 : ase_noc
-- noc_type_g 1 : ase_mesh1
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-12 1.0 ase Created
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.ase_noc_pkg.all;
use work.ase_mesh1_pkg.all;
 
entity pkt_codec_mk2 is
generic (
my_id_g : natural;
data_width_g : positive;
cmd_width_g : positive;
agents_g : positive;
cols_g : positive;
rows_g : positive;
agent_ports_g : positive;
addr_flit_en_g : natural;
address_mode_g : natural;
clock_mode_g : natural;
rip_addr_g : natural;
noc_type_g : natural);
 
port (
clk_ip : in std_logic;
clk_net : in std_logic;
rst_n : in std_logic;
 
-- IP read interface
ip_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0);
ip_data_out : out std_logic_vector(data_width_g-1 downto 0);
ip_stall_in : in std_logic;
 
-- IP write interface
ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0);
ip_data_in : in std_logic_vector(data_width_g-1 downto 0);
ip_stall_out : out std_logic;
 
-- NoC write interface
net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0);
net_data_out : out std_logic_vector(data_width_g-1 downto 0);
net_stall_in : in std_logic;
 
-- NoC read interface
net_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0);
net_data_in : in std_logic_vector(data_width_g-1 downto 0);
net_stall_out : out std_logic
);
 
end entity pkt_codec_mk2;
 
 
 
architecture rtl of pkt_codec_mk2 is
 
-----------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------
 
-- from ip to net path
-- cdc -> at
signal net_cmd_from_cdc : std_logic_vector(cmd_width_g-1 downto 0);
signal net_data_from_cdc : std_logic_vector(data_width_g-1 downto 0);
signal net_stall_to_cdc : std_logic;
-- at -> ag
signal net_cmd_from_at : std_logic_vector(cmd_width_g-1 downto 0);
signal net_data_from_at : std_logic_vector(data_width_g-1 downto 0);
signal net_stall_to_at : std_logic;
signal orig_addr_from_at : std_logic_vector(data_width_g-1 downto 0);
 
-- from net to ip path
-- ar -> cdc
signal ip_cmd_from_ar : std_logic_vector(cmd_width_g-1 downto 0);
signal ip_data_from_ar : std_logic_vector(data_width_g-1 downto 0);
signal ip_stall_to_ar : std_logic;
 
-------------------------------------------------------------------------------
begin -- architecture rtl
-------------------------------------------------------------------------------
 
-----------------------------------------------------------------------------
-- CLOCK DOMAIN CROSSING
-----------------------------------------------------------------------------
 
cdc_1 : entity work.cdc
generic map (
cmd_width_g => cmd_width_g,
data_width_g => data_width_g,
clock_mode_g => clock_mode_g)
port map (
clk_ip => clk_ip,
clk_net => clk_net,
rst_n => rst_n,
ip_cmd_out => ip_cmd_out,
ip_data_out => ip_data_out,
ip_stall_in => ip_stall_in,
ip_cmd_in => ip_cmd_in,
ip_data_in => ip_data_in,
ip_stall_out => ip_stall_out,
net_cmd_out => net_cmd_from_cdc,
net_data_out => net_data_from_cdc,
net_stall_in => net_stall_to_cdc,
net_cmd_in => ip_cmd_from_ar,
net_data_in => ip_data_from_ar,
net_stall_out => ip_stall_to_ar);
 
-----------------------------------------------------------------------------
-- ADDRESS TRANSLATION (only from IP to NET)
-----------------------------------------------------------------------------
 
addr_translation_1 : entity work.addr_translation
generic map (
my_id_g => my_id_g,
cmd_width_g => cmd_width_g,
data_width_g => data_width_g,
address_mode_g => address_mode_g,
cols_g => cols_g,
rows_g => rows_g,
agents_g => agents_g,
agent_ports_g => agent_ports_g,
addr_flit_en_g => addr_flit_en_g,
noc_type_g => noc_type_g)
port map (
clk => clk_net,
rst_n => rst_n,
ip_cmd_in => net_cmd_from_cdc,
ip_data_in => net_data_from_cdc,
ip_stall_out => net_stall_to_cdc,
net_cmd_out => net_cmd_from_at,
net_data_out => net_data_from_at,
net_stall_in => net_stall_to_at,
orig_addr_out => orig_addr_from_at);
 
 
-----------------------------------------------------------------------------
-- ADDRESS GENERATOR (only from IP to NET)
-----------------------------------------------------------------------------
addr_gen_1 : entity work.addr_gen
generic map (
cmd_width_g => cmd_width_g,
data_width_g => data_width_g,
addr_flit_en_g => addr_flit_en_g)
port map (
clk => clk_net,
rst_n => rst_n,
ip_cmd_in => net_cmd_from_at,
ip_data_in => net_data_from_at,
ip_stall_out => net_stall_to_at,
orig_addr_in => orig_addr_from_at,
net_cmd_out => net_cmd_out,
net_data_out => net_data_out,
net_stall_in => net_stall_in
);
 
 
-----------------------------------------------------------------------------
-- ADDRESS RIPPER / REPLACER (only from NET to IP)
-----------------------------------------------------------------------------
addr_rip_1 : entity work.addr_rip
generic map (
cmd_width_g => cmd_width_g,
data_width_g => data_width_g,
addr_flit_en_g => addr_flit_en_g,
rip_addr_g => rip_addr_g)
port map (
clk => clk_net,
rst_n => rst_n,
net_cmd_in => net_cmd_in,
net_data_in => net_data_in,
net_stall_out => net_stall_out,
ip_cmd_out => ip_cmd_from_ar,
ip_data_out => ip_data_from_ar,
ip_stall_in => ip_stall_to_ar);
 
end architecture rtl;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_rip.vhd
0,0 → 1,118
-------------------------------------------------------------------------------
-- Title : Address flit ripper / replacer
-- Project :
-------------------------------------------------------------------------------
-- File : addr_rip.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-10-12
-- Last update: 2011-10-25
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- Rips the address flit when wanted or replaces the network address
-- with original address (or doesn't do a thing).
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-10-12 1.0 lehton87 Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
 
entity addr_rip is
generic (
cmd_width_g : positive;
data_width_g : positive;
addr_flit_en_g : natural;
rip_addr_g : natural);
 
port (
clk : in std_logic;
rst_n : in std_logic;
net_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0);
net_data_in : in std_logic_vector(data_width_g-1 downto 0);
net_stall_out : out std_logic;
ip_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0);
ip_data_out : out std_logic_vector(data_width_g-1 downto 0);
ip_stall_in : in std_logic);
 
end addr_rip;
 
 
architecture rtl of addr_rip is
 
signal was_addr_r : std_logic;
begin -- rtl
 
addr_check_p : process (clk, rst_n)
begin -- process addr_check_p
if rst_n = '0' then -- asynchronous reset (active low)
was_addr_r <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if net_cmd_in = "01" then
was_addr_r <= '1';
else
was_addr_r <= '0';
end if;
end if;
end process addr_check_p;
 
ip_data_out <= net_data_in;
net_stall_out <= ip_stall_in;
 
rip : if rip_addr_g = 1 generate
replace : if addr_flit_en_g = 1 generate
m1 : process (net_cmd_in, was_addr_r)
begin -- process m
if net_cmd_in = "01" then
ip_cmd_out <= "00";
elsif was_addr_r = '1' then
ip_cmd_out <= "01";
else
ip_cmd_out <= net_cmd_in;
end if;
end process m1;
end generate replace;
 
dont_replace : if addr_flit_en_g = 0 generate
m2: process (net_cmd_in)
begin -- process m2
if net_cmd_in = "01" then
ip_cmd_out <= "00";
else
ip_cmd_out <= net_cmd_in;
end if;
end process m2;
end generate dont_replace;
end generate rip;
 
dont_rip : if rip_addr_g = 0 generate
replace1 : if addr_flit_en_g = 1 generate
m3 : process (net_cmd_in, was_addr_r)
begin -- process m
if net_cmd_in = "01" then
ip_cmd_out <= "00";
elsif was_addr_r = '1' then
ip_cmd_out <= "01";
else
ip_cmd_out <= net_cmd_in;
end if;
end process m3;
end generate replace1;
 
dont_replace1 : if addr_flit_en_g = 0 generate
ip_cmd_out <= net_cmd_in;
end generate dont_replace1;
end generate dont_rip;
 
end rtl;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_mesh1_pkg.vhd
0,0 → 1,166
-------------------------------------------------------------------------------
-- Title : Functions for ase_mesh1 and wrappers using it
-- Project :
-------------------------------------------------------------------------------
-- File : ase_mesh1_pkg.vhdl
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2010-06-16
-- Last update: 2011-11-09
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-16 1.0 ase Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.log2_pkg.all;
 
-------------------------------------------------------------------------------
-- PACKAGE DECLARATION
-------------------------------------------------------------------------------
 
package ase_mesh1_pkg is
 
-----------------------------------------------------------------------------
-- HELPER FUCTIONS
-----------------------------------------------------------------------------
 
-- Returns target address (ase_mesh1 network address)
pure function ase_mesh1_address (
src_id : in integer; -- Source agent id number
dst_id : in integer; -- Destination agent id number
rows : in positive;
cols : in positive;
bus_width : in positive)
return std_logic_vector;
 
end package ase_mesh1_pkg;
 
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
 
package body ase_mesh1_pkg is
 
pure function ase_mesh1_address (
constant src_id : in integer; -- Source agent id number
constant dst_id : in integer; -- Destination agent id number
constant rows : in positive;
constant cols : in positive;
constant bus_width : in positive)
return std_logic_vector is
variable retval : std_logic_vector(bus_width-1 downto 0);
variable lr_bit : std_logic;
variable here_bit : std_logic;
variable first_dir : std_logic_vector(1 downto 0);
variable src_row : integer;
variable src_col : integer;
variable dst_row : integer;
variable dst_col : integer;
constant mesh1_row_width_c : positive := log2_ceil(rows - 1);
constant mesh1_col_width_c : positive := log2_ceil(cols - 1);
constant mesh1_port_width_c : positive :=
bus_width - mesh1_row_width_c - mesh1_col_width_c - 4;
variable dst_port : integer := 0;
begin
 
retval := (others => '0');
lr_bit := '0';
here_bit := '0';
first_dir := "00";
src_row := (src_id / cols);
src_col := src_id - (src_row * cols);
dst_row := (dst_id / cols);
dst_col := dst_id - (dst_row * cols);
 
-- if src_id = 7 and dst_id = 4 then
-- report "srow " & integer'image(src_row) & ", drow "
-- & integer'image(dst_row) & ", scol "
-- & integer'image(src_col) & ", dcol "
-- & integer'image(dst_col) & ", cols "
-- & integer'image(cols) & ", rows "
-- & integer'image(rows)
-- severity note;
-- end if;
 
retval(bus_width-1 downto bus_width-mesh1_port_width_c) :=
std_logic_vector(to_unsigned(dst_port, mesh1_port_width_c));
if src_row = dst_row then
if src_col = dst_col then
 
elsif src_col < dst_col then
first_dir := "01";
retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
:= std_logic_vector
(to_unsigned
((2**mesh1_col_width_c)-(dst_col-src_col), mesh1_col_width_c));
else
first_dir := "11";
retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
:= std_logic_vector
(to_unsigned
((2**mesh1_col_width_c)-(src_col-dst_col), mesh1_col_width_c));
end if;
elsif src_row < dst_row then
first_dir := "10";
retval(mesh1_row_width_c-1 downto 0) :=
std_logic_vector
(to_unsigned
((2**mesh1_row_width_c)-(dst_row-src_row), mesh1_row_width_c));
if src_col = dst_col then
here_bit := '1';
elsif src_col < dst_col then
retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
:= std_logic_vector
(to_unsigned
((2**mesh1_col_width_c)-(dst_col-src_col), mesh1_col_width_c));
else
lr_bit := '1';
retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
:= std_logic_vector
(to_unsigned
((2**mesh1_col_width_c)-(src_col-dst_col), mesh1_col_width_c));
end if;
else
first_dir := "00";
retval(mesh1_row_width_c-1 downto 0) :=
std_logic_vector
(to_unsigned
((2**mesh1_row_width_c)-(src_row-dst_row), mesh1_row_width_c));
if src_col = dst_col then
here_bit := '1';
elsif src_col < dst_col then
retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
:= std_logic_vector
(to_unsigned
((2**mesh1_col_width_c)-(dst_col-src_col), mesh1_col_width_c));
else
lr_bit := '1';
retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
:= std_logic_vector
(to_unsigned
((2**mesh1_col_width_c)-(src_col-dst_col), mesh1_col_width_c));
end if;
end if;
 
retval(mesh1_row_width_c+mesh1_col_width_c+0) := lr_bit;
retval(mesh1_row_width_c+mesh1_col_width_c+1) := here_bit;
retval(mesh1_row_width_c+mesh1_col_width_c+2) := first_dir(0);
retval(mesh1_row_width_c+mesh1_col_width_c+3) := first_dir(1);
 
return retval;
end function ase_mesh1_address;
 
 
end package body ase_mesh1_pkg;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_noc_pkg.vhd
0,0 → 1,414
-------------------------------------------------------------------------------
-- Title : Mesh configuration package
-- Project :
-------------------------------------------------------------------------------
-- File : ase_noc_pkg.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-01-18
-- Last update: 2011-11-08
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-18 1.0 lehton87 Created
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.log2_pkg.all;
 
package ase_noc_pkg is
 
-- Commands
constant mesh_cmd_idle_c : std_logic_vector(1 downto 0) := "00";
constant mesh_cmd_addr_c : std_logic_vector(1 downto 0) := "01";
constant mesh_cmd_data_c : std_logic_vector(1 downto 0) := "10";
constant mesh_cmd_empty_c : std_logic_vector(1 downto 0) := "11";
 
-- Helper functions
function ase_noc_address (
constant own_id : in natural;
constant target_id : in natural;
constant mesh_cols_c : in positive;
constant mesh_rows_c : in positive;
constant mesh_agent_ports_c : in positive;
constant mesh_data_width_c : in positive)
return std_logic_vector;
 
function ase_noc_address_s (
constant own_id : in natural;
signal target_id : in integer;
constant mesh_cols_c : in positive;
constant mesh_rows_c : in positive;
constant mesh_agent_ports_c : in positive;
constant mesh_data_width_c : in positive)
return std_logic_vector;
end package ase_noc_pkg;
 
 
 
 
package body ase_noc_pkg is
 
function ase_noc_address (
constant own_id : in natural;
constant target_id : in natural;
constant mesh_cols_c : in positive;
constant mesh_rows_c : in positive;
constant mesh_agent_ports_c : in positive;
constant mesh_data_width_c : in positive)
return std_logic_vector is
variable ret : std_logic_vector(mesh_data_width_c-1 downto 0);
variable src_row : natural range 0 to mesh_rows_c-1;
variable src_col : natural range 0 to mesh_cols_c-1;
variable dst_row : natural range 0 to mesh_rows_c-1;
variable dst_col : natural range 0 to mesh_cols_c-1;
variable col_dif : integer range -mesh_cols_c/2-1 to mesh_cols_c/2+1;
variable row_dif : integer range -mesh_rows_c/2-1 to mesh_rows_c/2+1;
variable dst_port : natural range 4 to 4+mesh_agent_ports_c-1;
constant mesh_port_width_c : natural := log2_ceil(4+mesh_agent_ports_c);
constant mesh_ids_c : natural :=
mesh_rows_c*mesh_cols_c*mesh_agent_ports_c;
constant mesh_col_add_c : natural := log2_ceil(mesh_cols_c-1);
constant mesh_row_add_c : natural := log2_ceil(mesh_rows_c-1);
begin -- function mesh_address
 
ret := (others => '0');
src_row := (own_id / (mesh_cols_c * mesh_agent_ports_c));
src_col := own_id - (src_row * (mesh_cols_c * mesh_agent_ports_c));
dst_row := (target_id / (mesh_cols_c * mesh_agent_ports_c));
dst_col := target_id - (dst_row * (mesh_cols_c * mesh_agent_ports_c));
col_dif := dst_col - src_col;
row_dif := dst_row - src_row;
dst_port := target_id - (dst_row*mesh_cols_c+dst_col)*mesh_agent_ports_c+4;
 
if src_row = dst_row then
 
if src_col = dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
 
elsif src_col < dst_col then
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(1, mesh_port_width_c));
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
mesh_col_add_c));
ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto
mesh_col_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
else
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(3, mesh_port_width_c));
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
mesh_col_add_c));
ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto
mesh_col_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
end if;
 
elsif src_row < dst_row then
 
if src_col = dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(2, mesh_port_width_c));
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
mesh_row_add_c));
ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
elsif src_col < dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(2, mesh_port_width_c));
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
mesh_row_add_c));
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(1, mesh_port_width_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_port_width_c*2+mesh_row_add_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
mesh_col_add_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
else
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(2, mesh_port_width_c));
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
mesh_row_add_c));
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(3, mesh_port_width_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_port_width_c*2+mesh_row_add_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
mesh_col_add_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
end if;
else
 
if src_col = dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(0, mesh_port_width_c));
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
mesh_row_add_c));
ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
elsif src_col < dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(0, mesh_port_width_c));
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
mesh_row_add_c));
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(1, mesh_port_width_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_port_width_c*2+mesh_row_add_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
mesh_col_add_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
else
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(0, mesh_port_width_c));
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
mesh_row_add_c));
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(3, mesh_port_width_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_port_width_c*2+mesh_row_add_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
mesh_col_add_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
end if;
end if;
 
report "From " & integer'image(own_id) & " to " & integer'image(target_id)
& " gives " & integer'image(to_integer(unsigned(ret))) severity note;
report "col_add " & integer'image(mesh_col_add_c)
& ", row_add " & integer'image(mesh_row_add_c)
& ", port_w " & integer'image(mesh_port_width_c) severity note;
return ret;
end function ase_noc_address;
 
 
function ase_noc_address_s (
constant own_id : in natural;
signal target_id : in integer;
constant mesh_cols_c : in positive;
constant mesh_rows_c : in positive;
constant mesh_agent_ports_c : in positive;
constant mesh_data_width_c : in positive)
return std_logic_vector is
variable ret : std_logic_vector(mesh_data_width_c-1 downto 0);
variable src_row : natural range 0 to mesh_rows_c-1;
variable src_col : natural range 0 to mesh_cols_c-1;
variable dst_row : natural range 0 to mesh_rows_c-1;
variable dst_col : natural range 0 to mesh_cols_c-1;
variable col_dif : integer range -mesh_cols_c/2-1 to mesh_cols_c/2+1;
variable row_dif : integer range -mesh_rows_c/2-1 to mesh_rows_c/2+1;
variable dst_port : natural range 4 to 4+mesh_agent_ports_c-1;
constant mesh_port_width_c : natural := log2_ceil(4+mesh_agent_ports_c);
constant mesh_ids_c : natural :=
mesh_rows_c*mesh_cols_c*mesh_agent_ports_c;
constant mesh_col_add_c : natural := log2_ceil(mesh_cols_c-1);
constant mesh_row_add_c : natural := log2_ceil(mesh_rows_c-1);
begin -- function mesh_address
 
ret := (others => '0');
src_row := (own_id / (mesh_cols_c * mesh_agent_ports_c));
src_col := own_id - (src_row * (mesh_cols_c * mesh_agent_ports_c));
dst_row := (target_id / (mesh_cols_c * mesh_agent_ports_c));
dst_col := target_id - (dst_row * (mesh_cols_c * mesh_agent_ports_c));
col_dif := dst_col - src_col;
row_dif := dst_row - src_row;
dst_port := target_id - (dst_row*mesh_cols_c+dst_col)*mesh_agent_ports_c+4;
 
if src_row = dst_row then
 
if src_col = dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
 
elsif src_col < dst_col then
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(1, mesh_port_width_c));
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
mesh_col_add_c));
ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto
mesh_col_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
else
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(3, mesh_port_width_c));
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
mesh_col_add_c));
ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto
mesh_col_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
end if;
 
elsif src_row < dst_row then
 
if src_col = dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(2, mesh_port_width_c));
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
mesh_row_add_c));
ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
elsif src_col < dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(2, mesh_port_width_c));
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
mesh_row_add_c));
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(1, mesh_port_width_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_port_width_c*2+mesh_row_add_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
mesh_col_add_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
else
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(2, mesh_port_width_c));
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
mesh_row_add_c));
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(3, mesh_port_width_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_port_width_c*2+mesh_row_add_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
mesh_col_add_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
end if;
else
 
if src_col = dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(0, mesh_port_width_c));
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
mesh_row_add_c));
ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
elsif src_col < dst_col then
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(0, mesh_port_width_c));
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
mesh_row_add_c));
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(1, mesh_port_width_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_port_width_c*2+mesh_row_add_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
mesh_col_add_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
else
 
ret(mesh_port_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(0, mesh_port_width_c));
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
mesh_row_add_c));
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_row_add_c+mesh_port_width_c) :=
std_logic_vector(to_unsigned(3, mesh_port_width_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
mesh_port_width_c*2+mesh_row_add_c) :=
std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
mesh_col_add_c));
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
end if;
end if;
 
return ret;
end function ase_noc_address_s;
 
 
 
end package body ase_noc_pkg;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_translation.vhd
0,0 → 1,125
-------------------------------------------------------------------------------
-- Title : Address translation unit
-- Project :
-------------------------------------------------------------------------------
-- File : addr_translation.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-10-12
-- Last update: 2011-10-24
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- Translates various addressing styles to network adresses and also
-- handles inserting the original address behind the network address flit.
--
-- Generics:
--
-- address_mode_g 0 : IP gives raw network address
-- address_mode_g 1 : IP gives integer ID numbers as target address
-- address_mode_g 2 : IP gives memory mapped addresses
--
-- addr_flit_en_g 0 : Nothing done
-- addr_flit_en_g 1 : Places the original address to the second flit
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-10-12 1.0 lehton87 Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity addr_translation is
generic (
my_id_g : natural;
cmd_width_g : positive;
data_width_g : positive;
address_mode_g : natural;
cols_g : positive;
rows_g : positive;
agents_g : positive;
agent_ports_g : positive;
addr_flit_en_g : natural;
noc_type_g : natural);
 
port (
clk : in std_logic;
rst_n : in std_logic;
-- from IP side
ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0);
ip_data_in : in std_logic_vector(data_width_g-1 downto 0);
ip_stall_out : out std_logic;
-- to NET
net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0);
net_data_out : out std_logic_vector(data_width_g-1 downto 0);
net_stall_in : in std_logic;
orig_addr_out : out std_logic_vector(data_width_g-1 downto 0));
 
end addr_translation;
 
 
architecture rtl of addr_translation is
 
signal addr_to_lut : std_logic_vector(data_width_g-1 downto 0);
signal addr_from_lut : std_logic_vector(data_width_g-1 downto 0);
signal orig_addr_r : std_logic_vector(data_width_g-1 downto 0);
begin -- rtl
 
safe_p: process (ip_cmd_in, ip_data_in)
begin -- process safe_p
if ip_cmd_in = "01" then
addr_to_lut <= ip_data_in;
else
addr_to_lut <= (others => '0');
end if;
end process safe_p;
addr_lut_1 : entity work.addr_lut
generic map (
my_id_g => my_id_g,
data_width_g => data_width_g,
address_mode_g => address_mode_g,
cols_g => cols_g,
rows_g => rows_g,
agent_ports_g => agent_ports_g,
agents_g => agents_g,
noc_type_g => noc_type_g)
port map (
addr_in => addr_to_lut,
addr_out => addr_from_lut);
 
net_cmd_out <= ip_cmd_in;
ip_stall_out <= net_stall_in;
orig_addr_out <= orig_addr_r;
 
oa_p : process (clk, rst_n)
begin -- process oa_p
if rst_n = '0' then -- asynchronous reset (active low)
orig_addr_r <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
if ip_cmd_in = "01" then
orig_addr_r <= ip_data_in;
end if;
end if;
end process oa_p;
 
mux_p : process (ip_cmd_in, addr_from_lut, ip_data_in)
begin -- process mux_p
if ip_cmd_in = "01" then
net_data_out <= addr_from_lut;
else
net_data_out <= ip_data_in;
end if;
end process mux_p;
 
end rtl;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/cdc.vhd
0,0 → 1,222
-------------------------------------------------------------------------------
-- Title : CDC (Clock Domain Crossing)
-- Project :
-------------------------------------------------------------------------------
-- File : cdc.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-10-12
-- Last update: 2011-10-24
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- Generics:
--
-- clock_mode_g 0 : single clock
-- clock_mode_g 1 : two asynchronous clocks
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-10-12 1.0 lehton87 Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity cdc is
generic (
cmd_width_g : positive;
data_width_g : positive;
clock_mode_g : natural);
 
port (
clk_ip : in std_logic;
clk_net : in std_logic;
rst_n : in std_logic;
 
ip_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0);
ip_data_out : out std_logic_vector(data_width_g-1 downto 0);
ip_stall_in : in std_logic;
 
ip_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0);
ip_data_in : in std_logic_vector(data_width_g-1 downto 0);
ip_stall_out : out std_logic;
 
net_cmd_out : out std_logic_vector(cmd_width_g-1 downto 0);
net_data_out : out std_logic_vector(data_width_g-1 downto 0);
net_stall_in : in std_logic;
 
net_cmd_in : in std_logic_vector(cmd_width_g-1 downto 0);
net_data_in : in std_logic_vector(data_width_g-1 downto 0);
net_stall_out : out std_logic);
 
end cdc;
 
 
architecture rtl of cdc is
 
signal ip_in_cd : std_logic_vector(cmd_width_g+data_width_g-1 downto 0);
signal net_in_cd : std_logic_vector(cmd_width_g+data_width_g-1 downto 0);
signal ip_out_cd : std_logic_vector(cmd_width_g+data_width_g-1 downto 0);
signal net_out_cd : std_logic_vector(cmd_width_g+data_width_g-1 downto 0);
signal ip_out_cd_r : std_logic_vector(cmd_width_g+data_width_g-1 downto 0);
signal net_out_cd_r : std_logic_vector(cmd_width_g+data_width_g-1 downto 0);
signal ip_we : std_logic;
signal net_we : std_logic;
signal ip_re : std_logic;
signal net_re : std_logic;
signal ip_empty : std_logic;
signal net_empty : std_logic;
begin -- rtl
 
-----------------------------------------------------------------------------
-- ONE CLOCK
--
-- Just a direct combinatorial connection
-----------------------------------------------------------------------------
clock_mode_0 : if clock_mode_g = 0 generate
 
ip_cmd_out <= net_cmd_in;
ip_data_out <= net_data_in;
net_stall_out <= ip_stall_in;
 
net_cmd_out <= ip_cmd_in;
net_data_out <= ip_data_in;
ip_stall_out <= net_stall_in;
end generate clock_mode_0;
 
-----------------------------------------------------------------------------
-- TWO ASYNCHRONOUS CLOCKS
-----------------------------------------------------------------------------
clock_mode_1 : if clock_mode_g = 1 generate
 
---------------------------------------------------------------------------
-- FROM IP TO NET
---------------------------------------------------------------------------
ip_in_cd <= ip_cmd_in & ip_data_in;
net_re <= not net_stall_in;
 
ip_we_p : process (ip_cmd_in)
begin -- process ip_we_p
if ip_cmd_in /= "00" then
ip_we <= '1';
else
ip_we <= '0';
end if;
end process ip_we_p;
 
fifo_ip2net : entity work.fifo_2clk
generic map (
data_width_g => cmd_width_g+data_width_g,
depth_g => 4)
port map (
rst_n => rst_n,
 
clk_wr => clk_ip,
we_in => ip_we,
data_in => ip_in_cd,
full_out => ip_stall_out,
 
clk_rd => clk_net,
re_in => net_re,
data_out => net_out_cd,
empty_out => net_empty);
 
sto1_p: process (clk_net, rst_n)
begin -- process sto1_p
if rst_n = '0' then -- asynchronous reset (active low)
net_out_cd_r <= (others => '0');
elsif clk_net'event and clk_net = '1' then -- rising clock edge
if net_stall_in = '0' and net_empty = '0' then
net_out_cd_r <= net_out_cd;
end if;
end if;
end process sto1_p;
 
net_outs_p: process (net_stall_in, net_empty, net_out_cd, net_out_cd_r)
begin -- process net_outs_p
if net_stall_in = '1' then
net_cmd_out <= net_out_cd_r(cmd_width_g+data_width_g-1 downto
data_width_g);
net_data_out <= net_out_cd_r(data_width_g-1 downto 0);
elsif net_empty = '1' then
net_cmd_out <= (others => '0');
net_data_out <= (others => '0');
else
net_cmd_out <= net_out_cd(cmd_width_g+data_width_g-1 downto
data_width_g);
net_data_out <= net_out_cd(data_width_g-1 downto 0);
end if;
end process net_outs_p;
---------------------------------------------------------------------------
-- FROM NET TO IP
---------------------------------------------------------------------------
net_in_cd <= net_cmd_in & net_data_in;
ip_re <= not ip_stall_in;
 
net_we_p : process (net_cmd_in)
begin -- process ip_we_p
if net_cmd_in /= "00" then
net_we <= '1';
else
net_we <= '0';
end if;
end process net_we_p;
 
fifo_net2ip : entity work.fifo_2clk
generic map (
data_width_g => cmd_width_g+data_width_g,
depth_g => 4)
port map (
rst_n => rst_n,
 
clk_wr => clk_net,
we_in => net_we,
data_in => net_in_cd,
full_out => net_stall_out,
 
clk_rd => clk_ip,
re_in => ip_re,
data_out => ip_out_cd,
empty_out => ip_empty);
 
sto2_p: process (clk_ip, rst_n)
begin -- process sto1_p
if rst_n = '0' then -- asynchronous reset (active low)
ip_out_cd_r <= (others => '0');
elsif clk_ip'event and clk_ip = '1' then -- rising clock edge
if ip_stall_in = '0' and ip_empty = '0' then
ip_out_cd_r <= ip_out_cd;
end if;
end if;
end process sto2_p;
 
ip_outs_p: process (ip_stall_in, ip_empty, ip_out_cd, ip_out_cd_r)
begin -- process net_outs_p
if ip_stall_in = '1' then
ip_cmd_out <= ip_out_cd_r(cmd_width_g+data_width_g-1 downto
data_width_g);
ip_data_out <= ip_out_cd_r(data_width_g-1 downto 0);
elsif ip_empty = '1' then
ip_cmd_out <= (others => '0');
ip_data_out <= (others => '0');
else
ip_cmd_out <= ip_out_cd(cmd_width_g+data_width_g-1 downto
data_width_g);
ip_data_out <= ip_out_cd(data_width_g-1 downto 0);
end if;
end process ip_outs_p;
end generate clock_mode_1;
end rtl;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ram_1clk.vhd
0,0 → 1,83
-------------------------------------------------------------------------------
-- Title : Single clock one port RAM
-- Project :
-------------------------------------------------------------------------------
-- File : ram_1clk.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-01-13
-- Last update: 2011-10-19
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- Basic one port RAM with one clock, new data on read-during-write
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-13 1.0 ase Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity ram_1clk is
generic (
data_width_g : positive;
addr_width_g : positive;
depth_g : positive;
out_reg_en_g : natural);
 
port (
clk : in std_logic;
wr_addr_in : in std_logic_vector(addr_width_g-1 downto 0);
rd_addr_in : in std_logic_vector(addr_width_g-1 downto 0);
we_in : in std_logic;
data_in : in std_logic_vector(data_width_g-1 downto 0);
data_out : out std_logic_vector(data_width_g-1 downto 0));
 
end entity ram_1clk;
 
 
architecture rtl of ram_1clk is
 
type ram_type is array (0 to depth_g-1)
of std_logic_vector(data_width_g-1 downto 0);
 
signal ram_r : ram_type;
signal read_addr_r : integer range 0 to depth_g-1;
begin -- architecture rtl
 
ram_p : process (clk) is
begin -- process ram_p
if clk'event and clk = '1' then -- rising clock edge
 
if we_in = '1' then
ram_r(to_integer(unsigned(wr_addr_in))) <= data_in;
end if;
 
if out_reg_en_g = 1 then
read_addr_r <= to_integer(unsigned(rd_addr_in));
end if;
end if;
end process ram_p;
 
out_reg_en_1: if out_reg_en_g = 1 generate
data_out <= ram_r(read_addr_r);
end generate out_reg_en_1;
 
out_reg_en_0: if out_reg_en_g = 0 generate
data_out <= ram_r(to_integer(unsigned(rd_addr_in)));
end generate out_reg_en_0;
 
end architecture rtl;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/ase_dring1_pkg.vhd
0,0 → 1,166
-------------------------------------------------------------------------------
-- Title : Package for ase_ring1 and wrappers using it
-- Project :
-------------------------------------------------------------------------------
-- File : ase_ring1_pkg.vhdl
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2010-07-04
-- Last update: 2011-11-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-07-04 1.0 ase Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.log2_pkg.all;
 
-------------------------------------------------------------------------------
-- PACKAGE DECLARATION
-------------------------------------------------------------------------------
package ase_dring1_pkg is
 
-----------------------------------------------------------------------------
-- HELPER FUNCTIONS
-----------------------------------------------------------------------------
 
-- Returns data_width_c wide address calculated from source and
-- destination id numbers (ie. their position on the ring)
function dring1_address (
src_id : in integer;
dst_id : in integer;
agents_c : in positive;
data_width_c : in positive)
return std_logic_vector;
 
function dring1_address_s (
constant src_id : in integer;
signal dst_id : in integer;
constant agents_c : in positive;
constant data_width_c : in positive)
return std_logic_vector;
end package ase_dring1_pkg;
 
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body ase_dring1_pkg is
 
-----------------------------------------------------------------------------
-- FUNCTIONS
-----------------------------------------------------------------------------
function dring1_address (
src_id : in integer;
dst_id : in integer;
agents_c : in positive;
data_width_c : in positive)
return std_logic_vector is
variable retval_v : std_logic_vector(data_width_c-1 downto 0);
constant addr_width_c : positive := log2_ceil(agents_c/2);
variable src_v : integer; --natural range 0 to agents_c-1;
variable dst_v : integer; --natural range 0 to agents_c-1;
variable tmp_v : signed(addr_width_c+2 downto 0);
begin
retval_v := (others => '0');
src_v := src_id;
dst_v := dst_id;
if src_v < dst_v then
if dst_v - src_v <= agents_c / 2 then
report "#1 src: " & integer'image(src_id) & " dst: "
& integer'image(dst_id) severity note;
retval_v(addr_width_c) := '0';
retval_v(addr_width_c-1 downto 0) :=
std_logic_vector(to_signed
(2**addr_width_c - (dst_v - src_v), addr_width_c+3)
(addr_width_c-1 downto 0));
else
report "#2 src: " & integer'image(src_id) & " dst: "
& integer'image(dst_id) severity note;
retval_v(addr_width_c) := '1';
retval_v(addr_width_c-1 downto 0) :=
std_logic_vector(to_signed(
2**addr_width_c - (agents_c - dst_v + src_v), addr_width_c+3)
(addr_width_c-1 downto 0));
end if;
else
if src_v - dst_v <= agents_c / 2 then
report "#3 src: " & integer'image(src_id) & " dst: "
& integer'image(dst_id) severity note;
retval_v(addr_width_c) := '1';
retval_v(addr_width_c-1 downto 0) :=
std_logic_vector(to_signed
(2**addr_width_c - (src_v - dst_v), addr_width_c+3)
(addr_width_c-1 downto 0));
else
report "#4 src: " & integer'image(src_id) & " dst: "
& integer'image(dst_id) severity note;
retval_v(addr_width_c) := '0';
tmp_v := to_signed(
2**addr_width_c - (agents_c - src_v + dst_v), addr_width_c+3);
report "#4 tmpv: " & integer'image(to_integer(tmp_v));
retval_v(addr_width_c-1 downto 0) := std_logic_vector(tmp_v(addr_width_c-1 downto 0));
report "#4 resv: " &
integer'image(2**addr_width_c - (agents_c - src_v + dst_v))
severity note;
end if;
end if;
report "RESULT: " & integer'image(to_integer(unsigned(retval_v)))
severity note;
return retval_v;
end function dring1_address;
 
 
function dring1_address_s (
constant src_id : in integer;
signal dst_id : in integer;
constant agents_c : in positive;
constant data_width_c : in positive)
return std_logic_vector is
variable retval_v : std_logic_vector(data_width_c-1 downto 0);
constant addr_width_c : positive := log2_ceil(agents_c/2);
variable src_v : integer; --natural range 0 to agents_c-1;
variable dst_v : integer; --natural range 0 to agents_c-1;
begin
retval_v := (others => '0');
src_v := src_id;
dst_v := dst_id;
if src_v < dst_v then
if dst_v - src_v <= agents_c / 2 then
retval_v(addr_width_c) := '0';
retval_v(addr_width_c-1 downto 0) :=
std_logic_vector(to_unsigned
(2**addr_width_c - dst_v - src_v, addr_width_c));
else
retval_v(addr_width_c) := '1';
retval_v(addr_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(
2**addr_width_c - agents_c - dst_v + src_v, addr_width_c));
end if;
else
if src_v - dst_v <= agents_c / 2 then
retval_v(addr_width_c) := '1';
retval_v(addr_width_c-1 downto 0) :=
std_logic_vector(to_unsigned
(2**addr_width_c - src_v - dst_v, addr_width_c));
else
retval_v(addr_width_c) := '0';
retval_v(addr_width_c-1 downto 0) :=
std_logic_vector(to_unsigned(
2**addr_width_c - agents_c - src_v + dst_v, addr_width_c));
end if;
end if;
return retval_v;
end function dring1_address_s;
 
end package body ase_dring1_pkg;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/fifo_2clk.vhd
0,0 → 1,326
-------------------------------------------------------------------------------
-- Title : Basic FIFO with two clocks
-- Project :
-------------------------------------------------------------------------------
-- File : fifo_2clk.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-01-13
-- Last update: 2011-10-19
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- Fully asynchronous fifo.
--
-- Idea from:
-- Cummings et al., Simulation and Synthesis Techniques for Asynchronous
-- FIFO Design with Asynchronous Pointer Comparisons, SNUG San Jose 2002
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-13 1.0 ase Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity fifo_2clk is
generic (
data_width_g : positive;
depth_g : positive);
 
port (
rst_n : in std_logic;
-- Write
clk_wr : in std_logic;
we_in : in std_logic;
data_in : in std_logic_vector(data_width_g-1 downto 0);
full_out : out std_logic;
-- Read
clk_rd : in std_logic;
re_in : in std_logic;
data_out : out std_logic_vector(data_width_g-1 downto 0);
empty_out : out std_logic);
 
end entity fifo_2clk;
 
 
architecture rtl of fifo_2clk is
 
-----------------------------------------------------------------------------
-- FUNCTIONS
-----------------------------------------------------------------------------
-- purpose: Return ceiling log 2 of n
function log2_ceil (
constant n : positive)
return positive is
variable retval : positive := 1;
begin -- function log2_ceil
while 2**retval < n loop
retval := retval + 1;
end loop;
return retval;
end function log2_ceil;
 
-- binary to graycode conversion
function bin2gray (
signal num : integer range 0 to depth_g-1)
return std_logic_vector is
variable retval : std_logic_vector(log2_ceil(depth_g)-1 downto 0);
variable d1 : std_logic_vector(log2_ceil(depth_g)-1 downto 0);
begin
d1 := std_logic_vector((to_unsigned(num, log2_ceil(depth_g))));
retval := d1 xor ('0' & d1(log2_ceil(depth_g)-1 downto 1));
return retval;
end function bin2gray;
 
-----------------------------------------------------------------------------
-- CONSTANTS
-----------------------------------------------------------------------------
constant addr_width_c : positive := log2_ceil(depth_g);
 
-----------------------------------------------------------------------------
-- REGISTERS
-----------------------------------------------------------------------------
signal wr_addr_r : integer range 0 to depth_g-1;
signal rd_addr_r : integer range 0 to depth_g-1;
signal full_1_r : std_logic;
signal full_2_r : std_logic;
signal empty_1_r : std_logic;
signal empty_2_r : std_logic;
 
-----------------------------------------------------------------------------
-- COMBINATORIAL SIGNALS
-----------------------------------------------------------------------------
signal next_wr_addr : integer range 0 to depth_g-1;
signal next_rd_addr : integer range 0 to depth_g-1;
signal wr_addr : std_logic_vector(addr_width_c-1 downto 0);
signal rd_addr : std_logic_vector(addr_width_c-1 downto 0);
signal we : std_logic;
signal dirset_n : std_logic;
signal dirclr_n : std_logic;
signal direction : std_logic;
signal h : std_logic;
signal empty_n : std_logic;
signal full_n : std_logic;
begin -- architecture rtl
 
 
full_out <= full_2_r;
empty_out <= empty_2_r;
 
-----------------------------------------------------------------------------
-- WRITE
-----------------------------------------------------------------------------
 
write_p : process (clk_wr, rst_n)
begin -- process write_p
if rst_n = '0' then -- asynchronous reset (active low)
 
wr_addr_r <= 0;
elsif clk_wr'event and clk_wr = '1' then -- rising clock edge
 
if we_in = '1' and full_2_r = '0' then
wr_addr_r <= next_wr_addr;
end if;
 
end if;
end process write_p;
 
we <= we_in and not full_2_r;
 
-----------------------------------------------------------------------------
-- READ
-----------------------------------------------------------------------------
 
read_p : process (clk_rd, rst_n)
begin -- process read_p
if rst_n = '0' then -- asynchronous reset (active low)
 
rd_addr_r <= 0;
elsif clk_rd'event and clk_rd = '1' then -- rising clock edge
 
if re_in = '1' and empty_2_r = '0' then
rd_addr_r <= next_rd_addr;
end if;
end if;
end process read_p;
 
-----------------------------------------------------------------------------
-- RAM
-----------------------------------------------------------------------------
 
wr_addr <= std_logic_vector(to_unsigned(wr_addr_r, addr_width_c));
rd_addr <= std_logic_vector(to_unsigned(rd_addr_r, addr_width_c));
 
ram_2clk_1 : entity work.ram_1clk
generic map (
data_width_g => data_width_g,
addr_width_g => addr_width_c,
depth_g => depth_g,
out_reg_en_g => 0)
port map (
clk => clk_wr,
wr_addr_in => wr_addr,
rd_addr_in => rd_addr,
we_in => we,
data_in => data_in,
data_out => data_out);
 
-----------------------------------------------------------------------------
-- NEXT ADDRESSES
-----------------------------------------------------------------------------
next_wr_addr_p : process (wr_addr_r) is
begin
 
if wr_addr_r = depth_g-1 then
next_wr_addr <= 0;
else
next_wr_addr <= wr_addr_r + 1;
end if;
 
end process next_wr_addr_p;
 
next_rd_addr_p : process (rd_addr_r) is
begin
 
if rd_addr_r = depth_g-1 then
next_rd_addr <= 0;
else
next_rd_addr <= rd_addr_r + 1;
end if;
end process next_rd_addr_p;
 
-----------------------------------------------------------------------------
-- ASYNC COMPARISON (FULL AND EMPTY GENERATION)
-----------------------------------------------------------------------------
 
dirgen_p : process (wr_addr_r, rd_addr_r, rst_n)
variable wr_h1 : std_logic;
variable wr_h2 : std_logic;
variable rd_h1 : std_logic;
variable rd_h2 : std_logic;
begin -- process asyncomp_p
 
wr_h1 := bin2gray(wr_addr_r)(addr_width_c-1);
wr_h2 := bin2gray(wr_addr_r)(addr_width_c-2);
rd_h1 := bin2gray(rd_addr_r)(addr_width_c-1);
rd_h2 := bin2gray(rd_addr_r)(addr_width_c-2);
 
dirset_n <= not ((wr_h1 xor rd_h2) and not (wr_h2 xor rd_h1));
dirclr_n <= not ((not (wr_h1 xor rd_h2) and (wr_h2 xor rd_h1))
or not rst_n);
 
end process dirgen_p;
 
h <= '1';
 
-- dir_rs_flop_p : process (dirset_n, dirclr_n, h)
-- begin -- process dir_rs_flop_p
 
-- if (h'event and h = '1') or
-- (dirset_n'event and dirset_n = '0') or
-- (dirclr_n'event and dirclr_n = '0') then
 
-- if dirclr_n = '0' then
-- direction <= '0';
-- elsif dirset_n = '0' then
-- direction <= '1';
-- else
-- direction <= h;
-- end if;
 
-- end if;
 
-- end process dir_rs_flop_p;
 
rs_flop_p : process (dirclr_n, dirset_n, direction)
begin -- process rs_flop_p
if dirclr_n = '0' then
direction <= '0';
elsif dirset_n = '0' then
direction <= '1';
else
direction <= direction;
end if;
end process rs_flop_p;
 
full_empty_s : process (direction, wr_addr_r, rd_addr_r)
variable match_v : std_logic;
begin -- process empty_s
if rd_addr_r = wr_addr_r then
match_v := '1';
else
match_v := '0';
end if;
if match_v = '1' and direction = '1' then
full_n <= '0';
else
full_n <= '1';
end if;
if match_v = '1' and direction = '0' then
empty_n <= '0';
else
empty_n <= '1';
end if;
end process full_empty_s;
 
empty_sync_1p : process (clk_rd, rst_n, empty_n)
begin -- process empty_sync_p
if rst_n = '0' then -- asynchronous reset (active low)
empty_1_r <= '1';
elsif empty_n = '0' then
empty_1_r <= not empty_n;
elsif clk_rd'event and clk_rd = '1' then -- rising clock edge
empty_1_r <= not empty_n;
end if;
end process empty_sync_1p;
 
empty_sync_2p : process (clk_rd, rst_n, empty_n, empty_1_r)
begin -- process empty_sync_p
if rst_n = '0' then -- asynchronous reset (active low)
empty_2_r <= '1';
elsif empty_n = '0' then
empty_2_r <= empty_1_r;
elsif clk_rd'event and clk_rd = '1' then -- rising clock edge
empty_2_r <= empty_1_r;
end if;
end process empty_sync_2p;
 
full_sync_1p : process (clk_wr, rst_n, full_n)
begin -- process empty_sync_p
if rst_n = '0' then -- asynchronous reset (active low)
full_1_r <= '0';
elsif full_n = '0' then
full_1_r <= not full_n;
elsif clk_wr'event and clk_wr = '1' then -- rising clock edge
full_1_r <= not full_n;
end if;
end process full_sync_1p;
 
full_sync_2p : process (clk_wr, rst_n, full_n, full_1_r)
begin -- process empty_sync_p
if rst_n = '0' then -- asynchronous reset (active low)
full_2_r <= '0';
elsif full_n = '0' then
full_2_r <= full_1_r;
elsif clk_wr'event and clk_wr = '1' then -- rising clock edge
full_2_r <= full_1_r;
end if;
end process full_sync_2p;
end architecture rtl;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/vhd/addr_lut.vhd
0,0 → 1,198
-------------------------------------------------------------------------------
-- Title : Address look-up table
-- Project :
-------------------------------------------------------------------------------
-- File : addr_lut.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-01-12
-- Last update: 2011-11-09
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Converts memory mapped I/O address to NoC address
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-12 1.0 ase Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.ase_noc_pkg.all;
use work.ase_mesh1_pkg.all;
use work.ase_dring1_pkg.all;
 
entity addr_lut is
generic (
my_id_g : natural;
data_width_g : positive;
address_mode_g : natural;
cols_g : positive;
rows_g : positive;
agent_ports_g : positive;
agents_g : positive;
noc_type_g : natural);
 
port (
addr_in : in std_logic_vector(data_width_g-1 downto 0);
addr_out : out std_logic_vector(data_width_g-1 downto 0));
 
end entity addr_lut;
 
 
 
architecture rtl of addr_lut is
 
-- How many different address ranges there are
constant n_addr_ranges_c : positive := 32;
constant mesh_ids_c : positive := cols_g*rows_g*agent_ports_g;
 
signal noc_target : integer;
 
 
type addr_range_type is array (0 to 2) of unsigned(data_width_g-1 downto 0);
type addr_lut_type is array (0 to n_addr_ranges_c-1) of addr_range_type;
 
function addr_gen (
constant target : natural)
return unsigned is
variable retval : unsigned(data_width_g-1 downto 0);
begin
if noc_type_g = 0 then
retval := unsigned(ase_noc_address(my_id_g, target, cols_g, rows_g,
agent_ports_g, data_width_g));
return retval;
end if;
if noc_type_g = 1 then
retval := unsigned(ase_mesh1_address(my_id_g, target, rows_g, cols_g,
data_width_g));
return retval;
end if;
if noc_type_g = 2 then
retval := unsigned(dring1_address(my_id_g, target, agents_g,
data_width_g));
return retval;
end if;
end addr_gen;
 
function addr_gen_s (
signal target : integer)
return std_logic_vector is
variable retval : std_logic_vector(data_width_g-1 downto 0);
begin
if noc_type_g = 0 then
retval := ase_noc_address_s(my_id_g, target, cols_g, rows_g,
agent_ports_g, data_width_g);
return retval;
end if;
if noc_type_g = 1 then
retval := ase_mesh1_address(my_id_g, target, rows_g, cols_g,
data_width_g);
return retval;
end if;
if noc_type_g = 2 then
retval := dring1_address(my_id_g, target, agents_g, data_width_g);
return retval;
end if;
end addr_gen_s;
 
-- First = address range's minimum address
-- Second = address range's maximum address
-- Third = corresponding network address
 
constant addr_lut_c : addr_lut_type :=
(
(x"00000000", x"00FFFFFF", addr_gen(0)),
(x"01000000", x"01FFFFFF", addr_gen(1)),
(x"02000000", x"02FFFFFF", addr_gen(2)),
(x"03000000", x"03FFFFFF", addr_gen(3)),
(x"04000000", x"04FFFFFF", addr_gen(4)),
(x"05000000", x"05FFFFFF", addr_gen(5)),
(x"06000000", x"06FFFFFF", addr_gen(6)),
(x"07000000", x"07FFFFFF", addr_gen(7)),
(x"08000000", x"08FFFFFF", addr_gen(8)),
(x"09000000", x"09FFFFFF", addr_gen(9)),
(x"0A000000", x"0AFFFFFF", addr_gen(10)),
(x"0B000000", x"0BFFFFFF", addr_gen(11)),
(x"0C000000", x"0CFFFFFF", addr_gen(12)),
(x"0D000000", x"0DFFFFFF", addr_gen(13)),
(x"0E000000", x"0EFFFFFF", addr_gen(14)),
(x"0F000000", x"0FFFFFFF", addr_gen(15)),
(x"10000000", x"10FFFFFF", addr_gen(16)),
(x"11000000", x"11FFFFFF", addr_gen(17)),
(x"12000000", x"12FFFFFF", addr_gen(18)),
(x"13000000", x"13FFFFFF", addr_gen(19)),
(x"14000000", x"14FFFFFF", addr_gen(20)),
(x"15000000", x"15FFFFFF", addr_gen(21)),
(x"16000000", x"16FFFFFF", addr_gen(22)),
(x"17000000", x"17FFFFFF", addr_gen(23)),
(x"18000000", x"18FFFFFF", addr_gen(24)),
(x"19000000", x"19FFFFFF", addr_gen(25)),
(x"1A000000", x"1AFFFFFF", addr_gen(26)),
(x"1B000000", x"1BFFFFFF", addr_gen(27)),
(x"1C000000", x"1CFFFFFF", addr_gen(28)),
(x"1D000000", x"1DFFFFFF", addr_gen(29)),
(x"1E000000", x"1EFFFFFF", addr_gen(30)),
(x"1F000000", x"1FFFFFFF", addr_gen(31))
);
 
-- constant addr_lut_c : addr_lut_type :=
-- (
-- (x"0000", x"0FFF", addr_gen(0)),
-- (x"1000", x"1FFF", addr_gen(1)),
-- (x"2000", x"2FFF", addr_gen(2)),
-- (x"3000", x"3FFF", addr_gen(3))
-- );
 
begin -- architecture rtl
 
-----------------------------------------------------------------------------
-- MEMORY MAPPED ADDRESSES
-----------------------------------------------------------------------------
use_mem_addr_gen : if address_mode_g = 2 generate
translate_p : process (addr_in) is
begin -- process translate_p
addr_out <= (others => '1');
 
for i in 0 to n_addr_ranges_c-1 loop
 
if unsigned(addr_in) >= addr_lut_c(i)(0)
and unsigned(addr_in) <= addr_lut_c(i)(1) then
 
addr_out <= std_logic_vector(addr_lut_c(i)(2));
end if;
end loop; -- i
end process translate_p;
end generate use_mem_addr_gen;
 
-----------------------------------------------------------------------------
-- INTEGER ADDRESSES
-----------------------------------------------------------------------------
use_int_addr_gen : if address_mode_g = 1 generate
 
noc_target <= to_integer(unsigned(addr_in(data_width_g-2 downto 0)));
addr_out <= addr_gen_s(noc_target);
end generate use_int_addr_gen;
 
-----------------------------------------------------------------------------
-- NO ADDRESS TRANSLATION
-----------------------------------------------------------------------------
no_translation_g : if address_mode_g = 0 generate
 
addr_out <= addr_in;
end generate no_translation_g;
end architecture rtl;
/trunk/TUT/ip.hwp.communication/pkt_codec_mk2/1.0/pkt_codec_mk2.absDef.1.0.xml
0,0 → 1,71
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 18:01:52 ke marras 9 2011-->
<spirit:abstractionDefinition>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.communication</spirit:library>
<spirit:name>pkt_codec_mk2.absDef</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2" spirit:version="1.0"/>
<spirit:ports>
<spirit:port>
<spirit:logicalName>STALL_IN</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:requiresDriver spirit:driverType="any"/>false</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>DATA_OUT</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>32</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:requiresDriver spirit:driverType="any"/>false</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CMD_OUT</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>2</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:requiresDriver spirit:driverType="any"/>false</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>STALL_OUT</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:requiresDriver spirit:driverType="any"/>false</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>DATA_IN</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>32</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:requiresDriver spirit:driverType="any"/>false</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>CMD_IN</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>2</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:requiresDriver spirit:driverType="any"/>false</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:abstractionDefinition>
/trunk/TUT/ip.hwp.communication/ase_mesh1/ase_mesh1_top4/1.0/vhd/ase_mesh1_pkt_codec.vhd
0,0 → 1,132
-------------------------------------------------------------------------------
-- Title : Ase mesh1 top with packet codecs
-- Project :
-------------------------------------------------------------------------------
-- File : ase_mesh1_pkt_codec.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-09-25
-- Last update: 2011-10-20
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-18 1.0 ase Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
 
 
entity ase_mesh1_pkt_codec is
generic (
data_width_g : positive;
cmd_width_g : positive;
agents_g : positive;
cols_g : positive;
rows_g : positive;
agent_ports_g : positive;
addr_flit_en_g : natural;
address_mode_g : natural;
clock_mode_g : natural;
rip_addr_g : natural;
fifo_depth_g : natural);
 
port (
clk_ip : in std_logic;
clk_net : in std_logic;
rst_n : in std_logic;
cmd_in : in std_logic_vector(agents_g * cmd_width_g - 1 downto 0);
data_in : in std_logic_vector(agents_g * data_width_g - 1 downto 0);
stall_out : out std_logic_vector(agents_g - 1 downto 0);
cmd_out : out std_logic_vector(agents_g * cmd_width_g - 1 downto 0);
data_out : out std_logic_vector(agents_g * data_width_g - 1 downto 0);
stall_in : in std_logic_vector(agents_g - 1 downto 0));
 
end entity ase_mesh1_pkt_codec;
 
 
 
architecture rtl of ase_mesh1_pkt_codec is
 
constant noc_type_g : natural := 1;
-----------------------------------------------------------------------------
-- MESH
-----------------------------------------------------------------------------
 
signal cmd_to_n : std_logic_vector(agents_g * cmd_width_g - 1 downto 0);
signal data_to_n : std_logic_vector(agents_g * data_width_g - 1 downto 0);
signal stall_to_n : std_logic_vector(agents_g - 1 downto 0);
signal cmd_from_n : std_logic_vector(agents_g * cmd_width_g - 1 downto 0);
signal data_from_n : std_logic_vector(agents_g * data_width_g - 1 downto 0);
signal stall_from_n : std_logic_vector(agents_g - 1 downto 0);
 
begin -- architecture rtl
 
 
 
-----------------------------------------------------------------------------
-- GENERATE MESH
-----------------------------------------------------------------------------
noc_top_1 : entity work.ase_mesh1
generic map (
n_rows_g => rows_g,
n_cols_g => cols_g,
cmd_width_g => cmd_width_g,
bus_width_g => data_width_g)
port map (
clk => clk_net,
rst_n => rst_n,
cmd_in => cmd_to_n,
data_in => data_to_n,
stall_out => stall_from_n,
cmd_out => cmd_from_n,
data_out => data_from_n,
stall_in => stall_to_n);
 
codecs_g : for i in 0 to agents_g-1 generate
 
packet_codec_1 : entity work.pkt_codec_mk2
generic map (
my_id_g => i,
data_width_g => data_width_g,
cmd_width_g => cmd_width_g,
agents_g => agents_g,
cols_g => cols_g,
rows_g => rows_g,
agent_ports_g => agent_ports_g,
addr_flit_en_g => addr_flit_en_g,
address_mode_g => address_mode_g,
clock_mode_g => clock_mode_g,
rip_addr_g => rip_addr_g,
noc_type_g => noc_type_g)
port map (
clk_ip => clk_ip,
clk_net => clk_net,
rst_n => rst_n,
ip_cmd_out => cmd_out((i+1)*cmd_width_g-1 downto i*cmd_width_g),
ip_data_out => data_out((i+1)*data_width_g-1 downto i*data_width_g),
ip_stall_in => stall_in(i),
ip_cmd_in => cmd_in((i+1)*cmd_width_g-1 downto i*cmd_width_g),
ip_data_in => data_in((i+1)*data_width_g-1 downto i*data_width_g),
ip_stall_out => stall_out(i),
net_cmd_out => cmd_to_n((i+1)*cmd_width_g-1 downto i*cmd_width_g),
net_data_out => data_to_n((i+1)*data_width_g-1 downto i*data_width_g),
net_stall_in => stall_from_n(i),
net_cmd_in => cmd_from_n((i+1)*cmd_width_g-1 downto i*cmd_width_g),
net_data_in => data_from_n((i+1)*data_width_g-1 downto i*data_width_g),
net_stall_out => stall_to_n(i));
 
end generate codecs_g;
 
 
end architecture rtl;
 
/trunk/TUT/ip.hwp.communication/ase_mesh1/ase_mesh1_top4/1.0/vhd/ase_mesh1_router.vhd
0,0 → 1,892
-------------------------------------------------------------------------------
-- Title : 2D mesh mk1 by ase
-- Project :
-------------------------------------------------------------------------------
-- File : ase_mesh1_router.vhdl
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2010-04-06
-- Last update: 2011-10-21
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-04-06 1.0 ase Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.log2_pkg.all;
 
entity ase_mesh1_router is
generic (
n_rows_g : positive; -- Number of rows
n_cols_g : positive; -- Number of columns
bus_width_g : positive); -- Width of the data bus
port (
clk : in std_logic;
rst_n : in std_logic;
-- Agent interface
a_data_in : in std_logic_vector(bus_width_g-1 downto 0);
a_da_in : in std_logic;
a_av_in : in std_logic;
a_stall_out : out std_logic;
a_data_out : out std_logic_vector(bus_width_g-1 downto 0);
a_da_out : out std_logic;
a_av_out : out std_logic;
a_stall_in : in std_logic;
-- North interface
n_data_in : in std_logic_vector(bus_width_g-1 downto 0);
n_da_in : in std_logic;
n_av_in : in std_logic;
n_stall_out : out std_logic;
n_data_out : out std_logic_vector(bus_width_g-1 downto 0);
n_da_out : out std_logic;
n_av_out : out std_logic;
n_stall_in : in std_logic;
-- East interface
e_data_in : in std_logic_vector(bus_width_g-1 downto 0);
e_da_in : in std_logic;
e_av_in : in std_logic;
e_stall_out : out std_logic;
e_data_out : out std_logic_vector(bus_width_g-1 downto 0);
e_da_out : out std_logic;
e_av_out : out std_logic;
e_stall_in : in std_logic;
-- South interface
s_data_in : in std_logic_vector(bus_width_g-1 downto 0);
s_da_in : in std_logic;
s_av_in : in std_logic;
s_stall_out : out std_logic;
s_data_out : out std_logic_vector(bus_width_g-1 downto 0);
s_da_out : out std_logic;
s_av_out : out std_logic;
s_stall_in : in std_logic;
-- West interface
w_data_in : in std_logic_vector(bus_width_g-1 downto 0);
w_da_in : in std_logic;
w_av_in : in std_logic;
w_stall_out : out std_logic;
w_data_out : out std_logic_vector(bus_width_g-1 downto 0);
w_da_out : out std_logic;
w_av_out : out std_logic;
w_stall_in : in std_logic
);
 
end entity ase_mesh1_router;
 
 
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
 
architecture rtl of ase_mesh1_router is
 
-----------------------------------------------------------------------------
-- CONSTANTS
-----------------------------------------------------------------------------
 
constant r_addr_width_c : positive := log2_ceil(n_rows_g-1);
constant c_addr_width_c : positive := log2_ceil(n_cols_g-1);
constant lr_index_c : positive := r_addr_width_c + c_addr_width_c;
constant here_index_c : positive := r_addr_width_c + c_addr_width_c + 1;
constant first_index_h_c : positive := r_addr_width_c + c_addr_width_c + 3;
constant first_index_l_c : positive := r_addr_width_c + c_addr_width_c + 2;
 
-----------------------------------------------------------------------------
-- REGISTERS
-----------------------------------------------------------------------------
 
-- Output registers
signal a_stall_out_r : std_logic;
signal a_data_out_r : std_logic_vector(bus_width_g-1 downto 0);
signal a_da_out_r : std_logic;
signal a_av_out_r : std_logic;
signal n_stall_out_r : std_logic;
signal n_data_out_r : std_logic_vector(bus_width_g-1 downto 0);
signal n_da_out_r : std_logic;
signal n_av_out_r : std_logic;
signal e_stall_out_r : std_logic;
signal e_data_out_r : std_logic_vector(bus_width_g-1 downto 0);
signal e_da_out_r : std_logic;
signal e_av_out_r : std_logic;
signal s_stall_out_r : std_logic;
signal s_data_out_r : std_logic_vector(bus_width_g-1 downto 0);
signal s_da_out_r : std_logic;
signal s_av_out_r : std_logic;
signal w_stall_out_r : std_logic;
signal w_data_out_r : std_logic_vector(bus_width_g-1 downto 0);
signal w_da_out_r : std_logic;
signal w_av_out_r : std_logic;
 
-- Input registers
signal a_data_in_r : std_logic_vector(bus_width_g-1 downto 0);
signal a_av_in_r : std_logic;
signal a_da_in_r : std_logic;
signal n_data_in_r : std_logic_vector(bus_width_g-1 downto 0);
signal n_av_in_r : std_logic;
signal n_da_in_r : std_logic;
signal e_data_in_r : std_logic_vector(bus_width_g-1 downto 0);
signal e_av_in_r : std_logic;
signal e_da_in_r : std_logic;
signal s_data_in_r : std_logic_vector(bus_width_g-1 downto 0);
signal s_av_in_r : std_logic;
signal s_da_in_r : std_logic;
signal w_data_in_r : std_logic_vector(bus_width_g-1 downto 0);
signal w_av_in_r : std_logic;
signal w_da_in_r : std_logic;
 
-- Other registers
signal reroute_n_r : std_logic;
signal reroute_e_r : std_logic;
signal reroute_s_r : std_logic;
signal reroute_w_r : std_logic;
 
signal grant_s_n_r : std_logic;
signal grant_a_n_r : std_logic;
 
signal grant_n_e_r : std_logic;
signal grant_s_e_r : std_logic;
signal grant_w_e_r : std_logic;
signal grant_a_e_r : std_logic;
 
signal grant_n_s_r : std_logic;
signal grant_a_s_r : std_logic;
 
signal grant_n_w_r : std_logic;
signal grant_e_w_r : std_logic;
signal grant_s_w_r : std_logic;
signal grant_a_w_r : std_logic;
 
signal grant_n_a_r : std_logic;
signal grant_e_a_r : std_logic;
signal grant_s_a_r : std_logic;
signal grant_w_a_r : std_logic;
 
signal add_ar_r : std_logic_vector(r_addr_width_c-1 downto 0);
signal add_ac_r : std_logic_vector(c_addr_width_c-1 downto 0);
 
-----------------------------------------------------------------------------
-- COMBINATIORIAL SIGNALS
-----------------------------------------------------------------------------
signal add_n : std_logic_vector(r_addr_width_c downto 0);
signal add_e : std_logic_vector(c_addr_width_c downto 0);
signal add_s : std_logic_vector(r_addr_width_c downto 0);
signal add_w : std_logic_vector(c_addr_width_c downto 0);
 
signal data_n : std_logic_vector(bus_width_g-1 downto 0);
signal data_e : std_logic_vector(bus_width_g-1 downto 0);
signal data_s : std_logic_vector(bus_width_g-1 downto 0);
signal data_w : std_logic_vector(bus_width_g-1 downto 0);
signal data_a : std_logic_vector(bus_width_g-1 downto 0);
 
signal reroute_n : std_logic;
signal reroute_e : std_logic;
signal reroute_s : std_logic;
signal reroute_w : std_logic;
 
signal here_n : std_logic;
signal here_s : std_logic;
signal here_n_prev : std_logic;
signal here_s_prev : std_logic;
 
signal lr_n : std_logic;
signal lr_s : std_logic;
signal lr_n_prev : std_logic;
signal lr_s_prev : std_logic;
 
signal a_first_hi : std_logic;
signal a_first_lo : std_logic;
signal a_first_hi_prev : std_logic;
signal a_first_lo_prev : std_logic;
 
signal req_n_e : std_logic;
signal req_n_s : std_logic;
signal req_n_w : std_logic;
signal req_n_a : std_logic;
 
signal req_e_w : std_logic;
signal req_e_a : std_logic;
 
signal req_s_n : std_logic;
signal req_s_e : std_logic;
signal req_s_w : std_logic;
signal req_s_a : std_logic;
 
signal req_w_e : std_logic;
signal req_w_a : std_logic;
 
signal req_a_n : std_logic;
signal req_a_e : std_logic;
signal req_a_s : std_logic;
signal req_a_w : std_logic;
 
signal grant_s_n : std_logic;
signal grant_a_n : std_logic;
 
signal grant_n_e : std_logic;
signal grant_s_e : std_logic;
signal grant_w_e : std_logic;
signal grant_a_e : std_logic;
 
signal grant_n_s : std_logic;
signal grant_a_s : std_logic;
 
signal grant_n_w : std_logic;
signal grant_e_w : std_logic;
signal grant_s_w : std_logic;
signal grant_a_w : std_logic;
 
signal grant_n_a : std_logic;
signal grant_e_a : std_logic;
signal grant_s_a : std_logic;
signal grant_w_a : std_logic;
 
signal stall_n : std_logic;
signal stall_e : std_logic;
signal stall_s : std_logic;
signal stall_w : std_logic;
signal stall_a : std_logic;
begin -- architecture rtl
 
-----------------------------------------------------------------------------
-- CONNECT OUTPUT REGISTERS TO OUTPUT PORTS
-----------------------------------------------------------------------------
a_stall_out <= a_stall_out_r;
a_data_out <= a_data_out_r;
a_da_out <= a_da_out_r;
a_av_out <= a_av_out_r;
 
n_stall_out <= n_stall_out_r;
n_data_out <= n_data_out_r;
n_da_out <= n_da_out_r;
n_av_out <= n_av_out_r;
 
e_stall_out <= e_stall_out_r;
e_data_out <= e_data_out_r;
e_da_out <= e_da_out_r;
e_av_out <= e_av_out_r;
 
s_stall_out <= s_stall_out_r;
s_data_out <= s_data_out_r;
s_da_out <= s_da_out_r;
s_av_out <= s_av_out_r;
 
w_stall_out <= w_stall_out_r;
w_data_out <= w_data_out_r;
w_da_out <= w_da_out_r;
w_av_out <= w_av_out_r;
 
-----------------------------------------------------------------------------
-- COMINATORIAL SIGNALS
-----------------------------------------------------------------------------
 
 
add_n <=
std_logic_vector(resize(unsigned(n_data_in(r_addr_width_c-1 downto 0)),
r_addr_width_c+1)
+ to_unsigned(1, r_addr_width_c+1));
add_e <=
std_logic_vector(resize(unsigned(
e_data_in(c_addr_width_c + r_addr_width_c-1 downto r_addr_width_c)),
c_addr_width_c+1)
+ to_unsigned(1, c_addr_width_c+1));
add_s <=
std_logic_vector(resize(unsigned(s_data_in(r_addr_width_c-1 downto 0)),
r_addr_width_c+1)
+ to_unsigned(1, r_addr_width_c+1));
add_w <=
std_logic_vector(resize(unsigned(
w_data_in(c_addr_width_c + r_addr_width_c-1 downto r_addr_width_c)),
c_addr_width_c+1)
+ to_unsigned(1, c_addr_width_c+1));
 
with a_av_in select
data_a <=
a_data_in when '1',
a_data_in(bus_width_g-1 downto c_addr_width_c+r_addr_width_c) &
std_logic_vector(unsigned(a_data_in(c_addr_width_c+r_addr_width_c-1
downto r_addr_width_c)) +
unsigned(add_ac_r)) &
std_logic_vector(unsigned(a_data_in(r_addr_width_c-1 downto 0)) +
unsigned(add_ar_r)) when others;
 
reroute_n <= add_n(r_addr_width_c);
reroute_e <= add_e(c_addr_width_c);
reroute_s <= add_s(r_addr_width_c);
reroute_w <= add_w(c_addr_width_c);
 
here_n <= n_data_in(here_index_c);
here_s <= s_data_in(here_index_c);
here_n_prev <= n_data_in_r(here_index_c);
here_s_prev <= s_data_in_r(here_index_c);
 
lr_n <= n_data_in(lr_index_c);
lr_s <= s_data_in(lr_index_c);
lr_n_prev <= n_data_in_r(lr_index_c);
lr_s_prev <= s_data_in_r(lr_index_c);
 
a_first_hi <= a_data_in(first_index_h_c);
a_first_lo <= a_data_in(first_index_l_c);
a_first_hi_prev <= a_data_in_r(first_index_h_c);
a_first_lo_prev <= a_data_in_r(first_index_l_c);
 
data_n <= n_data_in(bus_width_g-1 downto r_addr_width_c) &
add_n(r_addr_width_c-1 downto 0);
data_e <= e_data_in(bus_width_g-1 downto c_addr_width_c + r_addr_width_c) &
add_e(c_addr_width_c-1 downto 0) &
e_data_in(r_addr_width_c-1 downto 0);
data_s <= s_data_in(bus_width_g-1 downto r_addr_width_c) &
add_s(r_addr_width_c-1 downto 0);
data_w <= w_data_in(bus_width_g-1 downto c_addr_width_c + r_addr_width_c) &
add_w(c_addr_width_c-1 downto 0) &
w_data_in(r_addr_width_c-1 downto 0);
req_n_e <= ((n_av_in and not n_stall_out_r) and reroute_n and (not here_n) and
(not lr_n)) or
(n_av_in_r and reroute_n_r and (not here_n_prev) and
(not lr_n_prev));
req_n_s <= ((n_av_in and not n_stall_out_r) and (not reroute_n)) or
(n_av_in_r and (not reroute_n_r));
req_n_w <= ((n_av_in and not n_stall_out_r) and reroute_n and (not here_n) and
(lr_n)) or
(n_av_in_r and reroute_n_r and (not here_n_prev) and
(lr_n_prev));
req_n_a <= ((n_av_in and not n_stall_out_r) and reroute_n and here_n) or
(n_av_in_r and reroute_n_r and here_n_prev);
req_e_w <= ((e_av_in and not e_stall_out_r) and (not reroute_e)) or
(e_av_in_r and (not reroute_e_r));
req_e_a <= ((e_av_in and not e_stall_out_r) and reroute_e) or
(e_av_in_r and reroute_e_r);
req_s_n <= ((s_av_in and not s_stall_out_r) and (not reroute_s)) or
(s_av_in_r and (not reroute_s_r));
req_s_e <= ((s_av_in and not s_stall_out_r) and reroute_s and (not here_s) and
(not lr_s)) or
(s_av_in_r and reroute_s_r and (not here_s_prev) and
(not lr_s_prev));
req_s_w <= ((s_av_in and not s_stall_out_r) and reroute_s and (not here_s) and
(lr_s)) or
(s_av_in_r and reroute_s_r and (not here_s_prev) and
(lr_s_prev));
req_s_a <= ((s_av_in and not s_stall_out_r) and reroute_s and here_s) or
(s_av_in_r and reroute_s_r and here_s_prev);
 
-- (was just w_av_in )
req_w_e <= ((w_av_in and not w_stall_out_r) and (not reroute_w)) or
(w_av_in_r and (not reroute_w_r));
req_w_a <= ((w_av_in and not w_stall_out_r) and reroute_w) or
(w_av_in_r and reroute_w_r);
-- ( was just a_av_in )
req_a_n <= ((a_av_in and not a_stall_out_r) and (not a_first_hi)
and (not a_first_lo)) or
(a_av_in_r and (not a_first_hi_prev)
and (not a_first_lo_prev));
req_a_e <= ((a_av_in and not a_stall_out_r) and (not a_first_hi)
and a_first_lo) or
(a_av_in_r and (not a_first_hi_prev)
and a_first_lo_prev);
req_a_s <= ((a_av_in and not a_stall_out_r) and a_first_hi
and (not a_first_lo)) or
(a_av_in_r and a_first_hi_prev
and (not a_first_lo_prev));
req_a_w <= ((a_av_in and not a_stall_out_r) and a_first_hi
and a_first_lo) or
(a_av_in_r and a_first_hi_prev
and a_first_lo_prev);
 
grant_s_n <= (req_s_n
and (not (grant_a_n_r and a_da_in and (not a_av_in)))
and (not (grant_a_n_r and a_da_in_r and (not a_av_in_r)))) or
(s_da_in and (not s_av_in) and grant_s_n_r) or
(s_da_in_r and (not s_av_in_r) and grant_s_n_r);
grant_a_n <= (req_a_n
and (not (grant_s_n))) or
(a_da_in and (not a_av_in) and grant_a_n_r) or
(a_da_in_r and (not a_av_in_r) and grant_a_n_r);
grant_n_e <= (req_n_e
and (not (s_da_in and (not s_av_in) and grant_s_e_r))
and (not (s_da_in_r and (not s_av_in_r) and grant_s_e_r))
and (not (w_da_in and (not w_av_in) and grant_w_e_r))
and (not (w_da_in_r and (not w_av_in_r) and grant_w_e_r))
and (not (a_da_in and (not a_av_in) and grant_a_e_r))
and (not (a_da_in_r and (not a_av_in_r) and grant_a_e_r))) or
(n_da_in and (not n_av_in) and grant_n_e_r) or
(n_da_in_r and (not n_av_in_r) and grant_n_e_r);
grant_s_e <= (req_s_e
and (not (grant_n_e))
and (not (w_da_in and (not w_av_in) and grant_w_e_r))
and (not (w_da_in_r and (not w_av_in_r) and grant_w_e_r))
and (not (a_da_in and (not a_av_in) and grant_a_e_r))
and (not (a_da_in_r and (not a_av_in_r) and grant_a_e_r))) or
(s_da_in and (not s_av_in) and grant_s_e_r) or
(s_da_in_r and (not s_av_in_r) and grant_s_e_r);
grant_w_e <= (req_w_e
and (not (grant_n_e))
and (not (grant_s_e))
and (not (a_da_in and (not a_av_in) and grant_a_e_r))
and (not (a_da_in_r and (not a_av_in_r) and grant_a_e_r))) or
(w_da_in and (not w_av_in) and grant_w_e_r) or
(w_da_in_r and (not w_av_in_r) and grant_w_e_r);
grant_a_e <= (req_a_e
and (not (grant_n_e))
and (not (grant_s_e))
and (not (grant_w_e))) or
(a_da_in and (not a_av_in) and grant_a_e_r) or
(a_da_in_r and (not a_av_in_r) and grant_a_e_r);
 
grant_n_s <= (req_n_s
and (not (a_da_in and (not a_av_in) and grant_a_s_r))
and (not (a_da_in_r and (not a_av_in_r) and grant_a_s_r))) or
(n_da_in and (not n_av_in) and grant_n_s_r) or
(n_da_in_r and (not n_av_in_r) and grant_n_s_r);
grant_a_s <= (req_a_s
and (not (grant_n_s))) or
(a_da_in and (not a_av_in) and grant_a_s_r) or
(a_da_in_r and (not a_av_in_r) and grant_a_s_r);
 
grant_n_w <= (req_n_w
and (not (s_da_in and (not s_av_in) and grant_s_w_r))
and (not (s_da_in_r and (not s_av_in_r) and grant_s_w_r))
and (not (e_da_in and (not e_av_in) and grant_e_w_r))
and (not (e_da_in_r and (not e_av_in_r) and grant_e_w_r))
and (not (a_da_in and (not a_av_in) and grant_a_w_r))
and (not (a_da_in_r and (not a_av_in_r) and grant_a_w_r))) or
(n_da_in and (not n_av_in) and grant_n_w_r) or
(n_da_in_r and (not n_av_in_r) and grant_n_w_r);
grant_e_w <= (req_e_w
and (not (grant_n_w))
and (not (s_da_in and (not s_av_in) and grant_s_w_r))
and (not (s_da_in_r and (not s_av_in_r) and grant_s_w_r))
and (not (a_da_in and (not a_av_in) and grant_a_w_r))
and (not (a_da_in_r and (not a_av_in_r) and grant_a_w_r))) or
(e_da_in and (not e_av_in) and grant_e_w_r) or
(e_da_in_r and (not e_av_in_r) and grant_e_w_r);
grant_s_w <= (req_s_w
and (not (grant_n_w))
and (not (grant_e_w))
and (not (a_da_in and (not a_av_in) and grant_a_w_r))
and (not (a_da_in_r and (not a_av_in_r) and grant_a_w_r))) or
(s_da_in and (not s_av_in) and grant_s_w_r) or
(s_da_in_r and (not s_av_in_r) and grant_s_w_r);
grant_a_w <= (req_a_w
and (not (grant_n_w))
and (not (grant_s_w))
and (not (grant_e_w))) or
(a_da_in and (not a_av_in) and grant_a_w_r) or
(a_da_in_r and (not a_av_in_r) and grant_a_w_r);
 
grant_n_a <= (req_n_a
and (not (s_da_in and (not s_av_in) and grant_s_a_r))
and (not (s_da_in_r and (not s_av_in_r) and grant_s_a_r))
and (not (w_da_in and (not w_av_in) and grant_w_a_r))
and (not (w_da_in_r and (not w_av_in_r) and grant_w_a_r))
and (not (e_da_in and (not e_av_in) and grant_e_a_r))
and (not (e_da_in_r and (not e_av_in_r) and grant_e_a_r))) or
(n_da_in and (not n_av_in) and grant_n_a_r) or
(n_da_in_r and (not n_av_in_r) and grant_n_a_r);
grant_e_a <= (req_e_a
and (not (grant_n_a))
and (not (s_da_in and (not s_av_in) and grant_s_a_r))
and (not (s_da_in_r and (not s_av_in_r) and grant_s_a_r))
and (not (w_da_in and (not w_av_in) and grant_w_a_r))
and (not (w_da_in_r and (not w_av_in_r) and grant_w_a_r))) or
(e_da_in and (not e_av_in) and grant_e_a_r) or
(e_da_in_r and (not e_av_in_r) and grant_e_a_r);
grant_s_a <= (req_s_a
and (not (grant_n_a))
and (not (grant_e_a))
and (not (w_da_in and (not w_av_in) and grant_w_a_r))
and (not (w_da_in_r and (not w_av_in_r) and grant_w_a_r))) or
(s_da_in and (not s_av_in) and grant_s_a_r) or
(s_da_in_r and (not s_av_in_r) and grant_s_a_r);
grant_w_a <= (req_w_a
and (not (grant_n_a))
and (not (grant_e_a))
and (not (grant_s_a))) or
(w_da_in and (not w_av_in) and grant_w_a_r) or
(w_da_in_r and (not w_av_in_r) and grant_w_a_r);
 
stall_n <= (req_n_e and (not grant_n_e or e_stall_in)) or
(grant_n_e_r and e_stall_in) or
(req_n_s and (not grant_n_s or s_stall_in)) or
(grant_n_s_r and s_stall_in) or
(req_n_w and (not grant_n_w or w_stall_in)) or
(grant_n_w_r and w_stall_in) or
(req_n_a and (not grant_n_a or a_stall_in)) or
(grant_n_a_r and a_stall_in);
stall_e <= (req_e_w and (not grant_e_w or w_stall_in)) or
(grant_e_w_r and w_stall_in) or
(req_e_a and (not grant_e_a or a_stall_in)) or
(grant_e_a_r and a_stall_in);
stall_s <= (req_s_e and (not grant_s_e or e_stall_in)) or
(grant_s_e_r and e_stall_in) or
(req_s_n and (not grant_s_n or n_stall_in)) or
(grant_s_n_r and n_stall_in) or
(req_s_w and (not grant_s_w or w_stall_in)) or
(grant_s_w_r and w_stall_in) or
(req_s_a and (not grant_s_a or a_stall_in)) or
(grant_s_a_r and a_stall_in);
stall_w <= (req_w_e and (not grant_w_e or e_stall_in)) or
(grant_w_e_r and e_stall_in) or
(req_w_a and (not grant_w_a or a_stall_in)) or
(grant_w_a_r and a_stall_in);
stall_a <= (req_a_n and (not grant_a_n or n_stall_in)) or
(grant_a_n_r and n_stall_in) or
(req_a_e and (not grant_a_e or e_stall_in)) or
(grant_a_e_r and e_stall_in) or
(req_a_s and (not grant_a_s or s_stall_in)) or
(grant_a_s_r and s_stall_in) or
(req_a_w and (not grant_a_w or w_stall_in)) or
(grant_a_w_r and w_stall_in);
 
 
 
-----------------------------------------------------------------------------
-- SYNCHRONOUS SIGNALS
-----------------------------------------------------------------------------
 
regs_p : process (clk, rst_n) is
begin -- process regs_p
if rst_n = '0' then -- asynchronous reset (active low)
 
n_stall_out_r <= '0';
n_da_out_r <= '0';
n_av_out_r <= '0';
e_stall_out_r <= '0';
e_da_out_r <= '0';
e_av_out_r <= '0';
s_stall_out_r <= '0';
s_da_out_r <= '0';
s_av_out_r <= '0';
w_stall_out_r <= '0';
w_da_out_r <= '0';
w_av_out_r <= '0';
a_stall_out_r <= '0';
a_da_out_r <= '0';
a_av_out_r <= '0';
 
n_data_out_r <= (others => '0');
e_data_out_r <= (others => '0');
s_data_out_r <= (others => '0');
w_data_out_r <= (others => '0');
a_data_out_r <= (others => '0');
 
n_data_in_r <= (others => '0');
n_av_in_r <= '0';
n_da_in_r <= '0';
e_data_in_r <= (others => '0');
e_av_in_r <= '0';
e_da_in_r <= '0';
s_data_in_r <= (others => '0');
s_av_in_r <= '0';
s_da_in_r <= '0';
w_data_in_r <= (others => '0');
w_av_in_r <= '0';
w_da_in_r <= '0';
a_data_in_r <= (others => '0');
a_av_in_r <= '0';
a_da_in_r <= '0';
 
reroute_n_r <= '0';
reroute_e_r <= '0';
reroute_s_r <= '0';
reroute_w_r <= '0';
 
grant_s_n_r <= '0';
grant_a_n_r <= '0';
grant_n_e_r <= '0';
grant_s_e_r <= '0';
grant_w_e_r <= '0';
grant_a_e_r <= '0';
grant_n_s_r <= '0';
grant_a_s_r <= '0';
grant_n_w_r <= '0';
grant_e_w_r <= '0';
grant_s_w_r <= '0';
grant_a_w_r <= '0';
grant_n_a_r <= '0';
grant_e_a_r <= '0';
grant_s_a_r <= '0';
grant_w_a_r <= '0';
 
add_ar_r <= (others => '0');
add_ac_r <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
 
n_stall_out_r <= stall_n;
e_stall_out_r <= stall_e;
s_stall_out_r <= stall_s;
w_stall_out_r <= stall_w;
a_stall_out_r <= stall_a;
 
grant_s_n_r <= grant_s_n;
grant_a_n_r <= grant_a_n;
grant_n_e_r <= grant_n_e;
grant_s_e_r <= grant_s_e;
grant_w_e_r <= grant_w_e;
grant_a_e_r <= grant_a_e;
grant_n_s_r <= grant_n_s;
grant_a_s_r <= grant_a_s;
grant_n_w_r <= grant_n_w;
grant_e_w_r <= grant_e_w;
grant_s_w_r <= grant_s_w;
grant_a_w_r <= grant_a_w;
grant_n_a_r <= grant_n_a;
grant_e_a_r <= grant_e_a;
grant_s_a_r <= grant_s_a;
grant_w_a_r <= grant_w_a;
 
if a_av_in = '1' then
add_ar_r <= a_data_in(r_addr_width_c-1 downto 0);
add_ac_r <= a_data_in(c_addr_width_c+r_addr_width_c-1 downto
r_addr_width_c);
end if;
 
if stall_n = '1' and n_stall_out_r = '0' then
n_data_in_r <= data_n;
n_da_in_r <= n_da_in;
n_av_in_r <= n_av_in;
reroute_n_r <= reroute_n;
elsif stall_n = '0' and n_stall_out_r = '1' then
n_data_in_r <= (others => '0');
n_da_in_r <= '0';
n_av_in_r <= '0';
reroute_n_r <= '0';
end if;
 
if stall_e = '1' and e_stall_out_r = '0' then
e_data_in_r <= data_e;
e_da_in_r <= e_da_in;
e_av_in_r <= e_av_in;
reroute_e_r <= reroute_e;
elsif stall_e = '0' and e_stall_out_r = '1' then
e_data_in_r <= (others => '0');
e_da_in_r <= '0';
e_av_in_r <= '0';
reroute_e_r <= '0';
end if;
 
if stall_s = '1' and s_stall_out_r = '0' then
s_data_in_r <= data_s;
s_da_in_r <= s_da_in;
s_av_in_r <= s_av_in;
reroute_s_r <= reroute_s;
elsif stall_s = '0' and s_stall_out_r = '1' then
s_data_in_r <= (others => '0');
s_da_in_r <= '0';
s_av_in_r <= '0';
reroute_s_r <= '0';
end if;
 
if stall_w = '1' and w_stall_out_r = '0' then
w_data_in_r <= data_w;
w_da_in_r <= w_da_in;
w_av_in_r <= w_av_in;
reroute_w_r <= reroute_w;
elsif stall_w = '0' and w_stall_out_r = '1' then
w_data_in_r <= (others => '0');
w_da_in_r <= '0';
w_av_in_r <= '0';
reroute_w_r <= '0';
end if;
 
if stall_a = '1' and a_stall_out_r = '0' then
a_data_in_r <= data_a;
a_da_in_r <= a_da_in;
a_av_in_r <= a_av_in;
elsif stall_a = '0' and a_stall_out_r = '1' then
a_data_in_r <= (others => '0');
a_da_in_r <= '0';
a_av_in_r <= '0';
end if;
 
if e_stall_in = '1' then
 
elsif grant_n_e = '1' and e_stall_in = '0' and n_stall_out_r = '0' then
e_data_out_r <= data_n;
e_da_out_r <= n_da_in;
e_av_out_r <= n_av_in;
elsif grant_n_e = '1' and e_stall_in = '0' and n_stall_out_r = '1' then
e_data_out_r <= n_data_in_r;
e_da_out_r <= n_da_in_r;
e_av_out_r <= n_av_in_r;
elsif grant_s_e = '1' and e_stall_in = '0' and s_stall_out_r = '0' then
e_data_out_r <= data_s;
e_da_out_r <= s_da_in;
e_av_out_r <= s_av_in;
elsif grant_s_e = '1' and e_stall_in = '0' and s_stall_out_r = '1' then
e_data_out_r <= s_data_in_r;
e_da_out_r <= s_da_in_r;
e_av_out_r <= s_av_in_r;
elsif grant_w_e = '1' and e_stall_in = '0' and w_stall_out_r = '0' then
e_data_out_r <= data_w;
e_da_out_r <= w_da_in;
e_av_out_r <= w_av_in;
elsif grant_w_e = '1' and e_stall_in = '0' and w_stall_out_r = '1' then
e_data_out_r <= w_data_in_r;
e_da_out_r <= w_da_in_r;
e_av_out_r <= w_av_in_r;
elsif grant_a_e = '1' and e_stall_in = '0' and a_stall_out_r = '0' then
e_data_out_r <= data_a;
e_da_out_r <= a_da_in;
e_av_out_r <= a_av_in;
elsif grant_a_e = '1' and e_stall_in = '0' and a_stall_out_r = '1' then
e_data_out_r <= a_data_in_r;
e_da_out_r <= a_da_in_r;
e_av_out_r <= a_av_in_r;
elsif grant_n_e = '0' and grant_s_e = '0'
and grant_w_e = '0' and grant_a_e = '0' then
e_data_out_r <= (others => '0');
e_da_out_r <= '0';
e_av_out_r <= '0';
end if;
 
if s_stall_in = '1' then
 
elsif grant_n_s = '1' and s_stall_in = '0' and n_stall_out_r = '0' then
s_data_out_r <= data_n;
s_da_out_r <= n_da_in;
s_av_out_r <= n_av_in;
elsif grant_n_s = '1' and s_stall_in = '0' and n_stall_out_r = '1' then
s_data_out_r <= n_data_in_r;
s_da_out_r <= n_da_in_r;
s_av_out_r <= n_av_in_r;
elsif grant_a_s = '1' and s_stall_in = '0' and a_stall_out_r = '0' then
s_data_out_r <= data_a;
s_da_out_r <= a_da_in;
s_av_out_r <= a_av_in;
elsif grant_a_s = '1' and s_stall_in = '0' and a_stall_out_r = '1' then
s_data_out_r <= a_data_in_r;
s_da_out_r <= a_da_in_r;
s_av_out_r <= a_av_in_r;
elsif grant_n_s = '0' and grant_a_s = '0' then
s_data_out_r <= (others => '0');
s_da_out_r <= '0';
s_av_out_r <= '0';
end if;
 
if w_stall_in = '1' then
 
elsif grant_n_w = '1' and w_stall_in = '0' and n_stall_out_r = '0' then
w_data_out_r <= data_n;
w_da_out_r <= n_da_in;
w_av_out_r <= n_av_in;
elsif grant_n_w = '1' and w_stall_in = '0' and n_stall_out_r = '1' then
w_data_out_r <= n_data_in_r;
w_da_out_r <= n_da_in_r;
w_av_out_r <= n_av_in_r;
elsif grant_s_w = '1' and w_stall_in = '0' and s_stall_out_r = '0' then
w_data_out_r <= data_s;
w_da_out_r <= s_da_in;
w_av_out_r <= s_av_in;
elsif grant_s_w = '1' and w_stall_in = '0' and s_stall_out_r = '1' then
w_data_out_r <= s_data_in_r;
w_da_out_r <= s_da_in_r;
w_av_out_r <= s_av_in_r;
elsif grant_e_w = '1' and w_stall_in = '0' and e_stall_out_r = '0' then
w_data_out_r <= data_e;
w_da_out_r <= e_da_in;
w_av_out_r <= e_av_in;
elsif grant_e_w = '1' and w_stall_in = '0' and e_stall_out_r = '1' then
w_data_out_r <= e_data_in_r;
w_da_out_r <= e_da_in_r;
w_av_out_r <= e_av_in_r;
elsif grant_a_w = '1' and w_stall_in = '0' and a_stall_out_r = '0' then
w_data_out_r <= data_a;
w_da_out_r <= a_da_in;
w_av_out_r <= a_av_in;
elsif grant_a_w = '1' and w_stall_in = '0' and a_stall_out_r = '1' then
w_data_out_r <= a_data_in_r;
w_da_out_r <= a_da_in_r;
w_av_out_r <= a_av_in_r;
elsif grant_n_w = '0' and grant_e_w = '0'
and grant_s_w = '0' and grant_a_w = '0' then
w_data_out_r <= (others => '0');
w_da_out_r <= '0';
w_av_out_r <= '0';
end if;
 
if n_stall_in = '1' then
 
elsif grant_s_n = '1' and n_stall_in = '0' and s_stall_out_r = '0' then
n_data_out_r <= data_s;
n_da_out_r <= s_da_in;
n_av_out_r <= s_av_in;
elsif grant_s_n = '1' and n_stall_in = '0' and s_stall_out_r = '1' then
n_data_out_r <= s_data_in_r;
n_da_out_r <= s_da_in_r;
n_av_out_r <= s_av_in_r;
elsif grant_a_n = '1' and n_stall_in = '0' and a_stall_out_r = '0' then
n_data_out_r <= data_a;
n_da_out_r <= a_da_in;
n_av_out_r <= a_av_in;
elsif grant_a_n = '1' and n_stall_in = '0' and a_stall_out_r = '1' then
n_data_out_r <= a_data_in_r;
n_da_out_r <= a_da_in_r;
n_av_out_r <= a_av_in_r;
elsif grant_s_n = '0' and grant_a_n = '0' then
n_data_out_r <= (others => '0');
n_da_out_r <= '0';
n_av_out_r <= '0';
end if;
 
if a_stall_in = '1' then
 
elsif grant_n_a = '1' and a_stall_in = '0' and n_stall_out_r = '0' then
a_data_out_r <= data_n;
a_da_out_r <= n_da_in;
a_av_out_r <= n_av_in;
elsif grant_n_a = '1' and a_stall_in = '0' and n_stall_out_r = '1' then
a_data_out_r <= n_data_in_r;
a_da_out_r <= n_da_in_r;
a_av_out_r <= n_av_in_r;
elsif grant_s_a = '1' and a_stall_in = '0' and s_stall_out_r = '0' then
a_data_out_r <= data_s;
a_da_out_r <= s_da_in;
a_av_out_r <= s_av_in;
elsif grant_s_a = '1' and a_stall_in = '0' and s_stall_out_r = '1' then
a_data_out_r <= s_data_in_r;
a_da_out_r <= s_da_in_r;
a_av_out_r <= s_av_in_r;
elsif grant_e_a = '1' and a_stall_in = '0' and e_stall_out_r = '0' then
a_data_out_r <= data_e;
a_da_out_r <= e_da_in;
a_av_out_r <= e_av_in;
elsif grant_e_a = '1' and a_stall_in = '0' and e_stall_out_r = '1' then
a_data_out_r <= e_data_in_r;
a_da_out_r <= e_da_in_r;
a_av_out_r <= e_av_in_r;
elsif grant_w_a = '1' and a_stall_in = '0' and w_stall_out_r = '0' then
a_data_out_r <= data_w;
a_da_out_r <= w_da_in;
a_av_out_r <= w_av_in;
elsif grant_w_a = '1' and a_stall_in = '0' and w_stall_out_r = '1' then
a_data_out_r <= w_data_in_r;
a_da_out_r <= w_da_in_r;
a_av_out_r <= w_av_in_r;
elsif grant_n_a = '0' and grant_e_a = '0'
and grant_s_a = '0' and grant_w_a = '0' then
a_data_out_r <= (others => '0');
a_da_out_r <= '0';
a_av_out_r <= '0';
end if;
end if;
end process regs_p;
 
 
end architecture rtl;
/trunk/TUT/ip.hwp.communication/ase_mesh1/ase_mesh1_top4/1.0/vhd/ase_mesh1.vhd
0,0 → 1,168
-------------------------------------------------------------------------------
-- Title : 2D mesh mk1 by ase
-- Project :
-------------------------------------------------------------------------------
-- File : ase_mesh1.vhdl
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2010-06-14
-- Last update: 2011-10-07
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-14 1.0 ase Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity ase_mesh1 is
 
generic (
n_rows_g : positive := 4; -- Nuber of rows
n_cols_g : positive := 4; -- Nuber of columns
cmd_width_g : positive := 2; -- Width of the cmd line
bus_width_g : positive := 32); -- Width of the data bus
port (
clk : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector(n_rows_g*n_cols_g*bus_width_g-1 downto 0);
cmd_in : in std_logic_vector(n_rows_g*n_cols_g*cmd_width_g-1 downto 0);
stall_out : out std_logic_vector(n_rows_g*n_cols_g-1 downto 0);
data_out : out std_logic_vector(n_rows_g*n_cols_g*bus_width_g-1 downto 0);
cmd_out : out std_logic_vector(n_rows_g*n_cols_g*cmd_width_g-1 downto 0);
stall_in : in std_logic_vector(n_rows_g*n_cols_g-1 downto 0));
 
end entity ase_mesh1;
 
 
architecture rtl of ase_mesh1 is
 
-- row data
type r_data_type is array (0 to n_rows_g) of
std_logic_vector(n_cols_g*bus_width_g-1 downto 0);
type r_bit_type is array (0 to n_rows_g) of
std_logic_vector(n_cols_g-1 downto 0);
signal sn_data : r_data_type;
signal sn_av : r_bit_type;
signal sn_da : r_bit_type;
signal sn_stall : r_bit_type;
 
signal ns_data : r_data_type;
signal ns_av : r_bit_type;
signal ns_da : r_bit_type;
signal ns_stall : r_bit_type;
 
-- col data
type c_data_type is array (0 to n_cols_g) of
std_logic_vector(n_rows_g*bus_width_g-1 downto 0);
type c_bit_type is array (0 to n_cols_g) of
std_logic_vector(n_rows_g-1 downto 0);
signal ew_data : c_data_type;
signal ew_av : c_bit_type;
signal ew_da : c_bit_type;
signal ew_stall : c_bit_type;
 
signal we_data : c_data_type;
signal we_av : c_bit_type;
signal we_da : c_bit_type;
signal we_stall : c_bit_type;
 
begin -- architecture rtl
 
ns_data(0) <= (others => '0');
ns_av(0) <= (others => '0');
ns_da(0) <= (others => '0');
ns_stall(n_rows_g) <= (others => '0');
 
we_data(0) <= (others => '0');
we_av(0) <= (others => '0');
we_da(0) <= (others => '0');
we_stall(n_cols_g) <= (others => '0');
 
sn_data(n_rows_g) <= (others => '0');
sn_av(n_rows_g) <= (others => '0');
sn_da(n_rows_g) <= (others => '0');
sn_stall(0) <= (others => '0');
 
ew_data(n_cols_g) <= (others => '0');
ew_av(n_cols_g) <= (others => '0');
ew_da(n_cols_g) <= (others => '0');
ew_stall(0) <= (others => '0');
 
 
 
row : for r in 0 to n_rows_g-1 generate
col : for c in 0 to n_cols_g-1 generate
 
i_router : entity work.ase_mesh1_router(rtl)
generic map (
n_rows_g => n_rows_g,
n_cols_g => n_cols_g,
bus_width_g => bus_width_g)
port map (
clk => clk,
rst_n => rst_n,
 
a_data_in => data_in(((r*n_cols_g)+c+1)*bus_width_g-1 downto
((r*n_cols_g)+c)*bus_width_g),
a_da_in => cmd_in(2*((r*n_cols_g)+c)+1),
a_av_in => cmd_in(2*((r*n_cols_g)+c)),
a_stall_out => stall_out((r*n_cols_g)+c),
a_data_out => data_out(((r*n_cols_g)+c+1)*bus_width_g-1 downto
((r*n_cols_g)+c)*bus_width_g),
a_da_out => cmd_out(2*((r*n_cols_g)+c)+1),
a_av_out => cmd_out(2*((r*n_cols_g)+c)),
a_stall_in => stall_in((r*n_cols_g)+c),
 
n_data_in => ns_data(r)((c+1)*bus_width_g-1 downto c*bus_width_g),
n_da_in => ns_da(r)(c),
n_av_in => ns_av(r)(c),
n_stall_out => ns_stall(r)(c),
n_data_out => sn_data(r)((c+1)*bus_width_g-1 downto c*bus_width_g),
n_da_out => sn_da(r)(c),
n_av_out => sn_av(r)(c),
n_stall_in => sn_stall(r)(c),
 
e_data_in => ew_data(c+1)((r+1)*bus_width_g-1 downto r*bus_width_g),
e_da_in => ew_da(c+1)(r),
e_av_in => ew_av(c+1)(r),
e_stall_out => ew_stall(c+1)(r),
e_data_out => we_data(c+1)((r+1)*bus_width_g-1 downto r*bus_width_g),
e_da_out => we_da(c+1)(r),
e_av_out => we_av(c+1)(r),
e_stall_in => we_stall(c+1)(r),
 
s_data_in => sn_data(r+1)((c+1)*bus_width_g-1 downto c*bus_width_g),
s_da_in => sn_da(r+1)(c),
s_av_in => sn_av(r+1)(c),
s_stall_out => sn_stall(r+1)(c),
s_data_out => ns_data(r+1)((c+1)*bus_width_g-1 downto c*bus_width_g),
s_da_out => ns_da(r+1)(c),
s_av_out => ns_av(r+1)(c),
s_stall_in => ns_stall(r+1)(c),
 
w_data_in => we_data(c)((r+1)*bus_width_g-1 downto r*bus_width_g),
w_da_in => we_da(c)(r),
w_av_in => we_av(c)(r),
w_stall_out => we_stall(c)(r),
w_data_out => ew_data(c)((r+1)*bus_width_g-1 downto r*bus_width_g),
w_da_out => ew_da(c)(r),
w_av_out => ew_av(c)(r),
w_stall_in => ew_stall(c)(r));
 
end generate col;
end generate row;
 
 
end architecture rtl;
/trunk/TUT/ip.hwp.communication/ase_mesh1/ase_mesh1_top4/1.0/vhd/ase_mesh1_top4.vhd
0,0 → 1,121
-------------------------------------------------------------------------------
-- Title : 4 agent top level for ase_mesh1
-- Project :
-------------------------------------------------------------------------------
-- File : ase_mesh1_top4.vhd
-- Author : Lasse Lehtonen
-- Company :
-- Created : 2011-11-09
-- Last update: 2011-11-09
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-11-09 1.0 lehton87 Created
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
 
entity ase_mesh1_top4 is
port (
clk : in std_logic;
rst_n : in std_logic;
cmd0_in : in std_logic_vector(1 downto 0);
data0_in : in std_logic_vector(31 downto 0);
stall0_out : out std_logic;
cmd0_out : out std_logic_vector(1 downto 0);
data0_out : out std_logic_vector(31 downto 0);
stall0_in : in std_logic;
cmd1_in : in std_logic_vector(1 downto 0);
data1_in : in std_logic_vector(31 downto 0);
stall1_out : out std_logic;
cmd1_out : out std_logic_vector(1 downto 0);
data1_out : out std_logic_vector(31 downto 0);
stall1_in : in std_logic;
cmd2_in : in std_logic_vector(1 downto 0);
data2_in : in std_logic_vector(31 downto 0);
stall2_out : out std_logic;
cmd2_out : out std_logic_vector(1 downto 0);
data2_out : out std_logic_vector(31 downto 0);
stall2_in : in std_logic;
cmd3_in : in std_logic_vector(1 downto 0);
data3_in : in std_logic_vector(31 downto 0);
stall3_out : out std_logic;
cmd3_out : out std_logic_vector(1 downto 0);
data3_out : out std_logic_vector(31 downto 0);
stall3_in : in std_logic);
 
end ase_mesh1_top4;
 
architecture rtl of ase_mesh1_top4 is
 
signal cmd_i : std_logic_vector(4*2-1 downto 0);
signal data_i : std_logic_vector(4*32-1 downto 0);
signal stall_i : std_logic_vector(3 downto 0);
signal cmd_o : std_logic_vector(4*2-1 downto 0);
signal data_o : std_logic_vector(4*32-1 downto 0);
signal stall_o : std_logic_vector(3 downto 0);
begin -- rtl
 
cmd_i((0+1)*2-1 downto 0*2) <= cmd0_in;
data_i((0+1)*32-1 downto 0*32) <= data0_in;
stall_i(0) <= stall0_in;
cmd0_out <= cmd_o((0+1)*2-1 downto 0*2);
data0_out <= data_o((0+1)*32-1 downto 0*32);
stall0_out <= stall_o(0);
 
cmd_i((1+1)*2-1 downto 1*2) <= cmd1_in;
data_i((1+1)*32-1 downto 1*32) <= data1_in;
stall_i(1) <= stall1_in;
cmd1_out <= cmd_o((1+1)*2-1 downto 1*2);
data1_out <= data_o((1+1)*32-1 downto 1*32);
stall1_out <= stall_o(1);
 
cmd_i((2+1)*2-1 downto 2*2) <= cmd2_in;
data_i((2+1)*32-1 downto 2*32) <= data2_in;
stall_i(2) <= stall2_in;
cmd2_out <= cmd_o((2+1)*2-1 downto 2*2);
data2_out <= data_o((2+1)*32-1 downto 2*32);
stall2_out <= stall_o(2);
 
cmd_i((3+1)*2-1 downto 3*2) <= cmd3_in;
data_i((3+1)*32-1 downto 3*32) <= data3_in;
stall_i(3) <= stall3_in;
cmd3_out <= cmd_o((3+1)*2-1 downto 3*2);
data3_out <= data_o((3+1)*32-1 downto 3*32);
stall3_out <= stall_o(3);
 
ase_mesh1_pkt_codec_1 : entity work.ase_mesh1_pkt_codec
generic map (
data_width_g => 32,
cmd_width_g => 2,
agents_g => 4,
cols_g => 2,
rows_g => 2,
agent_ports_g => 1,
addr_flit_en_g => 0,
address_mode_g => 1,
clock_mode_g => 0,
rip_addr_g => 0,
fifo_depth_g => 0)
port map (
clk_ip => clk,
clk_net => clk,
rst_n => rst_n,
cmd_in => cmd_i,
data_in => data_i,
stall_out => stall_o,
cmd_out => cmd_o,
data_out => data_o,
stall_in => stall_i);
 
end rtl;
/trunk/TUT/ip.hwp.communication/ase_mesh1/ase_mesh1_top4/1.0/ase_mesh1_top4.1.0.xml
0,0 → 1,1053
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 19:47:31 ke marras 9 2011-->
<spirit:component>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>ip.hwp.communication</spirit:library>
<spirit:name>ase_mesh1_top4</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clock</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>port0</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_IN</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall0_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_OUT</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>data0_out</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_OUT</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd0_out</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_OUT</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall0_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_IN</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>data0_in</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_IN</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd0_in</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>port1</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2.absDef" spirit:version="1.0"/>
<spirit:mirroredMaster/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_IN</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall1_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_OUT</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>data1_out</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_OUT</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd1_out</spirit:name>
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<spirit:right>0</spirit:right>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_OUT</spirit:name>
<spirit:vector>
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<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall1_out</spirit:name>
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<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_IN</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>data1_in</spirit:name>
<spirit:vector>
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<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_IN</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd1_in</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
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</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>port2</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2.absDef" spirit:version="1.0"/>
<spirit:mirroredMaster/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_IN</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall2_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_OUT</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>data2_out</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_OUT</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
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<spirit:vector>
<spirit:left>1</spirit:left>
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</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_OUT</spirit:name>
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</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
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<spirit:portMap>
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<spirit:name>DATA_IN</spirit:name>
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<spirit:physicalPort>
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<spirit:vector>
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</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_IN</spirit:name>
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</spirit:vector>
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<spirit:physicalPort>
<spirit:name>cmd2_in</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>port3</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="pkt_codec_mk2.absDef" spirit:version="1.0"/>
<spirit:mirroredMaster/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_IN</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
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</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall3_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_OUT</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>data3_out</spirit:name>
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<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_OUT</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd3_out</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>STALL_OUT</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>stall3_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA_IN</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>data3_in</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CMD_IN</spirit:name>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cmd3_in</spirit:name>
<spirit:vector>
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<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>reset</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
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<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RESETn</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>rst_n</spirit:name>
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</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
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<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:ports>
<spirit:port>
<spirit:name>clk</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
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