OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

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  • This comparison shows the changes necessary to convert path 
    /funbase_ip_library
    from Rev 60 to Rev 61
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  •

Rev 60 → Rev 61

/trunk/TUT/soc/altera_de_II_demo/1.0/altera_de_II_demo.1.0.xml
1,5 → 1,5
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 15:33:02 to loka 27 2011-->
<!--Created by Kactus 2 document generator 14:43:57 ke marras 16 2011-->
<spirit:component>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
8,6 → 8,7
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:description>clk input</spirit:description>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
35,6 → 36,7
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>port_out</spirit:name>
<spirit:description>port_out to leds</spirit:description>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="toggle_in" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="toggle_in.absDef" spirit:version="1.0"/>
<spirit:master/>
62,6 → 64,7
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>rst_n</spirit:name>
<spirit:description>active low reset in</spirit:description>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
<spirit:slave/>
203,9 → 206,18
<spirit:buildCommand>
<spirit:replaceDefaultFlags>false</spirit:replaceDefaultFlags>
</spirit:buildCommand>
<spirit:description>Pinmap file for Altera DE2 development board</spirit:description>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Simple demo for Altera DE2 development board.Instantietes two components sig_gen and port blinker.
Sig_gen reads switch[17] from DE2 board and activates port blinker to blink leds in DE2 Board.
 
DEMO INSTRUCTIONS.
1. Open altera_de_II_demo design in Kactus2
2. Generate top-level VHDL with Kactus2 vhdl generator the ribbon
3. Generate Qurtus project for synthesizing demo design by clicking Quartus project generator in the ribbon element.
4. Open generated project with quartus. Compile and synthesize.</spirit:description>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd
1,6 → 1,6
-- ****************************************************
-- ** File: altera_de_II_demo.vhd
-- ** Date: 27.10.2011 15:33:01
-- ** Date: 15.11.2011 16:25:14
-- ** Description:
-- **
-- ** This file was generated by Kactus2 vhdl generator
59,19 → 59,19
 
port_blinker_1 : port_blinker
port map (
ena_in => port_blinker_1_ena_in_sig_gen_1_ena_out,
clk => clk,
rst_n => rst_n,
val_in(31 downto 0) => port_blinker_1_val_in_sig_gen_1_sig_out(31 downto 0),
port_out => port_out,
ena_in => port_blinker_1_ena_in_sig_gen_1_ena_out,
clk => clk);
val_in(31 downto 0) => port_blinker_1_val_in_sig_gen_1_sig_out(31 downto 0));
 
sig_gen_1 : sig_gen
port map (
ena_out => port_blinker_1_ena_in_sig_gen_1_ena_out,
sig_out(31 downto 0) => port_blinker_1_val_in_sig_gen_1_sig_out(31 downto 0),
ena_out => port_blinker_1_ena_in_sig_gen_1_ena_out,
clk => clk,
rst_n => rst_n,
toggle_in => toggle_in,
rst_n => rst_n);
clk => clk);
 
end structural;
 
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.flow.rpt
1,5 → 1,5
Flow report for altera_de_II_demo
Fri Oct 28 11:32:49 2011
Tue Nov 15 16:26:23 2011
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
 
 
38,7 → 38,7
+-------------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+------------------------------------------------+
; Flow Status ; Successful - Fri Oct 28 11:32:49 2011 ;
; Flow Status ; Successful - Tue Nov 15 16:26:23 2011 ;
; Quartus II Version ; 11.0 Build 208 07/03/2011 SP 1 SJ Full Version ;
; Revision Name ; altera_de_II_demo ;
; Top-level Entity Name ; altera_de_II_demo ;
62,7 → 62,7
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 10/28/2011 11:32:29 ;
; Start date & time ; 11/15/2011 16:26:05 ;
; Main task ; Compilation ;
; Revision Name ; altera_de_II_demo ;
+-------------------+---------------------+
73,7 → 73,7
+-------------------------------------+------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 146449710050.131979074904228 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 146449710050.132136716403372 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
85,11 → 85,11
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 250 MB ; 00:00:01 ;
; Fitter ; 00:00:08 ; 1.2 ; 344 MB ; 00:00:06 ;
; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 236 MB ; 00:00:01 ;
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 250 MB ; 00:00:01 ;
; Fitter ; 00:00:06 ; 1.3 ; 344 MB ; 00:00:06 ;
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 236 MB ; 00:00:02 ;
; Assembler ; 00:00:03 ; 1.0 ; 271 MB ; 00:00:02 ;
; Total ; 00:00:18 ; -- ; -- ; 00:00:10 ;
; Total ; 00:00:15 ; -- ; -- ; 00:00:11 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.summary
1,4 → 1,4
Fitter Status : Successful - Fri Oct 28 11:32:43 2011
Fitter Status : Successful - Tue Nov 15 16:26:14 2011
Quartus II Version : 11.0 Build 208 07/03/2011 SP 1 SJ Full Version
Revision Name : altera_de_II_demo
Top-level Entity Name : altera_de_II_demo
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.hdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv.hdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.qmsg
1,6 → 1,6
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 28 11:32:46 2011 " "Info: Processing started: Fri Oct 28 11:32:46 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 16:26:20 2011 " "Info: Processing started: Tue Nov 15 16:26:20 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "271 " "Info: Peak virtual memory: 271 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 11:32:49 2011 " "Info: Processing ended: Fri Oct 28 11:32:49 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "271 " "Info: Peak virtual memory: 271 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 16:26:24 2011 " "Info: Processing ended: Tue Nov 15 16:26:24 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp0.ddb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.fit.qmsg
1,17 → 1,17
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 28 11:32:35 2011 " "Info: Processing started: Fri Oct 28 11:32:35 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 16:26:08 2011 " "Info: Processing started: Tue Nov 15 16:26:08 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "altera_de_II_demo EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"altera_de_II_demo\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 576 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 577 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 578 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 576 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 577 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { ~LVDS150p/nCEO~ } } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS150p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 578 5593 6598 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "altera_de_II_demo.sdc " "Critical Warning: Synopsys Design Constraints File file not found: 'altera_de_II_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 0 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "" 0 -1}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "Info: No user constrained base clocks found in the design" { } { } 0 0 "No user constrained %1!s! found in the design" 0 0 "" 0 -1}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { clk } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 20 0 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 5 5593 6598 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n (placed in PIN N25 (CLK4, LVDSCLK2p, Input)) " "Info: Automatically promoted node rst_n (placed in PIN N25 (CLK4, LVDSCLK2p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { rst_n } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 22 0 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 7 5593 6598 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { clk } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 20 0 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 5 5593 6598 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n (placed in PIN N25 (CLK4, LVDSCLK2p, Input)) " "Info: Automatically promoted node rst_n (placed in PIN N25 (CLK4, LVDSCLK2p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/11.0/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/11.0/quartus/bin/pin_planner.ppl" { rst_n } } } { "c:/altera/11.0/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/11.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 22 0 0 } } { "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/11.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/" { { 0 { 0 ""} 0 7 5593 6598 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
35,5 → 35,5
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "port_out 0 " "Info: Pin \"port_out\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 0 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg " "Info: Generated suppressed messages file D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 424 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 424 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Info: Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 11:32:43 2011 " "Info: Processing ended: Fri Oct 28 11:32:43 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg " "Info: Generated suppressed messages file D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 424 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 424 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Info: Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 16:26:15 2011 " "Info: Processing ended: Tue Nov 15 16:26:15 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp1.ddb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sta.qmsg
1,5 → 1,5
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 28 11:32:45 2011 " "Info: Processing started: Fri Oct 28 11:32:45 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 16:26:16 2011 " "Info: Processing started: Tue Nov 15 16:26:16 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_sta altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
27,4 → 27,4
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "Info: The selected device family is not supported by the report_metastability command." { } { } 0 0 "The selected device family is not supported by the report_metastability command." 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Info: Design is not fully constrained for setup requirements" { } { } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Info: Design is not fully constrained for hold requirements" { } { } 0 0 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "236 " "Info: Peak virtual memory: 236 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 11:32:47 2011 " "Info: Processing ended: Fri Oct 28 11:32:47 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "236 " "Info: Peak virtual memory: 236 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 16:26:20 2011 " "Info: Processing ended: Tue Nov 15 16:26:20 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.sgdiff.hdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg_swap.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.rtlv_sg.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.hdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.hdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.pre_map.hdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.qmsg
1,13 → 1,13
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 28 11:32:28 2011 " "Info: Processing started: Fri Oct 28 11:32:28 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version " "Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 16:26:04 2011 " "Info: Processing started: Tue Nov 15 16:26:04 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off altera_de_II_demo -c altera_de_II_demo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off altera_de_II_demo -c altera_de_II_demo" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sig_gen-rtl " "Info: Found design unit 1: sig_gen-rtl" { } { { "../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" 61 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 sig_gen " "Info: Found entity 1: sig_gen" { } { { "../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" 47 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 port_blinker-rtl " "Info: Found design unit 1: port_blinker-rtl" { } { { "../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" 60 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 port_blinker " "Info: Found entity 1: port_blinker" { } { { "../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" 47 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altera_de_II_demo-structural " "Info: Found design unit 1: altera_de_II_demo-structural" { } { { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 27 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 altera_de_II_demo " "Info: Found entity 1: altera_de_II_demo" { } { { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 17 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/repos/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/repos/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sig_gen-rtl " "Info: Found design unit 1: sig_gen-rtl" { } { { "../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" "" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" 61 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 sig_gen " "Info: Found entity 1: sig_gen" { } { { "../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" "" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd" 47 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/repos/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/repos/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 port_blinker-rtl " "Info: Found design unit 1: port_blinker-rtl" { } { { "../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" "" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" 60 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 port_blinker " "Info: Found entity 1: port_blinker" { } { { "../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" "" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd" 47 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/user/matilail/funbase/repos/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/repos/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altera_de_II_demo-structural " "Info: Found design unit 1: altera_de_II_demo-structural" { } { { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 27 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 altera_de_II_demo " "Info: Found entity 1: altera_de_II_demo" { } { { "../vhd/altera_de_II_demo.vhd" "" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 17 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "altera_de_II_demo " "Info: Elaborating entity \"altera_de_II_demo\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "port_blinker port_blinker:port_blinker_1 " "Info: Elaborating entity \"port_blinker\" for hierarchy \"port_blinker:port_blinker_1\"" { } { { "../vhd/altera_de_II_demo.vhd" "port_blinker_1" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 60 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sig_gen sig_gen:sig_gen_1 " "Info: Elaborating entity \"sig_gen\" for hierarchy \"sig_gen:sig_gen_1\"" { } { { "../vhd/altera_de_II_demo.vhd" "sig_gen_1" { Text "D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 68 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "port_blinker port_blinker:port_blinker_1 " "Info: Elaborating entity \"port_blinker\" for hierarchy \"port_blinker:port_blinker_1\"" { } { { "../vhd/altera_de_II_demo.vhd" "port_blinker_1" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 60 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sig_gen sig_gen:sig_gen_1 " "Info: Elaborating entity \"sig_gen\" for hierarchy \"sig_gen:sig_gen_1\"" { } { { "../vhd/altera_de_II_demo.vhd" "sig_gen_1" { Text "D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd" 68 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info: Generating hard_block partition \"hard_block:auto_generated_inst\"" { } { } 0 0 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "50 " "Info: Implemented 50 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "46 " "Info: Implemented 46 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 11:32:34 2011 " "Info: Processing ended: Fri Oct 28 11:32:34 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "250 " "Info: Peak virtual memory: 250 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 15 16:26:06 2011 " "Info: Processing ended: Tue Nov 15 16:26:06 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.idb.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.rdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.asm.rdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.bpm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.cmp.bpm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.hif
49,9 → 49,6
|user|matilail|funbase|opencores_lib|trunk|tut|ip.hwp.accelerator|sig_gen|1.0|src|sig_gen.vhd
d3cb4f38966ab5c1efe7799a8a75aa52
}
# hierarchies {
|
}
# macro_sequence
 
# end
89,9 → 86,6
PARAMETER_STRING
USR
}
# hierarchies {
port_blinker:port_blinker_1
}
# macro_sequence
 
# end
133,7 → 127,124
PARAMETER_STRING
USR
}
# macro_sequence
 
# end
# entity
altera_de_II_demo
# storage
db|altera_de_II_demo.(3).cnf
db|altera_de_II_demo.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|user|matilail|funbase|repos|opencores_lib|trunk|tut|soc|altera_de_ii_demo|1.0|vhd|altera_de_ii_demo.vhd
ba7ba46d8c531d3bf2d6278ada65cada
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# include_file {
|user|matilail|funbase|repos|opencores_lib|trunk|tut|ip.hwp.accelerator|port_blinker|1.0|src|port_blinker.vhd
6ad6d680d0e2cd2c32135b7829ff2d0
|user|matilail|funbase|repos|opencores_lib|trunk|tut|ip.hwp.accelerator|sig_gen|1.0|src|sig_gen.vhd
d3cb4f38966ab5c1efe7799a8a75aa52
}
# hierarchies {
|
}
# macro_sequence
 
# end
# entity
port_blinker
# storage
db|altera_de_II_demo.(4).cnf
db|altera_de_II_demo.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|user|matilail|funbase|repos|opencores_lib|trunk|tut|ip.hwp.accelerator|port_blinker|1.0|src|port_blinker.vhd
6ad6d680d0e2cd2c32135b7829ff2d0
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
signal_width
32
PARAMETER_SIGNED_DEC
USR
constraint(val_in)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
port_blinker:port_blinker_1
}
# macro_sequence
 
# end
# entity
sig_gen
# storage
db|altera_de_II_demo.(5).cnf
db|altera_de_II_demo.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
|user|matilail|funbase|repos|opencores_lib|trunk|tut|ip.hwp.accelerator|sig_gen|1.0|src|sig_gen.vhd
d3cb4f38966ab5c1efe7799a8a75aa52
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
signal_val
100000000
PARAMETER_SIGNED_DEC
USR
signal_width
32
PARAMETER_SIGNED_DEC
USR
constraint(sig_out)
31 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
sig_gen:sig_gen_1
}
# macro_sequence
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map_bb.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/db/altera_de_II_demo.map.kpt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.map.rpt
1,5 → 1,5
Analysis & Synthesis report for altera_de_II_demo
Fri Oct 28 11:32:34 2011
Tue Nov 15 16:26:06 2011
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
 
 
44,7 → 44,7
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Oct 28 11:32:34 2011 ;
; Analysis & Synthesis Status ; Successful - Tue Nov 15 16:26:06 2011 ;
; Quartus II Version ; 11.0 Build 208 07/03/2011 SP 1 SJ Full Version ;
; Revision Name ; altera_de_II_demo ;
; Top-level Entity Name ; altera_de_II_demo ;
160,15 → 160,15
+----------------------------+-------------+
 
 
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------------------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------------------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------+
; ../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd ; yes ; User VHDL File ; D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd ;
; ../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd ; yes ; User VHDL File ; D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd ;
; ../vhd/altera_de_II_demo.vhd ; yes ; User VHDL File ; D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd ;
+----------------------------------------------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------------------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------------------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------------+
; ../../../../ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd ; yes ; User VHDL File ; D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd ;
; ../../../../ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd ; yes ; User VHDL File ; D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd ;
; ../vhd/altera_de_II_demo.vhd ; yes ; User VHDL File ; D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd ;
+----------------------------------------------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------------+
 
 
+-----------------------------------------------------+
272,16 → 272,16
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Fri Oct 28 11:32:28 2011
Info: Processing started: Tue Nov 15 16:26:04 2011
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off altera_de_II_demo -c altera_de_II_demo
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd
Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/repos/opencores_lib/trunk/tut/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd
Info: Found design unit 1: sig_gen-rtl
Info: Found entity 1: sig_gen
Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd
Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/repos/opencores_lib/trunk/tut/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd
Info: Found design unit 1: port_blinker-rtl
Info: Found entity 1: port_blinker
Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd
Info: Found 2 design units, including 1 entities, in source file /user/matilail/funbase/repos/opencores_lib/trunk/tut/soc/altera_de_ii_demo/1.0/vhd/altera_de_ii_demo.vhd
Info: Found design unit 1: altera_de_II_demo-structural
Info: Found entity 1: altera_de_II_demo
Info: Elaborating entity "altera_de_II_demo" for the top level hierarchy
294,8 → 294,8
Info: Implemented 46 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 250 megabytes
Info: Processing ended: Fri Oct 28 11:32:34 2011
Info: Elapsed time: 00:00:06
Info: Processing ended: Tue Nov 15 16:26:06 2011
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
 
 
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.asm.rpt
1,5 → 1,5
Assembler report for altera_de_II_demo
Fri Oct 28 11:32:49 2011
Tue Nov 15 16:26:23 2011
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
 
 
10,8 → 10,8
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof
6. Assembler Device Options: D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof
5. Assembler Device Options: D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof
6. Assembler Device Options: D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof
7. Assembler Messages
 
 
38,7 → 38,7
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Oct 28 11:32:49 2011 ;
; Assembler Status ; Successful - Tue Nov 15 16:26:23 2011 ;
; Revision Name ; altera_de_II_demo ;
; Top-level Entity Name ; altera_de_II_demo ;
; Family ; Cyclone II ;
78,37 → 78,37
+-----------------------------------------------------------------------------+----------+---------------+
 
 
+----------------------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+----------------------------------------------------------------------------------------------------------+
; File Name ;
+----------------------------------------------------------------------------------------------------------+
; D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof ;
; D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof ;
+----------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+----------------------------------------------------------------------------------------------------------------+
; File Name ;
+----------------------------------------------------------------------------------------------------------------+
; D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof ;
; D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof ;
+----------------------------------------------------------------------------------------------------------------+
 
 
+------------------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof ;
+----------------+-------------------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+-------------------------------------------------------------------------------------------------------------------+
; Device ; EP2C35F672C6 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x002E88AB ;
+----------------+-------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sof ;
+----------------+-------------------------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+-------------------------------------------------------------------------------------------------------------------------+
; Device ; EP2C35F672C6 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x002E88AB ;
+----------------+-------------------------------------------------------------------------------------------------------------------------+
 
 
+------------------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof ;
+--------------------+---------------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+--------------------+---------------------------------------------------------------------------------------------------------------+
; Device ; EPCS16 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x1C7755AE ;
; Compression Ratio ; 3 ;
+--------------------+---------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Assembler Device Options: D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pof ;
+--------------------+---------------------------------------------------------------------------------------------------------------------+
; Option ; Setting ;
+--------------------+---------------------------------------------------------------------------------------------------------------------+
; Device ; EPCS16 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x1C7755AE ;
; Compression Ratio ; 3 ;
+--------------------+---------------------------------------------------------------------------------------------------------------------+
 
 
+--------------------+
117,14 → 117,14
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Fri Oct 28 11:32:46 2011
Info: Processing started: Tue Nov 15 16:26:20 2011
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 271 megabytes
Info: Processing ended: Fri Oct 28 11:32:49 2011
Info: Elapsed time: 00:00:03
Info: Processing ended: Tue Nov 15 16:26:24 2011
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:02
 
 
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.done
1,14 → 117,14
Fri Oct 28 11:32:50 2011
Tue Nov 15 16:26:24 2011
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.rpt
1,5 → 1,5
Fitter report for altera_de_II_demo
Fri Oct 28 11:32:43 2011
Tue Nov 15 16:26:14 2011
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
 
 
63,7 → 63,7
+-------------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+------------------------------------------------+
; Fitter Status ; Successful - Fri Oct 28 11:32:43 2011 ;
; Fitter Status ; Successful - Tue Nov 15 16:26:14 2011 ;
; Quartus II Version ; 11.0 Build 208 07/03/2011 SP 1 SJ Full Version ;
; Revision Name ; altera_de_II_demo ;
; Top-level Entity Name ; altera_de_II_demo ;
138,12 → 138,12
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.22 ;
; Average used ; 1.29 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2 processors ; 12.5% ;
; 2 processors ; 16.7% ;
+----------------------------+-------------+
 
 
613,7 → 613,7
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pin.
The pin-out file can be found in D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.pin.
 
 
+-------------------------------------------------------------------------------------------+
1863,7 → 1863,7
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Fri Oct 28 11:32:35 2011
Info: Processing started: Tue Nov 15 16:26:08 2011
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off altera_de_II_demo -c altera_de_II_demo
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Selected device EP2C35F672C6 for design "altera_de_II_demo"
2325,11 → 2325,11
Info: Pin "port_out" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info: Generated suppressed messages file D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg
Info: Generated suppressed messages file D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 424 warnings
Info: Peak virtual memory: 344 megabytes
Info: Processing ended: Fri Oct 28 11:32:43 2011
Info: Elapsed time: 00:00:08
Info: Processing ended: Tue Nov 15 16:26:15 2011
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:06
 
 
2336,6 → 2336,6
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg.
The suppressed messages can be found in D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.fit.smsg.
 
 
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.qpf
1,7 → 1,7
# ----------------------------------------------------------- #
 
# Quartus project generated by Kactus2
# Date created 15:33:10 27.10.2011
# Date created 16:25:32 15.11.2011
 
# ----------------------------------------------------------- #
 
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.qsf
1,15 → 1,15
# ----------------------------------------------------------- #
 
# Quartus project generated by Kactus2
# Date created 15:33:10 27.10.2011
# Date created 16:25:32 15.11.2011
 
# ----------------------------------------------------------- #
 
set_global_assignment -name TOP_LEVEL_ENTITY altera_de_II_demo
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
set_global_assignment -name VHDL_FILE D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd
set_global_assignment -name VHDL_FILE D:/user/matilail/funbase/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd
set_global_assignment -name VHDL_FILE D:/user/matilail/funbase/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd
set_global_assignment -name VHDL_FILE D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/ip.hwp.accelerator/sig_gen/1.0/src/sig_gen.vhd
set_global_assignment -name VHDL_FILE D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/ip.hwp.accelerator/port_blinker/1.0/src/port_blinker.vhd
set_global_assignment -name VHDL_FILE D:/user/matilail/funbase/repos/opencores_lib/trunk/TUT/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd
set_location_assignment PIN_N26 -to SW[1]
set_location_assignment PIN_P25 -to SW[2]
set_location_assignment PIN_AE14 -to SW[3]
440,7 → 440,7
 
set_global_assignment -name LAST_QUARTUS_VERSION "11.0 SP1"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.sta.rpt
1,5 → 1,5
TimeQuest Timing Analyzer report for altera_de_II_demo
Fri Oct 28 11:32:47 2011
Tue Nov 15 16:26:20 2011
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
 
 
1015,7 → 1015,7
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version
Info: Processing started: Fri Oct 28 11:32:45 2011
Info: Processing started: Tue Nov 15 16:26:16 2011
Info: Command: quartus_sta altera_de_II_demo -c altera_de_II_demo
Info: qsta_default_script.tcl version: #1
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
1065,8 → 1065,8
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 236 megabytes
Info: Processing ended: Fri Oct 28 11:32:47 2011
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Info: Processing ended: Tue Nov 15 16:26:20 2011
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:02
 
 
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hbdb.hdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.dpi Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.hdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.map.kpt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/incremental_db/compiled_partitions/altera_de_II_demo.root_partition.cmp.hdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/TUT/soc/altera_de_II_demo/1.0/quartus/altera_de_II_demo.map.summary
1,4 → 1,4
Analysis & Synthesis Status : Successful - Fri Oct 28 11:32:34 2011
Analysis & Synthesis Status : Successful - Tue Nov 15 16:26:06 2011
Quartus II Version : 11.0 Build 208 07/03/2011 SP 1 SJ Full Version
Revision Name : altera_de_II_demo
Top-level Entity Name : altera_de_II_demo
/trunk/TUT/soc/altera_de_II_demo/1.0/altera_de_II_demo.design.1.0.xml
1,5 → 1,5
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 10:49:55 pe loka 21 2011-->
<!--Created by Kactus 2 document generator 16:30:32 ti marras 15 2011-->
<spirit:design>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>
7,50 → 7,50
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>sig_gen_1</spirit:instanceName>
<spirit:instanceName>port_blinker_1</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.accelerator" spirit:name="sig_gen" spirit:version="1.0"/>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.accelerator" spirit:name="port_blinker" spirit:version="1.0"/>
<spirit:configurableElementValues/>
<spirit:vendorExtensions>
<kactus2:position x="250" y="60"/>
<kactus2:position x="250" y="180"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="clk">
<kactus2:position x="-80" y="40"/>
<kactus2:position x="-80" y="70"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="rst_n">
<kactus2:portPosition kactus2:busRef="port_out">
<kactus2:position x="80" y="70"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="rst_n">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="signal_gen_if">
<kactus2:position x="-80" y="70"/>
<kactus2:position x="-80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="toggle_in">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
</kactus2:portPositions>
</spirit:vendorExtensions>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>port_blinker_1</spirit:instanceName>
<spirit:instanceName>sig_gen_1</spirit:instanceName>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.accelerator" spirit:name="port_blinker" spirit:version="1.0"/>
<spirit:componentRef spirit:vendor="TUT" spirit:library="ip.hwp.accelerator" spirit:name="sig_gen" spirit:version="1.0"/>
<spirit:configurableElementValues/>
<spirit:vendorExtensions>
<kactus2:position x="250" y="180"/>
<kactus2:position x="250" y="60"/>
<kactus2:portPositions>
<kactus2:portPosition kactus2:busRef="clk">
<kactus2:position x="-80" y="70"/>
<kactus2:position x="-80" y="40"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="port_out">
<kactus2:position x="80" y="60"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="rst_n">
<kactus2:position x="80" y="40"/>
<kactus2:position x="80" y="70"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="signal_gen_if">
<kactus2:position x="-80" y="40"/>
<kactus2:position x="-80" y="70"/>
</kactus2:portPosition>
<kactus2:portPosition kactus2:busRef="toggle_in">
<kactus2:position x="80" y="40"/>
</kactus2:portPosition>
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</spirit:vendorExtensions>
</spirit:componentInstance>
65,45 → 65,30
</spirit:interconnection>
</spirit:interconnections>
<spirit:hierConnections>
<spirit:hierConnection spirit:interfaceRef="rst_n">
<spirit:interface spirit:componentRef="sig_gen_1" spirit:busRef="rst_n"/>
<spirit:hierConnection spirit:interfaceRef="toggle_in">
<spirit:interface spirit:componentRef="sig_gen_1" spirit:busRef="toggle_in"/>
<spirit:vendorExtensions>
<kactus2:position x="440" y="190"/>
<kactus2:position x="440" y="100"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:route>
<kactus2:position x="330" y="130"/>
<kactus2:position x="430" y="130"/>
<kactus2:position x="430" y="190"/>
<kactus2:position x="440" y="190"/>
<kactus2:position x="330" y="100"/>
<kactus2:position x="440" y="100"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="rst_n">
<spirit:interface spirit:componentRef="port_blinker_1" spirit:busRef="rst_n"/>
<spirit:hierConnection spirit:interfaceRef="clk">
<spirit:interface spirit:componentRef="port_blinker_1" spirit:busRef="clk"/>
<spirit:vendorExtensions>
<kactus2:position x="440" y="190"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:position x="60" y="100"/>
<kactus2:direction x="1" y="0"/>
<kactus2:route>
<kactus2:position x="330" y="220"/>
<kactus2:position x="430" y="220"/>
<kactus2:position x="430" y="190"/>
<kactus2:position x="440" y="190"/>
<kactus2:position x="170" y="250"/>
<kactus2:position x="90" y="250"/>
<kactus2:position x="90" y="100"/>
<kactus2:position x="60" y="100"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="port_out">
<spirit:interface spirit:componentRef="port_blinker_1" spirit:busRef="port_out"/>
<spirit:vendorExtensions>
<kactus2:position x="440" y="250"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:route>
<kactus2:position x="330" y="240"/>
<kactus2:position x="430" y="240"/>
<kactus2:position x="430" y="250"/>
<kactus2:position x="440" y="250"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="clk">
<spirit:interface spirit:componentRef="sig_gen_1" spirit:busRef="clk"/>
<spirit:vendorExtensions>
117,30 → 102,45
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="clk">
<spirit:interface spirit:componentRef="port_blinker_1" spirit:busRef="clk"/>
<spirit:hierConnection spirit:interfaceRef="port_out">
<spirit:interface spirit:componentRef="port_blinker_1" spirit:busRef="port_out"/>
<spirit:vendorExtensions>
<kactus2:position x="60" y="100"/>
<kactus2:direction x="1" y="0"/>
<kactus2:position x="440" y="250"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:route>
<kactus2:position x="170" y="250"/>
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<kactus2:position x="90" y="100"/>
<kactus2:position x="60" y="100"/>
<kactus2:position x="330" y="250"/>
<kactus2:position x="430" y="250"/>
<kactus2:position x="430" y="250"/>
<kactus2:position x="440" y="250"/>
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<spirit:hierConnection spirit:interfaceRef="toggle_in">
<spirit:interface spirit:componentRef="sig_gen_1" spirit:busRef="toggle_in"/>
<spirit:hierConnection spirit:interfaceRef="rst_n">
<spirit:interface spirit:componentRef="port_blinker_1" spirit:busRef="rst_n"/>
<spirit:vendorExtensions>
<kactus2:position x="440" y="100"/>
<kactus2:position x="440" y="190"/>
<kactus2:direction x="-1" y="0"/>
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<kactus2:position x="330" y="100"/>
<kactus2:position x="440" y="100"/>
<kactus2:position x="330" y="220"/>
<kactus2:position x="430" y="220"/>
<kactus2:position x="430" y="190"/>
<kactus2:position x="440" y="190"/>
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<spirit:hierConnection spirit:interfaceRef="rst_n">
<spirit:interface spirit:componentRef="sig_gen_1" spirit:busRef="rst_n"/>
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<kactus2:position x="430" y="130"/>
<kactus2:position x="430" y="190"/>
<kactus2:position x="440" y="190"/>
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</spirit:vendorExtensions>
</spirit:hierConnection>
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<spirit:vendorExtensions>
<kactus2:columnLayout>
/trunk/TUT/soc/altera_de_II_demo/1.0/altera_de_II_demo.designcfg.1.0.xml
1,5 → 1,5
<?xml version="1.0" encoding="UTF-8"?>
<!--Created by Kactus 2 document generator 10:49:55 pe loka 21 2011-->
<!--Created by Kactus 2 document generator 16:30:32 ti marras 15 2011-->
<spirit:designConfiguration>
<spirit:vendor>TUT</spirit:vendor>
<spirit:library>soc</spirit:library>

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