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/trunk/Release_Notes.txt
1,10 → 1,31
---------------------------------------------------------------
15-Feb-2014
---------------------------------------------------------------
 
This is second release of G.729A codec core version 1.0.
 
This release is intended to fix an issue occuring when the core
is synthesized using Xilinx tools and to clean up some code
imperfection.
 
Modified source files:
G729A_asip_addsub_pipeb.vhd
G729A_asip_cpu_2w_p6.vhd
G729A_asip_mulu_pipeb.vhd
G729A_asip_regfile_16x16_2w.vhd
G729A_asip_spc.vhd
G729A_asip_top_2w.vhd
G729A_codec_selftest.vhd
 
---------------------------------------------------------------
02-Nov-2013
---------------------------------------------------------------
 
This is first release of G.729A codec core version 1.0.
 
---------------------------------------------------------------
Release directory structure:
---------------------------------------------------------------
 
G729A_CODEC_V1_0
|
/trunk/DOCS/OpenCores G.729A codec.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/SYN/ALTERA/README.txt
12,10 → 12,10
If the self-test module is succesfully synthesized, after
donwloading the resulting SOF file to the NEEK board, the board
LED's should be in the following state:
LED0 : on (test completed).
LED1 : on (test passed, no error).
LED2 : off (permanently tied to VCC, just a safety check).
LED3 : on (permanently tied to GND, just a safety check).
LED1 : on (test completed).
LED2 : on (test passed, no error).
LED3 : off (permanently tied to VCC, just a safety check).
LED4 : on (permanently tied to GND, just a safety check).
 
This directory includes all the design files required by the
project:
/trunk/VHDL/G729A_asip_addsub_pipeb.vhd
51,9 → 51,6
 
architecture ARC of G729A_ASIP_ADDSUB_PIPEB is
 
constant ZERO : LDWORD_T := to_signed(0,LDLEN);
constant ONE : LDWORD_T := to_signed(1,LDLEN);
 
component G729A_ASIP_ADDER_F is
generic(
LEN1 : integer := 16;
76,7 → 73,8
return(XS);
end function;
 
signal IOPA,IOPB,CI,SUM : LDWORD_T;
signal IOPA,IOPB,SUM : LDWORD_T;
signal CI : std_logic;
 
begin
 
87,53 → 85,53
when AC_ABS|AC_NEG =>
-- tmp = -opa_i
IOPA <= not(EXTS(OPA_i(SDLEN-1 downto 0),LDLEN));
IOPB <= ZERO;
CI <= ONE;
IOPB <= (others => '0');
CI <= '1';
when AC_LABS|AC_LNEG =>
-- tmp = -opa_i
IOPA <= not(OPA_i);
IOPB <= ZERO;
CI <= ONE;
IOPB <= (others => '0');
CI <= '1';
--when AC_ADD =>
-- -- tmp = opa_i + opb_i
-- IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
-- IOPB <= EXTS(OPB_i(SDLEN-1 downto 0),LDLEN);
-- CI <= ZERO;
-- CI <= '0';
when AC_LADD =>
-- tmp = opa_i + opb_i
IOPA <= OPA_i;
IOPB <= OPB_i;
CI <= ZERO;
CI <= '0';
--when AC_SUB =>
-- -- tmp = opa_i - opb_i
-- IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
-- IOPB <= not(EXTS(OPB_i(SDLEN-1 downto 0),LDLEN));
-- CI <= ONE;
-- CI <= '1';
when AC_LSUB =>
-- tmp = opa_i - opb_i
IOPA <= OPA_i;
IOPB <= not(OPB_i);
CI <= ONE;
CI <= '1';
when AC_LEXT =>
-- tmp = opa_i - (opa_i(31:16)<<16)
IOPA <= OPA_i;
IOPB <= not(OPA_i(LDLEN-1 downto SDLEN) & to_signed(0,SDLEN));
CI <= ONE;
CI <= '1';
when others => -- RND
-- tmp = opa_i + 0x00008000
IOPA <= OPA_i;
IOPB <= (SDLEN-1 => '1',others => '0');
CI <= ZERO;
CI <= '0';
--when AC_INC =>
-- -- tmp = opa_i + 1
-- IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
-- IOPB <= (0 => '1',others => '0');
-- CI <= ZERO;
-- CI <= '0';
--when others => -- DEC
-- -- tmp = opa_i - 1
-- IOPA <= EXTS(OPA_i(SDLEN-1 downto 0),LDLEN);
-- IOPB <= (others => '1');
-- CI <= ZERO;
-- CI <= '0';
end case;
end process;
 
147,7 → 145,7
port map(
OPA_i => IOPA,
OPB_i => IOPB,
CI_i => CI(0),
CI_i => CI,
SUM_o => SUM
);
 
/trunk/VHDL/SELF_TEST/G729A_codec_selftest.vhd
490,17 → 490,22
-- This counter counts the data word to be read from
-- codec memory, or written to codec memory.
 
process(CDC_STS)
begin
case CDC_STS is
when STS_COD_DIN => CNT_INIT <= DECODED_LEN-1;
when STS_COD_DOUT => CNT_INIT <= ENCODED_LEN-1;
when STS_DEC_DIN => CNT_INIT <= ENCODED_LEN-1;
when STS_DEC_DOUT => CNT_INIT <= DECODED_LEN-1;
when others => CNT_INIT <= 0;
end case;
end process;
--process(CDC_STS)
--begin
-- case CDC_STS is
-- when STS_COD_DIN => CNT_INIT <= DECODED_LEN-1;
-- when STS_COD_DOUT => CNT_INIT <= ENCODED_LEN-1;
-- when STS_DEC_DIN => CNT_INIT <= ENCODED_LEN-1;
-- when STS_DEC_DOUT => CNT_INIT <= DECODED_LEN-1;
-- when others => CNT_INIT <= 0;
-- end case;
--end process;
 
CNT_INIT <= DECODED_LEN-1 when (
CDC_STS = STS_COD_DIN or
CDC_STS = STS_DEC_DOUT
) else ENCODED_LEN-1;
 
process(CLK_i)
begin
if(CLK_i = '1' and CLK_i'event) then
/trunk/VHDL/G729A_asip_regfile_16x16_2w.vhd
66,10 → 66,11
architecture ARC of G729A_ASIP_REGFILE_16X16_2W is
 
constant REGNUM : natural := 16;
constant ZERO : std_logic_vector(SDLEN-1 downto 0) := (others => '0');
 
subtype WORD_T is std_logic_vector(SDLEN-1 downto 0);
type MEM_T is array (REGNUM/2-1 downto 0) of WORD_T;
type RID_VEC_T is array (natural range <>) of RID_T;
type WORD_VEC_T is array (natural range <>) of WORD_T;
 
signal REG_EVEN,REG_ODD : MEM_T;
signal WE0_EVEN,WE0_ODD : std_logic;
79,6 → 80,8
signal IRA0,IRA1,IRA2,IRA3 : natural range 0 to REGNUM/2-1;
signal RA0_LSB,RA1_LSB,RA2_LSB,RA3_LSB : std_logic;
signal D0_LO,D0_HI : std_logic_vector(SDLEN-1 downto 0);
signal WE_EVEN,WE_ODD : std_logic_vector(REGNUM/2-1 downto 0);
signal D_EVEN,D_ODD : WORD_VEC_T(REGNUM/2-1 downto 0);
signal D0_EVEN,D0_ODD : std_logic_vector(SDLEN-1 downto 0);
signal D1_LO,D1_HI : std_logic_vector(SDLEN-1 downto 0);
signal D1_EVEN,D1_ODD : std_logic_vector(SDLEN-1 downto 0);
101,39 → 104,9
D0_LO <= D0_i(SDLEN-1 downto 0);
D0_HI <= D0_i(SDLEN*2-1 downto SDLEN);
 
D0_EVEN <= D0_LO;
D0_ODD <= D0_HI when (LW0_i = '1') else D0_LO;
 
process(WA0_LSB,WE0_i,LW0_i)
begin
if(LW0_i = '0') then
WE0_EVEN <= (WE0_i and not(WA0_LSB));
WE0_ODD <= (WE0_i and WA0_LSB);
else
WE0_EVEN <= WE0_i;
WE0_ODD <= WE0_i;
end if;
end process;
 
---------------------------------------------
 
D1_LO <= D1_i(SDLEN-1 downto 0);
D1_HI <= D1_i(SDLEN*2-1 downto SDLEN);
 
D1_EVEN <= D1_LO;
D1_ODD <= D1_HI when (LW1_i = '1') else D1_LO;
 
process(WA1_LSB,WE1_i,LW1_i)
begin
if(LW1_i = '0') then
WE1_EVEN <= (WE1_i and not(WA1_LSB));
WE1_ODD <= (WE1_i and WA1_LSB);
else
WE1_EVEN <= WE1_i;
WE1_ODD <= WE1_i;
end if;
end process;
 
---------------------------------------------
 
IWA0 <= WA0_i/2;
142,30 → 115,89
WA0_LSB <= GET_LSB(WA0_i);
WA1_LSB <= GET_LSB(WA1_i);
 
process(CLK_i)
begin
if(CLK_i = '1' and CLK_i'event) then
if(WE0_EVEN = '1') then
REG_EVEN(IWA0) <= D0_EVEN;
---------------------------------------------
 
G0 : for k in 0 to REGNUM/2-1 generate
 
WE_EVEN(k) <= '1' when (
(WE0_i = '1' and (IWA0 = k) and (WA0_LSB = '0') and (LW0_i = '0')) or
(WE1_i = '1' and (IWA1 = k) and (WA1_LSB = '0') and (LW1_i = '0')) or
(WE0_i = '1' and (IWA0 = k) and (LW0_i = '1')) or
(WE1_i = '1' and (IWA1 = k) and (LW1_i = '1'))
) else '0';
 
WE_ODD(k) <= '1' when (
(WE0_i = '1' and (IWA0 = k) and (WA0_LSB = '1') and (LW0_i = '0')) or
(WE1_i = '1' and (IWA1 = k) and (WA1_LSB = '1') and (LW1_i = '0')) or
(WE0_i = '1' and (IWA0 = k) and (LW0_i = '1')) or
(WE1_i = '1' and (IWA1 = k) and (LW1_i = '1'))
) else '0';
 
process(WE0_i,WE1_i,IWA0,IWA1,WA0_LSB,WA1_LSB,LW0_i,LW1_i,
D0_LO,D0_HI,D1_LO,D1_HI)
variable S : natural range 0 to 4-1;
begin
 
-- Write from port #1 must get higher priority because
-- instruction #1 is newer than instruction #0.
 
if(
(WE1_i = '1') and (IWA1 = k) and
((WA1_LSB = '0') or (LW1_i = '1'))
) then
-- write from port #1
D_EVEN(k) <= D1_LO;
else
-- write from port #0
D_EVEN(k) <= D0_LO;
end if;
if(WE1_EVEN = '1') then
REG_EVEN(IWA1) <= D1_EVEN;
 
if(
(WE1_i = '1') and (IWA1 = k) and
(WA1_LSB = '1') and (LW1_i = '0')
) then
-- word write from port #1
S := 0;
elsif(
(WE1_i = '1') and (IWA1 = k) and
(LW1_i = '1')
) then
-- long-word write from port #1
S := 1;
elsif(
(WE0_i = '1') and (IWA0 = k) and
(WA0_LSB = '1') and (LW0_i = '0')
) then
-- word write from port #0
S := 2;
else
-- long-word write from port #0
S := 3;
end if;
end if;
end process;
 
process(CLK_i)
begin
if(CLK_i = '1' and CLK_i'event) then
if(WE0_ODD = '1') then
REG_ODD(IWA0) <= D0_ODD;
case S is
when 0 => D_ODD(k) <= D1_LO;
when 1 => D_ODD(k) <= D1_HI;
when 2 => D_ODD(k) <= D0_LO;
when 3 => D_ODD(k) <= D0_HI;
end case;
 
end process;
 
process(CLK_i)
begin
if(CLK_i = '1' and CLK_i'event) then
if(WE_EVEN(k) = '1') then
REG_EVEN(k) <= D_EVEN(k);
end if;
if(WE_ODD(k) = '1') then
REG_ODD(k) <= D_ODD(k);
end if;
end if;
if(WE1_ODD = '1') then
REG_ODD(IWA1) <= D1_ODD;
end if;
end if;
end process;
end process;
 
end generate;
 
---------------------------------------------
 
IRA0 <= RA0_i/2;
244,4 → 276,4
end if;
end process;
 
end ARC;
end ARC;
/trunk/VHDL/G729A_asip_top_2w.vhd
235,12 → 235,13
function get_dadr_ram(DADR : unsigned(ALEN-1 downto 0)) return unsigned is
variable DADR_RAM : unsigned(12-1 downto 0);
begin
if(DADR(11 downto 10) /= "11") then
DADR_RAM(11 downto 10) := DADR(11 downto 10);
else
DADR_RAM(11 downto 10) := "00";
end if;
DADR_RAM(9 downto 0) := DADR(9 downto 0);
--if(DADR(11 downto 10) /= "11") then
-- DADR_RAM(11 downto 10) := DADR(11 downto 10);
--else
-- DADR_RAM(11 downto 10) := "00";
--end if;
--DADR_RAM(9 downto 0) := DADR(9 downto 0);
DADR_RAM(11 downto 0) := DADR(11 downto 0);
return(DADR_RAM);
end function;
 
285,10 → 286,14
signal DROM0_SEL,DROM1_SEL : std_logic;
signal DROM0_SEL_q,DROM1_SEL_q : std_logic;
signal DWE0_RAM : std_logic;
signal DADR0_RAM : unsigned(log2(CMEM_LIMIT)-1 downto 0);
signal DADR1_RAM : unsigned(log2(CMEM_LIMIT)-1 downto 0);
signal DADR0_ROM : unsigned(log2(DMEM_SIZE-CMEM_LIMIT)-1 downto 0);
signal DADR1_ROM : unsigned(log2(DMEM_SIZE-CMEM_LIMIT)-1 downto 0);
--signal DADR0_RAM : unsigned(log2(CMEM_LIMIT)-1 downto 0);
--signal DADR1_RAM : unsigned(log2(CMEM_LIMIT)-1 downto 0);
--signal DADR0_ROM : unsigned(log2(DMEM_SIZE-CMEM_LIMIT)-1 downto 0);
--signal DADR1_ROM : unsigned(log2(DMEM_SIZE-CMEM_LIMIT)-1 downto 0);
signal DADR0_ROM : unsigned(log2(CMEM_LIMIT)-1 downto 0);
signal DADR1_ROM : unsigned(log2(CMEM_LIMIT)-1 downto 0);
signal DADR0_RAM : unsigned(log2(DMEM_SIZE-CMEM_LIMIT)-1 downto 0);
signal DADR1_RAM : unsigned(log2(DMEM_SIZE-CMEM_LIMIT)-1 downto 0);
signal DDATI0_RAM : std_logic_vector(SDLEN-1 downto 0);
signal DDATI1_RAM : std_logic_vector(SDLEN-1 downto 0);
signal DDATI0_ROM : std_logic_vector(SDLEN-1 downto 0);
543,7 → 548,8
U_RAMD : G729_ASIP_RAM_1RW1R
generic map(
DWIDTH => SDLEN,
WCOUNT => DMEM_SIZE-CMEM_LIMIT
--WCOUNT => DMEM_SIZE-CMEM_LIMIT
WCOUNT => 4096
)
port map(
CLK_i => CLK_i,
/trunk/VHDL/G729A_asip_spc.vhd
94,6 → 94,8
constant IO_READ : std_logic_vector(2-1 downto 0) := "01";
constant IO_WRITE : std_logic_vector(2-1 downto 0) := "10";
 
constant MAX_IO_COUNT : natural := 2048;
 
-- sequencer "instruction" type
 
type PROG_T is record
102,7 → 104,7
-- I/O mode selector
IO_MODE : std_logic_vector(2-1 downto 0);
-- number of words to transfer when in read/write mode
IO_COUNT : natural range 0 to 2048-1;
IO_COUNT : natural range 0 to MAX_IO_COUNT-1;
-- I/O address selector
IO_ASEL : std_logic_vector(3-1 downto 0);
-- halt when sub-program ends
130,7 → 132,9
-- be used before encoding/decoding the first packet of a
-- conversation, while "b" must be used on following packets.
 
constant PROG_SEQ_q : PROG_SEQ_T(0 to 40-1) := (
constant MAX_PROG : natural := 40;
 
constant PROG_SEQ_q : PROG_SEQ_T(0 to MAX_PROG-1) := (
--
-- "init only" sub-program
--
215,12 → 219,12
);
 
signal TS,TS_q : TEST_STATE_T;
signal PROG_CNT_q : natural;
signal PROG_FIRST : natural;
signal PROG_CNT_q : natural range 0 to MAX_PROG-1;
signal PROG_FIRST : natural range 0 to MAX_PROG-1;
signal PROG_NEXT : std_logic;
signal PROG_LAST : std_logic;
signal IO_MODE : std_logic_vector(2-1 downto 0);
signal IO_COUNT : natural;
signal IO_COUNT : natural range 0 to MAX_IO_COUNT-1;
signal IO_ASEL : std_logic_vector(3-1 downto 0);
signal A_STRT,A_STRT_q : std_logic;
signal D_STRT,D_STRT_q : std_logic;
/trunk/VHDL/G729A_asip_mulu_pipeb.vhd
122,8 → 122,6
signal PROD1,PROD2 : LDWORD_T;
signal MULA_RES : LDWORD_T;
signal MULA_RES_q : LDWORD_T;
signal MULA_OVF : std_logic;
signal MULA_OVF_q : std_logic;
signal LMUL_PROD_q : LDWORD_T;
signal LMUL_RES : LDWORD_T;
signal LMUL_OVF : std_logic;
168,14 → 166,11
MULA_RES(SDLEN-1 downto 0) <= PROD1(SDLEN-1 downto 0);
MULA_RES(LDLEN-1 downto SDLEN) <= (others => '0');
 
MULA_OVF <= '0';
 
-- pipe register
process(CLK_i)
begin
if(CLK_i = '1' and CLK_i'event) then
MULA_RES_q <= MULA_RES;
MULA_OVF_q <= MULA_OVF;
end if;
end process;
 
448,13 → 443,13
 
--process(CTRL_q,MAC_RES_q,MAC_OVF_q,MULR_RES,MULR_OVF,LMUL_RES,LMUL_OVF,
-- M3216_RES,M3216_OVF)
process(CTRL_q,MULA_RES_q,MULA_OVF_q,MULR_RES,MULR_OVF,LMUL_RES,LMUL_OVF,
process(CTRL_q,MULA_RES_q,MULR_RES,MULR_OVF,LMUL_RES,LMUL_OVF,
M3216_RES,M3216_OVF)
begin
case CTRL_q is
when MC_MULA =>
RES_o <= MULA_RES_q;
OVF_o <= MULA_OVF_q;
OVF_o <= '0';
--when MC_LMAC|MC_LMSU =>
-- RES_o <= MAC_RES;
-- OVF_o <= MAC_OVF;
/trunk/VHDL/G729A_asip_cpu_2w_p6.vhd
869,7 → 869,7
 
U_PSTL0 : G729A_ASIP_PSTLLOG_2W_P6
generic map(
SIMULATION_ONLY => '1'
SIMULATION_ONLY => SIMULATION_ONLY
)
port map(
CLK_i => CLK_i,
893,7 → 893,7
 
U_PSTL1 : G729A_ASIP_PSTLLOG_2W_P6
generic map(
SIMULATION_ONLY => '1'
SIMULATION_ONLY => SIMULATION_ONLY
)
port map(
CLK_i => CLK_i,

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