OpenCores

/doc/Integration Manual.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

doc/Integration Manual.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: COMPILE_LIST =================================================================== --- COMPILE_LIST (nonexistent) +++ COMPILE_LIST (revision 38) @@ -0,0 +1,23 @@ + +Compile list for the GCpad core +=============================== +Version: $Date: 2004-10-28 20:00:09 $ + +rtl/vhdl/gcpad_pack-p.vhd +rtl/vhdl/gcpad_comp-p.vhd +rtl/vhdl/gcpad_ctrl.vhd +rtl/vhdl/gcpad_tx.vhd +rtl/vhdl/gcpad_sampler.vhd +rtl/vhdl/gcpad_rx.vhd +rtl/vhdl/gcpad_basic.vhd +rtl/vhdl/gcpad_full.vhd +bench/vhdl/gcpad_mod.vhd +bench/vhdl/tb.vhd +rtl/vhdl/gcpad_ctrl-c.vhd +rtl/vhdl/gcpad_tx-c.vhd +rtl/vhdl/gcpad_sampler-c.vhd +rtl/vhdl/gcpad_rx-c.vhd +rtl/vhdl/gcpad_basic-c.vhd +rtl/vhdl/gcpad_full-c.vhd +bench/vhdl/gcpad_mod-c.vhd +bench/vhdl/tb-c.vhd Index: README =================================================================== --- README (nonexistent) +++ README (revision 38) @@ -0,0 +1,114 @@ + +README for the GCpad core +========================= +Version: $Date: 2004-10-28 20:00:12 $ + + +Description +----------- + +The GCpad core interfaces to the gamepad used with the Nintendo Gamecube video +gaming system. The core communicates with the gamepad using its proprietary +communication protocol and offers the retrieved information for further +processing. + +To suit the needs of the integrating system, two different flavors of the core +are available: + + * For simple applications the basic flavor manages all communication issues + with the gamepad and provides the current status of the buttons and analog + axes at its interface. The integrating system does not need to interfere + with gamepad communication and can statically read the button and axes + status information. + + * The full flavor allows full control of the gamepad communication by the + integrating system. This flavor offers a command and response interface + which is driven by the system to send arbitrary commands to the + gamepad. The response of the gamepad is available for further processing. + + +Connecting the Pad +------------------ + +Information is exchanged between the gamepad and the host side over a single +wire. Both sides seem to implement an open-collector style output +driver. Therefore, an external pull-up resistor of 1kOhm to the 3.43V supply +is required at the DATA line. +Sticking exactly to the 3.3V supply seems not to be necessary. I use the 3.3V +supply which is available from the FPGA board. Please note that the 5V supply +is required for certain controller types even if the rumble motor is not used. + +The connector seems to be a special type designed for the Gamecube. It might +be hard to find a matching counterpart. If you do not want to rip up the +controller cable then your alternative option might be to reuse an extension +cable. They are quite cheap and pass through all required wires. Just remove +the connector that is plugged into the console and attach your favorite +standard connector. + +See gcpad.png. + + +Verification +------------ + +The GCpad core comes with a simple testbench that includes a simulation model +of a Gamecube controller. Serial information is sent to the core and the +reported button states are compared against the input. Both flavors are tested +in parallel there. +You should normally not need to run the testbench. But in case you modified +the VHDL code the testbench gives some hints if the design has been broken. + + +Directory Structure +------------------- + +The core's directory structure follows the proposal of OpenCores.org. + +gcpad + | + \--+-- doc : Integration Manual + | + +-- rtl + | | + | \-- vhdl : VHDL code containing the RTL description + | of the core. + | + +-- bench + | | + | \-- vhdl : VHDL testbench code. + | + \-- sim + | + \-- rtl_sim : Directory for running simulations. + + +Compiling the VHDL Code +----------------------- + +VHDL compilation and simulation tasks take place inside in sim/rtl_sim +directory. The project setup supports only the GHDL simulator (see +http://ghdl.free.fr). + +To compile the code simply type at the shell + +$ make + +This should result in a file called tb_behav_c0 which can be executed as any +other executable. + +The basic simple sequence list can be found in COMPILE_LIST. This can be +useful to quickly set up the analyze stage of any compiler or +synthesizer. Especially when synthesizing the code, you want to skip the VHDL +configurations in *-c.vhd and everything below the bench/ directory. + + +References +---------- + + * James' excellent page covering many details of the Gamecube controller + protocol + http://www.int03.co.uk/crema/hardware/gamecube/gc-control.htm + + * Yet Another Gamecube Documentation + http://www.gc-linux.org/docs/yagcd/index.html + Refer to section 5.8, 9.1 and 9.2. Index: gcpad.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: gcpad.png =================================================================== --- gcpad.png (nonexistent) +++ gcpad.png (revision 38)

gcpad.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: bench/vhdl/tb.vhd =================================================================== --- bench/vhdl/tb.vhd (nonexistent) +++ bench/vhdl/tb.vhd (revision 38) @@ -0,0 +1,676 @@ +------------------------------------------------------------------------------- +-- +-- Testbench for the +-- GCpad controller core +-- +-- $Id: tb.vhd,v 1.4 2004-10-10 20:19:49 arniml Exp $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/gamepads/ +-- +-- The project homepage is located at: +-- http://www.opencores.org/projects.cgi/web/gamepads/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity tb is + +end tb; + + +use work.gcpad_pack.all; +use work.gcpad_comp.gcpad_basic; +use work.gcpad_comp.gcpad_full; + +architecture behav of tb is + + ----------------------------------------------------------------------------- + -- Some known commands for the GC controller + ----------------------------------------------------------------------------- + constant cmd_get_id_c : std_logic_vector(7 downto 0) := "00000000"; + constant cmd_poll_c : std_logic_vector(7 downto 0) := "01000000"; + + + component gcpad_mod + generic ( + clocks_per_1us_g : natural := 2 + ); + port ( + clk_i : in std_logic; + pad_data_io : inout std_logic; + rx_data_i : in std_logic_vector(63 downto 0) + ); + end component; + + constant period_c : time := 100 ns; + constant reset_level_c : natural := 0; + constant clocks_per_1us_c : natural := 10; + + signal clk_s : std_logic; + signal reset_s : std_logic; + + -- signals for basic gcpad + signal stimuli_1_end_s : boolean; + signal pad_data_1_s : std_logic; + signal buttons_1_s : std_logic_vector(64 downto 0); + signal pad_request_1_s : std_logic; + signal pad_avail_1_s : std_logic; + signal pad_model_data_1_s : std_logic_vector(63 downto 0); + + -- signals for full gcpad + signal stimuli_2_end_s : boolean; + signal pad_data_2_s : std_logic; + signal pad_request_2_s : std_logic; + signal pad_avail_2_s : std_logic; + signal pad_timeout_2_s : std_logic; + signal tx_size_2_s : std_logic_vector( 1 downto 0); + signal tx_command_2_s : std_logic_vector(23 downto 0); + signal rx_size_2_s : std_logic_vector( 3 downto 0); + signal rx_data_2_s : std_logic_vector(63 downto 0); + signal pad_model_data_2_s : std_logic_vector(63 downto 0); + +begin + + basic_b : gcpad_basic + generic map ( + reset_level_g => reset_level_c, + clocks_per_1us_g => clocks_per_1us_c + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + pad_request_i => pad_request_1_s, + pad_avail_o => pad_avail_1_s, + pad_data_io => pad_data_1_s, + but_a_o => buttons_1_s(56), + but_b_o => buttons_1_s(57), + but_x_o => buttons_1_s(58), + but_y_o => buttons_1_s(59), + but_z_o => buttons_1_s(52), + but_start_o => buttons_1_s(60), + but_tl_o => buttons_1_s(54), + but_tr_o => buttons_1_s(53), + but_left_o => buttons_1_s(48), + but_right_o => buttons_1_s(49), + but_up_o => buttons_1_s(51), + but_down_o => buttons_1_s(50), + ana_joy_x_o => buttons_1_s(47 downto 40), + ana_joy_y_o => buttons_1_s(39 downto 32), + ana_c_x_o => buttons_1_s(31 downto 24), + ana_c_y_o => buttons_1_s(23 downto 16), + ana_l_o => buttons_1_s(15 downto 8), + ana_r_o => buttons_1_s( 7 downto 0) + ); + + buttons_1_s(64) <= '0'; + buttons_1_s(63 downto 61) <= (others => '0'); + buttons_1_s(55) <= '1'; + + + full_b: gcpad_full + generic map ( + reset_level_g => reset_level_c, + clocks_per_1us_g => clocks_per_1us_c + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + pad_request_i => pad_request_2_s, + pad_avail_o => pad_avail_2_s, + pad_timeout_o => pad_timeout_2_s, + tx_size_i => tx_size_2_s, + tx_command_i => tx_command_2_s, + rx_size_i => rx_size_2_s, + rx_data_o => rx_data_2_s, + pad_data_io => pad_data_2_s + ); + + + pad_1 : gcpad_mod + generic map ( + clocks_per_1us_g => clocks_per_1us_c + ) + port map ( + clk_i => clk_s, + pad_data_io => pad_data_1_s, + rx_data_i => pad_model_data_1_s + ); + + + ----------------------------------------------------------------------------- + -- Process stimuli_pad_1 + -- + -- Executes test stimuli with Pad 1, the gcpad_basic flavour. + -- + stimuli_pad_1: process + + --------------------------------------------------------------------------- + -- Procedure poll_pad + -- + -- Requests the status of Pad 1 and checks the received data. + -- + procedure poll_pad(packet : in std_logic_vector(63 downto 0)) is + begin + wait until clk_s'event and clk_s = '1'; + wait for 1 ns; + + pad_model_data_1_s <= packet; + + -- send request; + pad_request_1_s <= '1'; + wait for 1 * period_c; + pad_request_1_s <= '0'; + + wait for 10 * 40 * period_c; + + wait until pad_avail_1_s = '1'; + wait for 10 * period_c; + + -- check result + for i in 0 to packet'high loop + assert packet(i) = buttons_1_s(i) + report "Button mismatch on Pad 1!" + severity error; + end loop; + + end poll_pad; + -- + --------------------------------------------------------------------------- + + + --------------------------------------------------------------------------- + -- Procedure timeout_gcpad + -- + -- Generates a timeout in gcpad_basic by disturbing the communication. + -- + procedure timeout_gcpad is + begin + wait until clk_s'event and clk_s = '1'; + wait for 1 ns; + + -- send request; + pad_request_1_s <= '1'; + wait for 1 * period_c; + pad_request_1_s <= '0'; + + wait for 2 * period_c; + + -- disturb communication + pad_data_1_s <= 'X'; + + wait until pad_avail_1_s = '1'; + wait for 10 * period_c; + pad_data_1_s <= 'H'; + wait for 10 * period_c; + + end timeout_gcpad; + -- + --------------------------------------------------------------------------- + + begin + stimuli_1_end_s <= false; + + pad_data_1_s <= 'H'; + pad_request_1_s <= '0'; + pad_model_data_1_s <= (others => '0'); + + wait until reset_s = '1'; + wait for period_c * 4; + + timeout_gcpad; + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000"); + wait for clocks_per_1us_c * 100 * period_c; + poll_pad(packet => "0001111111111111111111111111111111111111111111111111111111111111"); + poll_pad(packet => "0001000010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000100010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000010010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000001010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000110000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000101010101010101010101010101010101010101010101010101010101010"); + poll_pad(packet => "0001010111010101010101010101010101010101010101010101010101010101"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000011000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010100000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010010000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010001000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000100000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000010000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000001000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000100000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000010000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000001000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000100000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000010000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000001000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000100000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000010000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000001000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000100000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000010000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000001000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000100000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000010000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000001000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000100000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000010000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000001000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000100000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000010000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000001000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000100000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000010000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000001000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000100000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000010000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000001000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000100000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000010000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000001000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000100000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000010000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000001000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000100000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000010000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000001000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000100000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000010000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000001000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000100000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000010000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000001000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000100000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000010000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000001000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000100"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000010"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000001"); + + + wait for period_c * 2*40; + stimuli_1_end_s <= true; + wait; + + end process stimuli_pad_1; + -- + ----------------------------------------------------------------------------- + + + pad_2 : gcpad_mod + generic map ( + clocks_per_1us_g => clocks_per_1us_c + ) + port map ( + clk_i => clk_s, + pad_data_io => pad_data_2_s, + rx_data_i => pad_model_data_2_s + ); + + + ----------------------------------------------------------------------------- + -- Process stimuli_pad_2 + -- + -- Executes test stimuli with Pad 2, the gcpad_full flavour. + -- + stimuli_pad_2: process + + --------------------------------------------------------------------------- + -- Procedure issue_command + -- + -- Sets the transmitter command for Pad 2 and starts the request. + -- + procedure issue_command(cmd : in std_logic_vector(23 downto 0); + size : in std_logic_vector( 1 downto 0)) is + begin + wait until clk_s'event and clk_s = '1'; + wait for 1 ns; + + tx_command_2_s <= cmd; + tx_size_2_s <= size; + -- send request; + pad_request_2_s <= '1'; + wait for 1 * period_c; + pad_request_2_s <= '0'; + + end issue_command; + -- + --------------------------------------------------------------------------- + + + --------------------------------------------------------------------------- + -- Procedure poll_pad + -- + -- Requests the status of Pad 2 and checks the received data. + -- + procedure poll_pad(packet : in std_logic_vector(63 downto 0)) is + variable cmd_v : std_logic_vector(23 downto 0); + begin + wait until clk_s'event and clk_s = '1'; + wait for 1 ns; + + -- set up model answer + pad_model_data_2_s <= packet; + -- set expected number of bytes for gcpad_full + rx_size_2_s <= "1000"; + + cmd_v(23 downto 16) := cmd_poll_c; + cmd_v(15 downto 0) := "0000001100000010"; + issue_command(cmd => cmd_v, + size => "11"); + + wait until pad_avail_2_s = '1'; + + assert pad_timeout_2_s = '0' + report "Timout signalled on Pad 2 during status polling!" + severity error; + + -- check result + for i in 0 to packet'high loop + assert packet(i) = rx_data_2_s(i) + report "Data mismatch on Pad 2!" + severity error; + end loop; + + end poll_pad; + -- + --------------------------------------------------------------------------- + + + --------------------------------------------------------------------------- + -- Procedure timeout_gcpad_x + -- + -- Generates a timeout in gcpad_full by disturbing the communication. + -- + procedure timeout_gcpad_x is + variable cmd_v : std_logic_vector(23 downto 0); + begin + wait until clk_s'event and clk_s = '1'; + wait for 1 ns; + + pad_model_data_2_s <= (others => '0'); + rx_size_2_s <= "1000"; + + + cmd_v(23 downto 16) := cmd_poll_c; + cmd_v(15 downto 0) := "0000001100000010"; + issue_command(cmd => cmd_v, + size => "11"); + + -- disturb communication + pad_data_2_s <= 'X'; + + wait until pad_avail_1_s = '1'; + wait for 10 * period_c; + pad_data_2_s <= 'H'; + wait for 10 * period_c; + + assert pad_timeout_2_s = '1' + report "No timeout indicated on Pad 2 when communication has been disturbed!" + severity error; + + end timeout_gcpad_x; + -- + --------------------------------------------------------------------------- + + + --------------------------------------------------------------------------- + -- Procedure timeout_gcpad_short + -- + -- Generates a timeout in gcpad_full by requesting too many bytes for + -- a "get id" command. + -- + procedure timeout_gcpad_short is + variable cmd_v : std_logic_vector(23 downto 0); + begin + wait until clk_s'event and clk_s = '1'; + wait for 1 ns; + + -- expect too many number of bytes + -- command is "get id", will yield 3 bytes, but 8 bytes are requested + rx_size_2_s <= "1000"; + + + cmd_v(23 downto 16) := cmd_get_id_c; + cmd_v(15 downto 0) := (others => '1'); + issue_command(cmd => cmd_v, + size => "01"); + + wait until pad_avail_2_s = '1'; + + assert pad_timeout_2_s = '1' + report "No timout indicated on Pad 2 when too many bytes requested!" + severity error; + + end timeout_gcpad_short; + -- + --------------------------------------------------------------------------- + + + --------------------------------------------------------------------------- + -- Procedure get_id + -- + -- Requests the ID information from the GC controller model. + -- + procedure get_id is + variable cmd_v : std_logic_vector(23 downto 0); + constant id_c : std_logic_vector(23 downto 0) := "000010010000000000000000"; + begin + wait until clk_s'event and clk_s = '1'; + wait for 1 ns; + + rx_size_2_s <= "0011"; + + + cmd_v(23 downto 16) := cmd_get_id_c; + cmd_v(15 downto 0) := (others => '1'); + issue_command(cmd => cmd_v, + size => "01"); + + wait until pad_avail_2_s = '1'; + + assert pad_timeout_2_s = '0' + report "Timout signalled on Pad 2 during get id!" + severity error; + + -- check result + for i in 0 to id_c'high loop + assert id_c(i) = rx_data_2_s(i) + report "ID mismatch on Pad 2!" + severity error; + end loop; + + end get_id; + -- + --------------------------------------------------------------------------- + +begin + stimuli_2_end_s <= false; + + pad_data_2_s <= 'H'; + pad_request_2_s <= '0'; + tx_size_2_s <= (others => '0'); + tx_command_2_s <= (others => '0'); + rx_size_2_s <= (others => '0'); + pad_model_data_2_s <= (others => '0'); + + wait until reset_s = '1'; + wait for period_c * 4; + + + get_id; + timeout_gcpad_x; + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000"); + wait for clocks_per_1us_c * 100 * period_c; + poll_pad(packet => "0001111111111111111111111111111111111111111111111111111111111111"); + timeout_gcpad_short; + poll_pad(packet => "0001000010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000100010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000010010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000001010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000110000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000101010101010101010101010101010101010101010101010101010101010"); + poll_pad(packet => "0001010111010101010101010101010101010101010101010101010101010101"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000011000000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010100000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010010000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010001000000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000100000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000010000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000001000000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000100000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000010000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000001000000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000100000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000010000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000001000000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000100000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000010000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000001000000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000100000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000010000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000001000000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000100000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000010000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000001000000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000100000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000010000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000001000000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000100000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000010000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000001000000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000100000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000010000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000001000000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000100000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000010000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000001000000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000100000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000010000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000001000000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000100000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000010000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000001000000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000100000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000010000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000001000000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000100000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000010000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000001000000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000100000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000010000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000001000000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000100000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000010000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000001000"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000100"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000010"); + poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000001"); + + + wait for period_c * 2*40; + stimuli_2_end_s <= true; + wait; + + end process stimuli_pad_2; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Clock Generator + ----------------------------------------------------------------------------- + clk: process + begin + clk_s <= '0'; + wait for period_c / 2; + clk_s <= '1'; + wait for period_c / 2; + end process clk; + + + ----------------------------------------------------------------------------- + -- Reset Generator + ----------------------------------------------------------------------------- + reset: process + begin + if reset_level_c = 0 then + reset_s <= '0'; + else + reset_s <= '1'; + end if; + + wait for period_c * 4 + 10 ns; + + reset_s <= not reset_s; + + wait; + end process reset; + + + ----------------------------------------------------------------------------- + -- End of simulation detection + ----------------------------------------------------------------------------- + eos: process (stimuli_1_end_s, stimuli_2_end_s) + begin + if stimuli_1_end_s and stimuli_2_end_s then + assert false + report "End of simulation reached." + severity failure; + end if; + end process eos; + +end behav; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.3 2004/10/10 17:27:44 arniml +-- added second pad +-- introduced testbench model for GC controller +-- +-- Revision 1.2 2004/10/09 17:05:59 arniml +-- delay assertion of request signal by real time (instead of delta cycles) +-- +-- Revision 1.1 2004/10/07 21:24:06 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- Index: bench/vhdl/gcpad_mod.vhd =================================================================== --- bench/vhdl/gcpad_mod.vhd (nonexistent) +++ bench/vhdl/gcpad_mod.vhd (revision 38) @@ -0,0 +1,207 @@ +------------------------------------------------------------------------------- +-- +-- A testbench model for the +-- GCpad controller core +-- +-- $Id: gcpad_mod.vhd,v 1.3 2004-10-10 20:12:06 arniml Exp $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/gamepads/ +-- +-- The project homepage is located at: +-- http://www.opencores.org/projects.cgi/web/gamepads/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity gcpad_mod is + + generic ( + clocks_per_1us_g : natural := 2 + ); + port ( + clk_i : in std_logic; + pad_data_io : inout std_logic; + rx_data_i : in std_logic_vector(63 downto 0) + ); + +end gcpad_mod; + + +architecture behav of gcpad_mod is + + ----------------------------------------------------------------------------- + -- Procedure wait_n_us + -- + -- Purpose: + -- Waits for the given number of clk_i cycles. + -- + procedure wait_n_us(clocks : in natural) is + begin + wait until clk_i = '0'; + for i in 1 to clocks loop + wait until clk_i = '1'; + wait until clk_i = '0'; + end loop; + end wait_n_us; + -- + ----------------------------------------------------------------------------- + + signal time_cnt_q : natural; + signal timeout_s : boolean; + +begin + + ----------------------------------------------------------------------------- + -- Process timeout + -- + -- Purpose: + -- Detects a timeout on incoming pad data stream after 5 us of + -- inactivity. Resynchronizes upon falling edge of pad_data_io. + -- + timeout: process (clk_i, pad_data_io) + begin + if pad_data_io = '0' then + timeout_s <= false; + time_cnt_q <= 0; + elsif clk_i'event and clk_i = '1' then + time_cnt_q <= time_cnt_q + 1; + + if time_cnt_q > 5 * clocks_per_1us_g then + timeout_s <= true; + else + timeout_s <= false; + end if; + end if; + end process timeout; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process model + -- + -- Purpose: + -- Simple model for the functionality of a GC controller pad. + -- + model: process + + procedure send_packet(packet : in std_logic_vector) is + variable time_low_v, time_high_v : time; + begin + for i in packet'high downto 0 loop + if packet(i) = '0' then + time_low_v := 3 us; + time_high_v := 1 us; + else + time_low_v := 1 us; + time_high_v := 3 us; + end if; + + pad_data_io <= '0'; + wait for time_low_v; + + pad_data_io <= 'H'; + wait for time_high_v; + + end loop; + + end send_packet; + + + variable command_v : std_logic_vector(24 downto 0); + constant id_c : std_logic_vector(23 downto 0) := "000010010000000000000000"; + begin + + loop + command_v := (others => '1'); + pad_data_io <= 'Z'; + + ------------------------------------------------------------------------- + -- Step 1: + -- Receive command and associated data. + -- + wait until pad_data_io = '0'; + wait for 1 ns; + for i in 24 downto 0 loop + -- skip rest if timeout occured + if not timeout_s then + wait_n_us(2 * clocks_per_1us_g); + + command_v(i) := pad_data_io; + + if pad_data_io = '0' then + wait until pad_data_io /= '0'; + end if; + + -- wait for high -> low edge + wait until (pad_data_io = '0') or timeout_s; + + end if; + + wait for 1 ns; + end loop; + + ------------------------------------------------------------------------- + -- Detect command and send response + -- + case command_v(24 downto 17) is + -- get ID + when "00000000" => + wait_n_us(5 * clocks_per_1us_g); + send_packet(id_c); + send_packet("1"); + + -- poll status + when "0H000000" => + wait_n_us(5 * clocks_per_1us_g); + send_packet(rx_data_i); + send_packet("1"); + + when others => + null; + + end case; + + end loop; + end process model; + -- + ----------------------------------------------------------------------------- + +end behav; Index: bench/vhdl/tb-c.vhd =================================================================== --- bench/vhdl/tb-c.vhd (nonexistent) +++ bench/vhdl/tb-c.vhd (revision 38) @@ -0,0 +1,28 @@ +------------------------------------------------------------------------------- +-- +-- Testbench for the +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: tb-c.vhd,v 1.2 2004-10-10 17:27:36 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_behav_c0 of tb is + + for behav + for basic_b : gcpad_basic + use configuration work.gcpad_basic_struct_c0; + end for; + + for full_b : gcpad_full + use configuration work.gcpad_full_struct_c0; + end for; + + for all : gcpad_mod + use configuration work.gcpad_mod_behav_c0; + end for; + end for; + +end tb_behav_c0; Index: bench/vhdl/gcpad_mod-c.vhd =================================================================== --- bench/vhdl/gcpad_mod-c.vhd (nonexistent) +++ bench/vhdl/gcpad_mod-c.vhd (revision 38) @@ -0,0 +1,17 @@ +------------------------------------------------------------------------------- +-- +-- A testbench model for the +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: gcpad_mod-c.vhd,v 1.1 2004-10-10 17:26:28 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration gcpad_mod_behav_c0 of gcpad_mod is + + for behav + end for; + +end gcpad_mod_behav_c0; Index: sim/rtl_sim/Makefile =================================================================== --- sim/rtl_sim/Makefile (nonexistent) +++ sim/rtl_sim/Makefile (revision 38) @@ -0,0 +1,124 @@ +############################################################################## +# +# Tool-specific Makefile for the GHDL compiler. +# +# $Id: Makefile,v 1.3 2004-10-10 17:28:21 arniml Exp $ +# +# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +# +# All rights reserved +# +############################################################################## + + +PROJECT_DIR = ../.. +RTL_DIR = $(PROJECT_DIR)/rtl/vhdl +BENCH_DIR = $(PROJECT_DIR)/bench/vhdl + + + +ANALYZE=ghdl -a --std=87 --workdir=work +ELABORATE=ghdl -e --std=87 --workdir=work + +.PHONY: all +all: work elaborate + +work: + mkdir work + +work/gcpad_pack-p.o: $(RTL_DIR)/gcpad_pack-p.vhd + $(ANALYZE) $(RTL_DIR)/gcpad_pack-p.vhd + +work/gcpad_sampler.o: $(RTL_DIR)/gcpad_sampler.vhd \ + work/gcpad_pack-p.o + $(ANALYZE) $(RTL_DIR)/gcpad_sampler.vhd +work/gcpad_sampler-c.o: $(RTL_DIR)/gcpad_sampler-c.vhd \ + work/gcpad_sampler.o + $(ANALYZE) $(RTL_DIR)/gcpad_sampler-c.vhd + +work/gcpad_rx.o: $(RTL_DIR)/gcpad_rx.vhd \ + work/gcpad_sampler.o \ + work/gcpad_pack-p.o + $(ANALYZE) $(RTL_DIR)/gcpad_rx.vhd +work/gcpad_rx-c.o: $(RTL_DIR)/gcpad_rx-c.vhd \ + work/gcpad_sampler-c.o \ + work/gcpad_rx.o + $(ANALYZE) $(RTL_DIR)/gcpad_rx-c.vhd + +work/gcpad_tx.o: $(RTL_DIR)/gcpad_tx.vhd \ + work/gcpad_pack-p.o + $(ANALYZE) $(RTL_DIR)/gcpad_tx.vhd +work/gcpad_tx-c.o: $(RTL_DIR)/gcpad_tx-c.vhd \ + work/gcpad_tx.o + $(ANALYZE) $(RTL_DIR)/gcpad_tx-c.vhd + +work/gcpad_ctrl.o: $(RTL_DIR)/gcpad_ctrl.vhd \ + work/gcpad_pack-p.o + $(ANALYZE) $(RTL_DIR)/gcpad_ctrl.vhd +work/gcpad_ctrl-c.o: $(RTL_DIR)/gcpad_ctrl-c.vhd \ + work/gcpad_ctrl.o + $(ANALYZE) $(RTL_DIR)/gcpad_ctrl-c.vhd + +work/gcpad_basic.o: $(RTL_DIR)/gcpad_basic.vhd \ + work/gcpad_pack-p.o \ + work/gcpad_ctrl.o \ + work/gcpad_tx.o \ + work/gcpad_rx.o + $(ANALYZE) $(RTL_DIR)/gcpad_basic.vhd +work/gcpad_basic-c.o: $(RTL_DIR)/gcpad_basic-c.vhd \ + work/gcpad_basic.o \ + work/gcpad_ctrl-c.o \ + work/gcpad_tx-c.o \ + work/gcpad_rx-c.o + $(ANALYZE) $(RTL_DIR)/gcpad_basic-c.vhd + +work/gcpad_full.o: $(RTL_DIR)/gcpad_full.vhd \ + work/gcpad_pack-p.o \ + work/gcpad_ctrl.o \ + work/gcpad_tx.o \ + work/gcpad_rx.o + $(ANALYZE) $(RTL_DIR)/gcpad_full.vhd +work/gcpad_full-c.o: $(RTL_DIR)/gcpad_full-c.vhd \ + work/gcpad_full.o \ + work/gcpad_ctrl-c.o \ + work/gcpad_tx-c.o \ + work/gcpad_rx-c.o + $(ANALYZE) $(RTL_DIR)/gcpad_full-c.vhd + +work/gcpad_comp-p.o: $(RTL_DIR)/gcpad_comp-p.vhd + $(ANALYZE) $(RTL_DIR)/gcpad_comp-p.vhd + +work/gcpad_mod.o: $(BENCH_DIR)/gcpad_mod.vhd + $(ANALYZE) $(BENCH_DIR)/gcpad_mod.vhd +work/gcpad_mod-c.o: $(BENCH_DIR)/gcpad_mod-c.vhd \ + work/gcpad_mod.o + $(ANALYZE) $(BENCH_DIR)/gcpad_mod-c.vhd + +work/tb.o: $(BENCH_DIR)/tb.vhd \ + work/gcpad_pack-p.o \ + work/gcpad_comp-p.o \ + work/gcpad_basic.o \ + work/gcpad_full.o \ + work/gcpad_mod.o + $(ANALYZE) $(BENCH_DIR)/tb.vhd +work/tb-c.o: $(BENCH_DIR)/tb-c.vhd \ + work/tb.o \ + work/gcpad_basic-c.o \ + work/gcpad_full-c.o \ + work/gcpad_mod-c.o + $(ANALYZE) $(BENCH_DIR)/tb-c.vhd + + +.PHONY: elaborate +elaborate: tb_behav_c0 + +tb_behav_c0: analyze + $(ELABORATE) tb_behav_c0; \ + strip tb_behav_c0 + +.PHONY: analyze +analyze: work/tb-c.o + +.PHONY: clean +clean: + rm -rf work tb_behav_c0 *~ Index: rtl/vhdl/gcpad_full-c.vhd =================================================================== --- rtl/vhdl/gcpad_full-c.vhd (nonexistent) +++ rtl/vhdl/gcpad_full-c.vhd (revision 38) @@ -0,0 +1,27 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: gcpad_full-c.vhd,v 1.1 2004-10-10 17:25:08 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration gcpad_full_struct_c0 of gcpad_full is + + for struct + for ctrl_b : gcpad_ctrl + use configuration work.gcpad_ctrl_rtl_c0; + end for; + + for tx_b : gcpad_tx + use configuration work.gcpad_tx_rtl_c0; + end for; + + for rx_b : gcpad_rx + use configuration work.gcpad_rx_rtl_c0; + end for; + end for; + +end gcpad_full_struct_c0; Index: rtl/vhdl/gcpad_full.vhd =================================================================== --- rtl/vhdl/gcpad_full.vhd (nonexistent) +++ rtl/vhdl/gcpad_full.vhd (revision 38) @@ -0,0 +1,209 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- $Id: gcpad_full.vhd,v 1.1 2004-10-10 17:25:08 arniml Exp $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/gamepads/ +-- +-- The project homepage is located at: +-- http://www.opencores.org/projects.cgi/web/gamepads/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity gcpad_full is + + generic ( + -- active level of reset_i + reset_level_g : integer := 0; + -- number of clk_i periods during 1us + clocks_per_1us_g : integer := 2 + ); + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + -- Pad Communication Interface -------------------------------------------- + pad_request_i : in std_logic; + pad_avail_o : out std_logic; + pad_timeout_o : out std_logic; + tx_size_i : in std_logic_vector( 1 downto 0); + tx_command_i : in std_logic_vector(23 downto 0); + rx_size_i : in std_logic_vector( 3 downto 0); + rx_data_o : out std_logic_vector(63 downto 0); + -- Gamepad Interface ------------------------------------------------------ + pad_data_io : inout std_logic + ); + +end gcpad_full; + + +use work.gcpad_pack.all; + +architecture struct of gcpad_full is + + component gcpad_ctrl + generic ( + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + pad_request_i : in std_logic; + pad_avail_o : out std_logic; + rx_timeout_o : out std_logic; + tx_start_o : out boolean; + tx_finished_i : in boolean; + rx_en_o : out boolean; + rx_done_i : in boolean; + rx_data_ok_i : in boolean + ); + end component; + + component gcpad_tx + generic ( + reset_level_g : natural := 0; + clocks_per_1us_g : natural := 2 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + pad_data_o : out std_logic; + tx_start_i : in boolean; + tx_finished_o : out boolean; + tx_size_i : in std_logic_vector( 1 downto 0); + tx_command_i : in std_logic_vector(23 downto 0) + ); + end component; + + component gcpad_rx + generic ( + reset_level_g : integer := 0; + clocks_per_1us_g : integer := 2 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + rx_en_i : in boolean; + rx_done_o : out boolean; + rx_data_ok_o : out boolean; + rx_size_i : in std_logic_vector(3 downto 0); + pad_data_i : in std_logic; + rx_data_o : out buttons_t + ); + end component; + + + signal pad_data_tx_s : std_logic; + + signal tx_start_s : boolean; + signal tx_finished_s : boolean; + + signal rx_en_s, + rx_done_s, + rx_data_ok_s : boolean; + +begin + + ctrl_b : gcpad_ctrl + generic map ( + reset_level_g => reset_level_g + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + pad_request_i => pad_request_i, + pad_avail_o => pad_avail_o, + rx_timeout_o => pad_timeout_o, + tx_start_o => tx_start_s, + tx_finished_i => tx_finished_s, + rx_en_o => rx_en_s, + rx_done_i => rx_done_s, + rx_data_ok_i => rx_data_ok_s + ); + + tx_b : gcpad_tx + generic map ( + reset_level_g => reset_level_g, + clocks_per_1us_g => clocks_per_1us_g + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + pad_data_o => pad_data_tx_s, + tx_start_i => tx_start_s, + tx_finished_o => tx_finished_s, + tx_size_i => tx_size_i, + tx_command_i => tx_command_i + ); + + rx_b : gcpad_rx + generic map ( + reset_level_g => reset_level_g, + clocks_per_1us_g => clocks_per_1us_g + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + rx_en_i => rx_en_s, + rx_done_o => rx_done_s, + rx_data_ok_o => rx_data_ok_s, + rx_size_i => rx_size_i, + pad_data_i => pad_data_io, + rx_data_o => rx_data_o + ); + + + ----------------------------------------------------------------------------- + -- Open collector driver to pad data + ----------------------------------------------------------------------------- + pad_data_io <= '0' + when pad_data_tx_s = '0' else + 'Z'; + +end struct; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: not supported by cvs2svn $ +------------------------------------------------------------------------------- Index: rtl/vhdl/gcpad_comp-p.vhd =================================================================== --- rtl/vhdl/gcpad_comp-p.vhd (nonexistent) +++ rtl/vhdl/gcpad_comp-p.vhd (revision 38) @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: gcpad_comp-p.vhd,v 1.1 2004-10-10 10:09:15 arniml Exp $ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package gcpad_comp is + + component gcpad_basic + generic ( + reset_level_g : integer := 0; + clocks_per_1us_g : integer := 2 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + pad_request_i : in std_logic; + pad_avail_o : out std_logic; + pad_data_io : inout std_logic; + but_a_o : out std_logic; + but_b_o : out std_logic; + but_x_o : out std_logic; + but_y_o : out std_logic; + but_z_o : out std_logic; + but_start_o : out std_logic; + but_tl_o : out std_logic; + but_tr_o : out std_logic; + but_left_o : out std_logic; + but_right_o : out std_logic; + but_up_o : out std_logic; + but_down_o : out std_logic; + ana_joy_x_o : out std_logic_vector(7 downto 0); + ana_joy_y_o : out std_logic_vector(7 downto 0); + ana_c_x_o : out std_logic_vector(7 downto 0); + ana_c_y_o : out std_logic_vector(7 downto 0); + ana_l_o : out std_logic_vector(7 downto 0); + ana_r_o : out std_logic_vector(7 downto 0) + ); + end component; + + component gcpad_full + generic ( + reset_level_g : integer := 0; + clocks_per_1us_g : integer := 2 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + pad_request_i : in std_logic; + pad_avail_o : out std_logic; + pad_timeout_o : out std_logic; + tx_size_i : in std_logic_vector( 1 downto 0); + tx_command_i : in std_logic_vector(23 downto 0); + rx_size_i : in std_logic_vector( 3 downto 0); + rx_data_o : out std_logic_vector(63 downto 0); + pad_data_io : inout std_logic + ); + end component; + + +end gcpad_comp; Index: rtl/vhdl/gcpad_basic.vhd =================================================================== --- rtl/vhdl/gcpad_basic.vhd (nonexistent) +++ rtl/vhdl/gcpad_basic.vhd (revision 38) @@ -0,0 +1,275 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- $Id: gcpad_basic.vhd,v 1.5 2004-10-09 22:18:35 arniml Exp $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/gamepads/ +-- +-- The project homepage is located at: +-- http://www.opencores.org/projects.cgi/web/gamepads/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity gcpad_basic is + + generic ( + -- active level of reset_i + reset_level_g : integer := 0; + -- number of clk_i periods during 1us + clocks_per_1us_g : integer := 2 + ); + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + pad_request_i : in std_logic; + pad_avail_o : out std_logic; + -- Gamepad Interface ------------------------------------------------------ + pad_data_io : inout std_logic; + -- Buttons Interface ------------------------------------------------------ + but_a_o : out std_logic; + but_b_o : out std_logic; + but_x_o : out std_logic; + but_y_o : out std_logic; + but_z_o : out std_logic; + but_start_o : out std_logic; + but_tl_o : out std_logic; + but_tr_o : out std_logic; + but_left_o : out std_logic; + but_right_o : out std_logic; + but_up_o : out std_logic; + but_down_o : out std_logic; + ana_joy_x_o : out std_logic_vector(7 downto 0); + ana_joy_y_o : out std_logic_vector(7 downto 0); + ana_c_x_o : out std_logic_vector(7 downto 0); + ana_c_y_o : out std_logic_vector(7 downto 0); + ana_l_o : out std_logic_vector(7 downto 0); + ana_r_o : out std_logic_vector(7 downto 0) + ); + +end gcpad_basic; + + +use work.gcpad_pack.all; + +architecture struct of gcpad_basic is + + component gcpad_ctrl + generic ( + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + pad_request_i : in std_logic; + pad_avail_o : out std_logic; + rx_timeout_o : out std_logic; + tx_start_o : out boolean; + tx_finished_i : in boolean; + rx_en_o : out boolean; + rx_done_i : in boolean; + rx_data_ok_i : in boolean + ); + end component; + + component gcpad_tx + generic ( + reset_level_g : natural := 0; + clocks_per_1us_g : natural := 2 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + pad_data_o : out std_logic; + tx_start_i : in boolean; + tx_finished_o : out boolean; + tx_size_i : in std_logic_vector( 1 downto 0); + tx_command_i : in std_logic_vector(23 downto 0) + ); + end component; + + component gcpad_rx + generic ( + reset_level_g : integer := 0; + clocks_per_1us_g : integer := 2 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + rx_en_i : in boolean; + rx_done_o : out boolean; + rx_data_ok_o : out boolean; + rx_size_i : in std_logic_vector(3 downto 0); + pad_data_i : in std_logic; + rx_data_o : out buttons_t + ); + end component; + + + ----------------------------------------------------------------------------- + -- constants for standard status polling + constant rx_size_c : std_logic_vector( 3 downto 0) := "1000"; + signal rx_size_s : std_logic_vector( 3 downto 0); + -- + constant tx_size_c : std_logic_vector( 1 downto 0) := "11"; + signal tx_size_s : std_logic_vector( 1 downto 0); + -- + constant tx_command_c : std_logic_vector(23 downto 0) := "010000000000001100000010"; + signal tx_command_s : std_logic_vector(23 downto 0); + -- + ----------------------------------------------------------------------------- + + signal pad_data_tx_s : std_logic; + + signal tx_start_s : boolean; + signal tx_finished_s : boolean; + + signal rx_en_s, + rx_done_s, + rx_data_ok_s : boolean; + + signal rx_data_s : buttons_t; + +begin + + rx_size_s <= rx_size_c; + tx_size_s <= tx_size_c; + tx_command_s <= tx_command_c; + + ctrl_b : gcpad_ctrl + generic map ( + reset_level_g => reset_level_g + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + pad_request_i => pad_request_i, + pad_avail_o => pad_avail_o, + rx_timeout_o => open, + tx_start_o => tx_start_s, + tx_finished_i => tx_finished_s, + rx_en_o => rx_en_s, + rx_done_i => rx_done_s, + rx_data_ok_i => rx_data_ok_s + ); + + tx_b : gcpad_tx + generic map ( + reset_level_g => reset_level_g, + clocks_per_1us_g => clocks_per_1us_g + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + pad_data_o => pad_data_tx_s, + tx_start_i => tx_start_s, + tx_finished_o => tx_finished_s, + tx_size_i => tx_size_s, + tx_command_i => tx_command_s + ); + + rx_b : gcpad_rx + generic map ( + reset_level_g => reset_level_g, + clocks_per_1us_g => clocks_per_1us_g + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + rx_en_i => rx_en_s, + rx_done_o => rx_done_s, + rx_data_ok_o => rx_data_ok_s, + rx_size_i => rx_size_s, + pad_data_i => pad_data_io, + rx_data_o => rx_data_s + ); + + + ----------------------------------------------------------------------------- + -- Open collector driver to pad data + ----------------------------------------------------------------------------- + pad_data_io <= '0' + when pad_data_tx_s = '0' else + 'Z'; + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + but_a_o <= rx_data_s(pos_a_c); + but_b_o <= rx_data_s(pos_b_c); + but_x_o <= rx_data_s(pos_x_c); + but_y_o <= rx_data_s(pos_y_c); + but_z_o <= rx_data_s(pos_z_c); + but_start_o <= rx_data_s(pos_start_c); + but_tl_o <= rx_data_s(pos_tl_c); + but_tr_o <= rx_data_s(pos_tr_c); + but_left_o <= rx_data_s(pos_left_c); + but_right_o <= rx_data_s(pos_right_c); + but_up_o <= rx_data_s(pos_up_c); + but_down_o <= rx_data_s(pos_down_c); + ana_joy_x_o <= rx_data_s(joy_x_high_c downto joy_x_low_c); + ana_joy_y_o <= rx_data_s(joy_y_high_c downto joy_y_low_c); + ana_c_x_o <= rx_data_s(c_x_high_c downto c_x_low_c); + ana_c_y_o <= rx_data_s(c_y_high_c downto c_y_low_c); + ana_l_o <= rx_data_s(l_high_c downto l_low_c); + ana_r_o <= rx_data_s(r_high_c downto r_low_c); + +end struct; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2004/10/09 17:03:43 arniml +-- enhance handshaking between gcpad_rx and gcpad_ctrl +-- +-- Revision 1.3 2004/10/09 00:33:55 arniml +-- shift rx_data to button assignment to toplevel +-- +-- Revision 1.2 2004/10/08 20:51:59 arniml +-- turn rx and tx size into bytes instead of bits +-- +-- Revision 1.1 2004/10/07 21:23:10 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- Index: rtl/vhdl/gcpad_rx.vhd =================================================================== --- rtl/vhdl/gcpad_rx.vhd (nonexistent) +++ rtl/vhdl/gcpad_rx.vhd (revision 38) @@ -0,0 +1,386 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- $Id: gcpad_rx.vhd,v 1.5 2004-10-09 17:05:12 arniml Exp $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/gamepads/ +-- +-- The project homepage is located at: +-- http://www.opencores.org/projects.cgi/web/gamepads/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use work.gcpad_pack.buttons_t; + +entity gcpad_rx is + + generic ( + reset_level_g : integer := 0; + clocks_per_1us_g : integer := 2 + ); + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + -- Control Interface ------------------------------------------------------ + rx_en_i : in boolean; + rx_done_o : out boolean; + rx_data_ok_o : out boolean; + rx_size_i : in std_logic_vector(3 downto 0); + -- Gamepad Interface ------------------------------------------------------ + pad_data_i : in std_logic; + -- Data Interface --------------------------------------------------------- + rx_data_o : out buttons_t + ); + +end gcpad_rx; + + +library ieee; +use ieee.numeric_std.all; +use work.gcpad_pack.all; + +architecture rtl of gcpad_rx is + + component gcpad_sampler + generic ( + reset_level_g : integer := 0; + clocks_per_1us_g : integer := 2 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + wrap_sample_i : in boolean; + sync_sample_i : in boolean; + sample_underflow_o : out boolean; + pad_data_i : in std_logic; + pad_data_o : out std_logic; + sample_o : out std_logic + ); + end component; + + type state_t is (IDLE, + DETECT_TIMEOUT, + WAIT_FOR_1, + WAIT_FOR_0, + FINISHED); + signal state_s, + state_q : state_t; + + signal buttons_q, + shift_buttons_q : buttons_t; + signal save_buttons_s : boolean; + signal shift_buttons_s : boolean; + + signal sync_sample_s : boolean; + signal wrap_sample_s : boolean; + + -- timeout counter counts three sample undeflows + constant cnt_timeout_high_c : natural := 3; + subtype cnt_timeout_t is natural range 0 to cnt_timeout_high_c; + signal cnt_timeout_q : cnt_timeout_t; + signal timeout_q : boolean; + signal sync_timeout_s : boolean; + + + subtype num_buttons_read_t is unsigned(6 downto 0); + signal num_buttons_read_q : num_buttons_read_t; + signal all_buttons_read_s : boolean; + signal reset_num_buttons_s : boolean; + + signal pad_data_s : std_logic; + signal sample_s : std_logic; + signal sample_underflow_s : boolean; + + signal rx_done_s, + rx_done_q : boolean; + +begin + + sampler_b : gcpad_sampler + generic map ( + reset_level_g => reset_level_g, + clocks_per_1us_g => clocks_per_1us_g + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + wrap_sample_i => wrap_sample_s, + sync_sample_i => sync_sample_s, + sample_underflow_o => sample_underflow_s, + pad_data_i => pad_data_i, + pad_data_o => pad_data_s, + sample_o => sample_s + ); + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements of this module. + -- + seq: process (reset_i, clk_i) + variable size_v : std_logic_vector(num_buttons_read_t'range); + begin + if reset_i = reset_level_g then + buttons_q <= (others => '0'); + shift_buttons_q <= (others => '0'); + + state_q <= IDLE; + + cnt_timeout_q <= cnt_timeout_high_c; + + timeout_q <= false; + + num_buttons_read_q <= (others => '0'); + rx_done_q <= false; + + elsif clk_i'event and clk_i = '1' then + state_q <= state_s; + + rx_done_q <= rx_done_s; + + -- timeout counter + if sync_timeout_s then + -- explicit preload + cnt_timeout_q <= cnt_timeout_high_c; + timeout_q <= false; + elsif cnt_timeout_q = 0 then + -- wrap-around + cnt_timeout_q <= cnt_timeout_high_c; + timeout_q <= true; + elsif sample_underflow_s then + -- decrement counter when sampler wraps around + cnt_timeout_q <= cnt_timeout_q - 1; + end if; + + + -- count remaining number of buttons to read + if shift_buttons_s then + shift_buttons_q(buttons_t'high downto 1) <= shift_buttons_q(buttons_t'high-1 downto 0); + + if sample_s = '1' then + shift_buttons_q(0) <= '1'; + else + shift_buttons_q(0) <= '0'; + end if; + + end if; + + if reset_num_buttons_s then + -- explicit preload + size_v(num_buttons_read_t'high downto 3) := rx_size_i; + size_v(2 downto 0) := (others => '0'); + num_buttons_read_q <= unsigned(size_v); + elsif shift_buttons_s then + -- decrement counter when a button bit has been read + if not all_buttons_read_s then + num_buttons_read_q <= num_buttons_read_q - 1; + end if; + end if; + + + -- the buttons + if save_buttons_s then + buttons_q <= shift_buttons_q; + end if; + + end if; + + end process seq; + -- + ----------------------------------------------------------------------------- + + -- indicates that all buttons have been read + all_buttons_read_s <= num_buttons_read_q = 0; + + + ----------------------------------------------------------------------------- + -- Process fsm + -- + -- Purpose: + -- Models the controlling state machine. + -- + fsm: process (state_q, + rx_en_i, + pad_data_s, + wrap_sample_s, + all_buttons_read_s, + sample_underflow_s, + timeout_q) + begin + sync_sample_s <= false; + sync_timeout_s <= false; + state_s <= IDLE; + shift_buttons_s <= false; + save_buttons_s <= false; + rx_done_s <= false; + reset_num_buttons_s <= false; + wrap_sample_s <= false; + + case state_q is + -- IDLE ----------------------------------------------------------------- + -- The idle state. + when IDLE => + if rx_en_i then + state_s <= DETECT_TIMEOUT; + + else + -- keep counters synchronized when no reception is running + sync_sample_s <= true; + sync_timeout_s <= true; + reset_num_buttons_s <= true; + state_s <= IDLE; + + end if; + + when DETECT_TIMEOUT => + state_s <= DETECT_TIMEOUT; + + if pad_data_s = '0' then + sync_sample_s <= true; + state_s <= WAIT_FOR_1; + + else + -- wait for timeout + wrap_sample_s <= true; + if timeout_q then + rx_done_s <= true; + state_s <= IDLE; + end if; + + end if; + + + -- WAIT_FOR_1 ----------------------------------------------------------- + -- Sample counter has expired and a 0 bit has been detected. + -- We must now wait for pad_data_s to become 1. + -- Or abort upon timeout. + when WAIT_FOR_1 => + if pad_data_s = '0' then + if not sample_underflow_s then + state_s <= WAIT_FOR_1; + else + -- timeout while reading buttons! + rx_done_s <= true; + state_s <= IDLE; + end if; + + else + state_s <= WAIT_FOR_0; + end if; + + -- WAIT_FOR_0 ----------------------------------------------------------- + -- pad_data_s is at 1 level now and no timeout occured so far. + -- We wait for the next 0 level on pad_data_s or abort upon timeout. + when WAIT_FOR_0 => + -- wait for falling edge of pad data + if pad_data_s = '0' then + sync_sample_s <= true; + + -- loop again in any case + state_s <= WAIT_FOR_1; + if not all_buttons_read_s then + shift_buttons_s <= true; + end if; + + else + if sample_underflow_s then + if all_buttons_read_s then + -- last button was read + -- so it's ok to timeout + state_s <= FINISHED; + else + -- timeout while reading buttons! + rx_done_s <= true; + state_s <= IDLE; + end if; + + else + state_s <= WAIT_FOR_0; + + end if; + + end if; + + when FINISHED => + -- finally save buttons + save_buttons_s <= true; + rx_done_s <= true; + + when others => + null; + + end case; + + end process fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + rx_done_o <= rx_done_q; + rx_data_ok_o <= save_buttons_s; + rx_data_o <= buttons_q; + + +end rtl; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2004/10/09 00:33:55 arniml +-- shift rx_data to button assignment to toplevel +-- +-- Revision 1.3 2004/10/08 21:18:39 arniml +-- move sampler to separate unit +-- +-- Revision 1.2 2004/10/08 20:51:59 arniml +-- turn rx and tx size into bytes instead of bits +-- +-- Revision 1.1 2004/10/07 21:23:10 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- Index: rtl/vhdl/gcpad_ctrl.vhd =================================================================== --- rtl/vhdl/gcpad_ctrl.vhd (nonexistent) +++ rtl/vhdl/gcpad_ctrl.vhd (revision 38) @@ -0,0 +1,250 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- $Id: gcpad_ctrl.vhd,v 1.2 2004-10-09 17:04:36 arniml Exp $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/gamepads/ +-- +-- The project homepage is located at: +-- http://www.opencores.org/projects.cgi/web/gamepads/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity gcpad_ctrl is + + generic ( + reset_level_g : integer := 0 + ); + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + pad_request_i : in std_logic; + pad_avail_o : out std_logic; + rx_timeout_o : out std_logic; + -- Control Interface ------------------------------------------------------ + tx_start_o : out boolean; + tx_finished_i : in boolean; + rx_en_o : out boolean; + rx_done_i : in boolean; + rx_data_ok_i : in boolean + ); + +end gcpad_ctrl; + + +use work.gcpad_pack.all; + +architecture rtl of gcpad_ctrl is + + type state_t is (IDLE, + TX, + RX1_START, + RX1_WAIT, + RX2_START, + RX2_WAIT, + RX3_START, + RX3_WAIT, + RX4_START, + RX4_WAIT); + signal state_s, + state_q : state_t; + + signal set_txrx_finished_s : boolean; + signal enable_txrx_finished_s : boolean; + signal txrx_finished_q : std_logic; + + signal timeout_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements. + -- + seq: process (reset_i, clk_i) + begin + if reset_i = reset_level_g then + state_q <= IDLE; + + txrx_finished_q <= '0'; + + timeout_q <= '1'; + + elsif clk_i'event and clk_i = '1' then + state_q <= state_s; + + -- transmit/receive finished flag + if set_txrx_finished_s then + txrx_finished_q <= '1'; + elsif pad_request_i = '1' then + txrx_finished_q <= '0'; + end if; + + if pad_request_i = '1' then + timeout_q <= '1'; + elsif rx_data_ok_i then + timeout_q <= '0'; + end if; + + end if; + + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process fsm + -- + -- Purpose: + -- Models the controlling state machine. + -- + fsm: process (state_q, + tx_finished_i, + rx_done_i, + pad_request_i) + begin + rx_en_o <= false; + state_s <= IDLE; + tx_start_o <= false; + set_txrx_finished_s <= false; + enable_txrx_finished_s <= false; + + case state_q is + when IDLE => + -- enable output of txrx_finished flag + -- the flag has to be suppressed while the FSM probes four times + enable_txrx_finished_s <= true; + + if pad_request_i = '1' then + state_s <= TX; + tx_start_o <= true; + else + state_s <= IDLE; + end if; + + when TX => + if not tx_finished_i then + state_s <= TX; + else + state_s <= RX1_START; + end if; + + when RX1_START => + rx_en_o <= true; + state_s <= RX1_WAIT; + + when RX1_WAIT => + if rx_done_i then + state_s <= RX2_START; + else + state_s <= RX1_WAIT; + end if; + + when RX2_START => + rx_en_o <= true; + state_s <= RX2_WAIT; + + when RX2_WAIT => + if rx_done_i then + state_s <= RX3_START; + else + state_s <= RX2_WAIT; + end if; + + when RX3_START => + rx_en_o <= true; + state_s <= RX3_WAIT; + + when RX3_WAIT => + if rx_done_i then + state_s <= RX4_START; + else + state_s <= RX3_WAIT; + end if; + + when RX4_START => + rx_en_o <= true; + state_s <= RX4_WAIT; + + when RX4_WAIT => + if rx_done_i then + state_s <= IDLE; + set_txrx_finished_s <= true; + else + state_s <= RX4_WAIT; + end if; + + when others => + null; + + end case; + + end process fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + pad_avail_o <= txrx_finished_q + when enable_txrx_finished_s else + '0'; + rx_timeout_o <= timeout_q + when enable_txrx_finished_s else + '0'; + +end rtl; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2004/10/07 21:23:10 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- Index: rtl/vhdl/gcpad_sampler.vhd =================================================================== --- rtl/vhdl/gcpad_sampler.vhd (nonexistent) +++ rtl/vhdl/gcpad_sampler.vhd (revision 38) @@ -0,0 +1,169 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- $Id: gcpad_sampler.vhd,v 1.3 2004-10-09 00:33:12 arniml Exp $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/gamepads/ +-- +-- The project homepage is located at: +-- http://www.opencores.org/projects.cgi/web/gamepads/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity gcpad_sampler is + + generic ( + reset_level_g : integer := 0; + clocks_per_1us_g : integer := 2 + ); + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + -- Control Interface ------------------------------------------------------ + wrap_sample_i : in boolean; + sync_sample_i : in boolean; + sample_underflow_o : out boolean; + -- Pad Interface ---------------------------------------------------------- + pad_data_i : in std_logic; + pad_data_o : out std_logic; + sample_o : out std_logic + ); + +end gcpad_sampler; + + +use work.gcpad_pack.all; + +architecture rtl of gcpad_sampler is + + signal pad_data_sync_q : std_logic_vector(1 downto 0); + signal pad_data_s : std_logic; + + constant cnt_sample_high_c : natural := clocks_per_1us_g * 4 - 1; + subtype cnt_sample_t is natural range 0 to cnt_sample_high_c; + signal cnt_zeros_q : cnt_sample_t; + signal cnt_ones_q : cnt_sample_t; + signal sample_underflow_q : boolean; + + signal more_ones_q : boolean; + +begin + + seq: process (reset_i, clk_i) + variable dec_timeout_v : boolean; + begin + if reset_i = reset_level_g then + cnt_zeros_q <= cnt_sample_high_c; + cnt_ones_q <= cnt_sample_high_c; + more_ones_q <= false; + sample_underflow_q <= false; + + pad_data_sync_q <= (others => '1'); + + elsif clk_i'event and clk_i = '1' then + -- synchronizer for pad data + pad_data_sync_q(0) <= pad_data_i; + pad_data_sync_q(1) <= pad_data_sync_q(0); + + -- sample counter + dec_timeout_v := false; + if sync_sample_i then + -- explicit preload + cnt_zeros_q <= cnt_sample_high_c; + cnt_ones_q <= cnt_sample_high_c; + else + if cnt_zeros_q = 0 then + if wrap_sample_i then + cnt_zeros_q <= cnt_sample_high_c; + end if; + dec_timeout_v := true; + elsif pad_data_s = '0' then + cnt_zeros_q <= cnt_zeros_q - 1; + end if; + + if cnt_ones_q = 0 then + if wrap_sample_i then + cnt_ones_q <= cnt_sample_high_c; + end if; + dec_timeout_v := true; + elsif pad_data_s /= '0' then + cnt_ones_q <= cnt_ones_q - 1; + end if; + end if; + + if cnt_ones_q < cnt_zeros_q then + more_ones_q <= true; + else + more_ones_q <= false; + end if; + + -- detect sample underflow + sample_underflow_q <= dec_timeout_v; + + end if; + + end process seq; + + pad_data_s <= pad_data_sync_q(1); + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + pad_data_o <= pad_data_s; + sample_o <= '1' + when more_ones_q else + '0'; + sample_underflow_o <= sample_underflow_q; + +end rtl; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/10/08 21:35:08 arniml +-- comments +-- +------------------------------------------------------------------------------- Index: rtl/vhdl/gcpad_sampler-c.vhd =================================================================== --- rtl/vhdl/gcpad_sampler-c.vhd (nonexistent) +++ rtl/vhdl/gcpad_sampler-c.vhd (revision 38) @@ -0,0 +1,16 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: gcpad_sampler-c.vhd,v 1.1 2004-10-08 21:19:17 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration gcpad_sampler_rtl_c0 of gcpad_sampler is + + for rtl + end for; + +end gcpad_sampler_rtl_c0; Index: rtl/vhdl/gcpad_rx-c.vhd =================================================================== --- rtl/vhdl/gcpad_rx-c.vhd (nonexistent) +++ rtl/vhdl/gcpad_rx-c.vhd (revision 38) @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: gcpad_rx-c.vhd,v 1.2 2004-10-08 21:18:39 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration gcpad_rx_rtl_c0 of gcpad_rx is + + for rtl + for sampler_b : gcpad_sampler + use configuration work.gcpad_sampler_rtl_c0; + end for; + end for; + +end gcpad_rx_rtl_c0; Index: rtl/vhdl/gcpad_tx.vhd =================================================================== --- rtl/vhdl/gcpad_tx.vhd (nonexistent) +++ rtl/vhdl/gcpad_tx.vhd (revision 38) @@ -0,0 +1,312 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- $Id: gcpad_tx.vhd,v 1.2 2004-10-08 20:51:59 arniml Exp $ +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/gamepads/ +-- +-- The project homepage is located at: +-- http://www.opencores.org/projects.cgi/web/gamepads/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity gcpad_tx is + + generic ( + reset_level_g : natural := 0; + clocks_per_1us_g : natural := 2 + ); + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + -- Pad Interface ---------------------------------------------------------- + pad_data_o : out std_logic; + -- Control Interface ------------------------------------------------------ + tx_start_i : in boolean; + tx_finished_o : out boolean; + tx_size_i : in std_logic_vector( 1 downto 0); + tx_command_i : in std_logic_vector(23 downto 0) + ); + +end gcpad_tx; + + +library ieee; +use ieee.numeric_std.all; + +use work.gcpad_pack.all; + +architecture rtl of gcpad_tx is + + subtype command_t is std_logic_vector(24 downto 0); + + signal command_q : command_t; + signal load_command_s : boolean; + signal shift_bits_s : boolean; + + constant cnt_long_c : natural := clocks_per_1us_g * 4 - 1; + constant cnt_short_c : natural := clocks_per_1us_g * 1 - 1; + subtype cnt_t is natural range 0 to cnt_long_c; + signal cnt_q : cnt_t; + signal cnt_load_long_s : boolean; + signal cnt_load_short_s : boolean; + signal cnt_finished_s : boolean; + + subtype num_bits_t is unsigned(4 downto 0); + signal num_bits_q : num_bits_t; + signal all_bits_sent_s : boolean; + signal cnt_bit_s : boolean; + + type state_t is (IDLE, + LOAD_COMMAND, + SEND_COMMAND_PHASE1, + SEND_COMMAND_PHASE2); + signal state_s, + state_q : state_t; + + signal pad_data_s, + pad_data_q : std_logic; + + signal tx_finished_s, + tx_finished_q : boolean; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements of this module. + -- + seq: process (reset_i, clk_i) + variable size_v : std_logic_vector(num_bits_t'range); + begin + if reset_i = reset_level_g then + command_q <= (others => '1'); + cnt_q <= cnt_long_c; + num_bits_q <= (others => '0'); + pad_data_q <= '1'; + state_q <= IDLE; + tx_finished_q <= false; + + elsif clk_i'event and clk_i = '1' then + tx_finished_q <= tx_finished_s; + + -- fsm + state_q <= state_s; + + -- command register and bit counter + if load_command_s then + command_q(24 downto 1) <= tx_command_i; + command_q(0) <= '1'; + + -- workaround for GHDL concatenation + size_v(num_bits_t'high downto 3) := tx_size_i; + size_v(2 downto 0) := (others => '0'); + num_bits_q <= unsigned(size_v) + 1; + + else + if shift_bits_s then + command_q(command_t'high downto 1) <= command_q(command_t'high-1 downto 0); + end if; + + if cnt_bit_s and not all_bits_sent_s then + num_bits_q <= num_bits_q - 1; + end if; + + end if; + + + -- PWM counter + if cnt_load_long_s then + cnt_q <= cnt_long_c; + elsif cnt_load_short_s then + cnt_q <= cnt_short_c; + else + if not cnt_finished_s then + cnt_q <= cnt_q - 1; + end if; + end if; + + -- PWM output = pad data + pad_data_q <= pad_data_s; + + end if; + + end process seq; + -- + ----------------------------------------------------------------------------- + + -- indicates that PWM counter has finished + cnt_finished_s <= cnt_q = 0; + -- indicates that all bits have been sent + all_bits_sent_s <= num_bits_q = 0; + + + ----------------------------------------------------------------------------- + -- Process fsm + -- + -- Purpose: + -- Models the controlling state machine. + -- + fsm: process (state_q, + cnt_finished_s, + all_bits_sent_s, + tx_start_i, + command_q) + begin + -- defaul assignments + state_s <= IDLE; + shift_bits_s <= false; + cnt_load_long_s <= false; + cnt_load_short_s <= false; + pad_data_s <= '1'; + tx_finished_s <= false; + load_command_s <= false; + cnt_bit_s <= false; + + case state_q is + -- IDLE ----------------------------------------------------------------- + -- The idle state. + -- Advances when the transmitter is started + when IDLE => + if tx_start_i then + state_s <= LOAD_COMMAND; + else + state_s <= IDLE; + end if; + + + -- LOAD_COMMAND --------------------------------------------------------- + -- Prepares the first and all subsequent low phases on pad_data_s. + when LOAD_COMMAND => + state_s <= SEND_COMMAND_PHASE2; + load_command_s <= true; + + -- start counter once to kick the loop + cnt_load_short_s <= true; + + + -- SEND_COMMAND_PHASE1 -------------------------------------------------- + -- Wait for completion of phase 1, the low phase of pad_data_s. + -- The high phase is prepared when the PWM counter has expired. + when SEND_COMMAND_PHASE1 => + state_s <= SEND_COMMAND_PHASE1; + pad_data_s <= '0'; + + if cnt_finished_s then + -- initiate high phase + pad_data_s <= '1'; + if command_q(command_t'high) = '1' then + cnt_load_long_s <= true; + else + cnt_load_short_s <= true; + end if; + + state_s <= SEND_COMMAND_PHASE2; + -- provide next bit + shift_bits_s <= true; + + end if; + + -- SEND_COMMAND_PHASE2 -------------------------------------------------- + -- Wait for completion of phase 2, the high phase of pad_data_s. + -- The next low phase is prepared when the PWM counter has expired. + -- In case all bits have been sent, the tx handshake is asserted and + -- the FSM returns to IDLE state. + when SEND_COMMAND_PHASE2 => + pad_data_s <= '1'; + state_s <= SEND_COMMAND_PHASE2; + + if cnt_finished_s then + if not all_bits_sent_s then + -- more bits to send so loop + + -- prepare low phase + if command_q(command_t'high) = '1' then + cnt_load_short_s <= true; + else + cnt_load_long_s <= true; + end if; + + -- decrement bit counter + cnt_bit_s <= true; + + state_s <= SEND_COMMAND_PHASE1; + + else + -- all bits sent, we're finished + tx_finished_s <= true; + state_s <= IDLE; + + end if; + + end if; + + when others => + null; + + end case; + + end process fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + tx_finished_o <= tx_finished_q; + pad_data_o <= pad_data_q; + +end rtl; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2004/10/07 21:23:10 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- Index: rtl/vhdl/gcpad_basic-c.vhd =================================================================== --- rtl/vhdl/gcpad_basic-c.vhd (nonexistent) +++ rtl/vhdl/gcpad_basic-c.vhd (revision 38) @@ -0,0 +1,27 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: gcpad_basic-c.vhd,v 1.1 2004-10-07 21:23:10 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration gcpad_basic_struct_c0 of gcpad_basic is + + for struct + for ctrl_b : gcpad_ctrl + use configuration work.gcpad_ctrl_rtl_c0; + end for; + + for tx_b : gcpad_tx + use configuration work.gcpad_tx_rtl_c0; + end for; + + for rx_b : gcpad_rx + use configuration work.gcpad_rx_rtl_c0; + end for; + end for; + +end gcpad_basic_struct_c0; Index: rtl/vhdl/gcpad_ctrl-c.vhd =================================================================== --- rtl/vhdl/gcpad_ctrl-c.vhd (nonexistent) +++ rtl/vhdl/gcpad_ctrl-c.vhd (revision 38) @@ -0,0 +1,16 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: gcpad_ctrl-c.vhd,v 1.1 2004-10-07 21:23:10 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration gcpad_ctrl_rtl_c0 of gcpad_ctrl is + + for rtl + end for; + +end gcpad_ctrl_rtl_c0; Index: rtl/vhdl/gcpad_pack-p.vhd =================================================================== --- rtl/vhdl/gcpad_pack-p.vhd (nonexistent) +++ rtl/vhdl/gcpad_pack-p.vhd (revision 38) @@ -0,0 +1,98 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: gcpad_pack-p.vhd,v 1.1 2004-10-07 21:23:10 arniml Exp $ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package gcpad_pack is + + subtype analog_axis_t is std_logic_vector(7 downto 0); + constant num_buttons_c : natural := 64; + subtype buttons_t is std_logic_vector(num_buttons_c-1 downto 0); + + function "=" (a : in std_logic; b : in integer) return boolean; + + ----------------------------------------------------------------------------- + -- The button positions inside a gc packet + ----------------------------------------------------------------------------- + -- byte 7 ------------------------------------------------------------------- + constant pos_errstat_c : natural := 63; + constant pos_errlatch_c : natural := 62; + constant pos_unknown1_c : natural := 61; + constant pos_start_c : natural := 60; + constant pos_y_c : natural := 59; + constant pos_x_c : natural := 58; + constant pos_b_c : natural := 57; + constant pos_a_c : natural := 56; + -- byte 6 ------------------------------------------------------------------- + constant pos_unknown2_c : natural := 55; + constant pos_tl_c : natural := 54; + constant pos_tr_c : natural := 53; + constant pos_z_c : natural := 52; + constant pos_up_c : natural := 51; + constant pos_down_c : natural := 50; + constant pos_right_c : natural := 49; + constant pos_left_c : natural := 48; + -- byte 5 ------------------------------------------------------------------- + constant joy_x_high_c : natural := 47; + constant joy_x_low_c : natural := 40; + -- byte 4 ------------------------------------------------------------------- + constant joy_y_high_c : natural := 39; + constant joy_y_low_c : natural := 32; + -- byte 3 ------------------------------------------------------------------- + constant c_x_high_c : natural := 31; + constant c_x_low_c : natural := 24; + -- byte 2 ------------------------------------------------------------------- + constant c_y_high_c : natural := 23; + constant c_y_low_c : natural := 16; + -- byte 1 ------------------------------------------------------------------- + constant l_high_c : natural := 15; + constant l_low_c : natural := 8; + -- byte 0 ------------------------------------------------------------------- + constant r_high_c : natural := 7; + constant r_low_c : natural := 0; + +end gcpad_pack; + + +package body gcpad_pack is + + ----------------------------------------------------------------------------- + -- Function = + -- + -- Compares a std_logic with an integer. + -- + function "=" (a : in std_logic; b : in integer) return boolean is + variable result_v : boolean; + begin + result_v := false; + + case a is + when '0' => + if b = 0 then + result_v := true; + end if; + + when '1' => + if b = 1 then + result_v := true; + end if; + + when others => + null; + + end case; + + return result_v; + end; + -- + ----------------------------------------------------------------------------- + +end gcpad_pack; Index: rtl/vhdl/gcpad_tx-c.vhd =================================================================== --- rtl/vhdl/gcpad_tx-c.vhd (nonexistent) +++ rtl/vhdl/gcpad_tx-c.vhd (revision 38) @@ -0,0 +1,16 @@ +------------------------------------------------------------------------------- +-- +-- GCpad controller core +-- +-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +-- +-- $Id: gcpad_tx-c.vhd,v 1.1 2004-10-07 21:23:10 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration gcpad_tx_rtl_c0 of gcpad_tx is + + for rtl + end for; + +end gcpad_tx_rtl_c0;

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