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URL https://opencores.org/ocsvn/gbiteth/gbiteth/trunk

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Rev 2 → Rev 3

/trunk/rtl/rgmii/eth_ddr_in.vhd
0,0 → 1,108
-- megafunction wizard: %ALTDDIO_IN%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTDDIO_IN
 
-- ============================================================
-- File Name: eth_ddr_in.vhd
-- Megafunction Name(s):
-- ALTDDIO_IN
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
 
ENTITY eth_ddr_in IS
PORT
(
datain : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
inclock : IN STD_LOGIC ;
dataout_h : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END eth_ddr_in;
 
 
ARCHITECTURE SYN OF eth_ddr_in IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
 
BEGIN
dataout_h <= sub_wire0(4 DOWNTO 0);
dataout_l <= sub_wire1(4 DOWNTO 0);
 
ALTDDIO_IN_component : ALTDDIO_IN
GENERIC MAP (
intended_device_family => "Cyclone IV E",
invert_input_clocks => "OFF",
lpm_hint => "UNUSED",
lpm_type => "altddio_in",
power_up_high => "OFF",
width => 5
)
PORT MAP (
datain => datain,
inclock => inclock,
dataout_h => sub_wire0,
dataout_l => sub_wire1
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL "datain[4..0]"
-- Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0
-- Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL "dataout_h[4..0]"
-- Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0
-- Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL "dataout_l[4..0]"
-- Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.cmp FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_in.ppf TRUE FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/rtl/rgmii/fifo_sc_6x64.vhd
0,0 → 1,185
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
 
-- ============================================================
-- File Name: fifo_sc_6x64.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY fifo_sc_6x64 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END fifo_sc_6x64;
 
 
ARCHITECTURE SYN OF fifo_sc_6x64 IS
 
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (5 DOWNTO 0);
 
 
 
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
rdreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
 
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(5 DOWNTO 0);
 
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "ON",
intended_device_family => "Cyclone IV E",
lpm_numwords => 64,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 6,
lpm_widthu => 6,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "64"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "6"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "6"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL "data[5..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 6 0 data 0 0 6 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 6 0 @q 0 0 6 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_6x64.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_6x64.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_6x64.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_6x64.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_6x64_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/rtl/rgmii/rgmii1000_io.vhd
0,0 → 1,125
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_io.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-10-26
-- Last update: 2013-05-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-10-26 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii1000_io IS
 
PORT (
iRst_n : IN STD_LOGIC;
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
TXC : OUT STD_LOGIC;
TX_CTL : OUT STD_LOGIC;
TD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
RXC : IN STD_LOGIC;
RX_CTL : IN STD_LOGIC;
RD : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
 
---------------------------------------------------------------------------
-- data to PHY
---------------------------------------------------------------------------
iTxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iTxEn : IN STD_LOGIC;
iTxErr : IN STD_LOGIC;
 
---------------------------------------------------------------------------
-- data from PHY
---------------------------------------------------------------------------
oRxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxDV : OUT STD_LOGIC;
oRxErr : OUT STD_LOGIC;
 
---------------------------------------------------------------------------
-- clock for MAC controller
---------------------------------------------------------------------------
oEthClk : OUT STD_LOGIC
);
 
END ENTITY rgmii1000_io;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii1000_io IS
 
SIGNAL ethIOClk : STD_LOGIC;
 
SIGNAL outDataH, outDataL, outData : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL inDataH, inDataL, inData : STD_LOGIC_VECTOR(4 DOWNTO 0);
 
SIGNAL pllLock : STD_LOGIC;
SIGNAL rstSync : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL rst_n : STD_LOGIC;
 
SIGNAL bufClk : STD_LOGIC;
 
SIGNAL ripple : BOOLEAN;
TYPE rxState_t IS (IDLE, RECEIVE);
SIGNAL rxState : rxState_t;
SIGNAL rxData : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rxErr, rxDV : STD_LOGIC;
SIGNAL tmp : STD_LOGIC;
 
SIGNAL rxData2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rxErr2, rxDV2 : STD_LOGIC;
 
SIGNAL rdreq,wrreq : STD_LOGIC;
SIGNAL rdempty : STD_LOGIC;
SIGNAL din,dout : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
 
oEthClk <= ethIOClk;
--oEthClk <= RXC;
TXC <= RXC;
 
pll: entity work.rgmii1000_pll
PORT map
(
inclk0 => RXC,
c0 => ethIOClk
);
 
TD <= outData(3 DOWNTO 0);
TX_CTL <= outData(4);
outDataH <= iTxEn & iTxData(3 DOWNTO 0);
outDataL <= (iTxEn XOR iTxErr) & iTxData(7 DOWNTO 4);
eth_ddr_out_1 : ENTITY work.eth_ddr_out
PORT MAP (
datain_h => outDataH,
datain_l => outDataL,
outclock => ethIOClk,
dataout => outData);
inData <= RX_CTL & RD;
oRxDV <= inDataL(4);
oRxErr <= inDataH(4) XOR inDataL(4);
oRxData <= inDataH(3 DOWNTO 0) & inDataL(3 DOWNTO 0);
eth_ddr_in_1 : ENTITY work.eth_ddr_in
PORT MAP (
datain => inData,
inclock => ethIOClk, -- shift 180~360 degree compared to RXC
dataout_h => inDataH,
dataout_l => inDataL);
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/rgmii100_pll.vhd
0,0 → 1,350
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
 
-- ============================================================
-- File Name: rgmii100_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY rgmii100_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END rgmii100_pll;
 
 
ARCHITECTURE SYN OF rgmii100_pll IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
 
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "20000",
compensate_clock => "CLK0",
inclk0_input_frequency => 40000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=rgmii100_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.500000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "12.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "90.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "rgmii100_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "20000"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
/trunk/rtl/rgmii/eth_ddr_out.vhd
0,0 → 1,110
-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTDDIO_OUT
 
-- ============================================================
-- File Name: eth_ddr_out.vhd
-- Megafunction Name(s):
-- ALTDDIO_OUT
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
 
ENTITY eth_ddr_out IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END eth_ddr_out;
 
 
ARCHITECTURE SYN OF eth_ddr_out IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
 
BEGIN
dataout <= sub_wire0(4 DOWNTO 0);
 
ALTDDIO_OUT_component : ALTDDIO_OUT
GENERIC MAP (
extend_oe_disable => "OFF",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_hint => "UNUSED",
lpm_type => "altddio_out",
oe_reg => "UNREGISTERED",
power_up_high => "OFF",
width => 5
)
PORT MAP (
datain_h => datain_h,
datain_l => datain_l,
outclock => outclock,
dataout => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: datain_h 0 0 5 0 INPUT NODEFVAL "datain_h[4..0]"
-- Retrieval info: CONNECT: @datain_h 0 0 5 0 datain_h 0 0 5 0
-- Retrieval info: USED_PORT: datain_l 0 0 5 0 INPUT NODEFVAL "datain_l[4..0]"
-- Retrieval info: CONNECT: @datain_l 0 0 5 0 datain_l 0 0 5 0
-- Retrieval info: USED_PORT: dataout 0 0 5 0 OUTPUT NODEFVAL "dataout[4..0]"
-- Retrieval info: CONNECT: dataout 0 0 5 0 @dataout 0 0 5 0
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.cmp FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.ppf TRUE FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/rtl/rgmii/rgmii_rx_top.vhd
0,0 → 1,191
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_rx_top.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2013-05-10
-- Last update: 2013-05-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-05-10 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.de2_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_rx_top IS
GENERIC (
MY_MAC : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"10BF487A0FED";
IN_SIMULATION : BOOLEAN := FALSE);
PORT (
iWbClk : IN STD_LOGIC;
iEthClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
iWbS2M : IN wbSlaveToMasterIF_t;
oWbM2S : OUT wbMasterToSlaveIF_t;
-- synthesis translate_off
oWbM2S_dat : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbM2S_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbM2S_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
oWbM2S_cyc : OUT STD_LOGIC;
oWbM2S_stb : OUT STD_LOGIC;
oWbM2S_we : OUT STD_LOGIC;
oWbM2S_cti : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
oWbM2S_bte : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
iWbS2M_ack : IN STD_LOGIC;
-- synthesis translate_on
 
iEnetRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iEnetRxDv : IN STD_LOGIC;
iEnetRxErr : IN STD_LOGIC;
 
iWbRxEn : IN STD_LOGIC;
iWbRxIntEn : IN STD_LOGIC;
iWbRxIntClr : IN STD_LOGIC;
oWbRxIntInfo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
iWbRxDescData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbRxDescData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
iWbRxDescWr : IN STD_LOGIC;
iWbRxDescAddr : IN STD_LOGIC_VECTOR(8 DOWNTO 2);
iRxBufBegin : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
iRxBufEnd : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
 
-- hardware checksum check
iCheckSumIPCheck : IN STD_LOGIC;
iCheckSumTCPCheck : IN STD_LOGIC;
iCheckSumUDPCheck : IN STD_LOGIC;
iCheckSumICMPCheck : IN STD_LOGIC;
oWbRxInt : OUT STD_LOGIC
);
 
END ENTITY rgmii_rx_top;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_rx_top IS
 
SIGNAL cSOF : STD_LOGIC;
SIGNAL cEof : STD_LOGIC;
SIGNAL cErrCrc : STD_LOGIC;
SIGNAL cErrLen : STD_LOGIC;
SIGNAL cGetArp : STD_LOGIC;
SIGNAL cErrCheckSum : STD_LOGIC;
SIGNAL cGetIPv4 : STD_LOGIC;
SIGNAL cGetCtrl : STD_LOGIC;
SIGNAL cGetRaw : STD_LOGIC;
SIGNAL cPayloadLen : UNSIGNED(15 DOWNTO 0);
SIGNAL cRxData : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cRxDV : STD_LOGIC;
 
SIGNAL cRxData32 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cRxInfo : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cRxDataRd, cRxInfoRd, cIntNewFrame, cIntNewFrameClr : STD_LOGIC;
BEGIN -- ARCHITECTURE rtl
 
rgmii_rx_1 : ENTITY work.rgmii_rx
PORT MAP (
iClk => iEthClk,
iRst_n => iRst_n,
iRxData => iEnetRxData,
iRxDV => iEnetRxDv,
iRxEr => iEnetRxErr,
iCheckSumIPCheck => iCheckSumIPCheck,
iCheckSumTCPCheck => iCheckSumTCPCheck,
iCheckSumUDPCheck => iCheckSumUDPCheck,
iCheckSumICMPCheck => iCheckSumICMPCheck,
oEOF => cEof,
oCRCErr => cErrCrc,
oRxErr => OPEN,
oLenErr => cErrLen,
oCheckSumErr => cErrCheckSum,
iMyMAC => MY_MAC,
oGetARP => cGetArp,
oGetIPv4 => cGetIPv4,
oGetCtrl => cGetCtrl,
oGetRaw => cGetRaw,
oSOF => cSOF,
oTaged => OPEN,
oTagInfo => OPEN,
oStackTaged => OPEN,
oTagInfo2 => OPEN,
oLink => OPEN,
oSpeed => OPEN,
oDuplex => OPEN,
oPayloadLen => cPayloadLen,
oRxData => cRxData,
oRxDV => cRxDV);
 
rgmii_rx_buf_1 : ENTITY work.rgmii_rx_buf
PORT MAP (
iEthClk => iEthClk,
iWbClk => iWbClk,
iRst_n => iRst_n,
iEOF => cEof,
iRxData => cRxData,
iPayloadLen => cPayloadLen,
iRxDV => cRxDV,
iErrCRC => cErrCrc,
iErrCheckSum => cErrCheckSum,
iErrLen => cErrLen,
iGetArp => cGetArp,
iGetIPv4 => cGetIPv4,
iGetRaw => cGetRaw,
iSOF => cSOF,
oRxData => cRxData32,
oRxLenInfo => cRxInfo,
iRxDataRead => cRxDataRd,
iRxInfoRead => cRxInfoRd,
oIntNewFrame => cIntNewFrame,
iIntNewFrameClr => cIntNewFrameClr,
iRxEn => iWbRxEn);
 
rgmii_rx_wbm_1 : ENTITY work.rgmii_rx_wbm
GENERIC MAP (
IN_SIMULATION => IN_SIMULATION)
PORT MAP (
iWbClk => iWbClk,
iRst_n => iRst_n,
oWbM2S => oWbM2S,
iWbS2M => iWbS2M,
-- synthesis translate_off
oWbM2S_dat => oWbM2S_dat,
oWbM2S_addr => oWbM2S_addr,
oWbM2S_sel => oWbM2S_sel,
oWbM2S_cyc => oWbM2S_cyc,
oWbM2S_stb => oWbM2S_stb,
oWbM2S_we => oWbM2S_we,
oWbM2S_cti => oWbM2S_cti,
oWbM2S_bte => oWbM2S_bte,
iWbS2M_ack => iWbS2M_ack,
-- synthesis translate_on
 
iIntNewFrame => cIntNewFrame,
oIntNewFrameClr => cIntNewFrameClr,
oRxDataRead => cRxDataRd,
iRxData => cRxData32,
oRxInfoRead => cRxInfoRd,
iRxInfo => cRxInfo,
 
iRegBufBegin => iRxBufBegin,
iRegBufEnd => iRxBufEnd,
iWbAddr => iWbRxDescAddr,
iWbWE => iWbRxDescWr,
iWbData => iWbRxDescData,
oWbData => oWbRxDescData,
iWbRxIntClr => iWbRxIntClr,
oWbRxIntInfo => oWbRxIntInfo,
oWbRxInt => oWbRxInt,
iWbRxIntEn => iWbRxIntEn);
 
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/rgmii_tx_top.vhd
0,0 → 1,164
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_tx_top.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2013-05-10
-- Last update: 2013-05-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-05-10 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.de2_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_tx_top IS
GENERIC (
IN_SIMULATION : BOOLEAN := FALSE);
PORT (
iWbClk : IN STD_LOGIC;
iEthClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
iWbS2M : IN wbSlaveToMasterIF_t;
oWbM2S : OUT wbMasterToSlaveIF_t;
-- synthesis translate_off
oWbM2S_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbM2S_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
oWbM2S_cyc : OUT STD_LOGIC;
oWbM2S_stb : OUT STD_LOGIC;
oWbM2S_we : OUT STD_LOGIC;
oWbM2S_cti : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
oWbM2S_bte : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
iWbS2M_ack : IN STD_LOGIC;
iWbS2M_dat : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- synthesis translate_on
 
oEnetTxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oEnetTxEn : OUT STD_LOGIC;
oEnetTxErr : OUT STD_LOGIC;
 
iWbTxEn : IN STD_LOGIC; -- tx module enable
iWbTxIntEn : IN STD_LOGIC; -- interrupt enable
iWbTxIntClr : IN STD_LOGIC; -- clear interrupt SIGNAL
oWbTxIntInfo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
iWbTxDescData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbTxDescData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
iWbTxDescWr : IN STD_LOGIC;
iWbTxDescAddr : IN STD_LOGIC_VECTOR(8 DOWNTO 2);
 
iCheckSumIPGen : IN STD_LOGIC;
iCheckSumTCPGen : IN STD_LOGIC;
iCheckSumUDPGen : IN STD_LOGIC;
iCheckSumICMPGen : IN STD_LOGIC;
 
oWbTxInt : OUT STD_LOGIC
);
 
END ENTITY rgmii_tx_top;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_tx_top IS
SIGNAL tx_done_info : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL tx_data_32 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL tx_data_32_wr : STD_LOGIC;
SIGNAL tx_info_32 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL tx_info_32_wr : STD_LOGIC;
SIGNAL tx_data_addr : UNSIGNED(10 DOWNTO 0);
 
SIGNAL sof, eof : STD_LOGIC;
SIGNAL cTxData : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cGenFrame : STD_LOGIC;
SIGNAL cGenFrameAck : STD_LOGIC;
BEGIN -- ARCHITECTURE rtl
 
rgmii_tx_1 : ENTITY work.rgmii_tx
PORT MAP (
iClk => iEthClk,
iRst_n => iRst_n,
iTxData => cTxData,
oSOF => sof,
iEOF => eof,
iGenFrame => cGenFrame,
oGenFrameAck => cGenFrameAck,
oTxData => oEnetTxData,
oTxEn => oEnetTxEn,
oTxErr => oEnetTxErr);
 
rgmii_tx_buf_1 : ENTITY work.rgmii_tx_buf
PORT MAP (
iEthClk => iEthClk,
iWbClk => iWbClk,
iRst_n => iRst_n,
 
oEthTxData => cTxData,
iEthSOF => sof,
oEthEOF => eof,
oEthGenFrame => cGenFrame,
iEthGenFrameAck => cGenFrameAck,
iWbTxData => tx_data_32,
iWbTxAddr => tx_data_addr,
iWbTxDataWr => tx_data_32_wr,
iWbTxInfo => tx_info_32,
iWbTxInfoWr => tx_info_32_wr,
iWbIntEn => '0',
iWbIntClr => '0',
oWbInt => OPEN,
oWbTxInfo => tx_done_info);
 
rgmii_tx_wbm_1 : ENTITY work.rgmii_tx_wbm
GENERIC MAP (
IN_SIMULATION => IN_SIMULATION)
PORT MAP (
iWbClk => iWbClk,
iRst_n => iRst_n,
 
oWbM2S => oWbM2S,
iWbS2M => iWbS2M,
-- synthesis translate_off
oWbM2S_addr => oWbM2S_addr,
oWbM2S_sel => oWbM2S_sel,
oWbM2S_cyc => oWbM2S_cyc,
oWbM2S_stb => oWbM2S_stb,
oWbM2S_we => oWbM2S_we,
oWbM2S_cti => oWbM2S_cti,
oWbM2S_bte => oWbM2S_bte,
iWbS2M_ack => iWbS2M_ack,
iWbS2M_dat => iWbS2M_dat,
-- synthesis translate_on
 
iTxDone => '0',
oTxDoneClr => OPEN,
iTxDoneInfo => tx_done_info,
oTxData => tx_data_32,
oTxAddr => tx_data_addr,
oTxDataWr => tx_data_32_wr,
oTxInfo => tx_info_32,
oTxInfoWr => tx_info_32_wr,
 
iCheckSumIPGen => iCheckSumIPGen,
iCheckSumTCPGen => iCheckSumTCPGen,
iCheckSumUDPGen => iCheckSumUDPGen,
iCheckSumICMPGen => iCheckSumICMPGen,
 
iWbTxEnable => iWbTxEn,
oWbTxInt => oWbTxInt,
iWbTxIntClr => iWbTxIntClr,
iWbTxIntEn => iWbTxIntEn,
iWbTxAddr => iWbTxDescAddr,
iWbTxWE => iWbTxDescWr,
iWbTxData => iWbTxDescData,
oWbTxData => oWbTxDescData,
oWbTxIntInfo => oWbTxIntInfo);
 
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/fifo32x8.vhd
0,0 → 1,193
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
 
-- ============================================================
-- File Name: fifo32x8.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY fifo32x8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
END fifo32x8;
 
 
ARCHITECTURE SYN OF fifo32x8 IS
 
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
 
 
 
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC
);
END COMPONENT;
 
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(31 DOWNTO 0);
rdempty <= sub_wire2;
 
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone IV E",
lpm_numwords => 8,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 32,
lpm_widthu => 3,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
wrsync_delaypipe => 4
)
PORT MAP (
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "8"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "32"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "32"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x8.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x6_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/rtl/rgmii/eth_crc32.vhd
0,0 → 1,98
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : eth_crc32.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-11-04
-- Last update: 2012-11-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-04 1.0 root Created
-- 经过测试没有问题！计算后输出到外面的crc值需要按照以太网的大小端模式发送才是正确的！
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY eth_crc32 IS
 
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iInit : IN STD_LOGIC;
iCalcEn : IN STD_LOGIC;
iData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
oCRC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oCRCErr : OUT STD_LOGIC);
 
END ENTITY eth_crc32;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF eth_crc32 IS
 
SIGNAL crc, nxtCrc : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
 
nxtCrc(0) <= crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(1) <= crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(2) <= crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(3) <= crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(4) <= crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(5) <= crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(6) <= crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(7) <= crc(31) XOR iData(0) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR iData(7);
nxtCrc(8) <= crc(0) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR iData(6) XOR crc(24) XOR iData(7);
nxtCrc(9) <= crc(1) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR iData(6);
nxtCrc(10) <= crc(2) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR iData(7);
nxtCrc(11) <= crc(3) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR iData(6) XOR crc(24) XOR iData(7);
nxtCrc(12) <= crc(4) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(13) <= crc(5) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(14) <= crc(6) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5);
nxtCrc(15) <= crc(7) XOR crc(31) XOR iData(0) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4);
nxtCrc(16) <= crc(8) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(24) XOR iData(7);
nxtCrc(17) <= crc(9) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(25) XOR iData(6);
nxtCrc(18) <= crc(10) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(26) XOR iData(5);
nxtCrc(19) <= crc(11) XOR crc(31) XOR iData(0) XOR crc(27) XOR iData(4);
nxtCrc(20) <= crc(12) XOR crc(28) XOR iData(3);
nxtCrc(21) <= crc(13) XOR crc(29) XOR iData(2);
nxtCrc(22) <= crc(14) XOR crc(24) XOR iData(7);
nxtCrc(23) <= crc(15) XOR crc(25) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(24) <= crc(16) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(25) <= crc(17) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5);
nxtCrc(26) <= crc(18) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(27) <= crc(19) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(28) <= crc(20) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(26) XOR iData(5);
nxtCrc(29) <= crc(21) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(27) XOR iData(4);
nxtCrc(30) <= crc(22) XOR crc(31) XOR iData(0) XOR crc(28) XOR iData(3);
nxtCrc(31) <= crc(23) XOR crc(29) XOR iData(2);
 
PROCESS (iClk,iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
crc <= (OTHERS => '0');
ELSIF rising_edge(iClk) THEN
IF iInit = '1' THEN
crc <= (OTHERS => '1');
ELSIF iCalcEn = '1' THEN
crc <= nxtCrc;
END IF;
END IF;
END PROCESS;
oCRC(31 DOWNTO 24) <= NOT (crc(24)&crc(25)&crc(26)&crc(27)&crc(28)&crc(29)&crc(30)&crc(31));
oCRC(23 DOWNTO 16) <= NOT (crc(16)&crc(17)&crc(18)&crc(19)&crc(20)&crc(21)&crc(22)&crc(23));
oCRC(15 DOWNTO 8) <= NOT (crc(8)&crc(9)&crc(10)&crc(11)&crc(12)&crc(13)&crc(14)&crc(15));
oCRC(7 DOWNTO 0) <= NOT (crc(0)&crc(1)&crc(2)&crc(3)&crc(4)&crc(5)&crc(6)&crc(7));
 
oCRCErr <= '1' WHEN crc /= X"c704dd7b" ELSE '0'; -- CRC not equal to magic number
END ARCHITECTURE rtl;
 
/trunk/rtl/rgmii/rgmii_rx_buf.vhd
0,0 → 1,239
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_rx_buf.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2013-05-05
-- Last update: 2013-05-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-05-05 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_rx_buf IS
 
PORT (
iEthClk : IN STD_LOGIC;
iWbClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
iEOF : IN STD_LOGIC;
iRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iPayloadLen : IN UNSIGNED(15 DOWNTO 0);
iRxDV : IN STD_LOGIC;
iErrCRC : IN STD_LOGIC;
iErrLen : IN STD_LOGIC;
iErrCheckSum: IN STD_LOGIC;
iGetArp : IN STD_LOGIC;
iGetIPv4 : IN STD_LOGIC;
iGetRaw : IN STD_LOGIC;
iSOF : IN STD_LOGIC;
 
oRxData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oRxLenInfo : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
iRxDataRead : IN STD_LOGIC;
iRxInfoRead : IN STD_LOGIC;
 
oIntNewFrame : OUT STD_LOGIC;
iIntNewFrameClr : IN STD_LOGIC;
 
-- receive enable
iRxEn : IN STD_LOGIC
);
 
END ENTITY rgmii_rx_buf;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_rx_buf IS
 
CONSTANT DATA_WIDTH : NATURAL := 32;
CONSTANT ADDR_WIDTH : NATURAL := 11;
-- Build a 2-D array type for the RAM
SUBTYPE word_t IS STD_LOGIC_VECTOR((DATA_WIDTH-1) DOWNTO 0);
TYPE memory_t IS ARRAY(2**ADDR_WIDTH-1 DOWNTO 0) OF word_t;
-- Declare the RAM signal.
SIGNAL ram : memory_t := (OTHERS => (OTHERS => '0'));
SIGNAL raddr : NATURAL RANGE 0 TO 2**ADDR_WIDTH - 1;
SIGNAL waddr : NATURAL RANGE 0 TO 2**ADDR_WIDTH - 1;
SIGNAL rWE : STD_LOGIC;
SIGNAL rRxData : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
SIGNAL rRxInfoI : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cRxInfoO : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cInfoFifoRd : STD_LOGIC;
SIGNAL rInfoFifoWr : STD_LOGIC;
SIGNAL cInfoFifoEmpty : STD_LOGIC;
SIGNAL cInfoFifoFull : STD_LOGIC;
 
BEGIN -- ARCHITECTURE rtl
 
blk0 : BLOCK IS
TYPE state_t IS (IDLE, DATA);
SIGNAL rState : state_t;
SIGNAL rCnt : UNSIGNED(1 DOWNTO 0);
SIGNAL rBeginAddr : NATURAL RANGE 0 TO 2**ADDR_WIDTH - 1;
 
--SIGNAL rNewFrame : STD_LOGIC;
--SIGNAL rNewFrameD : STD_LOGIC_VECTOR(1 DOWNTO 0);
 
SIGNAL rInfoFifoRdD1 : STD_LOGIC;
BEGIN -- BLOCK blk0
PROCESS (iEthClk, iRst_n) IS
--VARIABLE vGetFrame : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF iRst_n = '0' THEN
rState <= IDLE;
rCnt <= (OTHERS => '0');
waddr <= 0;
rBeginAddr <= 0;
rWE <= '0';
--rNewFrame <= '0';
rRxInfoI(15+ADDR_WIDTH DOWNTO 0) <= (OTHERS => '0');
rInfoFifoWr <= '0';
rRxInfoI(31 DOWNTO 28) <= (OTHERS => '0');
ELSIF rising_edge(iEthClk) THEN
rWE <= '0';
rInfoFifoWr <= '0';
--rRxInfoI(27 DOWNTO ADDR_WIDTH+16) <= (OTHERS => '0');
IF rWE = '1' THEN
-- synthesis translate_off
IF waddr < 2**ADDR_WIDTH-1 THEN
-- synthesis translate_on
waddr <= waddr + 1;
-- synthesis translate_off
END IF;
-- synthesis translate_on
END IF;
CASE rState IS
WHEN IDLE =>
rCnt <= (OTHERS => '0');
--vGetFrame := '0'&iGetArp&iGetIPv4&iGetRaw;
--rRxInfoI(31 DOWNTO 28) <= vGetFrame;
-- IF vGetFrame /= X"0" AND iRxEn = '1' AND cInfoFifoFull = '0' THEN
-- IF iSOF = '1' AND iRxEn = '1' AND cInfoFifoFull = '0' THEN
IF iSOF = '1' AND cInfoFifoFull = '0' THEN
rState <= DATA;
rBeginAddr <= waddr;
--rNewFrame <= '0';
 
rRxInfoI(15+ADDR_WIDTH DOWNTO 16) <= STD_LOGIC_VECTOR(TO_UNSIGNED(waddr, ADDR_WIDTH));
END IF;
---------------------------------------------------------------------
WHEN DATA =>
IF iRxDV = '1' THEN
rCnt <= rCnt + 1;
CASE rCnt IS
WHEN B"00" => rRxData(31 DOWNTO 24) <= iRxData;
WHEN B"01" => rRxData(23 DOWNTO 16) <= iRxData;
WHEN B"10" => rRxData(15 DOWNTO 8) <= iRxData;
WHEN B"11" =>
rRxData(7 DOWNTO 0) <= iRxData;
rWE <= '1';
WHEN OTHERS => NULL;
END CASE;
END IF;
IF iEOF = '1' THEN
rRxInfoI(31 DOWNTO 28) <= '0'&iGetArp&iGetIPv4&iGetRaw;
rRxInfoI(15 DOWNTO 0) <= STD_LOGIC_VECTOR(iPayloadLen);
rState <= IDLE;
IF iErrCheckSum = '1' OR iErrCRC = '1' OR iErrLen = '1' THEN -- discard wath we just write
waddr <= rBeginAddr;
ELSE -- no err
-- rNewFrame <= '1';
rInfoFifoWr <= '1';
IF rCnt /= B"00" THEN -- last one,length NOT multiple of 4
rWE <= '1';
END IF;
END IF;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
 
---------------------------------------------------------------------------
-- interrupt generate
---------------------------------------------------------------------------
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oIntNewFrame <= '0';
--rNewFrameD <= (OTHERS => '0');
--oRxLenInfo <= (OTHERS => '0');
--rInfoFifoRd <= '0';
rInfoFifoRdD1 <= '0';
raddr <= 0;
ELSIF rising_edge(iWbClk) THEN
IF iRxDataRead = '1' THEN
-- synthesis translate_off
IF raddr < 2**ADDR_WIDTH-1 THEN
-- synthesis translate_on
raddr <= raddr + 1;
-- synthesis translate_off
END IF;
-- synthesis translate_on
END IF;
--rNewFrameD <= rNewFrameD(0)&rNewFrame;
--rInfoFifoRd <= '0';
rInfoFifoRdD1 <= cInfoFifoRd;
IF rInfoFifoRdD1 = '1' THEN
raddr <= to_integer(UNSIGNED(cRxInfoO(15+ADDR_WIDTH DOWNTO 16)));
END IF;
IF cInfoFifoEmpty = '0' THEN
-- oIntNewFrame <= '1';
oIntNewFrame <= iRxEn;
END IF;
IF iIntNewFrameClr = '1' OR cInfoFifoEmpty = '1' THEN
oIntNewFrame <= '0';
END IF;
END IF;
END PROCESS;
END BLOCK blk0;
 
-----------------------------------------------------------------------------
-- data buffer
-----------------------------------------------------------------------------
PROCESS(iEthClk)
BEGIN
IF(rising_edge(iEthClk)) THEN
IF(rWE = '1') THEN
ram(waddr) <= rRxData;
END IF;
END IF;
END PROCESS;
PROCESS(iWbClk)
BEGIN
IF(rising_edge(iWbClk)) THEN
oRxData <= ram(raddr);
END IF;
END PROCESS;
 
-----------------------------------------------------------------------------
-- infomation fifo
-----------------------------------------------------------------------------
oRxLenInfo <= cRxInfoO;
cInfoFifoRd <= (iRxInfoRead OR NOT iRxEn) AND NOT cInfoFifoEmpty;
fifo32x8_1 : ENTITY work.fifo32x8
PORT MAP (
data => rRxInfoI,
rdclk => iWbClk,
rdreq => cInfoFifoRd,
wrclk => iEthClk,
wrreq => rInfoFifoWr,
q => cRxInfoO,
rdempty => cInfoFifoEmpty,
wrfull => cInfoFifoFull);
 
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/rgmii_tx_buf.vhd
0,0 → 1,222
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_tx_buf.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2013-05-06
-- Last update: 2013-05-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-05-06 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_tx_buf IS
 
PORT (
iEthClk : IN STD_LOGIC;
iWbClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
--oEthTxLen : OUT UNSIGNED(15 DOWNTO 0);
oEthTxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
iEthSOF : IN STD_LOGIC;
oEthEOF : OUT STD_LOGIC;
oEthGenFrame : OUT STD_LOGIC;
iEthGenFrameAck : IN STD_LOGIC;
 
iWbTxData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
iWbTxAddr : IN UNSIGNED(10 DOWNTO 0);
iWbTxDataWr : IN STD_LOGIC;
iWbTxInfo : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
iWbTxInfoWr : IN STD_LOGIC;
 
iWbIntEn : IN STD_LOGIC;
iWbIntClr : IN STD_LOGIC;
oWbInt : OUT STD_LOGIC;
oWbTxInfo : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
 
END ENTITY rgmii_tx_buf;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_tx_buf IS
 
CONSTANT DATA_WIDTH : NATURAL := 32;
CONSTANT ADDR_WIDTH : NATURAL := 11;
-- Build a 2-D array type for the RAM
SUBTYPE word_t IS STD_LOGIC_VECTOR((DATA_WIDTH-1) DOWNTO 0);
TYPE memory_t IS ARRAY(2**ADDR_WIDTH-1 DOWNTO 0) OF word_t;
-- Declare the RAM signal.
SIGNAL ram : memory_t;
SIGNAL raddr : UNSIGNED(ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
--SIGNAL waddr : UNSIGNED(ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rWE : STD_LOGIC := '0';
SIGNAL rTxData : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
SIGNAL cInfoFifoEmpty : STD_LOGIC;
SIGNAL cInfoFifoFull : STD_LOGIC;
SIGNAL cInfo : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
 
blk2 : BLOCK IS
SIGNAL rWbTxInfo : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN -- BLOCK blk2
oWbTxInfo(1 DOWNTO 0) <= B"00";
oWbTxInfo(31) <= cInfoFifoFull;
oWbTxInfo(30 DOWNTO ADDR_WIDTH+16) <= (OTHERS => '0');
-- tell the tx wbm module the next frame begin address in the buffer
-- this infomation will be send back to this module!
-- oWbTxInfo(ADDR_WIDTH+15 DOWNTO 16) <= STD_LOGIC_VECTOR(waddr);
oWbTxInfo(ADDR_WIDTH+15 DOWNTO 16) <= STD_LOGIC_VECTOR(iWbTxAddr);
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rWbTxInfo(15 DOWNTO 2) <= (OTHERS => '0');
oWbTxInfo(15 DOWNTO 2) <= (OTHERS => '0');
ELSIF rising_edge(iWbClk) THEN
rWbTxInfo(15 DOWNTO 2) <= STD_LOGIC_VECTOR(
TO_UNSIGNED(
--2**ADDR_WIDTH - TO_INTEGER(waddr) + TO_INTEGER(raddr), 14));
2**ADDR_WIDTH - TO_INTEGER(iWbTxAddr) + TO_INTEGER(raddr), 14));
oWbTxInfo(15 DOWNTO 2) <= rWbTxInfo(15 DOWNTO 2);
END IF;
END PROCESS;
END BLOCK blk2;
 
--PROCESS (iWbClk, iRst_n) IS
--BEGIN
-- IF iRst_n = '0' THEN
-- waddr <= (OTHERS => '0');
-- ELSIF rising_edge(iWbClk) THEN
-- IF iWbTxDataWr = '1' THEN
-- waddr <= waddr + 1;
-- END IF;
-- END IF;
--END PROCESS;
 
blk1 : BLOCK IS
--SIGNAL rWordCnt : UNSIGNED(15 DOWNTO 2);
SIGNAL rByteCnt : UNSIGNED(15 DOWNTO 0);
SIGNAL rLen : UNSIGNED(15 DOWNTO 0);
--SIGNAL rRipple : UNSIGNED(1 DOWNTO 0);
SIGNAL rFinished : STD_LOGIC;
TYPE state_t IS (IDLE, WAIT1, DATA);
SIGNAL rState : state_t;
BEGIN -- BLOCK blk1
PROCESS (iEthClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
raddr <= (OTHERS => '0');
--rWordCnt <= (OTHERS => '0');
--rRipple <= (OTHERS => '0');
rState <= IDLE;
oEthGenFrame <= '0';
oEthTxData <= (OTHERS => '0');
oWbInt <= '0';
oEthEOF <= '0';
rByteCnt <= (OTHERS => '0');
rFinished <= '0';
ELSIF rising_edge(iEthClk) THEN
oEthEOF <= '0';
IF iWbIntClr = '1' THEN
oWbInt <= '0';
END IF;
CASE rState IS
WHEN IDLE =>
rFinished <= '0';
rByteCnt <= (OTHERS => '0');
IF cInfoFifoEmpty = '0' THEN
oEthGenFrame <= '1';
END IF;
IF iEthGenFrameAck = '1' THEN
oEthGenFrame <= '0';
rState <= WAIT1;
END IF;
---------------------------------------------------------------------
WHEN WAIT1 =>
--IF cInfo(1 DOWNTO 0) /= B"00" THEN
-- rWordCnt <= UNSIGNED(cInfo(15 DOWNTO 2));
--ELSE
-- rWordCnt <= UNSIGNED(cInfo(15 DOWNTO 2)) - 1;
--END IF;
rLen <= UNSIGNED(cInfo(15 DOWNTO 0)) - 1;
raddr <= UNSIGNED(cInfo(ADDR_WIDTH+15 DOWNTO 16));
-- there's same clock cycles before iEthSOF asserted....
IF iEthSOF = '1' THEN
rState <= DATA;
END IF;
---------------------------------------------------------------------
WHEN DATA =>
--rRipple <= rRipple + 1;
rByteCnt <= rByteCnt + 1;
--CASE rRipple IS
IF rByteCnt = rLen THEN
oEthEOF <= '1';
rFinished <= '1';
END IF;
CASE rByteCnt(1 DOWNTO 0) IS
WHEN B"00" => oEthTxData <= rTxData(31 DOWNTO 24);
WHEN B"01" => oEthTxData <= rTxData(23 DOWNTO 16);
WHEN B"10" =>
oEthTxData <= rTxData(15 DOWNTO 8);
raddr <= raddr + 1;
WHEN B"11" =>
oEthTxData <= rTxData(7 DOWNTO 0);
--rWordCnt <= rWordCnt - 1;
--IF rWordCnt = X"000"&B"00" THEN
IF rFinished = '1' OR rByteCnt = rLen THEN
rState <= IDLE;
oWbInt <= iWbIntEn;
END IF;
WHEN OTHERS => NULL;
END CASE;
---------------------------------------------------------------------
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK blk1;
 
-----------------------------------------------------------------------------
-- data buffer
-----------------------------------------------------------------------------
PROCESS(iWbClk)
BEGIN
IF(rising_edge(iWbClk)) THEN
IF(iWbTxDataWr = '1') THEN
--ram(TO_INTEGER(waddr)) <= iWbTxData;
ram(TO_INTEGER(iWbTxAddr)) <= iWbTxData;
END IF;
END IF;
END PROCESS;
PROCESS(iEthClk)
BEGIN
IF(rising_edge(iEthClk)) THEN
rTxData <= ram(TO_INTEGER(raddr));
END IF;
END PROCESS;
 
--oEthTxLen <= UNSIGNED(cInfo(15 DOWNTO 0));
fifo32x8_1 : ENTITY work.fifo32x8
PORT MAP (
data => iWbTxInfo,
rdclk => iEthClk,
rdreq => iEthGenFrameAck,
wrclk => iWbClk,
wrreq => iWbTxInfoWr,
q => cInfo,
rdempty => cInfoFifoEmpty,
wrfull => cInfoFifoFull);
 
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/rgmii1000_pll.vhd
0,0 → 1,350
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
 
-- ============================================================
-- File Name: rgmii1000_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY rgmii1000_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END rgmii1000_pll;
 
 
ARCHITECTURE SYN OF rgmii1000_pll IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
 
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
 
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "6000",
compensate_clock => "CLK0",
inclk0_input_frequency => 8000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=rgmii1000_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "270.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "rgmii1000_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "6000"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
/trunk/rtl/rgmii/rgmii100_io.vhd
0,0 → 1,168
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_io.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-10-26
-- Last update: 2013-05-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-10-26 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii100_io IS
 
PORT (
iRst_n : IN STD_LOGIC;
---------------------------------------------------------------------------
-- RGMII Interface
---------------------------------------------------------------------------
TXC : OUT STD_LOGIC;
TX_CTL : OUT STD_LOGIC;
TD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
RXC : IN STD_LOGIC;
RX_CTL : IN STD_LOGIC;
RD : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
 
---------------------------------------------------------------------------
-- data to PHY
---------------------------------------------------------------------------
iTxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iTxEn : IN STD_LOGIC;
iTxErr : IN STD_LOGIC;
 
---------------------------------------------------------------------------
-- data from PHY
---------------------------------------------------------------------------
oRxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxDV : OUT STD_LOGIC;
oRxErr : OUT STD_LOGIC;
 
---------------------------------------------------------------------------
-- clock for MAC controller
---------------------------------------------------------------------------
oEthClk : OUT STD_LOGIC
);
 
END ENTITY rgmii100_io;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii100_io IS
 
SIGNAL ethIOClk : STD_LOGIC;
 
SIGNAL outDataH, outDataL, outData : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL inDataH, inDataL, inData : STD_LOGIC_VECTOR(4 DOWNTO 0);
 
SIGNAL pllLock : STD_LOGIC;
SIGNAL rstSync : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL rst_n : STD_LOGIC;
 
SIGNAL bufClk : STD_LOGIC;
 
SIGNAL ripple : BOOLEAN;
TYPE rxState_t IS (IDLE, RECEIVE);
SIGNAL rxState : rxState_t;
SIGNAL rxData : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rxErr, rxDV : STD_LOGIC;
SIGNAL tmp : STD_LOGIC;
 
SIGNAL rxData2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rxErr2, rxDV2 : STD_LOGIC;
 
SIGNAL rdreq,wrreq : STD_LOGIC;
SIGNAL rdempty : STD_LOGIC;
SIGNAL din,dout : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
 
oEthClk <= ethIOClk;
--oEthClk <= RXC;
TXC <= RXC;
 
rgmii_pll : ENTITY work.rgmii100_pll
PORT MAP (
inclk0 => RXC,
c0 => ethIOClk);
 
TD <= outData(3 DOWNTO 0);
TX_CTL <= outData(4);
outDataH <= iTxEn & iTxData(3 DOWNTO 0);
outDataL <= (iTxEn XOR iTxErr) & iTxData(7 DOWNTO 4);
eth_ddr_out_1 : ENTITY work.eth_ddr_out
PORT MAP (
datain_h => outDataH,
datain_l => outDataL,
outclock => ethIOClk,
dataout => outData);
 
oRxDV <= dout(9);
oRxErr <= dout(8);
oRxData <= dout(7 DOWNTO 0);
 
rdreq <= NOT rdempty;
din <= rxDV&rxErr&rxData;
rgmii100_io_fifo_1: ENTITY work.rgmii100_io_fifo
PORT MAP (
data => din,
rdclk => ethIOClk,
rdreq => rdreq,
wrclk => RXC,
wrreq => wrreq,
q => dout,
rdempty => rdempty,
wrfull => OPEN);
PROCESS (RXC, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
ripple <= FALSE;
rxState <= IDLE;
rxData <= (OTHERS => '0');
rxErr <= '0';
rxDV <= '0';
tmp <= '0';
wrreq <= '0';
ELSIF rising_edge(RXC) THEN
tmp <= RX_CTL;
wrreq <= '0';
CASE rxState IS
WHEN IDLE =>
rxData(3 DOWNTO 0) <= RD;
IF tmp = '0' AND RX_CTL = '1' AND RD = X"F" THEN
rxState <= RECEIVE;
ripple <= FALSE;
rxErr <= '1';
wrreq <= '1';
END IF;
WHEN RECEIVE =>
ripple <= NOT ripple;
IF ripple THEN
rxErr <= tmp XOR RX_CTL;
rxData(7 DOWNTO 4) <= RD;
wrreq <= '1';
ELSE
rxDV <= RX_CTL;
rxData(3 DOWNTO 0) <= RD;
IF RX_CTL = '0' THEN
rxState <= IDLE;
wrreq <= '1';
END IF;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/rgmii_mdio.vhd
0,0 → 1,240
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_mdio.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-12-02
-- Last update: 2012-12-02
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-12-02 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_mdio IS
 
PORT (
iWbClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
---------------------------------------------------------------------------
-- signals from register file
---------------------------------------------------------------------------
iPHYAddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
iRegAddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
iNoPre : IN STD_LOGIC;
iData2PHY : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
iClkDiv : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iRdOp : IN STD_LOGIC;
iWrOp : IN STD_LOGIC;
 
---------------------------------------------------------------------------
-- signals to register file
---------------------------------------------------------------------------
oDataFromPHY : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- data from PHY registers
oDataFromPHYValid : OUT STD_LOGIC; -- only valid for 1 clock cycle
oClrRdOp : OUT STD_LOGIC; -- only valid for 1 clock cycle
oClrWrOp : OUT STD_LOGIC; -- only valid for 1 clock cycle
oMDIOBusy : OUT STD_LOGIC; -- manegement is busy
 
---------------------------------------------------------------------------
-- Management interface
---------------------------------------------------------------------------
iMDI : IN STD_LOGIC;
oMDHz : OUT STD_LOGIC; -- mdio is in HighZ state
oMDC : OUT STD_LOGIC
);
 
END ENTITY rgmii_mdio;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_mdio IS
 
SIGNAL rdPend, wrPend : STD_LOGIC;
 
SIGNAL endOp : STD_LOGIC;
SIGNAL busy : STD_LOGIC;
 
SIGNAL sendEn : BOOLEAN; -- Data is output on sendEn. Delay it slightly from the
--clock to ensure setup and hold timing is met
SIGNAL receiveEn : BOOLEAN; -- Sample read data just before rising edge of MDC
 
BEGIN -- ARCHITECTURE rtl
 
-----------------------------------------------------------------------------
-- receive command from wishbone
-----------------------------------------------------------------------------
oMDIOBusy <= busy;
busy <= wrPend OR rdPend;
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rdPend <= '0';
wrPend <= '0';
oClrWrOp <= '0';
oClrRdOp <= '0';
ELSIF rising_edge(iWbClk) THEN
oClrWrOp <= '0';
oClrRdOp <= '0';
IF busy = '0' THEN
IF iRdOp = '1' THEN
rdPend <= '1';
oClrRdOp <= '1';
ELSIF iWrOp = '1' THEN
wrPend <= '1';
oClrWrOp <= '1';
END IF;
ELSIF endOp = '1' THEN
rdPend <= '0';
wrPend <= '0';
END IF;
END IF;
END PROCESS;
 
-----------------------------------------------------------------------------
-- MDC generation
-----------------------------------------------------------------------------
mdcGen : BLOCK IS
SIGNAL mdc : STD_LOGIC;
SIGNAL mdcClkDiv : INTEGER RANGE 0 TO 127;
SIGNAL clkDivTmp : INTEGER RANGE 0 TO 126;
BEGIN -- BLOCK mdc
oMDC <= mdc;
clkDivTmp <= 1 WHEN iClkDiv < 4 ELSE (conv_integer(iClkDiv(7 DOWNTO 1))-1);
sendEn <= mdc = '1' AND mdcClkDiv = 0; -- falling edge send
receiveEn <= mdc = '0' AND mdcClkDiv = 0; -- rising edge receive
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
mdc <= '0';
mdcClkDiv <= 0;
ELSIF rising_edge(iWbClk) THEN
IF mdcClkDiv = 0 THEN
mdcClkDiv <= clkDivTmp;
mdc <= NOT mdc;
ELSE
mdcClkDiv <= mdcClkDiv - 1;
END IF;
END IF;
END PROCESS;
END BLOCK mdcGen;
 
operation : BLOCK IS
TYPE state_t IS (PREAMBLE, IDLE, CTRL, WRITE, READ);
SIGNAL state : state_t;
SIGNAL bitCnt : INTEGER RANGE 0 TO 31;
SIGNAL shiftReg : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN -- BLOCK operation
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oMDHz <= '1';
state <= PREAMBLE;
endOp <= '0';
bitCnt <= 0;
shiftReg <= (OTHERS => '0');
oDataFromPHYValid <= '0';
oDataFromPHY <= (OTHERS => '0');
ELSIF rising_edge(iWbClk) THEN
endOp <= '0';
oDataFromPHYValid <= '0';
CASE state IS
WHEN PREAMBLE =>
IF sendEn THEN
bitCnt <= bitCnt + 1;
oMDHz <= '1';
IF bitCnt = 30 THEN
state <= IDLE;
END IF;
END IF;
WHEN IDLE =>
IF sendEn THEN
IF busy = '1' THEN -- start transaction
oMDHz <= '0'; -- firstbit of start word
state <= CTRL;
bitCnt <= 0;
shiftReg <= iData2PHY;
END IF;
END IF;
WHEN CTRL =>
IF sendEn THEN
bitCnt <= bitCnt + 1;
CASE bitCnt IS
WHEN 0 => oMDHz <= '1'; -- second bit of start word
-- OPCODE. 1 then 0 for read, 0 then 1 for write
WHEN 1 => oMDHz <= rdPend;
WHEN 2 => oMDHz <= NOT rdPend;
-- PHY address
WHEN 3 => oMDHz <= iPHYAddr(4);
WHEN 4 => oMDHz <= iPHYAddr(3);
WHEN 5 => oMDHz <= iPHYAddr(2);
WHEN 6 => oMDHz <= iPHYAddr(1);
WHEN 7 => oMDHz <= iPHYAddr(0);
-- Register address
WHEN 8 => oMDHz <= iRegAddr(4);
WHEN 9 => oMDHz <= iRegAddr(3);
WHEN 10 => oMDHz <= iRegAddr(2);
WHEN 11 => oMDHz <= iRegAddr(1);
WHEN 12 => oMDHz <= iRegAddr(0);
-- TA
WHEN 13 => oMDHz <= '1';
WHEN 14 =>
IF rdPend = '0' THEN
state <= WRITE;
oMDHz <= '0';
bitCnt <= 0;
END IF;
WHEN 15 =>
state <= READ;
bitCnt <= 0;
WHEN OTHERS => NULL;
END CASE;
END IF;
WHEN WRITE =>
IF sendEn THEN
oMDHz <= shiftReg(15);
shiftReg <= shiftReg(14 DOWNTO 0) & '0';
bitCnt <= bitCnt + 1;
IF bitCnt = 15 THEN
endOp <= '1';
bitCnt <= 0;
IF iNoPre = '1' THEN
state <= IDLE;
ELSE
state <= PREAMBLE;
END IF;
END IF;
END IF;
WHEN READ =>
IF receiveEn THEN
bitCnt <= bitCnt + 1;
shiftReg <= shiftReg(14 DOWNTO 0) & iMDI;
IF bitCnt = 15 THEN
bitCnt <= 0;
endOp <= '1';
oDataFromPHY <= shiftReg(14 DOWNTO 0) & iMDI;
oDataFromPHYValid <= '1';
IF iNoPre = '1' THEN
state <= IDLE;
ELSE
state <= PREAMBLE;
END IF;
END IF;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK operation;
 
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/fifo_sc_34x64.vhd
0,0 → 1,185
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
 
-- ============================================================
-- File Name: fifo_sc_34x64.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY fifo_sc_34x64 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (33 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (33 DOWNTO 0)
);
END fifo_sc_34x64;
 
 
ARCHITECTURE SYN OF fifo_sc_34x64 IS
 
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (33 DOWNTO 0);
 
 
 
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (33 DOWNTO 0);
rdreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (33 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
 
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(33 DOWNTO 0);
 
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "ON",
intended_device_family => "Cyclone IV E",
lpm_numwords => 64,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 34,
lpm_widthu => 6,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "64"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "34"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "34"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "34"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 34 0 INPUT NODEFVAL "data[33..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 34 0 OUTPUT NODEFVAL "q[33..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 34 0 data 0 0 34 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 34 0 @q 0 0 34 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_34x64.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_34x64.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_34x64.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_34x64.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_sc_34x64_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/rtl/rgmii/rgmii_rx.vhd
0,0 → 1,590
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_rx.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-11-14
-- Last update: 2013-05-21
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-14 1.0 root Created
-- 2013-05-13 1.0 liyi change dataen signal ,now the dest&sourcr mac
-- addr and type_len info are counted as valid data
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.eth_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_rx IS
 
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
iRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iRxDV : IN STD_LOGIC;
iRxEr : IN STD_LOGIC;
 
-- these signals come from wishbone clock domian, NOT synchronized
iCheckSumIPCheck : IN STD_LOGIC;
iCheckSumTCPCheck : IN STD_LOGIC;
iCheckSumUDPCheck : IN STD_LOGIC;
iCheckSumICMPCheck : IN STD_LOGIC;
 
oEOF : OUT STD_LOGIC;
oSOF : OUT STD_LOGIC;
oCRCErr : OUT STD_LOGIC;
oRxErr : OUT STD_LOGIC;
oLenErr : OUT STD_LOGIC;
oCheckSumErr : OUT STD_LOGIC;
 
iMyMAC : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
 
oGetARP : OUT STD_LOGIC;
oGetIPv4 : BUFFER STD_LOGIC;
oGetCtrl : OUT STD_LOGIC;
oGetRaw : BUFFER STD_LOGIC;
 
oTaged : OUT STD_LOGIC;
oTagInfo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
oStackTaged : BUFFER STD_LOGIC;
oTagInfo2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
 
oLink : OUT STD_LOGIC;
oSpeed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
oDuplex : OUT STD_LOGIC;
 
oPayloadLen : BUFFER UNSIGNED(15 DOWNTO 0);
oRxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxDV : OUT STD_LOGIC
);
 
END ENTITY rgmii_rx;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_rx IS
 
SIGNAL sof, eof : STD_LOGIC;
SIGNAL crcEn, crcEn2 : STD_LOGIC;
SIGNAL crcErr : STD_LOGIC;
 
SIGNAL dvDly : STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE dataAyy_t IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dataDly : dataAyy_t;
 
TYPE state_t IS (IDLE, SFD, DEST_MAC, SOURCE_MAC, FRAME_TYPE, TAG_INFO1, TAG_INFO2, PAYLOAD);
SIGNAL state : state_t;
SIGNAL byteCnt : UNSIGNED(15 DOWNTO 0);
SIGNAL destMACAddr : STD_LOGIC_VECTOR(47 DOWNTO 8);
 
SIGNAL frm4Me : STD_LOGIC;
 
SIGNAL rxDV, dataEn : STD_LOGIC;
 
SIGNAL rCheckSumOk : BOOLEAN;
 
BEGIN -- ARCHITECTURE rtl
 
-- check sum calc
blkCS : BLOCK IS
TYPE state_t IS (IDLE, IP4_HEAD, TCP, UDP, ICMP, UNKNOWN, DONE);
SIGNAL rState : state_t;
SIGNAL cRxDataD1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rCheckSum : UNSIGNED(31 DOWNTO 0);
SIGNAL cCheckSum : UNSIGNED(15 DOWNTO 0);
SIGNAL rIPCSOK : BOOLEAN; -- ip checksum ok
SIGNAL rByteCnt : UNSIGNED(15 DOWNTO 0);
SIGNAL cByteValid : STD_LOGIC;
SIGNAL rPesudoCS : UNSIGNED(18 DOWNTO 0);
SIGNAL rIPHeadLen : UNSIGNED(5 DOWNTO 0); -- 20~60 bytes
SIGNAL rTotalLen : UNSIGNED(15 DOWNTO 0);
SIGNAL cIPPayloadLen : UNSIGNED(15 DOWNTO 0);
SIGNAL rProtocol : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cIPCSCheckEn : BOOLEAN;
SIGNAL cTCPCSCheckEn : BOOLEAN;
SIGNAL cICMPCSCheckEn : BOOLEAN;
SIGNAL cUDPCSCheckEn : BOOLEAN;
SIGNAL rGetCheckSum : BOOLEAN;
SIGNAL rCsCheckSync : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN -- BLOCK blkCS
cRxDataD1 <= dataDly(0);
cByteValid <= dvDly(0);
cCheckSum <= rCheckSum(31 DOWNTO 16) + rCheckSum(15 DOWNTO 0);
--cCheckSumOk <= cCheckSum = X"FFFF";
cIPPayloadLen <= rTotalLen - rIPHeadLen;
cIPCSCheckEn <= rCsCheckSync(1) = '1';
cTCPCSCheckEn <= rCsCheckSync(3) = '1';
cUDPCSCheckEn <= rCsCheckSync(5) = '1';
cICMPCSCheckEn <= rCsCheckSync(7) = '1';
 
PROCESS (iClk) IS
BEGIN
IF rising_edge(iClk) THEN
rCsCheckSync(1 DOWNTO 0) <= rCsCheckSync(0)&iCheckSumIPCheck;
rCsCheckSync(3 DOWNTO 2) <= rCsCheckSync(2)&iCheckSumTCPCheck;
rCsCheckSync(5 DOWNTO 4) <= rCsCheckSync(4)&iCheckSumUDPCheck;
rCsCheckSync(7 DOWNTO 6) <= rCsCheckSync(6)&iCheckSumICMPCheck;
END IF;
END PROCESS;
 
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rState <= IDLE;
rCheckSum <= (OTHERS => '0');
rByteCnt <= (OTHERS => '0');
rPesudoCS <= (OTHERS => '0');
rIPHeadLen <= (OTHERS => '0');
rTotalLen <= (OTHERS => '0');
rProtocol <= (OTHERS => '0');
rCheckSumOk <= FALSE;
rGetCheckSum <= FALSE;
rIPCSOK <= FALSE;
ELSIF rising_edge(iClk) THEN
rGetCheckSum <= FALSE;
IF eof = '1' THEN
rState <= IDLE;
END IF;
CASE rState IS
WHEN IDLE =>
rPesudoCS <= (OTHERS => '0');
rCheckSum <= (OTHERS => '0');
rByteCnt <= X"0001";
rCheckSumOk <= TRUE;
rIPCSOK <= FALSE;
IF oGetIPv4 = '1' THEN
rState <= IP4_HEAD;
rCheckSumOk <= FALSE;
END IF;
---------------------------------------------------------------------
WHEN IP4_HEAD =>
IF cByteValid = '1' THEN
rByteCnt <= rByteCnt + 1;
IF rByteCnt(0) = '1' THEN -- higher byte
rCheckSum <= rCheckSum + to_integer(UNSIGNED(cRxDataD1)&X"00");
ELSE -- lower byte
rCheckSum <= rCheckSum + UNSIGNED(cRxDataD1);
END IF;
CASE rByteCnt(5 DOWNTO 0) IS
WHEN B"000001" =>
rIPHeadLen <= UNSIGNED(cRxDataD1(3 DOWNTO 0))&B"00";
WHEN B"000011" => rTotalLen(15 DOWNTO 8) <= UNSIGNED(cRxDataD1);
WHEN B"000100" => rTotalLen(7 DOWNTO 0) <= UNSIGNED(cRxDataD1);
WHEN B"001010" => -- Protocol
rPesudoCS <= rPesudoCS + UNSIGNED(cRxDataD1);
rProtocol <= cRxDataD1;
WHEN B"001011" =>
rPesudoCS <= rPesudoCS + cIPPayloadLen;
-- source &Destination ip addr
WHEN B"001101" | B"001111" | B"010001" | B"010011" =>
rPesudoCS <= rPesudoCS + to_integer(UNSIGNED(cRxDataD1)&X"00");
WHEN B"001110" | B"010000" | B"010010" | B"010100"=>
rPesudoCS <= rPesudoCS + UNSIGNED(cRxDataD1);
WHEN OTHERS => NULL;
END CASE;
IF rIPHeadLen = rByteCnt(5 DOWNTO 0) THEN
rGetCheckSum <= TRUE;
rState <= UNKNOWN;
CASE rProtocol IS
WHEN X"01" => -- ICMP
rState <= ICMP;
WHEN X"06" => -- TCP
rState <= TCP;
WHEN X"11" => -- UDP
rState <= UDP;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
---------------------------------------------------------------------
-- tcp & udp are the same,both contain a pesudo header
WHEN TCP | UDP =>
IF rGetCheckSum THEN
rIPCSOK <= NOT cIPCSCheckEn OR (cIPCSCheckEn AND cCheckSum = X"FFFF");
rCheckSum <= X"000"&B"0"&rPesudoCS;
END IF;
IF cByteValid = '1' THEN
rByteCnt <= rByteCnt + 1;
IF rByteCnt(0) = '1' THEN -- higher byte
IF rGetCheckSum THEN
rCheckSum <= X"000"&'0'&rPesudoCS + to_integer(UNSIGNED(cRxDataD1)&X"00");
ELSE
rCheckSum <= rCheckSum + to_integer(UNSIGNED(cRxDataD1)&X"00");
END IF;
ELSE -- lower byte
rCheckSum <= rCheckSum + UNSIGNED(cRxDataD1);
END IF;
IF rByteCnt = rTotalLen THEN
rState <= DONE;
rGetCheckSum <= TRUE;
END IF;
END IF;
---------------------------------------------------------------------
WHEN ICMP =>
IF rGetCheckSum THEN
rIPCSOK <= NOT cIPCSCheckEn OR (cIPCSCheckEn AND cCheckSum = X"FFFF");
rCheckSum <= (OTHERS => '0');
END IF;
IF cByteValid = '1' THEN
rByteCnt <= rByteCnt + 1;
IF rByteCnt(0) = '1' THEN -- higher byte
IF rGetCheckSum THEN
rCheckSum <= X"0000"&UNSIGNED(cRxDataD1)&X"00";
ELSE
rCheckSum <= rCheckSum + to_integer(UNSIGNED(cRxDataD1)&X"00");
END IF;
ELSE -- lower byte
rCheckSum <= rCheckSum + UNSIGNED(cRxDataD1);
END IF;
IF rByteCnt = rTotalLen THEN
rState <= DONE;
rGetCheckSum <= TRUE;
END IF;
END IF;
---------------------------------------------------------------------
WHEN UNKNOWN =>
IF rGetCheckSum THEN
rCheckSumOk <= NOT cIPCSCheckEn OR (cIPCSCheckEn AND cCheckSum = X"FFFF");
END IF;
---------------------------------------------------------------------
WHEN DONE =>
IF rGetCheckSum THEN
CASE rProtocol IS
WHEN X"01" =>
rCheckSumOk <= rIPCSOK AND
(NOT cICMPCSCheckEn OR
(cICMPCSCheckEn AND cCheckSum = X"FFFF"));
WHEN X"06" =>
rCheckSumOk <= rIPCSOK AND
(NOT cTCPCSCheckEn OR
(cTCPCSCheckEn AND cCheckSum = X"FFFF"));
WHEN X"11" =>
rCheckSumOk <= rIPCSOK AND
(NOT cUDPCSCheckEn OR
(cUDPCSCheckEn AND cCheckSum = X"FFFF"));
WHEN OTHERS => NULL;
END CASE;
END IF;
---------------------------------------------------------------------
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK blkCS;
 
-- USE normal inter-frame TO get link information
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oLink <= '0';
oSpeed <= B"00";
oDuplex <= '0';
ELSIF rising_edge(iClk) THEN
IF iRxEr = '0' AND iRxDV = '0' THEN
oLink <= iRxData(0); -- 0=down,1=up
oSpeed <= iRxData(2 DOWNTO 1); -- 00=10Mbps,01=100Mbps,10=1000Mbps,11=reserved
oDuplex <= iRxData(3); -- 0=half-duplex,1=full-duplex
END IF;
END IF;
END PROCESS;
 
oEOF <= eof;
oCRCErr <= crcErr;
 
-- delay! IN order TO get OUT OF the CRC part
rxDV <= iRxDV AND dataEn AND NOT iRxEr;
oRxData <= dataDly(3);
--oRxDV <= dvDly(3) AND rxDV;
oRxDV <= dvDly(3) AND dataEn; -- changed @ 2013-05-20
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
dvDly <= (OTHERS => '0');
dataDly(0) <= (OTHERS => '0');
dataDly(1) <= (OTHERS => '0');
dataDly(2) <= (OTHERS => '0');
dataDly(3) <= (OTHERS => '0');
ELSIF rising_edge(iClk) THEN
dvDly <= dvDly(2 DOWNTO 0) & rxDV;
dataDly(3) <= dataDly(2);
dataDly(2) <= dataDly(1);
dataDly(1) <= dataDly(0);
dataDly(0) <= iRxData;
END IF;
END PROCESS;
 
crcEn2 <= crcEn AND iRxDV AND NOT iRxEr;
crcCheck : ENTITY work.eth_crc32
PORT MAP (
iClk => iClk,
iRst_n => iRst_n,
iInit => sof,
iCalcEn => crcEn2,
iData => iRxData,
oCRC => OPEN,
oCRCErr => crcErr);
 
PROCESS (iClk, iRst_n) IS
VARIABLE ethType : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
IF iRst_n = '0' THEN
state <= IDLE;
eof <= '0';
byteCnt <= (OTHERS => '0');
oPayloadLen <= (OTHERS => '0');
oGetCtrl <= '0';
oGetARP <= '0';
oGetIPv4 <= '0';
oGetRaw <= '0';
--oDrop <= '0';
frm4Me <= '0';
crcEn <= '0';
sof <= '0';
dataEn <= '0';
destMACAddr <= (OTHERS => '0');
oTagInfo2 <= (OTHERS => '0');
oTaged <= '0';
oStackTaged <= '0';
oTagInfo <= (OTHERS => '0');
oLenErr <= '0';
oCheckSumErr <= '0';
oSOF <= '0';
ELSIF rising_edge(iClk) THEN
--oGetCtrl <= '0';
--oGetARP <= '0';
--oGetIPv4 <= '0';
--oGetRaw <= '0';
eof <= '0';
--oDrop <= '0';
sof <= '0';
oSOF <= '0';
IF iRxDV = '1' AND iRxEr = '1' THEN
oRxErr <= '1';
END IF;
 
CASE state IS
WHEN IDLE =>
crcEn <= '0';
dataEn <= '0';
frm4Me <= '0';
oGetCtrl <= '0';
oGetARP <= '0';
oGetIPv4 <= '0';
oGetRaw <= '0';
oRxErr <= '0';
oTaged <= '0';
oStackTaged <= '0';
oLenErr <= '0';
oCheckSumErr <= '0';
IF iRxData = X"55" THEN
state <= SFD;
byteCnt <= (OTHERS => '0');
sof <= '1';
END IF;
-----------------------------------------------------------------------
WHEN SFD =>
IF iRxData = X"55" THEN
byteCnt <= byteCnt + 1;
ELSIF iRxData = X"D5" THEN
IF byteCnt(2 DOWNTO 0) = B"110" THEN
state <= DEST_MAC;
crcEn <= '1';
dataEn <= '1'; -- 2013-05-13
oSOF <= '1';
byteCnt <= (OTHERS => '0');
ELSE
state <= IDLE;
END IF;
ELSE
state <= IDLE;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr <= '1';
END IF;
-----------------------------------------------------------------------
WHEN DEST_MAC =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
CASE byteCnt(2 DOWNTO 0) IS
WHEN B"000" => destMACAddr(47 DOWNTO 40) <= iRxData;
WHEN B"001" => destMACAddr(39 DOWNTO 32) <= iRxData;
WHEN B"010" => destMACAddr(31 DOWNTO 24) <= iRxData;
WHEN B"011" => destMACAddr(23 DOWNTO 16) <= iRxData;
WHEN B"100" => destMACAddr(15 DOWNTO 8) <= iRxData;
WHEN B"101" =>
byteCnt(2 DOWNTO 0) <= (OTHERS => '0');
state <= SOURCE_MAC;
IF destMACAddr(47 DOWNTO 8)&iRxData = iMyMAC -- unicast
OR destMACAddr(47 DOWNTO 8)&iRxData = MAC_ADDR_CTRL -- multicast for flow control
OR destMACAddr(47 DOWNTO 8)&iRxData = X"FFFFFFFFFFFF" THEN -- broadcast
--oDrop <= '1';
frm4Me <= '1';
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr <= '1';
END IF;
-----------------------------------------------------------------------
WHEN SOURCE_MAC =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
IF byteCnt(2 DOWNTO 0) = B"101" THEN
state <= FRAME_TYPE;
byteCnt(2 DOWNTO 0) <= (OTHERS => '0');
END IF;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr <= '1';
END IF;
-----------------------------------------------------------------------
WHEN FRAME_TYPE =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
IF byteCnt(0) = '0' THEN
destMACAddr(15 DOWNTO 8) <= iRxData;
ELSE
byteCnt(1 DOWNTO 0) <= (OTHERS => '0');
ethType := destMACAddr(15 DOWNTO 8) & iRxData;
IF ethType < X"0600" AND ethType > X"0000" THEN
oGetRaw <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
END IF;
oPayloadLen <= UNSIGNED(ethType);
-- check the ethnert frame TYPE ,only ARP AND IP PACKAGE are wanted
CASE ethType IS
WHEN ETH_TYPE_IPv4 =>
oGetIPv4 <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
WHEN ETH_TYPE_ARP =>
oGetARP <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
WHEN ETH_TYPE_CTRL =>
oGetCtrl <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
WHEN x"8100" =>
oTaged <= '1';
state <= TAG_INFO1;
dataEn <= '0';
WHEN x"88A8" | x"9100" =>
oStackTaged <= '1';
state <= TAG_INFO1;
dataEn <= '0';
WHEN OTHERS => --oDrop <= '1';
state <= PAYLOAD;
dataEn <= '0';
frm4Me <= '0'; -- add @ 2013-05-13
END CASE;
END IF;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr <= '1';
END IF;
-----------------------------------------------------------------------
WHEN TAG_INFO1 =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
IF byteCnt(0) = '0' THEN
oTagInfo(15 DOWNTO 8) <= iRxData;
ELSE
byteCnt(1 DOWNTO 0) <= (OTHERS => '0');
oTagInfo(7 DOWNTO 0) <= iRxData;
IF oStackTaged = '1' THEN
state <= TAG_INFO2;
ELSE
state <= FRAME_TYPE;
END IF;
END IF;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr <= '1';
END IF;
-----------------------------------------------------------------------
WHEN TAG_INFO2 =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
CASE byteCnt(1 DOWNTO 0) IS
-- we do NOT check,but 0x8100 is expected!
WHEN B"00" => NULL;
WHEN B"01" => NULL;
WHEN B"10" =>
oTagInfo2(15 DOWNTO 8) <= iRxData;
WHEN B"11" =>
oTagInfo2(7 DOWNTO 0) <= iRxData;
byteCnt(2 DOWNTO 0) <= (OTHERS => '0');
state <= FRAME_TYPE;
WHEN OTHERS => NULL;
END CASE;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr <= '1';
END IF;
-----------------------------------------------------------------------
WHEN PAYLOAD =>
IF oGetRaw = '1' THEN
IF byteCnt + 1 = oPayloadLen THEN -- PAD truncation
dataEn <= '0';
END IF;
END IF;
IF iRxDV = '1' THEN
IF iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
END IF;
ELSE
state <= IDLE;
eof <= '1';
IF rCheckSumOk THEN
oCheckSumErr <= '0';
ELSE
oCheckSumErr <= '1';
END IF;
IF frm4Me = '0' THEN -- add @ 2013-05-13
oLenErr <= '1';
END IF;
IF oGetRaw = '0' THEN
-- oPayloadLen <= byteCnt - 4; change @ 2013-05-13
oPayloadLen <= 14 + byteCnt - 4;
ELSIF oPayloadLen > byteCnt - 4 THEN
oLenErr <= '1';
END IF;
-- add @ 2013-05-13
IF oGetRaw = '1' THEN
oPayloadLen <= oPayloadLen + 14;
END IF;
IF byteCnt > X"0600" OR byteCnt < X"0020" THEN
oLenErr <= '1';
END IF;
END IF;
WHEN OTHERS => state <= IDLE;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/eth_pkg.vhd
0,0 → 1,72
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : eth_pkg.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-11-04
-- Last update: 2012-12-03
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-04 1.0 root Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
PACKAGE eth_pkg IS
 
CONSTANT ETH_TYPE_IPv4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0800";
CONSTANT ETH_TYPE_ARP : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0806";
CONSTANT ETH_TYPE_RARP : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8035";
CONSTANT ETH_TYPE_8021Q : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8100";
CONSTANT ETH_TYPE_CTRL : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8808";
CONSTANT ETH_TYPE_JUMBO : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8870";
 
CONSTANT IPv4_PROTOCOL_ICMP : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"01";
CONSTANT IPv4_PROTOCOL_TCP : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"06";
CONSTANT IPv4_PROTOCOL_UDP : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"11";
 
-- multicast address for control frame
CONSTANT MAC_ADDR_CTRL : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"0180C2000001";
 
CONSTANT TCP_OPT_EOL : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"00"; --end of list
CONSTANT TCP_OPT_NOP : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"01";
CONSTANT TCP_OPT_MSS : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"02";
CONSTANT TCP_OPT_WS : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"03"; --window scale
 
-----------------------------------------------------------------------------
-- registers address
-----------------------------------------------------------------------------
CONSTANT REG_ADDR_WIDTH : INTEGER := 5;
CONSTANT MDIO_MODER_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(0, REG_ADDR_WIDTH);
CONSTANT MDIO_CMD_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(1, REG_ADDR_WIDTH);
CONSTANT MDIO_ADDR_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(2, REG_ADDR_WIDTH);
CONSTANT MDIO_TxD_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(3, REG_ADDR_WIDTH);
CONSTANT MDIO_RxD_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(4, REG_ADDR_WIDTH);
 
CONSTANT RGMII_STATUS_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(5, REG_ADDR_WIDTH);
CONSTANT MAC_ADDR0L_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(6, REG_ADDR_WIDTH);
CONSTANT MAC_ADDR0H_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(7, REG_ADDR_WIDTH);
CONSTANT MAC_ADDR1L_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(8, REG_ADDR_WIDTH);
CONSTANT MAC_ADDR1H_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(9, REG_ADDR_WIDTH);
CONSTANT IP_ADDR0_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(10, REG_ADDR_WIDTH);
CONSTANT IP_ADDR1_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(11, REG_ADDR_WIDTH);
CONSTANT LISTEN_PORT_addr : UNSIGNED(REG_ADDR_WIDTH-1 DOWNTO 0) := to_unsigned(12, REG_ADDR_WIDTH);
 
END PACKAGE eth_pkg;
-------------------------------------------------------------------------------
PACKAGE BODY eth_pkg IS
 
 
 
END PACKAGE BODY eth_pkg;
/trunk/rtl/rgmii/rgmii100_io_fifo.vhd
0,0 → 1,193
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
 
-- ============================================================
-- File Name: rgmii100_io_fifo.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
-- ************************************************************
 
 
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.all;
 
ENTITY rgmii100_io_fifo IS
PORT
(
data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
END rgmii100_io_fifo;
 
 
ARCHITECTURE SYN OF rgmii100_io_fifo IS
 
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
 
 
 
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC
);
END COMPONENT;
 
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(9 DOWNTO 0);
rdempty <= sub_wire2;
 
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone IV E",
lpm_numwords => 16,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 10,
lpm_widthu => 4,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
wrsync_delaypipe => 4
)
PORT MAP (
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
wrfull => sub_wire0,
q => sub_wire1,
rdempty => sub_wire2
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "16"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "10"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "10"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_io_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_io_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_io_fifo.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_io_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii100_io_fifo_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/rtl/rgmii/rgmii_tx.vhd
0,0 → 1,155
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_tx.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-11-15
-- Last update: 2013-05-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-15 1.0 root Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_tx IS
 
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
-- from fifo
iTxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
oSOF : OUT STD_LOGIC;
iEOF : IN STD_LOGIC;
iGenFrame : IN STD_LOGIC;
oGenFrameAck : OUT STD_LOGIC;
 
-- signals TO PHY
oTxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oTxEn : OUT STD_LOGIC;
oTxErr : OUT STD_LOGIC
);
 
END ENTITY rgmii_tx;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_tx IS
 
TYPE state_t IS (IDLE, PREAMBLE, SEND_DATA, PAD, SEND_CRC, IPG);
SIGNAL state : state_t;
ATTRIBUTE syn_encoding : STRING;
ATTRIBUTE syn_encoding OF state_t : TYPE IS "safe,onehot";
 
SIGNAL byteCnt : UNSIGNED(15 DOWNTO 0);
 
SIGNAL crcInit : STD_LOGIC;
SIGNAL crcEn : STD_LOGIC;
SIGNAL crc : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
 
crcCalc : ENTITY work.eth_crc32
PORT MAP (
iClk => iClk,
iRst_n => iRst_n,
iInit => crcInit,
iCalcEn => crcEn,
iData => iTxData,
oCRC => crc,
oCRCErr => OPEN);
 
oTxErr <= '0';
 
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
state <= IDLE;
oSOF <= '0';
byteCnt <= (OTHERS => '0');
oGenFrameAck <= '0';
crcInit <= '0';
crcEn <= '0';
oTxData <= (OTHERS => '0');
oTxEn <= '0';
ELSIF rising_edge(iClk) THEN
oGenFrameAck <= '0';
crcInit <= '0';
oSOF <= '0';
byteCnt <= byteCnt + 1;
CASE state IS
WHEN IDLE =>
byteCnt <= (OTHERS => '0');
IF iGenFrame = '1' THEN
crcInit <= '1';
oGenFrameAck <= '1';
state <= PREAMBLE;
END IF;
-----------------------------------------------------------------------
WHEN PREAMBLE =>
oTxEn <= '1';
oTxData <= X"55";
CASE byteCnt(2 DOWNTO 0) IS
WHEN B"101" => oSOF <= '1';
WHEN B"111" =>
oTxData <= X"D5";
crcEn <= '1';
state <= SEND_DATA;
byteCnt <= (OTHERS => '0');
WHEN OTHERS => NULL;
END CASE;
-----------------------------------------------------------------------
WHEN SEND_DATA =>
oTxData <= iTxData;
IF iEOF = '1' THEN
IF byteCnt < X"003B" THEN
state <= PAD;
ELSE
state <= SEND_CRC;
crcEn <= '0';
byteCnt <= (OTHERS => '0');
END IF;
END IF;
-----------------------------------------------------------------------
WHEN PAD =>
oTxData <= iTxData;
IF byteCnt(7 DOWNTO 0) = X"3B" THEN
crcEn <= '0';
state <= SEND_CRC;
byteCnt <= (OTHERS => '0');
END IF;
-----------------------------------------------------------------------
WHEN SEND_CRC =>
CASE byteCnt(1 DOWNTO 0) IS
WHEN B"00" => oTxData <= crc(31 DOWNTO 24);
WHEN B"01" => oTxData <= crc(23 DOWNTO 16);
WHEN B"10" => oTxData <= crc(15 DOWNTO 8);
WHEN B"11" =>
oTxData <= crc(7 DOWNTO 0);
state <= IPG;
byteCnt <= (OTHERS => '0');
WHEN OTHERS => NULL;
END CASE;
-----------------------------------------------------------------------
WHEN IPG => -- 96 bits(12 Bytes) time
oTxEn <= '0';
IF byteCnt(3 DOWNTO 0) = X"B" THEN
state <= IDLE;
byteCnt <= (OTHERS => '0');
END IF;
-----------------------------------------------------------------------
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
 
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/rgmii_wbs.vhd
0,0 → 1,240
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_wbs.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-12-02
-- Last update: 2013-05-20
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-12-02 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.de2_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_wbs IS
GENERIC (
IN_SIMULATION : BOOLEAN := FALSE);
PORT (
iWbClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
iWbM2S : IN wbMasterToSlaveIF_t;
oWbS2M : OUT wbSlaveToMasterIF_t;
-- synthesis translate_off
iWbM2S_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
iWbM2S_dat : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
iWbM2S_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
iWbM2S_stb : IN STD_LOGIC;
iWbM2S_cyc : IN STD_LOGIC;
iWbM2S_we : IN STD_LOGIC;
oWbS2M_dat : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbS2M_ack : OUT STD_LOGIC;
-- synthesis translate_on
 
---------------------------------------------------------------------------
-- tx wishbone master
---------------------------------------------------------------------------
oTxEn : OUT STD_LOGIC; -- tx module enable
oTxIntEn : OUT STD_LOGIC; -- interrupt enable
oTxIntClr : OUT STD_LOGIC; -- clear interrupt SIGNAL
iTxIntInfo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
oTxDescData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
iTxDescData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
oTxDescWr : OUT STD_LOGIC;
oTxDescAddr : OUT STD_LOGIC_VECTOR(8 DOWNTO 2);
-- hardware checksum generation
oCheckSumIPGen : OUT STD_LOGIC;
oCheckSumTCPGen : OUT STD_LOGIC;
oCheckSumUDPGen : OUT STD_LOGIC;
oCheckSumICMPGen : OUT STD_LOGIC;
 
---------------------------------------------------------------------------
-- rx wishbone master
---------------------------------------------------------------------------
oRxEn : OUT STD_LOGIC;
oRxDescAddr : OUT STD_LOGIC_VECTOR(8 DOWNTO 2);
oRxDescWr : OUT STD_LOGIC;
oRxDescData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
iRxDescData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
oRxIntClr : OUT STD_LOGIC;
iRxIntInfo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxIntEn : OUT STD_LOGIC;
oRxBufBegin : OUT STD_LOGIC_VECTOR(31 DOWNTO 2);
oRxBufEnd : OUT STD_LOGIC_VECTOR(31 DOWNTO 2);
-- hardware checksum check
oCheckSumIPCheck : OUT STD_LOGIC;
oCheckSumTCPCheck : OUT STD_LOGIC;
oCheckSumUDPCheck : OUT STD_LOGIC;
oCheckSumICMPCheck : OUT STD_LOGIC;
 
---------------------------------------------------------------------------
-- MDIO
---------------------------------------------------------------------------
oPHYAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
oRegAddr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
oRdOp : OUT STD_LOGIC;
oWrOp : OUT STD_LOGIC;
oNoPre : OUT STD_LOGIC;
oClkDiv : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
iClrRdOp : IN STD_LOGIC := '0';
iClrWrOp : IN STD_LOGIC := '0';
oDataToPHY : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
iDataFromPHY : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
iDataFromPHYValid : IN STD_LOGIC := '0';
iMDIOBusy : IN STD_LOGIC := '0'
);
 
END ENTITY rgmii_wbs;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_wbs IS
TYPE state_t IS (IDLE, WAIT1, WAIT2, WAIT3);
SIGNAL rState : state_t;
SIGNAL rRegCtrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
SIGNAL cWbDatI : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cWbAddr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cWbWE : STD_LOGIC;
SIGNAL cWbCyc : STD_LOGIC;
SIGNAL cWbStb : STD_LOGIC;
SIGNAL cWbSel : STD_LOGIC_VECTOR(3 DOWNTO 0);
 
SIGNAL rWbAck : STD_LOGIC;
SIGNAL rWbDatO : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
 
oWbS2M.stall <= '0';
oWbS2M.err <= '0';
oWbS2M.rty <= '0';
oWbS2M.ack <= rWbAck;
oWbS2M.dat <= rWbDatO;
 
-- synthesis translate_off
gen0 : IF IN_SIMULATION GENERATE
cWbDatI <= iWbM2S_dat;
cWbAddr <= iWbM2S_addr;
cWbWE <= iWbM2S_we;
cWbCyc <= iWbM2S_cyc;
cWbStb <= iWbM2S_stb;
cWbSel <= iWbM2S_sel;
END GENERATE gen0;
oWbS2M_ack <= rWbAck;
oWbS2M_dat <= rWbDatO;
-- synthesis translate_on
gen1 : IF NOT IN_SIMULATION GENERATE
cWbDatI <= iWbM2S.dat;
cWbAddr <= iWbM2S.addr;
cWbWE <= iWbM2S.we;
cWbCyc <= iWbM2S.cyc;
cWbStb <= iWbM2S.stb;
cWbSel <= iWbM2S.sel;
END GENERATE gen1;
 
oTxDescData <= cWbDatI;
oTxDescAddr <= cWbAddr(8 DOWNTO 2);
oTxDescWr <= cWbWE AND
cWbStb AND
cWbCyc AND
NOT cWbAddr(10) AND
NOT cWbAddr(9);
 
oRxDescData <= cWbDatI;
oRxDescAddr <= cWbAddr(8 DOWNTO 2);
oRxDescWr <= cWbWE AND
cWbStb AND
cWbCyc AND
NOT cWbAddr(10) AND
cWbAddr(9);
 
oTxEn <= rRegCtrl(0);
oTxIntEn <= rRegCtrl(1);
oCheckSumIPGen <= rRegCtrl(8);
oCheckSumTCPGen <= rRegCtrl(9);
oCheckSumUDPGen <= rRegCtrl(10);
oCheckSumICMPGen <= rRegCtrl(11);
oRxEn <= rRegCtrl(16);
oRxIntEn <= rRegCtrl(17);
oCheckSumIPCheck <= rRegCtrl(24);
oCheckSumTCPCheck <= rRegCtrl(25);
oCheckSumUDPCheck <= rRegCtrl(26);
oCheckSumICMPCheck <= rRegCtrl(27);
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rWbAck <= '0';
rWbDatO <= (OTHERS => '0');
oTxIntClr <= '0';
oRxIntClr <= '0';
rRegCtrl <= (OTHERS => '0');
oRxBufBegin <= (OTHERS => '0');
oRxBufEnd <= (OTHERS => '0');
ELSIF rising_edge(iWbClk) THEN
oTxIntClr <= '0';
oRxIntClr <= '0';
rWbAck <= '0';
CASE rState IS
WHEN IDLE =>
IF cWbCyc = '1' AND cWbStb = '1' THEN
rWbAck <= cWbWE;
IF cWbWE = '1' THEN
rState <= WAIT3;
ELSE
rState <= WAIT1;
END IF;
 
IF cWbWE = '0' AND cWbAddr(10) = '1' THEN
IF cWbAddr(3 DOWNTO 2) = B"11" THEN
oTxIntClr <= cWbSel(0);
oRxIntClr <= cWbSel(1);
END IF;
END IF;
IF (cWbWE AND cWbAddr(10)) = '1' THEN
CASE cWbAddr(3 DOWNTO 2) IS
WHEN B"00" =>
rRegCtrl <= cWbDatI;
WHEN B"01" =>
oRxBufBegin <= cWbDatI(31 DOWNTO 2);
WHEN B"10" =>
oRxBufEnd <= cWbDatI(31 DOWNTO 2);
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
-----------------------------------------------------------------------
WHEN WAIT1 =>
rState <= WAIT2;
WHEN WAIT2 =>
rState <= WAIT3;
rWbAck <= '1';
IF cWbAddr(10) = '0' THEN
IF cWbAddr(9) = '0' THEN
rWbDatO <= iTxDescData;
ELSE
rWbDatO <= iRxDescData;
END IF;
ELSE
CASE cWbAddr(3 DOWNTO 2) IS
WHEN B"11" => rWbDatO <= X"0000"&iRxIntInfo&iTxIntInfo;
WHEN OTHERS => NULL;
END CASE;
END IF;
-----------------------------------------------------------------------
WHEN WAIT3 =>
rState <= IDLE;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/rgmii_rx_wbm.vhd
0,0 → 1,538
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_rx_wbm.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2013-05-07
-- Last update: 2013-05-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-05-07 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.de2_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_rx_wbm IS
GENERIC (
IN_SIMULATION : BOOLEAN := FALSE);
 
PORT (
iWbClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
oWbM2S : OUT wbMasterToSlaveIF_t;
iWbS2M : IN wbSlaveToMasterIF_t;
 
-- synthesis translate_off
oWbM2S_dat : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbM2S_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbM2S_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
oWbM2S_cyc : OUT STD_LOGIC;
oWbM2S_stb : OUT STD_LOGIC;
oWbM2S_we : OUT STD_LOGIC;
oWbM2S_cti : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
oWbM2S_bte : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
iWbS2M_ack : IN STD_LOGIC;
-- synthesis translate_on
 
iRegBufBegin : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
iRegBufEnd : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
 
-- from RX
iIntNewFrame : IN STD_LOGIC;
oIntNewFrameClr : OUT STD_LOGIC;
oRxDataRead : BUFFER STD_LOGIC;
iRxData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
oRxInfoRead : OUT STD_LOGIC;
iRxInfo : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 
---------------------------------------------------------------------------
-- wishbone slave
iWbAddr : IN STD_LOGIC_VECTOR(8 DOWNTO 2);
iWbWE : IN STD_LOGIC;
iWbData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
iWbRxIntClr : IN STD_LOGIC;
oWbRxIntInfo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oWbRxInt : OUT STD_LOGIC;
iWbRxIntEn : IN STD_LOGIC -- interrupt enable
);
 
END ENTITY rgmii_rx_wbm;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_rx_wbm IS
 
SIGNAL rStreamFifoWr : STD_LOGIC;
SIGNAL cStreamFifoRd : STD_LOGIC;
SIGNAL cStreamFifoDI : STD_LOGIC_VECTOR(33 DOWNTO 0);
SIGNAL cStreamFifoDO : STD_LOGIC_VECTOR(33 DOWNTO 0);
 
-----------------------------------------------------------------------------
SIGNAL rBurstReq : BOOLEAN;
SIGNAL rBurstDone : BOOLEAN;
 
-----------------------------------------------------------------------------
--
SIGNAL rDescWE : STD_LOGIC;
SIGNAL rDescAddr : UNSIGNED(6 DOWNTO 0);
SIGNAL rDescDO : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rDescDI : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
------------------------------------------------------------------------------
--
SIGNAL rStartTran : BOOLEAN;
SIGNAL rTransDone : BOOLEAN;
SIGNAL rStartAddr : STD_LOGIC_VECTOR(31 DOWNTO 2);
SIGNAL rFlush : BOOLEAN;
BEGIN -- ARCHITECTURE rtl
 
-----------------------------------------------------------------------------
-- FOR receive dma descriptors,32x128
-----------------------------------------------------------------------------
blkDescriptor : BLOCK IS
-- Build a 2-D array type for the RAM
SUBTYPE word_t IS STD_LOGIC_VECTOR(31 DOWNTO 0);
TYPE memory_t IS ARRAY(127 DOWNTO 0) OF word_t;
-- Declare the RAM
SHARED VARIABLE ram : memory_t := (OTHERS => (OTHERS => '0'));
BEGIN -- BLOCK blkDescriptor
-- Port A,wishbone slave
PROCESS(iWbClk)
BEGIN
IF(rising_edge(iWbClk)) THEN
IF(iWbWE = '1') THEN
ram(to_integer(UNSIGNED(iWbAddr))) := iWbData;
END IF;
oWbData <= ram(to_integer(UNSIGNED(iWbAddr)));
END IF;
END PROCESS;
-- Port B ,internal use
PROCESS(iWbClk)
BEGIN
IF(rising_edge(iWbClk)) THEN
IF(rDescWE = '1') THEN
ram(to_integer(rDescAddr)) := rDescDI;
END IF;
rDescDO <= ram(to_integer(rDescAddr));
END IF;
END PROCESS;
END BLOCK blkDescriptor;
 
fifo_sc_34x64_1 : ENTITY work.fifo_sc_34x64
PORT MAP (
clock => iWbClk,
data => cStreamFifoDI,
rdreq => cStreamFifoRd,
wrreq => rStreamFifoWr,
empty => OPEN,
full => OPEN,
q => cStreamFifoDO);
 
blk2 : BLOCK IS
TYPE state_t IS (FIRST_TIME, IDLE, WAIT1, FIND_USEABLE1, FLUSH,
FIND_USEABLE2, WRITE_ADDR, GET_INFO, TRANS);
SIGNAL rState : state_t;
SIGNAL rBeginAddr : UNSIGNED(6 DOWNTO 0);
SIGNAL cEmpty : STD_LOGIC;
SIGNAL cFull : STD_LOGIC;
SIGNAL cIntDesc : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rWrReq : STD_LOGIC;
SIGNAL cRdReq : STD_LOGIC;
SIGNAL rIntDesc : STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN -- BLOCK blk2
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oWbRxInt <= '0';
ELSIF rising_edge(iWbClk) THEN
IF cEmpty = '0' THEN
oWbRxInt <= iWbRxIntEn;
END IF;
IF cEmpty = '1' OR iWbRxIntClr = '1' THEN
oWbRxInt <= '0';
END IF;
END IF;
END PROCESS;
 
oWbRxIntInfo(6 DOWNTO 0) <= cIntDesc&'0';
cRdReq <= iWbRxIntClr AND NOT cEmpty;
PROCESS (iWbClk) IS
BEGIN
IF rising_edge(iWbClk) THEN
IF iWbRxIntClr = '1' THEN
oWbRxIntInfo(7) <= cEmpty;
END IF;
END IF;
END PROCESS;
fifo_sc_6x64_1 : ENTITY work.fifo_sc_6x64
PORT MAP (
clock => iWbClk,
data => rIntDesc,
rdreq => cRdReq,
wrreq => rWrReq,
empty => cEmpty,
full => cFull,
q => cIntDesc);
 
PROCESS (iWbClk, iRst_n) IS
VARIABLE vNextStartAddr : UNSIGNED(31 DOWNTO 2);
VARIABLE vIntDescAddr : UNSIGNED(5 DOWNTO 0);
BEGIN
IF iRst_n = '0' THEN
rState <= FIRST_TIME;
oIntNewFrameClr <= '0';
oRxInfoRead <= '0';
rStartTran <= FALSE;
rStartAddr <= (OTHERS => '0');
rBeginAddr <= (OTHERS => '0');
rDescAddr <= (OTHERS => '0');
rDescWE <= '0';
rDescDI <= (OTHERS => '0');
rIntDesc <= (OTHERS => '0');
rWrReq <= '0';
rFlush <= FALSE;
ELSIF rising_edge(iWbClk) THEN
rWrReq <= '0';
oIntNewFrameClr <= '0';
oRxInfoRead <= '0';
rDescWE <= '0';
rStartTran <= FALSE;
rFlush <= FALSE;
IF rDescWE = '1' THEN
rDescAddr <= rDescAddr + 1;
END IF;
CASE rState IS
WHEN FIRST_TIME =>
rStartAddr <= iRegBufBegin;
IF iIntNewFrame = '1' THEN
oIntNewFrameClr <= '1';
oRxInfoRead <= '1';
IF cFull = '0' THEN
IF rDescDO(16) = '0' THEN -- get a useable descriptor
rState <= WAIT1; -- WAIT FOR info ready
ELSE
rDescAddr <= rDescAddr + 2;
rState <= FIND_USEABLE1;
END IF;
rBeginAddr <= (OTHERS => '0');
ELSE
rState <= FLUSH;
rFlush <= TRUE;
END IF;
END IF;
WHEN IDLE=>
IF iIntNewFrame = '1' THEN
oIntNewFrameClr <= '1';
oRxInfoRead <= '1';
IF cFull = '0' THEN
IF rDescDO(16) = '0' THEN -- get a useable descriptor
rState <= WAIT1;
ELSE
rDescAddr <= rDescAddr + 2;
rState <= FIND_USEABLE1;
END IF;
rBeginAddr <= rDescAddr;
ELSE
rState <= FLUSH;
rFlush <= TRUE;
END IF;
END IF;
---------------------------------------------------------------------
WHEN WAIT1 =>
rState <= GET_INFO;
WHEN GET_INFO =>
rState <= WRITE_ADDR;
rStartTran <= TRUE;
rDescWE <= '1';
rDescDI(15 DOWNTO 0) <= iRxInfo(15 DOWNTO 0); -- length IN bytes
rDescDI(16) <= '1'; --flag
rDescDI(27 DOWNTO 24) <= iRxInfo(31 DOWNTO 28); -- frame TYPE
---------------------------------------------------------------------
WHEN FIND_USEABLE1 =>
rState <= FIND_USEABLE2;
WHEN FIND_USEABLE2 =>
IF rDescDO(16) = '0' THEN
-- find one
rStartTran <= TRUE;
rDescWE <= '1';
rDescDI(15 DOWNTO 0) <= iRxInfo(15 DOWNTO 0); -- length IN bytes
rDescDI(16) <= '1'; --flag
rDescDI(27 DOWNTO 24) <= iRxInfo(31 DOWNTO 28); -- frame TYPE
rState <= WRITE_ADDR;
ELSE
rDescAddr <= rDescAddr + 2;
IF rDescAddr = rBeginAddr THEN -- LOOP,still no useable
-- we just flush the received frame
rFlush <= TRUE;
rState <= FLUSH;
ELSE
rState <= FIND_USEABLE1;
END IF;
END IF;
---------------------------------------------------------------------
WHEN WRITE_ADDR =>
rDescWE <= '1';
rDescDI <= rStartAddr&B"00";
rState <= TRANS;
---------------------------------------------------------------------
WHEN TRANS =>
IF rTransDone THEN
vNextStartAddr := UNSIGNED(rStartAddr)+UNSIGNED(iRxInfo(15 DOWNTO 2))+1;
-- NEXT start addr
IF vNextStartAddr > UNSIGNED(iRegBufEnd) THEN
rStartAddr <= iRegBufBegin;
ELSE
rStartAddr <= STD_LOGIC_VECTOR(vNextStartAddr);
END IF;
rState <= IDLE;
rWrReq <= '1';
vIntDescAddr := rDescAddr(6 DOWNTO 1) - 1;
rIntDesc <= STD_LOGIC_VECTOR(vIntDescAddr);
END IF;
---------------------------------------------------------------------
WHEN FLUSH =>
IF rTransDone THEN
rState <= IDLE;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK blk2;
 
blk1 : BLOCK IS
SIGNAL rCyc : STD_LOGIC;
SIGNAL rPreRead : STD_LOGIC;
SIGNAL rReadEn : STD_LOGIC;
TYPE state_t IS (IDLE, PRE_READ, WAIT1, START, SINGLE, BURST, LAST_ONE);
SIGNAL rState : state_t;
SIGNAL rWbAddr : UNSIGNED(31 DOWNTO 2);
SIGNAL cWbS2MAck : STD_LOGIC;
BEGIN -- BLOCK blk1
oWbM2S.bte <= LINEAR;
oWbM2S.dat <= cStreamFifoDO(31 DOWNTO 0);
oWbM2S.stb <= rCyc;
oWbM2S.cyc <= rCyc;
oWbM2S.we <= '1';
oWbM2S.sel <= X"F";
oWbM2S.addr <= STD_LOGIC_VECTOR(rWbAddr)&B"00";
 
-- synthesis translate_off
oWbM2S_bte <= LINEAR;
oWbM2S_dat <= cStreamFifoDO(31 DOWNTO 0);
oWbM2S_stb <= rCyc;
oWbM2S_cyc <= rCyc;
oWbM2S_we <= '1';
oWbM2S_sel <= X"F";
oWbM2S_addr <= STD_LOGIC_VECTOR(rWbAddr)&B"00";
-- synthesis translate_on
-- synthesis translate_off
sim0 : IF IN_SIMULATION GENERATE
cWbS2MAck <= iWbS2M_ack;
END GENERATE sim0;
-- synthesis translate_on
sim1 : IF NOT IN_SIMULATION GENERATE
cWbS2MAck <= iWbS2M.ack;
END GENERATE sim1;
 
cStreamFifoRd <= rPreRead OR (rReadEn AND cWbS2MAck);
 
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rWbAddr <= (OTHERS => '0');
ELSIF rising_edge(iWbClk) THEN
IF rStartTran THEN
rWbAddr <= UNSIGNED(rStartAddr);
END IF;
IF cWbS2MAck = '1' THEN
rWbAddr <= rWbAddr + 1;
END IF;
END IF;
END PROCESS;
 
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rCyc <= '0';
rPreRead <= '0';
rReadEn <= '0';
-- synthesis translate_off
oWbM2S_cti <= CLASSIC;
-- synthesis translate_on
oWbM2S.cti <= CLASSIC;
rState <= IDLE;
rBurstDone <= FALSE;
ELSIF rising_edge(iWbClk) THEN
rPreRead <= '0';
rBurstDone <= FALSE;
CASE rState IS
WHEN IDLE =>
IF rBurstReq THEN
rPreRead <= '1';
rState <= WAIT1;
END IF;
---------------------------------------------------------------------
WHEN WAIT1 =>
rState <= START;
---------------------------------------------------------------------
WHEN START =>
rCyc <= '1';
IF cStreamFifoDO(32) = '1' THEN -- last
-- synthesis translate_off
oWbM2S_cti <= CLASSIC;
-- synthesis translate_on
oWbM2S.cti <= CLASSIC;
rState <= SINGLE;
ELSE
-- synthesis translate_off
oWbM2S_cti <= INCR;
-- synthesis translate_on
oWbM2S.cti <= INCR;
rState <= BURST;
rReadEn <= '1';
END IF;
---------------------------------------------------------------------
WHEN SINGLE =>
IF cWbS2MAck = '1' THEN
rState <= IDLE;
rBurstDone <= TRUE;
rCyc <= '0';
END IF;
---------------------------------------------------------------------
WHEN BURST =>
IF cStreamFifoDO(33) = '1' AND cWbS2MAck = '1' THEN -- pre last
-- synthesis translate_off
oWbM2S_cti <= LAST;
-- synthesis translate_on
oWbM2S.cti <= LAST;
rReadEn <= '0';
rState <= LAST_ONE;
END IF;
---------------------------------------------------------------------
WHEN LAST_ONE =>
IF cWbS2MAck = '1' THEN
rState <= IDLE;
rBurstDone <= TRUE;
rCyc <= '0';
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK blk1;
 
 
blk0 : BLOCK IS
TYPE state_t IS (IDLE, REFILL, WAIT_DONE);
SIGNAL rState : state_t;
SIGNAL rCnt : UNSIGNED(15 DOWNTO 2);
SIGNAL rCnt64 : INTEGER RANGE 0 TO 63;
SIGNAL rLast : STD_LOGIC;
SIGNAL rPreLast : STD_LOGIC;
SIGNAL rNotFlush : STD_LOGIC;
SIGNAL rFinished : BOOLEAN;
BEGIN -- BLOCK blk0
cStreamFifoDI(32) <= rLast;
cStreamFifoDI(33) <= rPreLast;
cStreamFifoDI(31 DOWNTO 0) <= iRxData;
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oRxDataRead <= '0';
rCnt <= (OTHERS => '0');
rStreamFifoWr <= '0';
rTransDone <= FALSE;
rBurstReq <= FALSE;
rLast <= '0';
rPreLast <= '0';
rCnt64 <= 0;
rNotFlush <= '0';
rFinished <= FALSE;
ELSIF rising_edge(iWbClk) THEN
IF oRxDataRead = '1' THEN
rCnt <= rCnt - 1;
-- synthesis translate_off
IF rCnt64 > 0 THEN
-- synthesis translate_on
rCnt64 <= rCnt64 - 1;
-- synthesis translate_off
END IF;
-- synthesis translate_on
END IF;
rStreamFifoWr <= oRxDataRead AND rNotFlush;
rTransDone <= FALSE;
rBurstReq <= FALSE;
rLast <= '0';
rPreLast <= '0';
CASE rState IS
WHEN IDLE =>
rFinished <= FALSE;
IF rStartTran OR rFlush THEN
oRxDataRead <= '1';
IF iRxInfo(1 DOWNTO 0) /= B"00" THEN
rCnt <= UNSIGNED(iRxInfo(15 DOWNTO 2));
ELSE
rCnt <= UNSIGNED(iRxInfo(15 DOWNTO 2)) - 1;
END IF;
rCnt64 <= 63;
rState <= REFILL;
END IF;
IF rFlush THEN
rNotFlush <= '0';
END IF;
IF rStartTran THEN
rNotFlush <= '1';
END IF;
---------------------------------------------------------------------
WHEN REFILL =>
IF rCnt64 = 0 THEN
oRxDataRead <= '0';
rState <= WAIT_DONE;
rLast <= '1';
rBurstReq <= To_Boolean(rNotFlush);
END IF;
IF rCnt = X"000"&B"00" THEN
rFinished <= TRUE;
oRxDataRead <= '0';
rState <= WAIT_DONE;
rLast <= '1';
rBurstReq <= To_Boolean(rNotFlush);
END IF;
IF rCnt = X"000"&B"01" OR rCnt64 = 1 THEN
rPreLast <= '1';
END IF;
---------------------------------------------------------------------
WHEN WAIT_DONE =>
rCnt64 <= 63;
IF rBurstDone OR rNotFlush = '0' THEN
IF rFinished THEN
rTransDone <= TRUE;
rState <= IDLE;
ELSE
rState <= REFILL;
oRxDataRead <= '1';
END IF;
END IF;
WHEN OTHERS => NULL;
END CASE;
-------------------------------------------------------------------------
END IF;
END PROCESS;
END BLOCK blk0;
 
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/rgmii_tx_wbm.vhd
0,0 → 1,937
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_tx_wbm.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2013-05-09
-- Last update: 2013-05-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-05-09 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.de2_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_tx_wbm IS
GENERIC (
IN_SIMULATION : BOOLEAN := FALSE);
PORT (
iWbClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
oWbM2S : OUT wbMasterToSlaveIF_t;
iWbS2M : IN wbSlaveToMasterIF_t;
 
-- synthesis translate_off
oWbM2S_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbM2S_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
oWbM2S_cyc : OUT STD_LOGIC;
oWbM2S_stb : OUT STD_LOGIC;
oWbM2S_we : OUT STD_LOGIC;
oWbM2S_cti : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
oWbM2S_bte : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
iWbS2M_ack : IN STD_LOGIC;
iWbS2M_dat : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- synthesis translate_on
 
-- tx buf
iTxDone : IN STD_LOGIC; -- act as an interrupt SIGNAL(if used)
oTxDoneClr : OUT STD_LOGIC;
iTxDoneInfo : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
oTxData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oTxAddr : OUT UNSIGNED(10 DOWNTO 0);
oTxDataWr : OUT STD_LOGIC;
oTxInfo : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oTxInfoWr : BUFFER STD_LOGIC;
 
--wb
iWbTxEnable : IN STD_LOGIC;
oWbTxInt : OUT STD_LOGIC;
iWbTxIntClr : IN STD_LOGIC;
iWbTxIntEn : IN STD_LOGIC;
iWbTxAddr : IN STD_LOGIC_VECTOR(8 DOWNTO 2);
iWbTxWE : IN STD_LOGIC;
iWbTxData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbTxData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbTxIntInfo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 
iCheckSumIPGen : IN STD_LOGIC;
iCheckSumTCPGen : IN STD_LOGIC;
iCheckSumUDPGen : IN STD_LOGIC;
iCheckSumICMPGen : IN STD_LOGIC
);
 
END ENTITY rgmii_tx_wbm;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_tx_wbm IS
 
SIGNAL rDescWE : STD_LOGIC;
SIGNAL rDescAddr : UNSIGNED(6 DOWNTO 0);
SIGNAL cDescDI : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rDescDO : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
-- the length OF current frame descriptor
SIGNAL rFrameLen : UNSIGNED(15 DOWNTO 0):=(OTHERS => '0');
SIGNAL rDescriptorLen : STD_LOGIC_VECTOR(15 DOWNTO 0);-- 当前descriptor的长度
SIGNAL rStartTran : BOOLEAN;
SIGNAL rTransDone : BOOLEAN;
SIGNAL rCheckSumDone : BOOLEAN;
 
SIGNAL cWbAck : STD_LOGIC;
SIGNAL rWbAck : STD_LOGIC;
SIGNAL rLastOne : BOOLEAN;
SIGNAL cWbData : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- 当前descriptor里面，从wishbone总线读取的32bit宽度数据中，
-- 第一个和最后一个，有效字节数各为多少(大端模式)
SIGNAL rFirstNibbleBytes : NATURAL RANGE 1 TO 4;
SIGNAL rLastNibbleBytes : NATURAL RANGE 1 TO 4;
-- 一个以太网帧可能占用多个descriptor，例如帧的头和载荷在不同的物理区域，
-- 那么下面一个信号表示这是当前帧的最后一个descriptor
SIGNAL rLastDescriptor : STD_LOGIC;
 
-- the data read from outer buf to be send
SIGNAL rDMADat : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL rDMADatV : STD_LOGIC;
 
-- 当前帧的最后一个wishbone读取
SIGNAL rRellyLastOne : BOOLEAN;
BEGIN -- ARCHITECTURE rtl
-- synthesis translate_off
gen0 : IF IN_SIMULATION GENERATE
cWbAck <= iWbS2M_ack;
cWbData <= iWbS2M_dat;
END GENERATE gen0;
-- synthesis translate_on
gen1 : IF NOT IN_SIMULATION GENERATE
cWbAck <= iWbS2M.ack;
cWbData <= iWbS2M.dat;
END GENERATE gen1;
 
PROCESS (iWbClk) IS
BEGIN
IF rising_edge(iWbClk) THEN
rWbAck <= cWbAck;
END IF;
END PROCESS;
csGen : BLOCK IS
SIGNAL rTxAddr : UNSIGNED(10 DOWNTO 0);
TYPE state_t IS (IDLE, TYPE_LEN, TAGED, STACK_TAG,IP4_PAYLOAD,
--ICMP, TCP, UDP,
IP4_HEAD, WAIT_FINISH, CS1, CS2, DONE, DONE2);
SIGNAL rState : state_t;
SIGNAL rAddrRecord : UNSIGNED(10 DOWNTO 0);
SIGNAL rCheckSum : UNSIGNED(31 DOWNTO 0);
SIGNAL cCheckSum : UNSIGNED(15 DOWNTO 0);
SIGNAL rCheckSum2 : UNSIGNED(31 DOWNTO 0);
SIGNAL cCheckSum2 : UNSIGNED(15 DOWNTO 0);
SIGNAL rWordCnt : UNSIGNED(13 DOWNTO 0):=(OTHERS => '0');
SIGNAL rIPHeadLen : UNSIGNED(3 DOWNTO 0); -- IN 32bit
SIGNAL rIPTotalLen : UNSIGNED(15 DOWNTO 0);
SIGNAL rProtocol : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cIPPayloadLen : UNSIGNED(15 DOWNTO 0);
SIGNAL rCS1Addr : UNSIGNED(10 DOWNTO 0);
SIGNAL rCS2Addr : UNSIGNED(10 DOWNTO 0);
SIGNAL rCS1DatBak : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL rCS2DatBak : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL rDMADatVD1 : STD_LOGIC;
BEGIN -- BLOCK csGen
cIPPayloadLen <= rIPTotalLen - to_integer(rIPHeadLen&B"00");
cCheckSum <= NOT (rCheckSum(31 DOWNTO 16)+rCheckSum(15 DOWNTO 0));
cCheckSum2 <= NOT (rCheckSum2(31 DOWNTO 16)+rCheckSum2(15 DOWNTO 0));
oTxAddr <= rTxAddr; -- BUFFER address
 
PROCESS (iWbClk) IS
BEGIN
IF rising_edge(iWbClk) THEN
rDMADatVD1 <= rDMADatV;
END IF;
END PROCESS;
PROCESS (iWbClk, iRst_n) IS
-- VARIABLE vTemp17 : UNSIGNED(16 DOWNTO 0);
VARIABLE vTemp17 : NATURAL RANGE 0 TO 131071;
BEGIN
IF iRst_n = '0' THEN
rTxAddr <= (OTHERS => '0');
rAddrRecord <= (OTHERS => '0');
rState <= IDLE;
rWordCnt <= (OTHERS => '0');
rCheckSumDone <= FALSE;
rIPHeadLen <= (OTHERS => '0');
rIPTotalLen <= (OTHERS => '0');
rProtocol <= (OTHERS => '0');
rCheckSum2 <= (OTHERS => '0');
rCS1Addr <= (OTHERS => '0');
rCS2Addr <= (OTHERS => '0');
rCS1DatBak <= (OTHERS => '0');
rCS2DatBak <= (OTHERS => '0');
ELSIF rising_edge(iWbClk) THEN
rCheckSumDone <= FALSE;
oTxDataWr <= rDMADatV;
oTxData <= rDMADat;
IF rDMADatVD1 = '1' THEN
rTxAddr <= rTxAddr + 1;
END IF;
IF rDMADatV = '1' THEN
rWordCnt <= rWordCnt + 1;
END IF;
IF rRellyLastOne THEN
rAddrRecord <= rTxAddr + 2;
rWordCnt <= (OTHERS => '0');
END IF;
--IF rRellyLastOne THEN
-- rCheckSumDone <= TRUE;
--END IF;
CASE rState IS
WHEN IDLE =>
--rWordCnt <= (OTHERS => '0');
rCheckSum <= (OTHERS => '0');
rCheckSum2 <= (OTHERS => '0');
--IF rStartTran THEN
-- rState <= MAC;
--END IF;
IF rWordCnt(1 DOWNTO 0) = B"10" AND rDMADatV = '1' THEN
rState <= TYPE_LEN;
END IF;
---------------------------------------------------------------------
--WHEN MAC =>
-- IF rWordCnt(1 DOWNTO 0) = B"10" AND rDMADatV = '1' THEN
-- rState <= TYPE_LEN;
-- END IF;
-- IF rRellyLastOne THEN -- this should nerver happen
-- rCheckSumDone <= TRUE;
-- rState <= IDLE;
-- END IF;
---------------------------------------------------------------------
WHEN TYPE_LEN =>
IF rDMADatV = '1' THEN
rState <= DONE;
CASE rDMADat(31 DOWNTO 16) IS
WHEN X"0800" => -- IPv4
rCheckSum <= rCheckSum + UNSIGNED(rDMADat(15 DOWNTO 0));
rIPHeadLen <= UNSIGNED(rDMADat(11 DOWNTO 8));
rWordCnt(3 DOWNTO 0) <= X"1";
rState <= IP4_HEAD;
WHEN X"8100" => -- taged,4 bytes
rState <= TAGED;
WHEN X"88A8" | X"9100" => -- stack taged,8 bytes
rState <= STACK_TAG;
WHEN OTHERS => NULL;
END CASE;
END IF;
IF rRellyLastOne THEN -- this should nerver happen
rCheckSumDone <= TRUE;
rState <= IDLE;
END IF;
---------------------------------------------------------------------
WHEN TAGED =>
IF rDMADatV = '1' THEN
IF rDMADat(31 DOWNTO 16) = X"0800" THEN
rCheckSum <= rCheckSum + UNSIGNED(rDMADat(15 DOWNTO 0));
rIPHeadLen <= UNSIGNED(rDMADat(11 DOWNTO 8));
rWordCnt(3 DOWNTO 0) <= X"1";
rState <= IP4_HEAD;
ELSE
rState <= DONE;
END IF;
END IF;
IF rRellyLastOne THEN -- this should nerver happen
rCheckSumDone <= TRUE;
rState <= IDLE;
END IF;
---------------------------------------------------------------------
WHEN STACK_TAG =>
IF rDMADatV = '1' THEN
rState <= TAGED;
END IF;
IF rRellyLastOne THEN -- this should nerver happen
rCheckSumDone <= TRUE;
rState <= IDLE;
END IF;
---------------------------------------------------------------------
WHEN IP4_HEAD =>
-- rCheckSum2 here used FOR pesudo head sum
IF rDMADatV = '1' THEN
CASE rWordCnt(3 DOWNTO 0) IS
-- 16位的总长度+16位的标识
WHEN X"1" => -- byte 3,4,5,6
rIPTotalLen <= UNSIGNED(rDMADat(31 DOWNTO 16));
vTemp17 := to_integer(UNSIGNED(rDMADat(31 DOWNTO 16)))+
to_integer(UNSIGNED(rDMADat(15 DOWNTO 0)));
rCheckSum <= rCheckSum + vTemp17;
-- 3bit标志+13bit片偏移量 + 8bit TTL + 8 bit Protocol
WHEN X"2" => -- byte 7,8,9,10
vTemp17 := to_integer(UNSIGNED(rDMADat(31 DOWNTO 16)))+
to_integer(UNSIGNED(rDMADat(15 DOWNTO 0)));
rCheckSum <= rCheckSum + vTemp17;
rCheckSum2 <= X"0000"&cIPPayloadLen +
to_integer((UNSIGNED(rDMADat(7 DOWNTO 0))));
rProtocol <= rDMADat(7 DOWNTO 0);
-- 16bit 校验和+源IP地址的高16bit
WHEN X"3" => -- byte 11,12,13,14
-- checksum assumed TO be zero
-- add the higher two bytes OF Source IP Address
rCheckSum <= rCheckSum + UNSIGNED(rDMADat(15 DOWNTO 0));
rCheckSum2 <= rCheckSum2 + UNSIGNED(rDMADat(15 DOWNTO 0));
rCS1DatBak <= rDMADat(15 DOWNTO 0);
-- 记录下相对地址，一会儿checksum计算完成后要写入
IF rDMADatVD1 = '1' THEN
rCS1Addr <= rTxAddr + 1;
ELSE
rCS1Addr <= rTxAddr;
END IF;
-- 源IP地址低16bit + 目的IP地址高16bit
WHEN X"4" => -- byte 15,16,17,18
vTemp17 := to_integer(UNSIGNED(rDMADat(31 DOWNTO 16)))+
to_integer(UNSIGNED(rDMADat(15 DOWNTO 0)));
rCheckSum <= rCheckSum + vTemp17;
rCheckSum2 <= rCheckSum2 + vTemp17;
-- 目的IP地址低16bit + 选项(或数据) 16bit
WHEN X"5" =>
-- rCheckSum2 表示的伪头在这里就计算结束了
rCheckSum2 <= rCheckSum2 + UNSIGNED(rDMADat(31 DOWNTO 16));
-- 但是对于IP头的校验和，还要继续计算选项部分
vTemp17 := to_integer(UNSIGNED(rDMADat(31 DOWNTO 16)))+
to_integer(UNSIGNED(rDMADat(15 DOWNTO 0)));
rCheckSum <= rCheckSum + vTemp17;
WHEN OTHERS =>
vTemp17 := to_integer(UNSIGNED(rDMADat(31 DOWNTO 16)))+
to_integer(UNSIGNED(rDMADat(15 DOWNTO 0)));
rCheckSum <= rCheckSum + vTemp17;
END CASE;
IF rIPHeadLen = rWordCnt(3 DOWNTO 0) THEN -- ip head finished
rCheckSum <= rCheckSum + UNSIGNED(rDMADat(31 DOWNTO 16));
rWordCnt <= (OTHERS => '0');
rState <= WAIT_FINISH;
IF cIPPayloadLen /= X"0000" THEN
CASE rProtocol IS
WHEN X"01" => -- icmp
rCheckSum2 <= X"0000"&UNSIGNED(rDMADat(15 DOWNTO 0));
rState <= IP4_PAYLOAD;
WHEN X"06" | X"11" => -- tcp
IF rIPHeadLen = X"5" THEN -- 没有IP头选项部分
vTemp17 := to_integer(UNSIGNED(rDMADat(31 DOWNTO 16)))+
to_integer(UNSIGNED(rDMADat(15 DOWNTO 0)));
rCheckSum2 <= rCheckSum2 + vTemp17;
ELSE
rCheckSum2 <= rCheckSum2 + UNSIGNED(rDMADat(15 DOWNTO 0));
END IF;
rState <= IP4_PAYLOAD;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END IF;
IF rRellyLastOne THEN -- this should nerver happen
rCheckSumDone <= TRUE;
rState <= IDLE;
END IF;
---------------------------------------------------------------------
WHEN IP4_PAYLOAD =>
IF rDMADatV = '1' THEN
-- 最后一个32位数据，但是，4字节不都是有效的，但是已经保证其它的无效
-- 的数据为0了，因此，跟平常一样加起来也无所谓
vTemp17 := to_integer(UNSIGNED(rDMADat(31 DOWNTO 16)))+
to_integer(UNSIGNED(rDMADat(15 DOWNTO 0)));
rCheckSum2 <= rCheckSum2 + vTemp17;
CASE rProtocol IS
WHEN X"01" => -- icmp
IF rWordCnt = X"000"&B"00" THEN
rCS2DatBak <= rDMADat(15 DOWNTO 0);
rCheckSum2 <= rCheckSum2 + UNSIGNED(rDMADat(15 DOWNTO 0));
IF rDMADatVD1 = '1' THEN
rCS2Addr <= rTxAddr + 1;
ELSE
rCS2Addr <= rTxAddr;
END IF;
END IF;
---------------------------------------------------------------
WHEN X"06" => -- tcp
IF rWordCnt = X"000"&B"11" THEN
rCS2DatBak <= rDMADat(31 DOWNTO 16);
rCheckSum2 <= rCheckSum2 + UNSIGNED(rDMADat(31 DOWNTO 16));
IF rDMADatVD1 = '1' THEN
rCS2Addr <= rTxAddr + 1;
ELSE
rCS2Addr <= rTxAddr;
END IF;
END IF;
---------------------------------------------------------------
WHEN X"11" => -- udp
IF rWordCnt = X"000"&B"01" THEN
rCS2DatBak <= rDMADat(15 DOWNTO 0);
rCheckSum2 <= rCheckSum2 + UNSIGNED(rDMADat(15 DOWNTO 0));
IF rDMADatVD1 = '1' THEN
rCS2Addr <= rTxAddr + 1;
ELSE
rCS2Addr <= rTxAddr;
END IF;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
IF rRellyLastOne THEN
rState <= CS2;
END IF;
---------------------------------------------------------------------
WHEN WAIT_FINISH =>
IF rRellyLastOne THEN
rState <= CS1;
END IF;
---------------------------------------------------------------------
WHEN CS1 => -- ip checksum
rTxAddr <= rCS1Addr;
oTxData <= STD_LOGIC_VECTOR(cCheckSum)&rCS1DatBak;
oTxDataWr <= '1';
rState <= DONE2;
---------------------------------------------------------------------
WHEN CS2 => -- tcp udp icmp checksum
IF rProtocol = X"06" THEN -- tcp
oTxData <= rCS2DatBak&STD_LOGIC_VECTOR(cCheckSum2);
ELSE
oTxData <= STD_LOGIC_VECTOR(cCheckSum2)&rCS2DatBak;
END IF;
rTxAddr <= rCS2Addr;
oTxDataWr <= '1';
rState <= CS1;
---------------------------------------------------------------------
-- 不是ipv4的帧
WHEN DONE =>
IF rRellyLastOne THEN
rCheckSumDone <= TRUE;
rState <= IDLE;
END IF;
---------------------------------------------------------------------
WHEN DONE2 =>
oTxDataWr <= '0';
rState <= IDLE;
rCheckSumDone <= TRUE;
rTxAddr <= rAddrRecord;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK csGen;
 
 
-----------------------------------------------------------------------------
-- FOR receive dma descriptors,32x128
-----------------------------------------------------------------------------
blkDescriptor : BLOCK IS
-- Build a 2-D array type for the RAM
SUBTYPE word_t IS STD_LOGIC_VECTOR(31 DOWNTO 0);
TYPE memory_t IS ARRAY(127 DOWNTO 0) OF word_t;
-- Declare the RAM
SHARED VARIABLE ram : memory_t := (OTHERS => (OTHERS => '0'));
BEGIN -- BLOCK blkDescriptor
-- Port A,wishbone slave
PROCESS(iWbClk)
BEGIN
IF(rising_edge(iWbClk)) THEN
IF(iWbTxWE = '1') THEN
ram(to_integer(UNSIGNED(iWbTxAddr))) := iWbTxData;
END IF;
oWbTxData <= ram(to_integer(UNSIGNED(iWbTxAddr)));
END IF;
END PROCESS;
-- Port B ,internal use
PROCESS(iWbClk)
BEGIN
IF(rising_edge(iWbClk)) THEN
IF(rDescWE = '1') THEN
ram(to_integer(rDescAddr)) := cDescDI;
END IF;
rDescDO <= ram(to_integer(rDescAddr));
END IF;
END PROCESS;
END BLOCK blkDescriptor;
 
-----------------------------------------------------------------------------
-- un-unsed
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oTxDoneClr <= '0';
ELSIF rising_edge(iWbClk) THEN
oTxDoneClr <= '0';
IF iTxDone = '1' THEN
oTxDoneClr <= '1';
END IF;
END IF;
END PROCESS;
 
blk0 : BLOCK IS
TYPE state_t IS (IDLE, FIND_USEABLE1, WAIT2, TRANS);
SIGNAL rState : state_t;
SIGNAL cEmpty : STD_LOGIC;
SIGNAL cFull : STD_LOGIC;
SIGNAL cIntDesc : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rWrReq : STD_LOGIC;
SIGNAL cRdReq : STD_LOGIC;
SIGNAL rIntDesc : STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN -- BLOCK blk0
cDescDI <= (OTHERS => '0');
oTxInfo(31) <= '0';
oTxInfo(15 DOWNTO 0) <= STD_LOGIC_VECTOR(rFrameLen);
 
oWbTxIntInfo(6 DOWNTO 0) <= cIntDesc&'0';
cRdReq <= iWbTxIntClr AND NOT cEmpty;
PROCESS (iWbClk) IS
BEGIN
IF rising_edge(iWbClk) THEN
IF iWbTxIntClr = '1' THEN
oWbTxIntInfo(7) <= cEmpty;
END IF;
END IF;
END PROCESS;
 
fifo_sc_6x64_1 : ENTITY work.fifo_sc_6x64
PORT MAP (
clock => iWbClk,
data => rIntDesc,
rdreq => cRdReq,
wrreq => rWrReq,
empty => cEmpty,
full => cFull,
q => cIntDesc);
 
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oWbTxInt <= '0';
ELSIF rising_edge(iWbClk) THEN
IF cEmpty = '0' THEN
oWbTxInt <= iWbTxIntEn;
END IF;
IF cEmpty = '1' OR iWbTxIntClr = '1' THEN
oWbTxInt <= '0';
END IF;
END IF;
END PROCESS;
 
PROCESS (iWbClk) IS
BEGIN
IF rising_edge(iWbClk) THEN
rWrReq <= '0';
IF rTransDone THEN
--IF rCheckSumDone THEN
rWrReq <= iWbTxIntEn;
rIntDesc <= STD_LOGIC_VECTOR(rDescAddr(6 DOWNTO 1));
END IF;
END IF;
END PROCESS;
 
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rState <= IDLE;
rDescAddr <= (OTHERS => '0');
rDescWE <= '0';
rFrameLen <= (OTHERS => '0');
rStartTran <= FALSE;
oTxInfo(30 DOWNTO 16) <= (OTHERS => '0');
oTxInfoWr <= '0';
rLastDescriptor <= '0';
rDescriptorLen <= (OTHERS => '0');
ELSIF rising_edge(iWbClk) THEN
rDescWE <= '0';
rStartTran <= FALSE;
oTxInfoWr <= '0';
IF oTxInfoWr = '1' THEN
rFrameLen <= (OTHERS => '0');
END IF;
CASE rState IS
WHEN IDLE =>
IF cFull = '0' AND iWbTxEnable = '1' AND
-- NOT too much frames pending...
iTxDoneInfo(31) = '0' THEN
IF rDescDO(16) = '1' AND rDescDO(15 DOWNTO 0) /= X"0000" THEN -- ready to be send
-- 当前帧的最后一个descriptor了
rLastDescriptor <= rDescDO(17);
-- and theres is plenty room for this frame
IF rDescDO(15 DOWNTO 0) < iTxDoneInfo(15 DOWNTO 0) THEN
-- then start sending...
rFrameLen <= UNSIGNED(rDescDO(15 DOWNTO 0))+rFrameLen;
rDescriptorLen <= rDescDO(15 DOWNTO 0);
rState <= WAIT2;
-- start addr in the tx buf
oTxInfo(30 DOWNTO 16) <= iTxDoneInfo(30 DOWNTO 16);
--this will give us the location of the current frame
rDescAddr <= rDescAddr + 1;
END IF;
ELSE -- find NEXT one
rDescAddr <= rDescAddr + 2;
rState <= FIND_USEABLE1;
END IF;
END IF;
---------------------------------------------------------------------
WHEN FIND_USEABLE1 =>
rState <= IDLE;
---------------------------------------------------------------------
--WHEN WAIT1 =>
-- rState <= WAIT2;
WHEN WAIT2 =>
rStartTran <= TRUE;
rState <= TRANS;
rDescAddr <= rDescAddr - 1;
rDescWE <= '1';
WHEN TRANS =>
-- 如果当前descriptor已经读入完成，并且不是最后一个，那么就不等待
-- checksum计算完成，直接进入下一个descriptor的查找
IF rTransDone AND rLastDescriptor = '0' THEN
rState <= IDLE;
ELSIF rCheckSumDone THEN
rState <= IDLE;
-- this will info the tx_buf module a valid frame has been
-- successfully writen into the buf,and ready to be send out
oTxInfoWr <= '1';
-- IF we clear now AND jump TO IDLE,the flag IS NOT fully cleared
-- rDescWE <= '1';move TO the previous state !!!BUG
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK blk0;
 
blk1 : BLOCK IS
SIGNAL rCnt : UNSIGNED(15 DOWNTO 2);
SIGNAL rCnt64 : UNSIGNED(5 DOWNTO 0);
TYPE state_t IS (IDLE, REFILL, WAIT1, WASTE);
SIGNAL rState : state_t;
SIGNAL rCycStb : STD_LOGIC;
SIGNAL rWbAddr : UNSIGNED(31 DOWNTO 2);
SIGNAL rWbCti : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN -- BLOCK blk1
oWbM2S.bte <= LINEAR;
oWbM2S.cyc <= rCycStb;
oWbM2S.stb <= rCycStb;
oWbM2S.we <= '0';
oWbM2S.addr <= STD_LOGIC_VECTOR(rWbAddr)&B"00";
oWbM2S.sel <= X"F";
oWbM2S.cti <= rWbCti;
-- synthesis translate_off
oWbM2S_bte <= LINEAR;
oWbM2S_cyc <= rCycStb;
oWbM2S_stb <= rCycStb;
oWbM2S_we <= '0';
oWbM2S_addr <= STD_LOGIC_VECTOR(rWbAddr)&B"00";
oWbM2S_sel <= X"F";
oWbM2S_cti <= rWbCti;
-- synthesis translate_on
 
PROCESS (iWbClk, iRst_n) IS
VARIABLE vCnt : UNSIGNED(15 DOWNTO 2);
VARIABLE vTemp16 : UNSIGNED(15 DOWNTO 0);
BEGIN
IF iRst_n = '0' THEN
rTransDone <= FALSE;
rCnt64 <= (OTHERS => '0');
rCnt <= (OTHERS => '0');
rState <= IDLE;
rCycStb <= '0';
rWbCti <= CLASSIC;
rWbAddr <= (OTHERS => '0');
rLastOne <= FALSE;
rFirstNibbleBytes <= 1;
rLastNibbleBytes <= 1;
ELSIF rising_edge(iWbClk) THEN
rTransDone <= FALSE;
IF cWbAck = '1' THEN
rWbAddr <= rWbAddr + 1;
rCnt <= rCnt - 1;
rCnt64 <= rCnt64 - 1;
END IF;
CASE rState IS
WHEN IDLE =>
rWbAddr <= UNSIGNED(rDescDO(31 DOWNTO 2));
-- 注意，这里rFirstNibbleBytes直接记录的首次有多少
-- 有效字节数，在大端模式下，rDescDO(1 DOWNTO 0)=B"00"表示
-- 4字节有效，rDescDO(1 DOWNTO 0)=B"10"表示高16bit有效
rFirstNibbleBytes <= 4 - to_integer(UNSIGNED(rDescDO(1 DOWNTO 0)));
 
-- descriptors 给出的目标数据的起始地址很可能不是4字节对齐的
vTemp16 := UNSIGNED(rDescriptorLen) - 4 + to_integer(UNSIGNED(rDescDO(1 DOWNTO 0)));
IF vTemp16(1 DOWNTO 0) /= B"00" THEN
vCnt := vTemp16(15 DOWNTO 2)+1;
-- rLastNibbleBytes给出的是当前descriptor最后一次32位读取中，有效的
-- 字节数
rLastNibbleBytes <= to_integer(vTemp16(1 DOWNTO 0));
ELSE
vCnt := vTemp16(15 DOWNTO 2);
rLastNibbleBytes <= 4;
END IF;
--IF rFrameLen(1 DOWNTO 0) /= B"00" THEN
-- vCnt := UNSIGNED(rFrameLen(15 DOWNTO 2));
--ELSE
-- vCnt := UNSIGNED(rFrameLen(15 DOWNTO 2)) - 1;
--END IF;
rCnt <= vCnt;
rCnt64 <= (OTHERS => '1');
IF rStartTran THEN
rLastOne <= FALSE; -- last in a frame
IF vCnt = 0 THEN
rState <= WAIT1;
rWbCti <= CLASSIC;
rLastOne <= TRUE;
ELSE
rState <= REFILL;
rWbCti <= INCR;
END IF;
rCycStb <= '1';
END IF;
---------------------------------------------------------------------
WHEN REFILL =>
IF cWbAck = '1' THEN
IF rCnt = X"000"&B"01" THEN
rWbCti <= LAST;
rState <= WAIT1;
rLastOne <= TRUE;
ELSIF rCnt64 = 1 THEN
rWbCti <= LAST;
rState <= WASTE;
END IF;
END IF;
---------------------------------------------------------------------
WHEN WAIT1 =>
IF cWbAck = '1' THEN
rState <= IDLE;
rCycStb <= '0';
rTransDone <= TRUE;
END IF;
---------------------------------------------------------------------
WHEN WASTE =>
rCnt64 <= rCnt64 + 1;
IF rCnt64 = 16 THEN
rCycStb <= '1';
IF rCnt = 0 THEN
rState <= WAIT1;
rWbCti <= CLASSIC;
rLastOne <= TRUE;
ELSE
rState <= REFILL;
rWbCti <= INCR;
END IF;
END IF;
IF cWbAck = '1' THEN
rCycStb <= '0';
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK blk1;
 
blkDataMix : BLOCK IS
TYPE state_t IS (ST1, ST2);
SIGNAL rState : state_t;
-- 当前wishbone读取的，有效字节数
SIGNAL rValidBytes : NATURAL RANGE 1 TO 4;
TYPE array8x8_t IS ARRAY (8 DOWNTO 1) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rArray8x8_2 : array8x8_t;
SIGNAL rArray8x8_1 : array8x8_t; -- 实际上只使用了4 DOWNTO 1
SIGNAL rReveivedBytes : NATURAL RANGE 0 TO 8;
SIGNAL rStateLittle : BOOLEAN;
SIGNAL rLastOneD1 : BOOLEAN;
BEGIN -- BLOCK blkDataMix
 
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rState <= ST1;
ELSIF rising_edge(iWbClk) THEN
CASE rState IS
-- 这是每一个descriptor的第一个读取的32位数，当然，不一定全部有效
-- rFirstNibbleBytes 会告诉我们到底有几个字节有效
WHEN ST1 =>
IF cWbAck = '1' THEN
rValidBytes <= rFirstNibbleBytes;
rArray8x8_1(1) <= cWbData(7 DOWNTO 0);
rArray8x8_1(2) <= cWbData(15 DOWNTO 8);
rArray8x8_1(3) <= cWbData(23 DOWNTO 16);
rArray8x8_1(4) <= cWbData(31 DOWNTO 24);
-- 当前descriptor只需要读一次
IF rLastOne THEN -- 在大端下，
NULL;
--rArray8x8_1(1) <= cWbData(7 DOWNTO 0);
--rArray8x8_1(2) <= cWbData(15 DOWNTO 8);
--rArray8x8_1(3) <= cWbData(23 DOWNTO 16);
--rArray8x8_1(4) <= cWbData(31 DOWNTO 24);
ELSE
rState <= ST2;
--rArray8x8_1(1) <= cWbData(7 DOWNTO 0);
--rArray8x8_1(2) <= cWbData(15 DOWNTO 8);
--rArray8x8_1(3) <= cWbData(23 DOWNTO 16);
--rArray8x8_1(4) <= cWbData(31 DOWNTO 24);
END IF;
END IF;
---------------------------------------------------------------------
WHEN ST2 =>
IF cWbAck = '1' THEN
IF rLastOne THEN
rValidBytes <= rLastNibbleBytes;
rState <= ST1;
-- 大端下，残留的最后一个是靠齐。。。
CASE rLastNibbleBytes IS
WHEN 1 =>
rArray8x8_1(1) <= cWbData(31 DOWNTO 24);
WHEN 2 =>
rArray8x8_1(2) <= cWbData(31 DOWNTO 24);
rArray8x8_1(1) <= cWbData(23 DOWNTO 16);
WHEN 3 =>
rArray8x8_1(3) <= cWbData(31 DOWNTO 24);
rArray8x8_1(2) <= cWbData(23 DOWNTO 16);
rArray8x8_1(1) <= cWbData(15 DOWNTO 8);
WHEN 4 =>
rArray8x8_1(4) <= cWbData(31 DOWNTO 24);
rArray8x8_1(3) <= cWbData(23 DOWNTO 16);
rArray8x8_1(2) <= cWbData(15 DOWNTO 8);
rArray8x8_1(1) <= cWbData(7 DOWNTO 0);
WHEN OTHERS => NULL;
END CASE;
ELSE
rValidBytes <= 4;
rArray8x8_1(1) <= cWbData(7 DOWNTO 0);
rArray8x8_1(2) <= cWbData(15 DOWNTO 8);
rArray8x8_1(3) <= cWbData(23 DOWNTO 16);
rArray8x8_1(4) <= cWbData(31 DOWNTO 24);
END IF;
END IF;
---------------------------------------------------------------------
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
 
PROCESS (iWbClk) IS
BEGIN
IF rising_edge(iWbClk) THEN
rLastOneD1 <= rLastOne;
END IF;
END PROCESS;
PROCESS (iWbClk, iRst_n) IS
VARIABLE vReceivedBytes : NATURAL RANGE 1 TO 8;
VARIABLE vArray8x8 : array8x8_t;
BEGIN
IF iRst_n = '0' THEN
rDMADatV <= '0';
rDMADat <= (OTHERS => '0');
rReveivedBytes <= 0;
rRellyLastOne <= FALSE;
rStateLittle <= FALSE;
ELSIF rising_edge(iWbClk) THEN
rDMADatV <= '0';
rRellyLastOne <= FALSE;
CASE rStateLittle IS
WHEN FALSE =>
IF rWbAck = '1' THEN
vArray8x8(rValidBytes DOWNTO 1) := rArray8x8_1(rValidBytes DOWNTO 1);
vArray8x8(8 DOWNTO rValidBytes+1) := rArray8x8_2(8-rValidBytes DOWNTO 1);
--rArray8x8_2(rValidBytes DOWNTO 1) <= rArray8x8_1(rValidBytes DOWNTO 1);
--rArray8x8_2(8 DOWNTO rValidBytes+1) <= rArray8x8_2(8-rValidBytes DOWNTO 1);
rArray8x8_2 <= vArray8x8;
vReceivedBytes := rReveivedBytes + rValidBytes;
IF rLastOneD1 AND rLastDescriptor = '1' THEN
IF vReceivedBytes > 4 THEN
rDMADatV <= '1';
rStateLittle <= TRUE;
rReveivedBytes <= vReceivedBytes - 4;
rDMADat(31 DOWNTO 24) <= vArray8x8(vReceivedBytes);
rDMADat(23 DOWNTO 16) <= vArray8x8(vReceivedBytes-1);
rDMADat(15 DOWNTO 8) <= vArray8x8(vReceivedBytes-2);
rDMADat(7 DOWNTO 0) <= vArray8x8(vReceivedBytes-3);
ELSE
rDMADatV <= '1';
rRellyLastOne <= TRUE;
rReveivedBytes <= 0;
CASE vReceivedBytes IS
WHEN 1 =>
rDMADat(31 DOWNTO 24) <= vArray8x8(1);
rDMADat(23 DOWNTO 0) <= (OTHERS => '0');
WHEN 2 =>
rDMADat(31 DOWNTO 24) <= vArray8x8(2);
rDMADat(23 DOWNTO 16) <= vArray8x8(1);
rDMADat(15 DOWNTO 0) <= (OTHERS => '0');
WHEN 3 =>
rDMADat(31 DOWNTO 24) <= vArray8x8(3);
rDMADat(23 DOWNTO 16) <= vArray8x8(2);
rDMADat(15 DOWNTO 8) <= vArray8x8(1);
rDMADat(7 DOWNTO 0) <= (OTHERS => '0');
WHEN 4 =>
rDMADat(31 DOWNTO 24) <= vArray8x8(4);
rDMADat(23 DOWNTO 16) <= vArray8x8(3);
rDMADat(15 DOWNTO 8) <= vArray8x8(2);
rDMADat(7 DOWNTO 0) <= vArray8x8(1);
WHEN OTHERS => NULL;
END CASE;
END IF;
ELSE -- NOT really last one
IF vReceivedBytes >= 4 THEN
rDMADatV <= '1';
rReveivedBytes <= vReceivedBytes - 4;
rDMADat(31 DOWNTO 24) <= vArray8x8(vReceivedBytes);
rDMADat(23 DOWNTO 16) <= vArray8x8(vReceivedBytes-1);
rDMADat(15 DOWNTO 8) <= vArray8x8(vReceivedBytes-2);
rDMADat(7 DOWNTO 0) <= vArray8x8(vReceivedBytes-3);
ELSE
rReveivedBytes <= vReceivedBytes;
END IF;
END IF;
END IF;
---------------------------------------------------------------------
WHEN TRUE =>
rStateLittle <= FALSE;
rRellyLastOne <= TRUE;
rDMADatV <= '1';
rReveivedBytes <= 0;
CASE rReveivedBytes IS
WHEN 1 =>
rDMADat(31 DOWNTO 24) <= rArray8x8_2(1);
rDMADat(23 DOWNTO 0) <= (OTHERS => '0');
WHEN 2 =>
rDMADat(31 DOWNTO 24) <= rArray8x8_2(2);
rDMADat(23 DOWNTO 16) <= rArray8x8_2(1);
rDMADat(15 DOWNTO 0) <= (OTHERS => '0');
WHEN 3 =>
rDMADat(31 DOWNTO 24) <= rArray8x8_2(3);
rDMADat(23 DOWNTO 16) <= rArray8x8_2(2);
rDMADat(15 DOWNTO 8) <= rArray8x8_2(1);
rDMADat(7 DOWNTO 0) <= (OTHERS => '0');
-- 应该不会到4这个分支的！！
WHEN 4 =>
rDMADat(31 DOWNTO 24) <= rArray8x8_2(4);
rDMADat(23 DOWNTO 16) <= rArray8x8_2(3);
rDMADat(15 DOWNTO 8) <= rArray8x8_2(2);
rDMADat(7 DOWNTO 0) <= rArray8x8_2(1);
WHEN OTHERS => NULL;
END CASE;
---------------------------------------------------------------------
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK blkDataMix;
 
END ARCHITECTURE rtl;
/trunk/rtl/rgmii/rgmii_top.vhd
0,0 → 1,343
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_top.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-12-02
-- Last update: 2013-05-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-12-02 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.de2_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_top IS
GENERIC(
MY_MAC : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"10BF487A0FED";
IN_SIMULATION : BOOLEAN := FALSE);
PORT (
iWbClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
 
---------------------------------------------------------------------------
-- wishbone slave
---------------------------------------------------------------------------
iWbM2S : IN wbMasterToSlaveIF_t;
oWbS2M : OUT wbSlaveToMasterIF_t;
-- synthesis translate_off
iWbM2S_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
iWbM2S_dat : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
iWbM2S_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
iWbM2S_stb : IN STD_LOGIC := '0';
iWbM2S_cyc : IN STD_LOGIC := '0';
iWbM2S_we : IN STD_LOGIC := '0';
oWbS2M_dat : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWbS2M_ack : OUT STD_LOGIC;
-- synthesis translate_ON
 
---------------------------------------------------------------------------
-- wishbone master for read
---------------------------------------------------------------------------
oWb0M2S : OUT wbMasterToSlaveIF_t;
iWb0S2M : IN wbSlaveToMasterIF_t;
-- synthesis translate_off
oWb0M2S_dat : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWb0M2S_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWb0M2S_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
oWb0M2S_cyc : OUT STD_LOGIC;
oWb0M2S_stb : OUT STD_LOGIC;
oWb0M2S_we : OUT STD_LOGIC;
oWb0M2S_cti : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
oWb0M2S_bte : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
iWb0S2M_ack : IN STD_LOGIC := '0';
-- synthesis translate_on
 
---------------------------------------------------------------------------
-- wishbone master for write
---------------------------------------------------------------------------
oWb1M2S : OUT wbMasterToSlaveIF_t;
iWb1S2M : IN wbSlaveToMasterIF_t;
-- synthesis translate_off
oWb1M2S_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oWb1M2S_sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
oWb1M2S_cyc : OUT STD_LOGIC;
oWb1M2S_stb : OUT STD_LOGIC;
oWb1M2S_we : OUT STD_LOGIC;
oWb1M2S_cti : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
oWb1M2S_bte : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
iWb1S2M_ack : IN STD_LOGIC := '0';
iWb1S2M_dat : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- synthesis translate_on
 
---------------------------------------------------------------------------
-- rgmii for enet0
---------------------------------------------------------------------------
ENET1_MDC : OUT STD_LOGIC;
ENET1_MDIO : INOUT STD_LOGIC;
ENET1_RX_CLK : IN STD_LOGIC;
ENET1_RX_DV : IN STD_LOGIC;
ENET1_RX_DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ENET1_GTX_CLK : OUT STD_LOGIC;
ENET1_TX_EN : OUT STD_LOGIC;
ENET1_TX_DATA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
 
oTxInt : OUT STD_LOGIC;
oRxInt : OUT STD_LOGIC
);
 
END ENTITY rgmii_top;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_top IS
 
SIGNAL mdHz, mdi0, mdi1, mdi, mdc : STD_LOGIC;
SIGNAL phyAddr, regAddr : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL noPre : STD_LOGIC;
SIGNAL rdOp, wrOp : STD_LOGIC;
SIGNAL clkDiv : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL clrRdOp, clrWrOp : STD_LOGIC;
SIGNAL data2PHY, dataFromPhy : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL dataFromPhyValid : STD_LOGIC;
SIGNAL mdioBusy : STD_LOGIC;
 
SIGNAL cEnetTxData : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cEnetTxEn : STD_LOGIC;
SIGNAL cEnetTxErr : STD_LOGIC;
SIGNAL cEnetRxData : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cEnetRxDV : STD_LOGIC;
SIGNAL cEnetRxErr : STD_LOGIC;
SIGNAL cEthClk : STD_LOGIC;
 
SIGNAL cTxEn : STD_LOGIC;
SIGNAL cTxIntEn : STD_LOGIC;
SIGNAL cTxIntClr : STD_LOGIC;
SIGNAL cTxIntInfo : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cTxDescDataO : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cTxDescDataI : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cTxDescWr : STD_LOGIC;
SIGNAL cTxDescAddr : STD_LOGIC_VECTOR(8 DOWNTO 2);
 
SIGNAL cRxEn : STD_LOGIC;
SIGNAL cRxDescAddr : STD_LOGIC_VECTOR(8 DOWNTO 2);
SIGNAL cRxDescWr : STD_LOGIC;
SIGNAL cRxDescDataO : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cRxDescDataI : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cRxIntClr : STD_LOGIC;
SIGNAL cRxIntInfo : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cRxIntEn : STD_LOGIC;
SIGNAL cRxBufBegin : STD_LOGIC_VECTOR(31 DOWNTO 2);
SIGNAL cRxBufEnd : STD_LOGIC_VECTOR(31 DOWNTO 2);
 
SIGNAL cCheckSumIPCheck : STD_LOGIC;
SIGNAL cCheckSumTCPCheck : STD_LOGIC;
SIGNAL cCheckSumUDPCheck : STD_LOGIC;
SIGNAL cCheckSumICMPCheck : STD_LOGIC;
 
SIGNAL cCheckSumIPGen : STD_LOGIC;
SIGNAL cCheckSumTCPGen : STD_LOGIC;
SIGNAL cCheckSumUDPGen : STD_LOGIC;
SIGNAL cCheckSumICMPGen : STD_LOGIC;
BEGIN -- ARCHITECTURE rtl
 
--ENET0_MDC <= mdc;
ENET1_MDC <= mdc;
--ENET0_MDIO <= 'Z' WHEN mdHz = '1' ELSE '0';
ENET1_MDIO <= 'Z' WHEN mdHz = '1' ELSE '0';
--mdi0 <= ENET0_MDIO;
mdi1 <= ENET1_MDIO;
mdi0 <= '1';
mdi <= mdi0 AND mdi1;
rgmii_mdio_1 : ENTITY work.rgmii_mdio
PORT MAP (
iWbClk => iWbClk,
iRst_n => iRst_n,
iPHYAddr => phyAddr,
iRegAddr => regAddr,
iNoPre => noPre,
iData2PHY => data2PHY,
--iClkDiv => clkDiv,
iClkDiv => X"FF",
iRdOp => rdOp,
iWrOp => wrOp,
oDataFromPHY => dataFromPhy,
oDataFromPHYValid => dataFromPhyValid,
oClrRdOp => clrRdOp,
oClrWrOp => clrWrOp,
oMDIOBusy => mdioBusy,
iMDI => mdi,
oMDHz => mdHz,
oMDC => mdc);
 
rgmii_wbs_1 : ENTITY work.rgmii_wbs
GENERIC MAP (
IN_SIMULATION => IN_SIMULATION)
PORT MAP (
iWbClk => iWbClk,
iRst_n => iRst_n,
iWbM2S => iWbM2S,
oWbS2M => oWbS2M,
 
-- synthesis translate_off
iWbM2S_addr => iWbM2S_addr,
iWbM2S_dat => iWbM2S_dat,
iWbM2S_sel => iWbM2S_sel,
iWbM2S_stb => iWbM2S_stb,
iWbM2S_cyc => iWbM2S_cyc,
iWbM2S_we => iWbM2S_we,
oWbS2M_dat => oWbS2M_dat,
oWbS2M_ack => oWbS2M_ack,
-- synthesis translate_on
 
oTxEn => cTxEn,
oTxIntEn => cTxIntEn,
oTxIntClr => cTxIntClr,
iTxIntInfo => cTxIntInfo,
oTxDescData => cTxDescDataO,
iTxDescData => cTxDescDataI,
oTxDescWr => cTxDescWr,
oTxDescAddr => cTxDescAddr,
 
oCheckSumIPGen => cCheckSumIPGen,
oCheckSumTCPGen => cCheckSumTCPGen,
oCheckSumUDPGen => cCheckSumUDPGen,
oCheckSumICMPGen => cCheckSumICMPGen,
 
oRxEn => cRxEn,
oRxDescAddr => cRxDescAddr,
oRxDescWr => cRxDescWr,
oRxDescData => cRxDescDataO,
iRxDescData => cRxDescDataI,
oRxIntClr => cRxIntClr,
iRxIntInfo => cRxIntInfo,
oRxIntEn => cRxIntEn,
oRxBufBegin => cRxBufBegin,
oRxBufEnd => cRxBufEnd,
 
oCheckSumIPCheck => cCheckSumIPCheck,
oCheckSumTCPCheck => cCheckSumTCPCheck,
oCheckSumUDPCheck => cCheckSumUDPCheck,
oCheckSumICMPCheck => cCheckSumICMPCheck,
 
oPHYAddr => phyAddr,
oRegAddr => regAddr,
oRdOp => rdOp,
oWrOp => wrOp,
oNoPre => noPre,
oClkDiv => clkDiv,
iClrRdOp => clrRdOp,
iClrWrOp => clrWrOp,
oDataToPHY => data2PHY,
iDataFromPHY => dataFromPhy,
iDataFromPHYValid => dataFromPhyValid,
iMDIOBusy => mdioBusy);
 
rgmii_io_1 : ENTITY work.rgmii100_io
PORT MAP (
iRst_n => iRst_n,
TXC => ENET1_GTX_CLK,
TX_CTL => ENET1_TX_EN,
TD => ENET1_TX_DATA,
RXC => ENET1_RX_CLK,
RX_CTL => ENET1_RX_DV,
RD => ENET1_RX_DATA,
iTxData => cEnetTxData,
iTxEn => cEnetTxEn,
iTxErr => cEnetTxErr,
oRxData => cEnetRxData,
oRxDV => cEnetRxDV,
oRxErr => cEnetRxErr,
oEthClk => cEthClk);
 
rgmii_rx_top_1 : ENTITY work.rgmii_rx_top
GENERIC MAP (
MY_MAC => MY_MAC,
IN_SIMULATION => IN_SIMULATION)
PORT MAP (
iWbClk => iWbClk,
iEthClk => cEthClk,
iRst_n => iRst_n,
iWbS2M => iWb0S2M,
oWbM2S => oWb0M2S,
-- synthesis translate_off
oWbM2S_dat => oWb0M2S_dat,
oWbM2S_addr => oWb0M2S_addr,
oWbM2S_sel => oWb0M2S_sel,
oWbM2S_cyc => oWb0M2S_cyc,
oWbM2S_stb => oWb0M2S_stb,
oWbM2S_we => oWb0M2S_we,
oWbM2S_cti => oWb0M2S_cti,
oWbM2S_bte => oWb0M2S_bte,
iWbS2M_ack => iWb0S2M_ack,
-- synthesis translate_on
iEnetRxData => cEnetRxData,
iEnetRxDv => cEnetRxDv,
iEnetRxErr => cEnetRxErr,
iWbRxEn => cRxEn,
iWbRxIntEn => cRxIntEn,
iWbRxIntClr => cRxIntClr,
oWbRxIntInfo => cRxIntInfo,
iWbRxDescData => cRxDescDataO,
oWbRxDescData => cRxDescDataI,
iWbRxDescWr => cRxDescWr,
iWbRxDescAddr => cRxDescAddr,
iRxBufBegin => cRxBufBegin,
iRxBufEnd => cRxBufEnd,
 
iCheckSumIPCheck => cCheckSumIPCheck,
iCheckSumTCPCheck => cCheckSumTCPCheck,
iCheckSumUDPCheck => cCheckSumUDPCheck,
iCheckSumICMPCheck => cCheckSumICMPCheck,
 
oWbRxInt => oRxInt);
 
rgmii_tx_top_1 : ENTITY work.rgmii_tx_top
GENERIC MAP (
IN_SIMULATION => IN_SIMULATION)
PORT MAP (
iWbClk => iWbClk,
iEthClk => cEthClk,
iRst_n => iRst_n,
iWbS2M => iWb1S2M,
oWbM2S => oWb1M2S,
-- synthesis translate_off
oWbM2S_addr => oWb1M2S_addr,
oWbM2S_sel => oWb1M2S_sel,
oWbM2S_cyc => oWb1M2S_cyc,
oWbM2S_stb => oWb1M2S_stb,
oWbM2S_we => oWb1M2S_we,
oWbM2S_cti => oWb1M2S_cti,
oWbM2S_bte => oWb1M2S_bte,
iWbS2M_ack => iWb1S2M_ack,
iWbS2M_dat => iWb1S2M_dat,
-- synthesis translate_on
oEnetTxData => cEnetTxData,
oEnetTxEn => cEnetTxEn,
oEnetTxErr => cEnetTxErr,
iWbTxEn => cTxEn,
iWbTxIntEn => cTxIntEn,
iWbTxIntClr => cTxIntClr,
oWbTxIntInfo => cTxIntInfo,
iWbTxDescData => cTxDescDataO,
oWbTxDescData => cTxDescDataI,
iWbTxDescWr => cTxDescWr,
iWbTxDescAddr => cTxDescAddr,
 
iCheckSumIPGen => cCheckSumIPGen,
iCheckSumTCPGen => cCheckSumTCPGen,
iCheckSumUDPGen => cCheckSumUDPGen,
iCheckSumICMPGen => cCheckSumICMPGen,
oWbTxInt => oTxInt);
 
END ARCHITECTURE rtl;

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