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/boards/GECKO3main/data/LICENSE

boards/GECKO3main/data/LICENSE Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: boards/GECKO3main/data/GECKO3main_v2_2_0.xbd =================================================================== --- boards/GECKO3main/data/GECKO3main_v2_2_0.xbd (nonexistent) +++ boards/GECKO3main/data/GECKO3main_v2_2_0.xbd (revision 5) @@ -0,0 +1,899 @@ +# -------------------------------------------------------------------------------- +# GECKO3 SoC Co-Design Environment: +# GECKO3 Microblaze +# ___ ___ _ _ +# ( _`\ ( __)( ) ( ) +# | (_) )| ( | |_| | Bern University of Applied Sciences +# | _ <'| _) | _ | School of Engineering and +# | (_) )| | | | | | Information Technology +# (____/'(_) (_) (_) +# +# +# Author: Christoph Zimmermann +# Date of creation: 22. September 2008 +# Description: +# +# +# Tool versions: Xilinx EDK 8.2i and higher +# +# License: +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published +# by the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Lesser General Public License for more details. +# You should have received a copy of the GNU Lesser General Public License +# along with this program. If not, see . +# +# History: +# 30. september 2008 +# working with edk 9.2i without ddr ram +# testing in 10.1, 9.1 and 8.2 missing +# +# 1. october 2008 +# testing with edk 9.1. 9.1 still uses the ddr ip-core and not the new mpmc +# as in 9.2. looks fine. needed to change the iostandard of the ddr feedback +# to lvcmos33. +# single ddr ram works +# +# 2. october 2008 +# added the second ddr ram configurations using both ram chips with a 32 bit +# width databus. the ddr blocks use the "exclusive" attribute so a user can only +# select one of the two configurations. +# still a bug somwhere +# -------------------------------------------------------------------------------- + +ATTRIBUTE VENDOR = MicroLab +ATTRIBUTE SPEC_URL = www.microlab.ch +ATTRIBUTE CONTACT_INFO_URL=http://labs.ti.bfh.ch/gecko/ +ATTRIBUTE NAME = GECKO3main Board + + +ATTRIBUTE REVISION = 1 +ATTRIBUTE DESC = GECKO3main Board Revision 1 +ATTRIBUTE LONG_DESC = 'GECKO3main Board utilizes Xilinx Spartan-3 XC3S4000-4FG679 device. The board includes one RS232 serial ports, 4 DIP switches, 4 push buttons (one for Reset), 4 Bi-Color LEDs, 10/100 Ethernet port, 32 MByte of parallel NOR flash and 128 MByte DDR SDRAM, USB 2.0 High Speed Interface for FPGA configuration and data transfer.' + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_CLOCK_V1 + ATTRIBUTE INSTANCE =sysclk + PARAMETER CLK_FREQ =50000000, IO_IS=clk_freq, RANGE=(50000000) # 50 Mhz + PORT SYSCLK = CONN_CLK, IO_IS=ext_clk +END + + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_CLOCK_V1 + ATTRIBUTE INSTANCE = clk_ext0 + PARAMETER CLK_FREQ =50000000, IO_IS=clk_freq + PORT CLK_EXT0 = CONN_OSC_EXT0, IO_IS=ext_clk +END + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_CLOCK_V1 + ATTRIBUTE INSTANCE = clk_ext1 + PARAMETER CLK_FREQ =50000000, IO_IS=clk_freq + PORT CLK_EXT1 = CONN_OSC_EXT1, IO_IS=ext_clk +END + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_RESET_V1 + ATTRIBUTE INSTANCE =rst_0 + PARAMETER RST_POLARITY =0, IO_IS=polarity, VALUE_NOTE=Active Low + # push button 1 is dedicated to system reset. + PORT RESET = CONN_RESET, IO_IS=ext_rst +END + +# Uses Micron device MT46V32M16-5B +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_DDR_V1 + ATTRIBUTE INSTANCE = DDR_SDRAM_64Mx16 + ATTRIBUTE EXCLUSIVE = DDR_MEMORY + ATTRIBUTE ALERT = 'DDR device on this board requires minimum clock frequency of 66Mhz to operate properly.' + PARAMETER C_DDR_ASYNC_SUPPORT=1, IO_IS=C_DDR_ASYNC_SUPPORT + PARAMETER C_INCLUDE_BURST_SUPPORT=1, IO_IS=C_INCLUDE_BURST_SUPPORT + PARAMETER C_REG_DIMM=0, IO_IS=C_REG_DIMM + PARAMETER C_EXTRA_TSU=0, IO_IS=C_EXTRA_TSU + PARAMETER C_NUM_BANKS_MEM=1, IO_IS=C_NUM_BANKS_MEM + PARAMETER C_NUM_CLK_PAIRS=1, IO_IS=C_NUM_CLK_PAIRS + PARAMETER C_DDR_TMRD=15000, IO_IS=C_DDR_TMRD + PARAMETER C_DDR_TWR=15000, IO_IS=C_DDR_TWR + PARAMETER C_DDR_TWTR=1, IO_IS=C_DDR_TWTR + PARAMETER C_DDR_TRAS=40000, IO_IS=C_DDR_TRAS + PARAMETER C_DDR_TRC=65000, IO_IS=C_DDR_TRC + PARAMETER C_DDR_TRFC=75000, IO_IS=C_DDR_TRFC + PARAMETER C_DDR_TRCD=20000, IO_IS=C_DDR_TRCD + PARAMETER C_DDR_TRRD=15000, IO_IS=C_DDR_TRRD + PARAMETER C_DDR_TREFC=70000000, IO_IS=C_DDR_TREFC + PARAMETER C_DDR_TREFI=7800000, IO_IS=C_DDR_TREFI + PARAMETER C_DDR_TRP=20000, IO_IS=C_DDR_TRP + PARAMETER C_DDR_CAS_LAT=3, IO_IS=C_DDR_CAS_LAT + PARAMETER C_DDR_DWIDTH=16, IO_IS=C_DDR_DWIDTH + PARAMETER C_DDR_AWIDTH=14, IO_IS=C_DDR_AWIDTH + PARAMETER C_DDR_COL_AWIDTH=10, IO_IS=C_DDR_COL_AWIDTH + PARAMETER C_DDR_BANK_AWIDTH=2, IO_IS=C_DDR_BANK_AWIDTH + PARAMETER C_MCH0_ACCESSBUF_DEPTH = 16, IO_IS=C_MCH0_ACCESSBUF_DEPTH + PARAMETER C_MCH0_RDDATABUF_DEPTH = 0, IO_IS=C_MCH0_RDDATABUF_DEPTH + PARAMETER C_XCL0_LINESIZE = 4, IO_IS=C_XCL0_LINESIZE + PARAMETER C_XCL0_WRITEXFER = 0, IO_IS=C_XCL0_WRITEXFER + PARAMETER C_MCH1_ACCESSBUF_DEPTH = 16, IO_IS=C_MCH1_ACCESSBUF_DEPTH + PARAMETER C_MCH1_RDDATABUF_DEPTH = 0, IO_IS=C_MCH1_RDDATABUF_DEPTH + PARAMETER C_XCL1_LINESIZE = 4, IO_IS=C_XCL1_LINESIZE + PARAMETER C_XCL1_WRITEXFER = 1, IO_IS=C_XCL1_WRITEXFER + PARAMETER C_MEM0_BASEADDR=0x00000000, IO_IS=C_BASEADDR, SHORT_DESC=DDR_SDRAM + PARAMETER C_MEM0_HIGHADDR=0x03ffffff, IO_IS=C_HIGHADDR + + PORT DDR_CLK = ddr_clk, IO_IS = ddr_clk_out + PORT DDR_CLKn = ddr_clk_n, IO_IS = ddr_clk_out_n + PORT DDR_CLK_FB = ddr_clk_fb, IO_IS=feedback_clock, FEEDBACK_PHASE=0 + + PORT DDR_A0 = ddr_addr_0_, IO_IS = address[13] + PORT DDR_A1 = ddr_addr_1_, IO_IS = address[12] + PORT DDR_A2 = ddr_addr_2_, IO_IS = address[11] + PORT DDR_A3 = ddr_addr_3_, IO_IS = address[10] + PORT DDR_A4 = ddr_addr_4_, IO_IS = address[9] + PORT DDR_A5 = ddr_addr_5_, IO_IS = address[8] + PORT DDR_A6 = ddr_addr_6_, IO_IS = address[7] + PORT DDR_A7 = ddr_addr_7_, IO_IS = address[6] + PORT DDR_A8 = ddr_addr_8_, IO_IS = address[5] + PORT DDR_A9 = ddr_addr_9_, IO_IS = address[4] + PORT DDR_A10 = ddr_addr_10_, IO_IS = address[3] + PORT DDR_A11 = ddr_addr_11_, IO_IS = address[2] + PORT DDR_A12 = ddr_addr_12_, IO_IS = address[1] + PORT DDR_A13 = ddr_addr_13_, IO_IS = address[0] + + PORT DDR_BA0 = ddr_ba_0_, IO_IS = bank_addr[1] + PORT DDR_BA1 = ddr_ba_1_, IO_IS = bank_addr[0] + + PORT DDR_CASn = ddr_cas_n, IO_IS = col_addr_select + PORT DDR_CKE = ddr_cke, IO_IS = clk_enable + PORT DDR_CSn = ddr_cs_n, IO_IS = chip_select + PORT DDR_RASn = ddr_ras_n, IO_IS = row_addr_select + PORT DDR_WEn = ddr_we_n, IO_IS = write_enable + + # Point-to-point connections for data pins from FPGA to DDR SDRAM devices + PORT DDR_LDM = ddr_dm_0_, IO_IS = data_mask[1] + PORT DDR_UDM = ddr_dm_1_, IO_IS = data_mask[0] + + PORT DDR_LDQS = ddr_dqs_0_, IO_IS = data_strobe[1] + PORT DDR_UDQS = ddr_dqs_1_, IO_IS = data_strobe[0] + + PORT DDR_DQ0 = ddr_dq_0_, IO_IS = data[15] + PORT DDR_DQ1 = ddr_dq_1_, IO_IS = data[14] + PORT DDR_DQ2 = ddr_dq_2_, IO_IS = data[13] + PORT DDR_DQ3 = ddr_dq_3_, IO_IS = data[12] + PORT DDR_DQ4 = ddr_dq_4_, IO_IS = data[11] + PORT DDR_DQ5 = ddr_dq_5_, IO_IS = data[10] + PORT DDR_DQ6 = ddr_dq_6_, IO_IS = data[9] + PORT DDR_DQ7 = ddr_dq_7_, IO_IS = data[8] + PORT DDR_DQ8 = ddr_dq_8_, IO_IS = data[7] + PORT DDR_DQ9 = ddr_dq_9_, IO_IS = data[6] + PORT DDR_DQ10 = ddr_dq_10_, IO_IS = data[5] + PORT DDR_DQ11 = ddr_dq_11_, IO_IS = data[4] + PORT DDR_DQ12 = ddr_dq_12_, IO_IS = data[3] + PORT DDR_DQ13 = ddr_dq_13_, IO_IS = data[2] + PORT DDR_DQ14 = ddr_dq_14_, IO_IS = data[1] + PORT DDR_DQ15 = ddr_dq_15_, IO_IS = data[0] + +END + +# Uses two Micron device MT46V32M16-5B +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_DDR_V1 + ATTRIBUTE INSTANCE = DDR_SDRAM_128Mx32 + ATTRIBUTE EXCLUSIVE = DDR_MEMORY + ATTRIBUTE ALERT = 'DDR device on this board requires minimum clock frequency of 66Mhz to operate properly.' + PARAMETER C_DDR_ASYNC_SUPPORT=1, IO_IS=C_DDR_ASYNC_SUPPORT + PARAMETER C_INCLUDE_BURST_SUPPORT=1, IO_IS=C_INCLUDE_BURST_SUPPORT + PARAMETER C_REG_DIMM=0, IO_IS=C_REG_DIMM + PARAMETER C_EXTRA_TSU=0, IO_IS=C_EXTRA_TSU + PARAMETER C_NUM_BANKS_MEM=1, IO_IS=C_NUM_BANKS_MEM + PARAMETER C_NUM_CLK_PAIRS=2, IO_IS=C_NUM_CLK_PAIRS + PARAMETER C_DDR_TMRD=15000, IO_IS=C_DDR_TMRD + PARAMETER C_DDR_TWR=15000, IO_IS=C_DDR_TWR + PARAMETER C_DDR_TWTR=1, IO_IS=C_DDR_TWTR + PARAMETER C_DDR_TRAS=40000, IO_IS=C_DDR_TRAS + PARAMETER C_DDR_TRC=65000, IO_IS=C_DDR_TRC + PARAMETER C_DDR_TRFC=75000, IO_IS=C_DDR_TRFC + PARAMETER C_DDR_TRCD=20000, IO_IS=C_DDR_TRCD + PARAMETER C_DDR_TRRD=15000, IO_IS=C_DDR_TRRD + PARAMETER C_DDR_TREFC=70000000, IO_IS=C_DDR_TREFC + PARAMETER C_DDR_TREFI=7800000, IO_IS=C_DDR_TREFI + PARAMETER C_DDR_TRP=20000, IO_IS=C_DDR_TRP + PARAMETER C_DDR_CAS_LAT=3, IO_IS=C_DDR_CAS_LAT + PARAMETER C_DDR_DWIDTH=32, IO_IS=C_DDR_DWIDTH + PARAMETER C_DDR_AWIDTH=14, IO_IS=C_DDR_AWIDTH + PARAMETER C_DDR_COL_AWIDTH=10, IO_IS=C_DDR_COL_AWIDTH + PARAMETER C_DDR_BANK_AWIDTH=2, IO_IS=C_DDR_BANK_AWIDTH + PARAMETER C_MCH0_ACCESSBUF_DEPTH = 16, IO_IS=C_MCH0_ACCESSBUF_DEPTH + PARAMETER C_MCH0_RDDATABUF_DEPTH = 0, IO_IS=C_MCH0_RDDATABUF_DEPTH + PARAMETER C_XCL0_LINESIZE = 4, IO_IS=C_XCL0_LINESIZE + PARAMETER C_XCL0_WRITEXFER = 0, IO_IS=C_XCL0_WRITEXFER + PARAMETER C_MCH1_ACCESSBUF_DEPTH = 16, IO_IS=C_MCH1_ACCESSBUF_DEPTH + PARAMETER C_MCH1_RDDATABUF_DEPTH = 0, IO_IS=C_MCH1_RDDATABUF_DEPTH + PARAMETER C_XCL1_LINESIZE = 4, IO_IS=C_XCL1_LINESIZE + PARAMETER C_XCL1_WRITEXFER = 1, IO_IS=C_XCL1_WRITEXFER + PARAMETER C_MEM0_BASEADDR=0x00000000, IO_IS=C_BASEADDR, SHORT_DESC=DDR_SDRAM + PARAMETER C_MEM0_HIGHADDR=0x07ffffff, IO_IS=C_HIGHADDR + + PORT DDR32a_CLK = ddr32a_clk, IO_IS = ddr_clk_out[0] + PORT DDR32a_CLKn = ddr32a_clk_n, IO_IS = ddr_clk_out_n[0] + PORT DDR32b_CLK = ddr32b_clk, IO_IS = ddr_clk_out[1] + PORT DDR32b_CLKn = ddr32b_clk_n, IO_IS = ddr_clk_out_n[1] + PORT DDR32_CLK_FB= ddr32_clk_fb, IO_IS = feedback_clock, FEEDBACK_PHASE=0 + + PORT DDR32_CASn = ddr32_cas_n, IO_IS = col_addr_select + PORT DDR32_CKE = ddr32_cke, IO_IS = clk_enable + PORT DDR32_CSn = ddr32_cs_n, IO_IS = chip_select + PORT DDR32_RASn = ddr32_ras_n, IO_IS = row_addr_select + PORT DDR32_WEn = ddr32_we_n, IO_IS = write_enable + + PORT DDR32_A0 = ddr32_addr_0_, IO_IS = address[13] + PORT DDR32_A1 = ddr32_addr_1_, IO_IS = address[12] + PORT DDR32_A2 = ddr32_addr_2_, IO_IS = address[11] + PORT DDR32_A3 = ddr32_addr_3_, IO_IS = address[10] + PORT DDR32_A4 = ddr32_addr_4_, IO_IS = address[9] + PORT DDR32_A5 = ddr32_addr_5_, IO_IS = address[8] + PORT DDR32_A6 = ddr32_addr_6_, IO_IS = address[7] + PORT DDR32_A7 = ddr32_addr_7_, IO_IS = address[6] + PORT DDR32_A8 = ddr32_addr_8_, IO_IS = address[5] + PORT DDR32_A9 = ddr32_addr_9_, IO_IS = address[4] + PORT DDR32_A10 = ddr32_addr_10_, IO_IS = address[3] + PORT DDR32_A11 = ddr32_addr_11_, IO_IS = address[2] + PORT DDR32_A12 = ddr32_addr_12_, IO_IS = address[1] + PORT DDR32_A13 = ddr32_addr_13_, IO_IS = address[0] + + PORT DDR32_BA0 = ddr32_ba_0_, IO_IS = bank_addr[1] + PORT DDR32_BA1 = ddr32_ba_1_, IO_IS = bank_addr[0] + + # Point-to-point connections for data pins from FPGA to DDR SDRAM devices + PORT DDR32a_LDM = ddr32_dm_0_, IO_IS = data_mask[3] + PORT DDR32a_UDM = ddr32_dm_1_, IO_IS = data_mask[2] + PORT DDR32b_LDM = ddr32_dm_2_, IO_IS = data_mask[1] + PORT DDR32b_UDM = ddr32_dm_3_, IO_IS = data_mask[0] + + PORT DDR32a_LDQS = ddr32_dqs_0_, IO_IS = data_strobe[3] + PORT DDR32a_UDQS = ddr32_dqs_1_, IO_IS = data_strobe[2] + PORT DDR32b_LDQS = ddr32_dqs_2_, IO_IS = data_strobe[1] + PORT DDR32b_UDQS = ddr32_dqs_3_, IO_IS = data_strobe[0] + + PORT DDR32_DQ0 = ddr32_dq_0_, IO_IS = data[31] + PORT DDR32_DQ1 = ddr32_dq_1_, IO_IS = data[30] + PORT DDR32_DQ2 = ddr32_dq_2_, IO_IS = data[29] + PORT DDR32_DQ3 = ddr32_dq_3_, IO_IS = data[28] + PORT DDR32_DQ4 = ddr32_dq_4_, IO_IS = data[27] + PORT DDR32_DQ5 = ddr32_dq_5_, IO_IS = data[26] + PORT DDR32_DQ6 = ddr32_dq_6_, IO_IS = data[25] + PORT DDR32_DQ7 = ddr32_dq_7_, IO_IS = data[24] + PORT DDR32_DQ8 = ddr32_dq_8_, IO_IS = data[23] + PORT DDR32_DQ9 = ddr32_dq_9_, IO_IS = data[22] + PORT DDR32_DQ10 = ddr32_dq_10_, IO_IS = data[21] + PORT DDR32_DQ11 = ddr32_dq_11_, IO_IS = data[20] + PORT DDR32_DQ12 = ddr32_dq_12_, IO_IS = data[19] + PORT DDR32_DQ13 = ddr32_dq_13_, IO_IS = data[18] + PORT DDR32_DQ14 = ddr32_dq_14_, IO_IS = data[17] + PORT DDR32_DQ15 = ddr32_dq_15_, IO_IS = data[16] + PORT DDR32_DQ16 = ddr32_dq_16_, IO_IS = data[15] + PORT DDR32_DQ17 = ddr32_dq_17_, IO_IS = data[14] + PORT DDR32_DQ18 = ddr32_dq_18_, IO_IS = data[13] + PORT DDR32_DQ19 = ddr32_dq_19_, IO_IS = data[12] + PORT DDR32_DQ20 = ddr32_dq_20_, IO_IS = data[11] + PORT DDR32_DQ21 = ddr32_dq_21_, IO_IS = data[10] + PORT DDR32_DQ22 = ddr32_dq_22_, IO_IS = data[9] + PORT DDR32_DQ23 = ddr32_dq_23_, IO_IS = data[8] + PORT DDR32_DQ24 = ddr32_dq_24_, IO_IS = data[7] + PORT DDR32_DQ25 = ddr32_dq_25_, IO_IS = data[6] + PORT DDR32_DQ26 = ddr32_dq_26_, IO_IS = data[5] + PORT DDR32_DQ27 = ddr32_dq_27_, IO_IS = data[4] + PORT DDR32_DQ28 = ddr32_dq_28_, IO_IS = data[3] + PORT DDR32_DQ29 = ddr32_dq_29_, IO_IS = data[2] + PORT DDR32_DQ30 = ddr32_dq_30_, IO_IS = data[1] + PORT DDR32_DQ31 = ddr32_dq_31_, IO_IS = data[0] + +END + +BEGIN IO_ADAPTER + ATTRIBUTE CORENAME = util_vector_logic + ATTRIBUTE INSTANCE = DDR_SDRAM_128Mx32_splitA + PARAMETER C_OPERATION = or + PARAMETER C_SIZE = 21 + + PORT Op1[0] = ddr32_addr_0_ + PORT Op1[1] = ddr32_addr_1_ + PORT Op1[2] = ddr32_addr_2_ + PORT Op1[3] = ddr32_addr_3_ + PORT Op1[4] = ddr32_addr_4_ + PORT Op1[5] = ddr32_addr_5_ + PORT Op1[6] = ddr32_addr_6_ + PORT Op1[7] = ddr32_addr_7_ + PORT Op1[8] = ddr32_addr_8_ + PORT Op1[9] = ddr32_addr_9_ + PORT Op1[10] = ddr32_addr_10_ + PORT Op1[11] = ddr32_addr_11_ + PORT Op1[12] = ddr32_addr_12_ + PORT Op1[13] = ddr32_addr_13_ + PORT Op1[14] = ddr32_cas_n + PORT Op1[15] = ddr32_cke + PORT Op1[16] = ddr32_cs_n + PORT Op1[17] = ddr32_ras_n + PORT Op1[18] = ddr32_we_n + PORT Op1[19] = ddr32_ba_0_ + PORT Op1[20] = ddr32_ba_1_ + + PORT Op2 = net_gnd + + PORT Res[0] = ddr32a_addr_0_ + PORT Res[1] = ddr32a_addr_1_ + PORT Res[2] = ddr32a_addr_2_ + PORT Res[3] = ddr32a_addr_3_ + PORT Res[4] = ddr32a_addr_4_ + PORT Res[5] = ddr32a_addr_5_ + PORT Res[6] = ddr32a_addr_6_ + PORT Res[7] = ddr32a_addr_7_ + PORT Res[8] = ddr32a_addr_8_ + PORT Res[9] = ddr32a_addr_9_ + PORT Res[10] = ddr32a_addr_10_ + PORT Res[11] = ddr32a_addr_11_ + PORT Res[12] = ddr32a_addr_12_ + PORT Res[13] = ddr32a_addr_13_ + PORT Res[14] = ddr32a_cas_n + PORT Res[15] = ddr32a_cke + PORT Res[16] = ddr32a_cs_n + PORT Res[17] = ddr32a_ras_n + PORT Res[18] = ddr32a_we_n + PORT Res[19] = ddr32a_ba_0_ + PORT Res[20] = ddr32a_ba_1_ +END + +BEGIN IO_ADAPTER + ATTRIBUTE CORENAME = util_vector_logic + ATTRIBUTE INSTANCE = DDR_SDRAM_128Mx32_splitB + PARAMETER C_OPERATION = or + PARAMETER C_SIZE = 21 + + PORT Op1[0] = ddr32_addr_0_ + PORT Op1[1] = ddr32_addr_1_ + PORT Op1[2] = ddr32_addr_2_ + PORT Op1[3] = ddr32_addr_3_ + PORT Op1[4] = ddr32_addr_4_ + PORT Op1[5] = ddr32_addr_5_ + PORT Op1[6] = ddr32_addr_6_ + PORT Op1[7] = ddr32_addr_7_ + PORT Op1[8] = ddr32_addr_8_ + PORT Op1[9] = ddr32_addr_9_ + PORT Op1[10] = ddr32_addr_10_ + PORT Op1[11] = ddr32_addr_11_ + PORT Op1[12] = ddr32_addr_12_ + PORT Op1[13] = ddr32_addr_13_ + PORT Op1[14] = ddr32_cas_n + PORT Op1[15] = ddr32_cke + PORT Op1[16] = ddr32_cs_n + PORT Op1[17] = ddr32_ras_n + PORT Op1[18] = ddr32_we_n + PORT Op1[19] = ddr32_ba_0_ + PORT Op1[20] = ddr32_ba_1_ + + PORT Op2 = net_gnd + + PORT Res[0] = ddr32b_addr_0_ + PORT Res[1] = ddr32b_addr_1_ + PORT Res[2] = ddr32b_addr_2_ + PORT Res[3] = ddr32b_addr_3_ + PORT Res[4] = ddr32b_addr_4_ + PORT Res[5] = ddr32b_addr_5_ + PORT Res[6] = ddr32b_addr_6_ + PORT Res[7] = ddr32b_addr_7_ + PORT Res[8] = ddr32b_addr_8_ + PORT Res[9] = ddr32b_addr_9_ + PORT Res[10] = ddr32b_addr_10_ + PORT Res[11] = ddr32b_addr_11_ + PORT Res[12] = ddr32b_addr_12_ + PORT Res[13] = ddr32b_addr_13_ + PORT Res[14] = ddr32b_cas_n + PORT Res[15] = ddr32b_cke + PORT Res[16] = ddr32b_cs_n + PORT Res[17] = ddr32b_ras_n + PORT Res[18] = ddr32b_we_n + PORT Res[19] = ddr32b_ba_0_ + PORT Res[20] = ddr32b_ba_1_ +END + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_EMC_V1 + ATTRIBUTE INSTANCE = NOR_FLASH + ATTRIBUTE EXCLUSIVE = FLASH + PARAMETER C_NUM_BANKS_MEM = 1, IO_IS=C_NUM_BANKS_MEM + PARAMETER C_INCLUDE_BURST = 1, IO_IS=C_INCLUDE_BURST + PARAMETER C_DEV_MIR_ENABLE = 0, IO_IS=C_DEV_MIR_ENABLE + PARAMETER C_MAX_MEM_WIDTH = 32, IO_IS=C_MAX_MEM_WIDTH + PARAMETER C_MEM0_BASEADDR = 0x0, IO_IS=C_MEM0_BASEADDR, SHORT_DESC=FLASH, MEMORY_TYPE=FLASH + PARAMETER C_MEM0_HIGHADDR = 0x1FFFFFF, IO_IS=C_MEM0_HIGHADDR + PARAMETER C_MEM0_WIDTH = 32, IO_IS=C_MEM0_WIDTH + PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1, IO_IS=C_INCLUDE_DATAWIDTH_MATCHING_0 + PARAMETER C_SYNCH_MEM_0 = 0, IO_IS=C_SYNCH_MEM_0 + PARAMETER C_SYNCH_PIPEDELAY_0 = 2, IO_IS=C_SYNCH_PIPEDELAY_0 + PARAMETER C_TCEDV_PS_MEM_0 = 75000, IO_IS = C_TCEDV_PS_MEM_0 + PARAMETER C_TAVDV_PS_MEM_0 = 75000, IO_IS = C_TAVDV_PS_MEM_0 + PARAMETER C_THZCE_PS_MEM_0 = 25000, IO_IS = C_THZCE_PS_MEM_0 + PARAMETER C_THZOE_PS_MEM_0 = 15000, IO_IS = C_THZOE_PS_MEM_0 + PARAMETER C_TWC_PS_MEM_0 = 15000, IO_IS = C_TWC_PS_MEM_0 + PARAMETER C_TWP_PS_MEM_0 = 60000, IO_IS = C_TWP_PS_MEM_0 + PARAMETER C_TLZWE_PS_MEM_0 = 3500, IO_IS = C_TLZWE_PS_MEM_0 + + PORT FLASH_A0 = FLASH_A0, IO_IS = emc_addr[30] + PORT FLASH_A1 = FLASH_A1, IO_IS = emc_addr[29] + PORT FLASH_A2 = FLASH_A2, IO_IS = emc_addr[28] + PORT FLASH_A3 = FLASH_A3, IO_IS = emc_addr[27] + PORT FLASH_A4 = FLASH_A4, IO_IS = emc_addr[26] + PORT FLASH_A5 = FLASH_A5, IO_IS = emc_addr[25] + PORT FLASH_A6 = FLASH_A6, IO_IS = emc_addr[24] + PORT FLASH_A7 = FLASH_A7, IO_IS = emc_addr[23] + PORT FLASH_A8 = FLASH_A8, IO_IS = emc_addr[22] + PORT FLASH_A9 = FLASH_A9, IO_IS = emc_addr[21] + PORT FLASH_A10 = FLASH_A10, IO_IS = emc_addr[20] + PORT FLASH_A11 = FLASH_A11, IO_IS = emc_addr[19] + PORT FLASH_A12 = FLASH_A12, IO_IS = emc_addr[18] + PORT FLASH_A13 = FLASH_A13, IO_IS = emc_addr[17] + PORT FLASH_A14 = FLASH_A14, IO_IS = emc_addr[16] + PORT FLASH_A15 = FLASH_A15, IO_IS = emc_addr[15] + PORT FLASH_A16 = FLASH_A16, IO_IS = emc_addr[14] + PORT FLASH_A17 = FLASH_A17, IO_IS = emc_addr[13] + PORT FLASH_A18 = FLASH_A18, IO_IS = emc_addr[12] + PORT FLASH_A19 = FLASH_A19, IO_IS = emc_addr[11] + PORT FLASH_A20 = FLASH_A20, IO_IS = emc_addr[10] + PORT FLASH_A21 = FLASH_A21, IO_IS = emc_addr[9] + PORT FLASH_A22 = FLASH_A22, IO_IS = emc_addr[8] + PORT FLASH_A23 = FLASH_A23, IO_IS = emc_addr[7] + + PORT FLASH_D0 = FLASH_D0, IO_IS = emc_data[31] + PORT FLASH_D1 = FLASH_D1, IO_IS = emc_data[30] + PORT FLASH_D2 = FLASH_D2, IO_IS = emc_data[29] + PORT FLASH_D3 = FLASH_D3, IO_IS = emc_data[28] + PORT FLASH_D4 = FLASH_D4, IO_IS = emc_data[27] + PORT FLASH_D5 = FLASH_D5, IO_IS = emc_data[26] + PORT FLASH_D6 = FLASH_D6, IO_IS = emc_data[25] + PORT FLASH_D7 = FLASH_D7, IO_IS = emc_data[24] + PORT FLASH_D8 = FLASH_D8, IO_IS = emc_data[23] + PORT FLASH_D9 = FLASH_D9, IO_IS = emc_data[22] + PORT FLASH_D10 = FLASH_D10, IO_IS = emc_data[21] + PORT FLASH_D11 = FLASH_D11, IO_IS = emc_data[20] + PORT FLASH_D12 = FLASH_D12, IO_IS = emc_data[19] + PORT FLASH_D13 = FLASH_D13, IO_IS = emc_data[18] + PORT FLASH_D14 = FLASH_D14, IO_IS = emc_data[17] + PORT FLASH_D15 = FLASH_D15, IO_IS = emc_data[16] + PORT FLASH_D16 = FLASH_D16, IO_IS = emc_data[15] + PORT FLASH_D17 = FLASH_D17, IO_IS = emc_data[14] + PORT FLASH_D18 = FLASH_D18, IO_IS = emc_data[13] + PORT FLASH_D19 = FLASH_D19, IO_IS = emc_data[12] + PORT FLASH_D20 = FLASH_D20, IO_IS = emc_data[11] + PORT FLASH_D21 = FLASH_D21, IO_IS = emc_data[10] + PORT FLASH_D22 = FLASH_D22, IO_IS = emc_data[9] + PORT FLASH_D23 = FLASH_D23, IO_IS = emc_data[8] + PORT FLASH_D24 = FLASH_D24, IO_IS = emc_data[7] + PORT FLASH_D25 = FLASH_D25, IO_IS = emc_data[6] + PORT FLASH_D26 = FLASH_D26, IO_IS = emc_data[5] + PORT FLASH_D27 = FLASH_D27, IO_IS = emc_data[4] + PORT FLASH_D28 = FLASH_D28, IO_IS = emc_data[3] + PORT FLASH_D29 = FLASH_D29, IO_IS = emc_data[2] + PORT FLASH_D30 = FLASH_D30, IO_IS = emc_data[1] + PORT FLASH_D31 = FLASH_D31, IO_IS = emc_data[0] + + PORT FLASH_OEn = FLASH_OEn, IO_IS = emc_oen + PORT FLASH_WEn = FLASH_WEn, IO_IS = emc_wen + PORT FLASH_CEn = FLASH_CEn, IO_IS = emc_csn[0] + PORT FLASH_BEn = FLASH_BEn, IO_IS = emc_ben_vcc, INITIALVAL=VCC + PORT FLASH_RPn = FLASH_RPn, IO_IS = emc_rpn +END + + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_UART_V1 + ATTRIBUTE INSTANCE=RS232 + PARAMETER C_BAUDRATE = 128000, IO_IS=C_BAUDRATE + + PORT RXD = CONN_RXD, IO_IS=serial_in + PORT TXD = CONN_TXD, IO_IS=serial_out, INITIALVAL = GND +END + + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_GPIO_V1 + ATTRIBUTE INSTANCE = LEDs_8Bit + PARAMETER num_bits =8, IO_IS=num_bits + PARAMETER is_dual=0, IO_IS=is_dual + PARAMETER bidir_data=0, IO_IS=is_bidir # Non-bidir data pins + PARAMETER all_inputs =0, IO_IS=all_inputs # All outputs + + PORT LED0 = CONN_LED0, IO_IS = gpio_data_out[0], INITIALVAL = VCC + PORT LED1 = CONN_LED1, IO_IS = gpio_data_out[1], INITIALVAL = VCC + PORT LED2 = CONN_LED2, IO_IS = gpio_data_out[2], INITIALVAL = VCC + PORT LED3 = CONN_LED3, IO_IS = gpio_data_out[3], INITIALVAL = VCC + PORT LED4 = CONN_LED4, IO_IS = gpio_data_out[4], INITIALVAL = VCC + PORT LED5 = CONN_LED5, IO_IS = gpio_data_out[5], INITIALVAL = VCC + PORT LED6 = CONN_LED6, IO_IS = gpio_data_out[6], INITIALVAL = VCC + PORT LED7 = CONN_LED7, IO_IS = gpio_data_out[7], INITIALVAL = VCC +END + + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_GPIO_V1 + ATTRIBUTE INSTANCE = Switches_4Bit + PARAMETER num_bits =4, IO_IS=num_bits + PARAMETER is_dual=0, IO_IS=is_dual + PARAMETER bidir_data=0, IO_IS=is_bidir # Non-bidir data pins + PARAMETER all_inputs=1, IO_IS=all_inputs # All inputs + + PORT DIP0 = CONN_DIP0, IO_IS = gpio_data_in[0] + PORT DIP1 = CONN_DIP1, IO_IS = gpio_data_in[1] + PORT DIP2 = CONN_DIP2, IO_IS = gpio_data_in[2] + PORT DIP3 = CONN_DIP3, IO_IS = gpio_data_in[3] +END + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_GPIO_V1 + ATTRIBUTE INSTANCE = Buttons_3Bit + PARAMETER num_bits =3, IO_IS=num_bits + PARAMETER is_dual=0, IO_IS=is_dual + PARAMETER bidir_data=0, IO_IS=is_bidir # Non-bidir data pins + PARAMETER all_inputs=1, IO_IS=all_inputs # All inputs + + PORT BUT0 = CONN_BUT0, IO_IS = gpio_data_in[0] + PORT BUT1 = CONN_BUT1, IO_IS = gpio_data_in[1] + PORT BUT2 = CONN_BUT2, IO_IS = gpio_data_in[2] +END + + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_SPI_V1 + ATTRIBUTE INSTANCE = SPI_FLASH + ATTRIBUTE EXCLUSIVE = SPI + PARAMETER C_BASEADDR=0x00000000, IO_IS=C_BASEADDR + PARAMETER C_HIGHADDR=0x0000007f, IO_IS=C_HIGHADDR + PARAMETER C_NUM_OFFCHIP_SS_BITS=4, IO_IS=offchip_ss_bits + PARAMETER C_NUM_SS_BITS=1,IO_IS=ss_bits + PARAMETER C_FIFO_EXIST=1, IO_IS=fifo_exist + + PORT SPISEL = net_vcc, IO_IS=slave_select_n + PORT MISO = spi_MISO, IO_IS=data_out + PORT MOSI = spi_MOSI, IO_IS=data_in + PORT SCK = spi_SCK, IO_IS=clk_out + PORT SS0 = spi_cs_0_, IO_IS=chip_select[0] +END + + +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_ETHERNET_V1 + ATTRIBUTE INSTANCE = Ethernet_MAC + ATTRIBUTE EXCLUSIVE = Ethernet + PORT ETH_TXER = ETH_TXER, IO_IS=ETH_TXER + PORT ETH_TXC = ETH_TXC, IO_IS=ETH_TXC + PORT ETH_RXC = ETH_RXC, IO_IS=ETH_RXC + PORT ETH_CRS = ETH_CRS, IO_IS=ETH_CRS + PORT ETH_RXDV = ETH_RXDV, IO_IS=ETH_RXDV + PORT ETH_RXD0 = ETH_RXD0, IO_IS = ETH_RXD[0] + PORT ETH_RXD1 = ETH_RXD1, IO_IS = ETH_RXD[1] + PORT ETH_RXD2 = ETH_RXD2, IO_IS = ETH_RXD[2] + PORT ETH_RXD3 = ETH_RXD3, IO_IS = ETH_RXD[3] + PORT ETH_COL = ETH_COL, IO_IS=ETH_COL + PORT ETH_RXER = ETH_RXER , IO_IS=ETH_RXER + PORT ETH_TXEN = ETH_TXEN , IO_IS=ETH_TXEN + PORT ETH_TXD0 = ETH_TXD0, IO_IS = ETH_TXD[0] + PORT ETH_TXD1 = ETH_TXD1, IO_IS = ETH_TXD[1] + PORT ETH_TXD2 = ETH_TXD2, IO_IS = ETH_TXD[2] + PORT ETH_TXD3 = ETH_TXD3, IO_IS = ETH_TXD[3] + PORT ETH_MDC = ETH_MDC, IO_IS=ETH_MDC + PORT ETH_MDIO = ETH_MDIO, IO_IS=ETH_MDIO + PORT ETH_RESETn = ETH_RESETn,IO_IS = PHY_RESETn, INITIALVAL = VCC + PORT ETH_MDINT= ETH_MDINT, IO_IS = mii_int_n, INITIALVAL = VCC + +END + + +# Inter Integrated Circuit (IIC) Bus +BEGIN IO_INTERFACE + ATTRIBUTE IOTYPE = XIL_IIC_V1 + ATTRIBUTE INSTANCE = IIC_EXT + PARAMETER C_IIC_FREQ = 100000, IO_IS = clk_out_freq # 100 KHz + PARAMETER C_TEN_BIT_ADR = 0, IO_IS = slave_respond_mode # 7-bit addrs + PORT SCL = iic_scl, IO_IS = Serial_Clock + PORT SDA = iic_sda, IO_IS = Serial_Data +END + + +BEGIN FPGA + ATTRIBUTE INSTANCE = fpga_0 + ATTRIBUTE FAMILY = spartan3 + ATTRIBUTE DEVICE = XC3S4000 + ATTRIBUTE PACKAGE = FG676 + ATTRIBUTE SPEED_GRADE = -4 + ATTRIBUTE JTAG_POSITION = 1 + + ### CLOCK ### + PORT SYSCLK = CONN_CLK,UCF_NET_STRING=("LOC=af14", "IOSTANDARD = LVCMOS33") + + PORT CLK_EXT0 = CONN_OSC_EXT0,UCF_NET_STRING=("LOC=ae13", "IOSTANDARD = LVCMOS33") # Input CLK + PORT CLK_EXT1 = CONN_OSC_EXT1, UCF_NET_STRING=("LOC=ad13", "IOSTANDARD = LVCMOS33") # Input CLK + + ### RESET ### + PORT RESET = CONN_RESET, UCF_NET_STRING=("LOC=ae19", "IOSTANDARD = LVCMOS33") + + ### UART ### + PORT RXD = CONN_RXD, UCF_NET_STRING=("LOC=ac7", "IOSTANDARD = LVCMOS33") + PORT TXD = CONN_TXD, UCF_NET_STRING=("LOC=ac6", "IOSTANDARD = LVCMOS33") + + ### LED ### + PORT LED0 = CONN_LED0, UCF_NET_STRING=("LOC=f9", "IOSTANDARD = LVCMOS33", "SLEW = SLOW") + PORT LED1 = CONN_LED1, UCF_NET_STRING=("LOC=g9", "IOSTANDARD = LVCMOS33", "SLEW = SLOW") + PORT LED2 = CONN_LED2, UCF_NET_STRING=("LOC=f10", "IOSTANDARD = LVCMOS33", "SLEW = SLOW") + PORT LED3 = CONN_LED3, UCF_NET_STRING=("LOC=e10", "IOSTANDARD = LVCMOS33", "SLEW = SLOW") + PORT LED4 = CONN_LED4, UCF_NET_STRING=("LOC=c12", "IOSTANDARD = LVCMOS33", "SLEW = SLOW") + PORT LED5 = CONN_LED5, UCF_NET_STRING=("LOC=e13", "IOSTANDARD = LVCMOS33", "SLEW = SLOW") + PORT LED6 = CONN_LED6, UCF_NET_STRING=("LOC=d13", "IOSTANDARD = LVCMOS33", "SLEW = SLOW") + PORT LED7 = CONN_LED7, UCF_NET_STRING=("LOC=c13", "IOSTANDARD = LVCMOS33", "SLEW = SLOW") + + ### DIP_Switches ### + PORT DIP0 = CONN_DIP0, UCF_NET_STRING=("LOC=d7, "IOSTANDARD = LVCMOS33") + PORT DIP1 = CONN_DIP1, UCF_NET_STRING=("LOC=f7, "IOSTANDARD = LVCMOS33") + PORT DIP2 = CONN_DIP2, UCF_NET_STRING=("LOC=c6, "IOSTANDARD = LVCMOS33") + PORT DIP3 = CONN_DIP3, UCF_NET_STRING=("LOC=d6, "IOSTANDARD = LVCMOS33") + + ### BUTTONS ### + PORT BUT0 = CONN_BUT0, UCF_NET_STRING=("LOC=e7, "IOSTANDARD = LVCMOS33") + PORT BUT1 = CONN_BUT1, UCF_NET_STRING=("LOC=g10, "IOSTANDARD = LVCMOS33") + PORT BUT2 = CONN_BUT2, UCF_NET_STRING=("LOC=e12, "IOSTANDARD = LVCMOS33") + + ### NOR FLASH ### + PORT FLASH_OEn = FLASH_OEn, UCF_NET_STRING=("LOC=b21", "IOSTANDARD = LVCMOS33") + PORT FLASH_CEn = FLASH_CEn, UCF_NET_STRING=("LOC=e15", "IOSTANDARD = LVCMOS33") + PORT FLASH_WEn = FLASH_WEn, UCF_NET_STRING=("LOC=b3", "IOSTANDARD = LVCMOS33") + PORT FLASH_BEn = FLASH_BEn, UCF_NET_STRING=("LOC=h16", "IOSTANDARD = LVCMOS33") + PORT FLASH_RPn = FLASH_RPn, UCF_NET_STRING=("LOC=f15", "IOSTANDARD = LVCMOS33") + PORT FLASH_A0 = FLASH_A0, UCF_NET_STRING=("LOC=g17", "IOSTANDARD = LVCMOS33") + PORT FLASH_A1 = FLASH_A1, UCF_NET_STRING=("LOC=h15", "IOSTANDARD = LVCMOS33") + PORT FLASH_A2 = FLASH_A2, UCF_NET_STRING=("LOC=g15", "IOSTANDARD = LVCMOS33") + PORT FLASH_A3 = FLASH_A3, UCF_NET_STRING=("LOC=h14", "IOSTANDARD = LVCMOS33") + PORT FLASH_A4 = FLASH_A4, UCF_NET_STRING=("LOC=g14", "IOSTANDARD = LVCMOS33") + PORT FLASH_A5 = FLASH_A5, UCF_NET_STRING=("LOC=g13", "IOSTANDARD = LVCMOS33") + PORT FLASH_A6 = FLASH_A6, UCF_NET_STRING=("LOC=h13", "IOSTANDARD = LVCMOS33") + PORT FLASH_A7 = FLASH_A7, UCF_NET_STRING=("LOC=g12", "IOSTANDARD = LVCMOS33") + PORT FLASH_A8 = FLASH_A8, UCF_NET_STRING=("LOC=d17", "IOSTANDARD = LVCMOS33") + PORT FLASH_A9 = FLASH_A9, UCF_NET_STRING=("LOC=g11", "IOSTANDARD = LVCMOS33") + PORT FLASH_A10 = FLASH_A10, UCF_NET_STRING=("LOC=f16", "IOSTANDARD = LVCMOS33") + PORT FLASH_A11 = FLASH_A11, UCF_NET_STRING=("LOC=f12", "IOSTANDARD = LVCMOS33") + PORT FLASH_A12 = FLASH_A12, UCF_NET_STRING=("LOC=f11", "IOSTANDARD = LVCMOS33") + PORT FLASH_A13 = FLASH_A13, UCF_NET_STRING=("LOC=f14", "IOSTANDARD = LVCMOS33") + PORT FLASH_A14 = FLASH_A14, UCF_NET_STRING=("LOC=e11", "IOSTANDARD = LVCMOS33") + PORT FLASH_A15 = FLASH_A15, UCF_NET_STRING=("LOC=e14", "IOSTANDARD = LVCMOS33") + PORT FLASH_A16 = FLASH_A16, UCF_NET_STRING=("LOC=d11", "IOSTANDARD = LVCMOS33") + PORT FLASH_A17 = FLASH_A17, UCF_NET_STRING=("LOC=h12", "IOSTANDARD = LVCMOS33") + PORT FLASH_A18 = FLASH_A18, UCF_NET_STRING=("LOC=h11", "IOSTANDARD = LVCMOS33") + PORT FLASH_A19 = FLASH_A19, UCF_NET_STRING=("LOC=d10", "IOSTANDARD = LVCMOS33") + PORT FLASH_A20 = FLASH_A20, UCF_NET_STRING=("LOC=c10", "IOSTANDARD = LVCMOS33") + PORT FLASH_A21 = FLASH_A21, UCF_NET_STRING=("LOC=a12", "IOSTANDARD = LVCMOS33") + PORT FLASH_A22 = FLASH_A22, UCF_NET_STRING=("LOC=b12", "IOSTANDARD = LVCMOS33") + PORT FLASH_A23 = FLASH_A23, UCF_NET_STRING=("LOC=g16", "IOSTANDARD = LVCMOS33") + + # Data Bus Flash 0 + PORT FLASH_D0 = FLASH_D0, UCF_NET_STRING=("LOC=f18", "IOSTANDARD = LVCMOS33") + PORT FLASH_D1 = FLASH_D1, UCF_NET_STRING=("LOC=g19", "IOSTANDARD = LVCMOS33") + PORT FLASH_D2 = FLASH_D2, UCF_NET_STRING=("LOC=a20", "IOSTANDARD = LVCMOS33") + PORT FLASH_D3 = FLASH_D3, UCF_NET_STRING=("LOC=e20", "IOSTANDARD = LVCMOS33") + PORT FLASH_D4 = FLASH_D4, UCF_NET_STRING=("LOC=e21", "IOSTANDARD = LVCMOS33") + PORT FLASH_D5 = FLASH_D5, UCF_NET_STRING=("LOC=h23", "IOSTANDARD = LVCMOS33") + PORT FLASH_D6 = FLASH_D6, UCF_NET_STRING=("LOC=h24", "IOSTANDARD = LVCMOS33") + PORT FLASH_D7 = FLASH_D7, UCF_NET_STRING=("LOC=b20", "IOSTANDARD = LVCMOS33") + PORT FLASH_D8 = FLASH_D8, UCF_NET_STRING=("LOC=g18", "IOSTANDARD = LVCMOS33") + PORT FLASH_D9 = FLASH_D9, UCF_NET_STRING=("LOC=f20", "IOSTANDARD = LVCMOS33") + PORT FLASH_D10 = FLASH_D10, UCF_NET_STRING=("LOC=d20", "IOSTANDARD = LVCMOS33") + PORT FLASH_D11 = FLASH_D11, UCF_NET_STRING=("LOC=a21", "IOSTANDARD = LVCMOS33") + PORT FLASH_D12 = FLASH_D12, UCF_NET_STRING=("LOC=f21", "IOSTANDARD = LVCMOS33") + PORT FLASH_D13 = FLASH_D13, UCF_NET_STRING=("LOC=e23", "IOSTANDARD = LVCMOS33") + PORT FLASH_D14 = FLASH_D14, UCF_NET_STRING=("LOC=e24", "IOSTANDARD = LVCMOS33") + PORT FLASH_D15 = FLASH_D15, UCF_NET_STRING=("LOC=d25", "IOSTANDARD = LVCMOS33") + + # Data Bus Flash 1 + PORT FLASH_D16 = FLASH_D16, UCF_NET_STRING=("LOC=e6", "IOSTANDARD = LVCMOS33") + PORT FLASH_D17 = FLASH_D17, UCF_NET_STRING=("LOC=d5", "IOSTANDARD = LVCMOS33") + PORT FLASH_D18 = FLASH_D18, UCF_NET_STRING=("LOC=c4", "IOSTANDARD = LVCMOS33") + PORT FLASH_D19 = FLASH_D19, UCF_NET_STRING=("LOC=b8", "IOSTANDARD = LVCMOS33") + PORT FLASH_D20 = FLASH_D20, UCF_NET_STRING=("LOC=b7", "IOSTANDARD = LVCMOS33") + PORT FLASH_D21 = FLASH_D21, UCF_NET_STRING=("LOC=b6", "IOSTANDARD = LVCMOS33") + PORT FLASH_D22 = FLASH_D22, UCF_NET_STRING=("LOC=b5", "IOSTANDARD = LVCMOS33") + PORT FLASH_D23 = FLASH_D23, UCF_NET_STRING=("LOC=b4", "IOSTANDARD = LVCMOS33") + PORT FLASH_D24 = FLASH_D24, UCF_NET_STRING=("LOC=c5", "IOSTANDARD = LVCMOS33") + PORT FLASH_D25 = FLASH_D25, UCF_NET_STRING=("LOC=e5", "IOSTANDARD = LVCMOS33") + PORT FLASH_D26 = FLASH_D26, UCF_NET_STRING=("LOC=a8", "IOSTANDARD = LVCMOS33") + PORT FLASH_D27 = FLASH_D27, UCF_NET_STRING=("LOC=a7", "IOSTANDARD = LVCMOS33") + PORT FLASH_D28 = FLASH_D28, UCF_NET_STRING=("LOC=a6", "IOSTANDARD = LVCMOS33") + PORT FLASH_D29 = FLASH_D29, UCF_NET_STRING=("LOC=a5", "IOSTANDARD = LVCMOS33") + PORT FLASH_D30 = FLASH_D30, UCF_NET_STRING=("LOC=a4", "IOSTANDARD = LVCMOS33") + PORT FLASH_D31 = FLASH_D31, UCF_NET_STRING=("LOC=a3", "IOSTANDARD = LVCMOS33") + + ### SPI FLASH ### + PORT MISO = spi_MISO, UCF_NET_STRING=("LOC=aa11", "IOSTANDARD = LVCMOS33") + PORT MOSI = spi_MOSI, UCF_NET_STRING=("LOC=aa9", "IOSTANDARD = LVCMOS33") + PORT SCK = spi_SCK, UCF_NET_STRING=("LOC=aa10", "IOSTANDARD = LVCMOS33") + PORT SS0 = spi_cs_0_, UCF_NET_STRING=("LOC=y8", "IOSTANDARD = LVCMOS33") + + + ### DDR SDRAM 64Mx16 configuration ### + PORT DDR_CLK = ddr_clk, UCF_NET_STRING=("LOC=w1", "IOSTANDARD = SSTL2_II") + PORT DDR_CLKn = ddr_clk_n, UCF_NET_STRING=("LOC=w2", "IOSTANDARD = SSTL2_II") + PORT DDR_CLK_FB = ddr_clk_fb, UCF_NET_STRING=("LOC=ae14", "IOSTANDARD = LVCMOS33") + + PORT DDR_A0 = ddr_addr_0_, UCF_NET_STRING=("LOC=p6", "IOSTANDARD = SSTL2_II") + PORT DDR_A1 = ddr_addr_1_, UCF_NET_STRING=("LOC=r7", "IOSTANDARD = SSTL2_II") + PORT DDR_A2 = ddr_addr_2_, UCF_NET_STRING=("LOC=p7", "IOSTANDARD = SSTL2_II") + PORT DDR_A3 = ddr_addr_3_, UCF_NET_STRING=("LOC=r8", "IOSTANDARD = SSTL2_II") + PORT DDR_A4 = ddr_addr_4_, UCF_NET_STRING=("LOC=t8", "IOSTANDARD = SSTL2_II") + PORT DDR_A5 = ddr_addr_5_, UCF_NET_STRING=("LOC=ab4", "IOSTANDARD = SSTL2_II") + PORT DDR_A6 = ddr_addr_6_, UCF_NET_STRING=("LOC=ab3", "IOSTANDARD = SSTL2_II") + PORT DDR_A7 = ddr_addr_7_, UCF_NET_STRING=("LOC=ac1", "IOSTANDARD = SSTL2_II") + PORT DDR_A8 = ddr_addr_8_, UCF_NET_STRING=("LOC=ad2", "IOSTANDARD = SSTL2_II") + PORT DDR_A9 = ddr_addr_9_, UCF_NET_STRING=("LOC=ad1", "IOSTANDARD = SSTL2_II") + PORT DDR_A10 = ddr_addr_10_, UCF_NET_STRING=("LOC=t6", "IOSTANDARD = SSTL2_II") + PORT DDR_A11 = ddr_addr_11_, UCF_NET_STRING=("LOC=w7", "IOSTANDARD = SSTL2_II") + PORT DDR_A12 = ddr_addr_12_, UCF_NET_STRING=("LOC=w6", "IOSTANDARD = SSTL2_II") + PORT DDR_A13 = ddr_addr_13_, UCF_NET_STRING=("LOC=v3", "IOSTANDARD = SSTL2_II") + + PORT DDR_BA0 = ddr_ba_0_, UCF_NET_STRING=("LOC=v5", "IOSTANDARD = SSTL2_II") + PORT DDR_BA1 = ddr_ba_1_, UCF_NET_STRING=("LOC=u6", "IOSTANDARD = SSTL2_II") + + PORT DDR_CASn = ddr_cas_n, UCF_NET_STRING=("LOC=u7", "IOSTANDARD = SSTL2_II") + PORT DDR_CKE = ddr_cke, UCF_NET_STRING=("LOC=w5", "IOSTANDARD = SSTL2_II") + PORT DDR_CSn = ddr_cs_n, UCF_NET_STRING=("LOC=v7", "IOSTANDARD = SSTL2_II") + PORT DDR_RASn = ddr_ras_n, UCF_NET_STRING=("LOC=v6", "IOSTANDARD = SSTL2_II") + PORT DDR_WEn = ddr_we_n, UCF_NET_STRING=("LOC=t7", "IOSTANDARD = SSTL2_II") + + PORT DDR_LDM = ddr_dm_0_, UCF_NET_STRING=("LOC=v2", "IOSTANDARD = SSTL2_II") + PORT DDR_UDM = ddr_dm_1_, UCF_NET_STRING=("LOC=v4", "IOSTANDARD = SSTL2_II") + + PORT DDR_LDQS = ddr_dqs_0_, UCF_NET_STRING=("LOC=r1", "IOSTANDARD = SSTL2_II") + PORT DDR_UDQS = ddr_dqs_1_, UCF_NET_STRING=("LOC=w4", "IOSTANDARD = SSTL2_II", "PULLUP") + + PORT DDR_DQ0 = ddr_dq_0_, UCF_NET_STRING=("LOC=p3", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ1 = ddr_dq_1_, UCF_NET_STRING=("LOC=p8", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ2 = ddr_dq_2_, UCF_NET_STRING=("LOC=t2", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ3 = ddr_dq_3_, UCF_NET_STRING=("LOC=r3", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ4 = ddr_dq_4_, UCF_NET_STRING=("LOC=p2", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ5 = ddr_dq_5_, UCF_NET_STRING=("LOC=t1", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ6 = ddr_dq_6_, UCF_NET_STRING=("LOC=u2", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ7 = ddr_dq_7_, UCF_NET_STRING=("LOC=u1", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ8 = ddr_dq_8_, UCF_NET_STRING=("LOC=u5", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ9 = ddr_dq_9_, UCF_NET_STRING=("LOC=u3", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ10 = ddr_dq_10_, UCF_NET_STRING=("LOC=t5", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ11 = ddr_dq_11_, UCF_NET_STRING=("LOC=t4", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ12 = ddr_dq_12_, UCF_NET_STRING=("LOC=r5", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ13 = ddr_dq_13_, UCF_NET_STRING=("LOC=r6", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ14 = ddr_dq_14_, UCF_NET_STRING=("LOC=p4", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR_DQ15 = ddr_dq_15_, UCF_NET_STRING=("LOC=p5", "IOSTANDARD = SSTL2_II", "PULLUP") + +### DDR SDRAM 128Mx32 configuration ### + PORT DDR32a_CLK = ddr32a_clk, UCF_NET_STRING=("LOC=w1", "IOSTANDARD = SSTL2_II") + PORT DDR32a_CLKn = ddr32a_clk_n, UCF_NET_STRING=("LOC=w2", "IOSTANDARD = SSTL2_II") + PORT DDR32b_CLK = ddr32b_clk, UCF_NET_STRING=("LOC=f5", "IOSTANDARD = SSTL2_II") + PORT DDR32b_CLKn = ddr32b_clk_n, UCF_NET_STRING=("LOC=f6", "IOSTANDARD = SSTL2_II") + PORT DDR32_CLK_FB = ddr32_clk_fb, UCF_NET_STRING=("LOC=ae14", "IOSTANDARD = LVCMOS33") + + PORT DDR32a_A0 = ddr32a_addr_0_, UCF_NET_STRING=("LOC=p6", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A1 = ddr32a_addr_1_, UCF_NET_STRING=("LOC=r7", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A2 = ddr32a_addr_2_, UCF_NET_STRING=("LOC=p7", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A3 = ddr32a_addr_3_, UCF_NET_STRING=("LOC=r8", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A4 = ddr32a_addr_4_, UCF_NET_STRING=("LOC=t8", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A5 = ddr32a_addr_5_, UCF_NET_STRING=("LOC=ab4", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A6 = ddr32a_addr_6_, UCF_NET_STRING=("LOC=ab3", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A7 = ddr32a_addr_7_, UCF_NET_STRING=("LOC=ac1", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A8 = ddr32a_addr_8_, UCF_NET_STRING=("LOC=ad2", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A9 = ddr32a_addr_9_, UCF_NET_STRING=("LOC=ad1", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A10 = ddr32a_addr_10_, UCF_NET_STRING=("LOC=t6", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A11 = ddr32a_addr_11_, UCF_NET_STRING=("LOC=w7", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A12 = ddr32a_addr_12_, UCF_NET_STRING=("LOC=w6", "IOSTANDARD = SSTL2_II") + PORT DDR32a_A13 = ddr32a_addr_13_, UCF_NET_STRING=("LOC=v3", "IOSTANDARD = SSTL2_II") + + PORT DDR32a_BA0 = ddr32a_ba_0_, UCF_NET_STRING=("LOC=v5", "IOSTANDARD = SSTL2_II") + PORT DDR32a_BA1 = ddr32a_ba_1_, UCF_NET_STRING=("LOC=u6", "IOSTANDARD = SSTL2_II") + + PORT DDR32a_CASn = ddr32a_cas_n, UCF_NET_STRING=("LOC=u7", "IOSTANDARD = SSTL2_II") + PORT DDR32a_CKE = ddr32a_cke, UCF_NET_STRING=("LOC=w5", "IOSTANDARD = SSTL2_II") + PORT DDR32a_CSn = ddr32a_cs_n, UCF_NET_STRING=("LOC=v7", "IOSTANDARD = SSTL2_II") + PORT DDR32a_RASn = ddr32a_ras_n, UCF_NET_STRING=("LOC=v6", "IOSTANDARD = SSTL2_II") + PORT DDR32a_WEn = ddr32a_we_n, UCF_NET_STRING=("LOC=t7", "IOSTANDARD = SSTL2_II") + + PORT DDR32b_A0 = ddr32b_addr_0_, UCF_NET_STRING=("LOC=l2", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A1 = ddr32b_addr_1_, UCF_NET_STRING=("LOC=m3", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A2 = ddr32b_addr_2_, UCF_NET_STRING=("LOC=k1", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A3 = ddr32b_addr_3_, UCF_NET_STRING=("LOC=m2", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A4 = ddr32b_addr_4_, UCF_NET_STRING=("LOC=l1", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A5 = ddr32b_addr_5_, UCF_NET_STRING=("LOC=m1", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A6 = ddr32b_addr_6_, UCF_NET_STRING=("LOC=n8", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A7 = ddr32b_addr_7_, UCF_NET_STRING=("LOC=n6", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A8 = ddr32b_addr_8_, UCF_NET_STRING=("LOC=n7", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A9 = ddr32b_addr_9_, UCF_NET_STRING=("LOC=m5", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A10 = ddr32b_addr_10_, UCF_NET_STRING=("LOC=n5", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A11 = ddr32b_addr_11_, UCF_NET_STRING=("LOC=n2", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A12 = ddr32b_addr_12_, UCF_NET_STRING=("LOC=n3", "IOSTANDARD = SSTL2_II") + PORT DDR32b_A13 = ddr32b_addr_13_, UCF_NET_STRING=("LOC=k5", "IOSTANDARD = SSTL2_II") + + PORT DDR32b_BA0 = ddr32b_ba_0_, UCF_NET_STRING=("LOC=k3", "IOSTANDARD = SSTL2_II") + PORT DDR32b_BA1 = ddr32b_ba_1_, UCF_NET_STRING=("LOC=j2", "IOSTANDARD = SSTL2_II") + + PORT DDR32b_CASn = ddr32b_cas_n, UCF_NET_STRING=("LOC=k4", "IOSTANDARD = SSTL2_II") + PORT DDR32b_CKE = ddr32b_cke, UCF_NET_STRING=("LOC=n4", "IOSTANDARD = SSTL2_II") + PORT DDR32b_CSn = ddr32b_cs_n, UCF_NET_STRING=("LOC=m8", "IOSTANDARD = SSTL2_II") + PORT DDR32b_RASn = ddr32b_ras_n, UCF_NET_STRING=("LOC=j4", "IOSTANDARD = SSTL2_II") + PORT DDR32b_WEn = ddr32b_we_n, UCF_NET_STRING=("LOC=l4", "IOSTANDARD = SSTL2_II") + + PORT DDR32a_LDM = ddr32_dm_0_, UCF_NET_STRING=("LOC=v2", "IOSTANDARD = SSTL2_II") + PORT DDR32a_UDM = ddr32_dm_1_, UCF_NET_STRING=("LOC=v4", "IOSTANDARD = SSTL2_II") + PORT DDR32b_LDM = ddr32_dm_2_, UCF_NET_STRING=("LOC=l5", "IOSTANDARD = SSTL2_II") + PORT DDR32b_UDM = ddr32_dm_3_, UCF_NET_STRING=("LOC=k2", "IOSTANDARD = SSTL2_II") + + PORT DDR32a_LDQS = ddr32_dqs_0_, UCF_NET_STRING=("LOC=r1", "IOSTANDARD = SSTL2_II") + PORT DDR32a_UDQS = ddr32_dqs_1_, UCF_NET_STRING=("LOC=w4", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32b_LDQS = ddr32_dqs_2_, UCF_NET_STRING=("LOC=l7", "IOSTANDARD = SSTL2_II") + PORT DDR32b_UDQS = ddr32_dqs_3_, UCF_NET_STRING=("LOC=h2", "IOSTANDARD = SSTL2_II", "PULLUP") + + PORT DDR32_DQ0 = ddr32_dq_0_, UCF_NET_STRING=("LOC=p3", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ1 = ddr32_dq_1_, UCF_NET_STRING=("LOC=p8", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ2 = ddr32_dq_2_, UCF_NET_STRING=("LOC=t2", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ3 = ddr32_dq_3_, UCF_NET_STRING=("LOC=r3", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ4 = ddr32_dq_4_, UCF_NET_STRING=("LOC=p2", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ5 = ddr32_dq_5_, UCF_NET_STRING=("LOC=t1", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ6 = ddr32_dq_6_, UCF_NET_STRING=("LOC=u2", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ7 = ddr32_dq_7_, UCF_NET_STRING=("LOC=u1", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ8 = ddr32_dq_8_, UCF_NET_STRING=("LOC=u5", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ9 = ddr32_dq_9_, UCF_NET_STRING=("LOC=u3", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ10 = ddr32_dq_10_, UCF_NET_STRING=("LOC=t5", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ11 = ddr32_dq_11_, UCF_NET_STRING=("LOC=t4", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ12 = ddr32_dq_12_, UCF_NET_STRING=("LOC=r5", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ13 = ddr32_dq_13_, UCF_NET_STRING=("LOC=r6", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ14 = ddr32_dq_14_, UCF_NET_STRING=("LOC=p4", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ15 = ddr32_dq_15_, UCF_NET_STRING=("LOC=p5", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ16 = ddr32_dq_16_, UCF_NET_STRING=("LOC=l6", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ17 = ddr32_dq_17_, UCF_NET_STRING=("LOC=k7", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ18 = ddr32_dq_18_, UCF_NET_STRING=("LOC=j7", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ19 = ddr32_dq_19_, UCF_NET_STRING=("LOC=k6", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ20 = ddr32_dq_20_, UCF_NET_STRING=("LOC=j6", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ21 = ddr32_dq_21_, UCF_NET_STRING=("LOC=j5", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ22 = ddr32_dq_22_, UCF_NET_STRING=("LOC=m7", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ23 = ddr32_dq_23_, UCF_NET_STRING=("LOC=m6", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ24 = ddr32_dq_24_, UCF_NET_STRING=("LOC=j3", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ25 = ddr32_dq_25_, UCF_NET_STRING=("LOC=g1", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ26 = ddr32_dq_26_, UCF_NET_STRING=("LOC=g2", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ27 = ddr32_dq_27_, UCF_NET_STRING=("LOC=h3", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ28 = ddr32_dq_28_, UCF_NET_STRING=("LOC=h4", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ29 = ddr32_dq_29_, UCF_NET_STRING=("LOC=d2", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ30 = ddr32_dq_30_, UCF_NET_STRING=("LOC=e3", "IOSTANDARD = SSTL2_II", "PULLUP") + PORT DDR32_DQ31 = ddr32_dq_31_, UCF_NET_STRING=("LOC=e4", "IOSTANDARD = SSTL2_II", "PULLUP") + + ### Ethernet ### + #PORT ETH_TXER = ETH_TXER, UCF_NET_STRING=("LOC=xx", "IOSTANDARD = LVCMOS33") + PORT ETH_TXC = ETH_TXC, UCF_NET_STRING=("LOC=ab9", "IOSTANDARD = LVCMOS33") + PORT ETH_RXC = ETH_RXC, UCF_NET_STRING=("LOC=ae7", "IOSTANDARD = LVCMOS33") + PORT ETH_CRS = ETH_CRS, UCF_NET_STRING=("LOC=af7", "IOSTANDARD = LVCMOS33") + PORT ETH_RXDV = ETH_RXDV, UCF_NET_STRING=("LOC=ad5", "IOSTANDARD = LVCMOS33") + PORT ETH_RXD0 = ETH_RXD0, UCF_NET_STRING=("LOC=ad6", "IOSTANDARD = LVCMOS33") + PORT ETH_RXD1 = ETH_RXD1, UCF_NET_STRING=("LOC=af8", "IOSTANDARD = LVCMOS33") + PORT ETH_RXD2 = ETH_RXD2, UCF_NET_STRING=("LOC=ae4", "IOSTANDARD = LVCMOS33") + PORT ETH_RXD3 = ETH_RXD3, UCF_NET_STRING=("LOC=ae8", "IOSTANDARD = LVCMOS33") + PORT ETH_COL = ETH_COL, UCF_NET_STRING=("LOC=af5", "IOSTANDARD = LVCMOS33") + PORT ETH_RXER = ETH_RXER, UCF_NET_STRING=("LOC=ad4", "IOSTANDARD = LVCMOS33") + PORT ETH_TXEN = ETH_TXEN, UCF_NET_STRING=("LOC=ab10", "IOSTANDARD = LVCMOS33") + PORT ETH_TXD0 = ETH_TXD0, UCF_NET_STRING=("LOC=ab11", "IOSTANDARD = LVCMOS33") + PORT ETH_TXD1 = ETH_TXD1, UCF_NET_STRING=("LOC=ac10", "IOSTANDARD = LVCMOS33") + PORT ETH_TXD2 = ETH_TXD2, UCF_NET_STRING=("LOC=ac11", "IOSTANDARD = LVCMOS33") + PORT ETH_TXD3 = ETH_TXD3, UCF_NET_STRING=("LOC=ad10", "IOSTANDARD = LVCMOS33") + PORT ETH_MDC = ETH_MDC, UCF_NET_STRING=("LOC=ae12", "IOSTANDARD = LVCMOS33") + PORT ETH_RESETn = ETH_RESETn,UCF_NET_STRING=("LOC=af13", "IOSTANDARD = LVCMOS33") + PORT ETH_MDIO = ETH_MDIO, UCF_NET_STRING=("LOC=af12", "IOSTANDARD = LVCMOS33") + PORT ETH_MDINT = ETH_MDINT, UCF_NET_STRING=("LOC=ad12", "IOSTANDARD = LVCMOS33") + + ### IIC ### + PORT IIC_CLK = iic_scl, UCF_NET_STRING=("LOC=u21", "SLEW = SLOW", "DRIVE = 6", "IOSTANDARD = LVCMOS33") + PORT IIC_DATA = iic_sda, UCF_NET_STRING=("LOC=y17", "SLEW = SLOW", "DRIVE = 6", "IOSTANDARD = LVCMOS33") + +END +

boards/GECKO3main/data/GECKO3main_v2_2_0.xbd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: boards/GECKO3main/data/README =================================================================== --- boards/GECKO3main/data/README (nonexistent) +++ boards/GECKO3main/data/README (revision 5) @@ -0,0 +1,11 @@ +The folder "edk_user_repository" contains the board support package for the GECKO3main module to use in Xilinx EDK + +Extract this file in the folder where the EDK folder is located. Don't extract it inside the EDK folder! +After extracting you should have a "edk_user_repository" folder on the same level as the EDK installation folder. + +Compatible with EDK 8.2 and 9.1. + +Known issues: +- EDK 9.2 and above is not supported yet (Xilinx changed the IP-Core they use for memory interfaces. This gives us a lot of problems) + +- The 128 Mbyte DDR RAM configurations does not work yet. I'm unsure where the problem is. Index: boards/GECKO3main/data/COPYING =================================================================== --- boards/GECKO3main/data/COPYING (nonexistent) +++ boards/GECKO3main/data/COPYING (revision 5) @@ -0,0 +1,165 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. Additional Definitions. + + As used herein, "this License" refers to version 3 of the GNU Lesser +General Public License, and the "GNU GPL" refers to version 3 of the GNU +General Public License. + + "The Library" refers to a covered work governed by this License, +other than an Application or a Combined Work as defined below. + + An "Application" is any work that makes use of an interface provided +by the Library, but which is not otherwise based on the Library. +Defining a subclass of a class defined by the Library is deemed a mode +of using an interface provided by the Library. + + A "Combined Work" is a work produced by combining or linking an +Application with the Library. The particular version of the Library +with which the Combined Work was made is also called the "Linked +Version". + + The "Minimal Corresponding Source" for a Combined Work means the +Corresponding Source for the Combined Work, excluding any source code +for portions of the Combined Work that, considered in isolation, are +based on the Application, and not on the Linked Version. + + The "Corresponding Application Code" for a Combined Work means the +object code and/or source code for the Application, including any data +and utility programs needed for reproducing the Combined Work from the +Application, but excluding the System Libraries of the Combined Work. + + 1. Exception to Section 3 of the GNU GPL. + + You may convey a covered work under sections 3 and 4 of this License +without being bound by section 3 of the GNU GPL. + + 2. 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