URL
https://opencores.org/ocsvn/gecko3/gecko3/trunk
Subversion Repositories gecko3
Compare Revisions
- This comparison shows the changes necessary to convert path
/gecko3/trunk/GECKO3COM/gecko3com-fw/firmware
- from Rev 18 to Rev 19
- ↔ Reverse comparison
Rev 18 → Rev 19
/include/gecko3com_gpif.h
41,6 → 41,9
#define bmGPIF_READ_IN_PROGRESS 1 |
#define bmGPIF_PENDING_DATA 2 |
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/** flag to signal, that the GPIF receives data from the FPGA */ |
volatile static idata uint8_t flGPIF; |
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/** \brief initialize GPIF system |
* |
* initialize GPIF with waveform data. |
/src/gecko3com_main.c
848,13 → 848,6
} |
} /* end of IN Transfer clause */ |
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/* if(!(EP2468STAT & bmEP2EMPTY) && flLOCAL == GECKO3COM_REMOTE) { */ |
/* flGPIF &= ~bmGPIF_PENDING_DATA; */ |
/* OUTPKTEND = USB_TMC_EP_OUT; */ |
/* gpif_trigger_write(); */ |
/* EP2FIFOCFG |= bmAUTOOUT; */ |
/* } */ |
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/* if the LED flag is set to off, disable the external LED */ |
if(flLED == LEDS_OFF) { |
set_led_ext(LEDS_OFF); |
/src/gecko3com_gpif.c
77,8 → 77,8
extern const char InitData[7]; |
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/** private flag to signal, that the GPIF receives data from the FPGA */ |
volatile static uint8_t flGPIF; |
//** private flag to signal, that the GPIF receives data from the FPGA */ |
//volatile static uint8_t flGPIF; |
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90,23 → 90,22
{ |
ISR_DEBUG_PORT |= bmGPIF_DONE; |
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clear_fifo_gpif_irq(); |
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//EA = 0; /* disable all interrupts */ |
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/* check if there is data available for an OUT transfer */ |
if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) { |
//if(!(EP2468STAT & bmEP2EMPTY)) { |
/*if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) { |
//if(!(EP2468STAT & bmEP2EMPTY)) { |
flGPIF &= ~bmGPIF_PENDING_DATA; |
GPIFABORT = 0xFF; |
SYNCDELAY; |
gpif_trigger_write(); |
} |
else { |
INPKTEND = USB_TMC_EP_IN; |
else*/ { |
/* check if this is a end of a IN transfer */ |
//INPKTEND = USB_TMC_EP_IN; |
while(!(GPIFTRIG & bmGPIF_IDLE)); |
gpif_trigger_read(); |
} |
//EA = 1; /* global interrupt enable */ |
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clear_fifo_gpif_irq(); |
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ISR_DEBUG_PORT &= ~bmGPIF_DONE; |
} |
120,21 → 119,19
{ |
ISR_DEBUG_PORT |= bmFIFO_PF; |
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clear_fifo_gpif_irq(); |
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/* check if there is a active IN transfer */ |
if((GPIFIDLECTL & bmBIT3) == bmBIT3) { |
/*if((GPIFIDLECTL & bmBIT3) == bmBIT3) { |
flGPIF |= bmGPIF_PENDING_DATA; |
} |
else { |
//EA = 0; /* disable all interrupts */ |
else*/ { |
GPIFABORT = 0xFF; |
SYNCDELAY; |
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while(!(GPIFTRIG & bmGPIF_IDLE)); |
gpif_trigger_write(); |
//EA = 1; /* global interrupt enable */ |
} |
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clear_fifo_gpif_irq(); |
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ISR_DEBUG_PORT &= ~bmFIFO_PF; |
} |
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145,8 → 142,9
uint8_t i; |
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#ifdef GECKO3MAIN |
/* IFCLK is generated internally and runs at 48 MHz; GPIF "master mode" */ |
IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmGSTATE | bmIFGPIF; |
/* IFCLK is generated internally and runs at 30 MHz; GPIF "master mode" */ |
//IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmGSTATE | bmIFGPIF; |
IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmGSTATE | bmIFGPIF; |
SYNCDELAY; |
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/* we have to commit the currently processed packet BEFORE we switch to auto out mode */ |
168,11 → 166,11
* flag has to change one cycle before the FIFO is completly empty, else we |
* transfer one word too much */ |
EP2FIFOPFH = bmDECIS; |
EP2FIFOPFL = 1; |
EP2FIFOPFL = 4; |
SYNCDELAY; |
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//EP2GPIFFLGSEL = bmFLAG_PROGRAMMABLE; |
EP2GPIFFLGSEL = bmFLAG_EMPTY; |
EP2GPIFFLGSEL = bmFLAG_PROGRAMMABLE; |
//EP2GPIFFLGSEL = bmFLAG_EMPTY; |
SYNCDELAY; |
EP6GPIFFLGSEL = bmFLAG_FULL; |
SYNCDELAY; |
286,7 → 284,6
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#ifdef GECKO3MAIN |
//EP2FIFOCFG &= ~bmOEP; |
EP2FIFOCFG &= ~bmAUTOOUT; /* disable AutoOUT feature */ |
SYNCDELAY; |
//EP6FIFOCFG &= ~bmINFM; |
/gpif-design/gecko3main_fifo_transfer.gpf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/gpif-design/gecko3main_gpif.c
103,18 → 103,18
// DataMode NO Data NO Data NO Data Activate Activate NO Data NO Data |
// NextData SameData SameData SameData SameData NextData SameData SameData |
// Int Trig No Int No Int No Int No Int Trig Int No Int No Int |
// IF/Wait IF Wait 2 Wait 1 IF Wait 1 IF IF |
// Term A WRX WRX WRX WRX |
// LFunc AND AND AND AND |
// Term B WRX WRX WRX WRX |
// Branch1 Then 1 Then 3 ThenIdle ThenIdle |
// Branch0 Else 0 Else 4 ElseIdle ElseIdle |
// Re-Exec No Yes No Yes |
// IF/Wait IF IF Wait 1 IF Wait 1 IF IF |
// Term A WRX WRX RDYX WRX WRX |
// LFunc AND AND !A AND B AND AND |
// Term B WRX RDYX WRX WRX WRX |
// Branch1 Then 1 Then 0 Then 3 ThenIdle ThenIdle |
// Branch0 Else 0 Else 2 Else 4 ElseIdle ElseIdle |
// Re-Exec No Yes Yes No Yes |
// Sngl/CRC Default Default Default Default Default Default Default |
// RDYU 0 0 0 0 0 0 0 0 |
// WRU 0 0 0 0 0 0 0 0 |
// RDYU 0 0 1 1 1 0 0 0 |
// X2U_ex 0 1 1 1 1 0 0 0 |
// X2U_ex 0 0 1 1 1 0 0 0 |
// U2X_th 0 0 0 0 0 0 0 0 |
// unused 0 0 0 0 0 0 0 0 |
// |
130,13 → 130,13
// DataMode NO Data NO Data NO Data Activate Activate Activate NO Data |
// NextData SameData SameData SameData SameData NextData NextData SameData |
// Int Trig No Int No Int No Int No Int No Int Trig Int No Int |
// IF/Wait IF Wait 1 IF Wait 1 IF IF IF |
// Term A WRX WRX FIFOFlag RDYX WRX |
// LFunc AND AND AND AND AND |
// Term B WRX WRX FIFOFlag RDYX WRX |
// Branch1 ThenIdle Then 2 Then 5 Then 5 ThenIdle |
// Branch0 Else 1 Else 3 Else 4 ElseIdle ElseIdle |
// Re-Exec No No Yes No No |
// IF/Wait IF Wait 1 IF IF IF IF IF |
// Term A WRX WRX RDYX FIFOFlag RDYX WRX |
// LFunc AND AND AND AND AND AND |
// Term B WRX WRX RDYX FIFOFlag RDYX WRX |
// Branch1 ThenIdle Then 2 Then 4 Then 4 Then 5 ThenIdle |
// Branch0 Else 1 Else 3 Else 3 Else 5 ElseIdle ElseIdle |
// Re-Exec No No No Yes No No |
// Sngl/CRC Default Default Default Default Default Default Default |
// RDYU 0 0 0 0 0 0 0 0 |
// WRU 0 1 1 1 1 0 0 0 |
169,15 → 169,15
/* Output*/ 0x00, 0x02, 0x02, 0x06, 0x06, 0x06, 0x06, 0x00, |
/* LFun */ 0x40, 0x09, 0x0F, 0x09, 0x00, 0x00, 0x00, 0x3F, |
// Wave 2 |
/* LenBr */ 0x08, 0x02, 0x01, 0x9C, 0x01, 0x3F, 0xBF, 0x07, |
/* Opcode*/ 0x01, 0x00, 0x00, 0x03, 0x16, 0x01, 0x01, 0x00, |
/* Output*/ 0x00, 0x08, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00, |
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, |
/* LenBr */ 0x08, 0x82, 0x01, 0x9C, 0x01, 0x3F, 0xBF, 0x07, |
/* Opcode*/ 0x01, 0x01, 0x00, 0x03, 0x16, 0x01, 0x01, 0x00, |
/* Output*/ 0x00, 0x00, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00, |
/* LFun */ 0x00, 0x01, 0x00, 0xC8, 0x00, 0x00, 0x00, 0x3F, |
// Wave 3 |
/* LenBr */ 0x39, 0x01, 0x13, 0x01, 0xAC, 0x2F, 0x3F, 0x07, |
/* Opcode*/ 0x01, 0x00, 0x01, 0x02, 0x07, 0x17, 0x01, 0x00, |
/* LenBr */ 0x39, 0x01, 0x13, 0x23, 0xA5, 0x2F, 0x3F, 0x07, |
/* Opcode*/ 0x01, 0x00, 0x01, 0x03, 0x07, 0x17, 0x01, 0x00, |
/* Output*/ 0x00, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, |
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x36, 0x09, 0x00, 0x3F, |
/* LFun */ 0x00, 0x00, 0x00, 0x09, 0x36, 0x09, 0x00, 0x3F, |
}; |
// END DO NOT EDIT |
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187,7 → 187,7
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
/* Wave 2 FlowStates */ 0x83,0x36,0x04,0x00,0x03,0x23,0x03,0x02,0x00, |
/* Wave 3 FlowStates */ 0x84,0x09,0x02,0x02,0x04,0x23,0x03,0x02,0x00, |
/* Wave 3 FlowStates */ 0x84,0x09,0x02,0x02,0x04,0x24,0x03,0x02,0x00, |
}; |
// END DO NOT EDIT |
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