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URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /gecko3/trunk/GECKO3COM/gecko3com-fw/firmware
    from Rev 19 to Rev 20
    ↔ Reverse comparison
  •

Rev 19 → Rev 20

/include/gecko3com_regs.h
114,6 → 114,17
#define bmXILINX_BUSY bmBIT1 /**< bitmask to access busy */
 
 
/* define pinning of the GPIF interface RDY signals
accessible in the GPIFREADYSTAT register */
#define bmWRX bmBIT0 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */
#define bmRDYX bmBIT1 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx
 
/* define pinning of the GPIF interface CTL signals
accessible while the GPIF is in the IDLE state through the
GPIFIDLECTL register */
#define bmWRU bmBIT1 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */
#define bmRDYU bmBIT2 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx
 
/*
* Port A (bit addressable):
*/
/src/gecko3com_main.c
744,8 → 744,13
* After this command all endpoint 2 and 6 data goes directly to the
* FPGA, the FX2 doesn't parse commands anymore. Use endpoint 0 TMC
* commands to switch back */
init_gpif();
flLOCAL = GECKO3COM_REMOTE;
if(fpga_done()) {
init_gpif();
flLOCAL = GECKO3COM_REMOTE;
}
else {
ieee488_status.EventStatusRegister |= bmEXECUTION_ERROR;
}
usb_tmc_state = TMC_STATE_IDLE;
break;
 
848,11 → 853,22
}
} /* end of IN Transfer clause */
 
/* if we operate in REMOTE mode (means we pass the data to the FPGA)
* continously check the DONE pin from the FPGA, to avoid that bad things
* happen when someone reconfigures the FPGA through JTAG */
if(flLOCAL == GECKO3COM_REMOTE && !fpga_done()) {
deactivate_gpif();
flLOCAL = GECKO3COM_LOCAL;
}
 
 
/* if the LED flag is set to off, disable the external LED */
if(flLED == LEDS_OFF) {
set_led_ext(LEDS_OFF);
}
 
 
/* resets the watchdog timer back to the initial value */
watchdog_count = WATCHDOG_TIME;
 
/src/gecko3com_gpif.c
83,7 → 83,7
 
 
/**
* \brief exectuted when the gpif wafeform terminates
* \brief exectuted when the gpif waveform terminates
*/
void
isr_gpif_done (void) interrupt
90,19 → 90,24
{
ISR_DEBUG_PORT |= bmGPIF_DONE;
 
/* check if this is a end of a IN transfer */
if((flGPIF & bmGPIF_READ_IN_PROGRESS) == bmGPIF_READ_IN_PROGRESS){
INPKTEND = USB_TMC_EP_IN;
}
 
while(!(GPIFTRIG & bmGPIF_IDLE));
 
/* check if there is data available for an OUT transfer */
/*if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
//if(!(EP2468STAT & bmEP2EMPTY)) {
flGPIF &= ~bmGPIF_PENDING_DATA;
GPIFABORT = 0xFF;
SYNCDELAY;
gpif_trigger_write();
flGPIF &= ~bmGPIF_READ_IN_PROGRESS;
}
else*/ {
/* check if this is a end of a IN transfer */
//INPKTEND = USB_TMC_EP_IN;
while(!(GPIFTRIG & bmGPIF_IDLE));
gpif_trigger_read();
else {
gpif_trigger_read();
flGPIF |= bmGPIF_READ_IN_PROGRESS;
}
 
clear_fifo_gpif_irq();
120,14 → 125,15
ISR_DEBUG_PORT |= bmFIFO_PF;
 
/* check if there is a active IN transfer */
/*if((GPIFIDLECTL & bmBIT3) == bmBIT3) {
if((GPIFREADYSTAT & bmWRX) == bmWRX) {
flGPIF |= bmGPIF_PENDING_DATA;
}
else*/ {
else {
GPIFABORT = 0xFF;
SYNCDELAY;
while(!(GPIFTRIG & bmGPIF_IDLE));
gpif_trigger_write();
flGPIF &= ~bmGPIF_READ_IN_PROGRESS;
}
 
clear_fifo_gpif_irq();
229,27 → 235,28
/** \brief aborts any gpif running gpif transaction */
void abort_gpif(void) {
 
#ifdef GECKO3MAIN
/* signal an abort condition to the FPGA */
//if(!(GPIFTRIG & bmGPIF_IDLE)) {
//GPIFREADYCFG &= ~bmINTRDY;
//udelay(10);
//}
#endif
EA = 0; /* disable all interrupts */
flGPIF = 0;
 
/* abort the current GPIF waveform */
GPIFABORT = 0xFF;
SYNCDELAY;
while(!(GPIFTRIG & bmGPIF_IDLE));
//print_info("gpif aborted\n");
 
EA = 1; /* global interrupt enable */
 
//print_info("gpif aborted\n");
 
#ifdef GECKO3MAIN
/* signal an abort condition to the FPGA (both WRU and RDYU high) */
GPIFIDLECTL |= bmRDYU | bmWRU;
udelay(10);
GPIFIDLECTL = InitData[ 3 ]; /* restore original state */
#endif
 
gpif_trigger_read();
flGPIF |= bmGPIF_READ_IN_PROGRESS;
}
 
 
256,18 → 263,8
/** \brief disables gpif system */
void deactivate_gpif(void) {
 
#ifdef GECKO3MAIN
/* signal an abort condition to the FPGA */
//if(!(GPIFTRIG & bmGPIF_IDLE)) {
//GPIFREADYCFG &= ~bmINTRDY;
//udelay(10);
//}
#endif
EA = 0; /* disable all interrupts */
 
 
EA = 0; /* disable all interrupts */
 
EP2FIFOIE = 0; /* disable FIFO interrupt */
SYNCDELAY;
GPIFIE = 0; /* disable all GPIF interrupts */
282,17 → 279,21
 
flGPIF = 0; /* unset all internal GPIF flags */
 
EA = 1; /* global interrupt enable */
 
while(!(GPIFTRIG & bmGPIF_IDLE));
 
#ifdef GECKO3MAIN
/* signal an abort condition to the FPGA (both WRU and RDYU high) */
GPIFIDLECTL |= bmRDYU | bmWRU;
udelay(10);
GPIFIDLECTL = InitData[ 3 ]; /* restore original state */
 
EP2FIFOCFG &= ~bmAUTOOUT; /* disable AutoOUT feature */
SYNCDELAY;
//EP6FIFOCFG &= ~bmINFM;
EP6FIFOCFG &= ~bmAUTOIN; /* disable AutoIN feature */
 
#endif
 
EA = 1; /* global interrupt enable */
 
 
//print_info("gpif deactivated\n");
}
/gpif-design/gecko3main_fifo_transfer.gpf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/gpif-design/gecko3main_gpif.c
103,13 → 103,13
// DataMode NO Data NO Data NO Data Activate Activate NO Data NO Data
// NextData SameData SameData SameData SameData NextData SameData SameData
// Int Trig No Int No Int No Int No Int Trig Int No Int No Int
// IF/Wait IF IF Wait 1 IF Wait 1 IF IF
// Term A WRX WRX RDYX WRX WRX
// LFunc AND AND !A AND B AND AND
// Term B WRX RDYX WRX WRX WRX
// Branch1 Then 1 Then 0 Then 3 ThenIdle ThenIdle
// Branch0 Else 0 Else 2 Else 4 ElseIdle ElseIdle
// Re-Exec No Yes Yes No Yes
// IF/Wait IF IF Wait 2 IF Wait 1 IF IF
// Term A RDYX RDYX WRX WRX WRX
// LFunc !A AND B !A AND B AND AND AND
// Term B WRX WRX WRX WRX WRX
// Branch1 Then 1 Then 2 Then 3 ThenIdle ThenIdle
// Branch0 Else 0 Else 0 Else 4 ElseIdle ElseIdle
// Re-Exec No No Yes No Yes
// Sngl/CRC Default Default Default Default Default Default Default
// RDYU 0 0 0 0 0 0 0 0
// WRU 0 0 0 0 0 0 0 0
169,10 → 169,10
/* Output*/ 0x00, 0x02, 0x02, 0x06, 0x06, 0x06, 0x06, 0x00,
/* LFun */ 0x40, 0x09, 0x0F, 0x09, 0x00, 0x00, 0x00, 0x3F,
// Wave 2
/* LenBr */ 0x08, 0x82, 0x01, 0x9C, 0x01, 0x3F, 0xBF, 0x07,
/* LenBr */ 0x08, 0x10, 0x02, 0x9C, 0x01, 0x3F, 0xBF, 0x07,
/* Opcode*/ 0x01, 0x01, 0x00, 0x03, 0x16, 0x01, 0x01, 0x00,
/* Output*/ 0x00, 0x00, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00,
/* LFun */ 0x00, 0x01, 0x00, 0xC8, 0x00, 0x00, 0x00, 0x3F,
/* LFun */ 0xC8, 0xC8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
// Wave 3
/* LenBr */ 0x39, 0x01, 0x13, 0x23, 0xA5, 0x2F, 0x3F, 0x07,
/* Opcode*/ 0x01, 0x00, 0x01, 0x03, 0x07, 0x17, 0x01, 0x00,
186,7 → 186,7
{
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 2 FlowStates */ 0x83,0x36,0x04,0x00,0x03,0x23,0x03,0x02,0x00,
/* Wave 2 FlowStates */ 0x83,0x4E,0x04,0x00,0x04,0x03,0x03,0x02,0x00,
/* Wave 3 FlowStates */ 0x84,0x09,0x02,0x02,0x04,0x24,0x03,0x02,0x00,
};
// END DO NOT EDIT

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