URL
https://opencores.org/ocsvn/gecko3/gecko3/trunk
Subversion Repositories gecko3
Compare Revisions
- This comparison shows the changes necessary to convert path
/gecko3/trunk/GECKO3COM/gecko3com-ip/core
- from Rev 20 to Rev 21
- ↔ Reverse comparison
Rev 20 → Rev 21
/gecko3com_test_chipscope.cdc
1,5 → 1,5
#ChipScope Core Inserter Project File Version 3.0 |
#Tue Jan 26 16:27:50 CET 2010 |
#Wed Jan 27 15:45:20 CET 2010 |
Project.device.designInputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc |
Project.device.designOutputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc |
Project.device.deviceFamily=6 |
18,14 → 18,14
Project.unit<0>.clockChannel=i_IFCLK_BUFGP |
Project.unit<0>.clockEdge=Rising |
Project.unit<0>.dataChannel<0>=o_WRX_OBUF |
Project.unit<0>.dataChannel<10>=GPIF_INTERFACE s_dbus_out<8> |
Project.unit<0>.dataChannel<11>=GPIF_INTERFACE s_dbus_out<9> |
Project.unit<0>.dataChannel<12>=GPIF_INTERFACE s_dbus_out<10> |
Project.unit<0>.dataChannel<13>=GPIF_INTERFACE s_dbus_out<11> |
Project.unit<0>.dataChannel<14>=GPIF_INTERFACE s_dbus_out<12> |
Project.unit<0>.dataChannel<15>=GPIF_INTERFACE s_dbus_out<13> |
Project.unit<0>.dataChannel<16>=GPIF_INTERFACE s_dbus_out<14> |
Project.unit<0>.dataChannel<17>=GPIF_INTERFACE s_dbus_out<15> |
Project.unit<0>.dataChannel<10>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd9 |
Project.unit<0>.dataChannel<11>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd10 |
Project.unit<0>.dataChannel<12>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd11 |
Project.unit<0>.dataChannel<13>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd12 |
Project.unit<0>.dataChannel<14>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd13 |
Project.unit<0>.dataChannel<15>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd14 |
Project.unit<0>.dataChannel<16>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd15 |
Project.unit<0>.dataChannel<17>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd16 |
Project.unit<0>.dataChannel<18>=GPIF_INTERFACE s_dbus_trans_dir |
Project.unit<0>.dataChannel<19>=GPIF_INTERFACE o_RX |
Project.unit<0>.dataChannel<1>=i_RDYU_IBUF |
39,7 → 39,7
Project.unit<0>.dataChannel<27>=s_RX_DATA<2> |
Project.unit<0>.dataChannel<28>=s_RX_DATA<3> |
Project.unit<0>.dataChannel<29>=s_RX_DATA<4> |
Project.unit<0>.dataChannel<2>=GPIF_INTERFACE s_dbus_out<0> |
Project.unit<0>.dataChannel<2>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd1 |
Project.unit<0>.dataChannel<30>=s_RX_DATA<5> |
Project.unit<0>.dataChannel<31>=s_RX_DATA<6> |
Project.unit<0>.dataChannel<32>=s_RX_DATA<7> |
50,7 → 50,7
Project.unit<0>.dataChannel<37>=s_RX_DATA<12> |
Project.unit<0>.dataChannel<38>=s_RX_DATA<13> |
Project.unit<0>.dataChannel<39>=s_RX_DATA<14> |
Project.unit<0>.dataChannel<3>=GPIF_INTERFACE s_dbus_out<1> |
Project.unit<0>.dataChannel<3>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd2 |
Project.unit<0>.dataChannel<40>=s_RX_DATA<15> |
Project.unit<0>.dataChannel<41>=s_EMPTY |
Project.unit<0>.dataChannel<42>=i_WRU_IBUF |
58,12 → 58,13
Project.unit<0>.dataChannel<44>=s_RD_EN |
Project.unit<0>.dataChannel<45>=GPIF_INTERFACE i_EOM |
Project.unit<0>.dataChannel<46>=GPIF_INTERFACE s_X2U_FULL_IFCLK |
Project.unit<0>.dataChannel<4>=GPIF_INTERFACE s_dbus_out<2> |
Project.unit<0>.dataChannel<5>=GPIF_INTERFACE s_dbus_out<3> |
Project.unit<0>.dataChannel<6>=GPIF_INTERFACE s_dbus_out<4> |
Project.unit<0>.dataChannel<7>=GPIF_INTERFACE s_dbus_out<5> |
Project.unit<0>.dataChannel<8>=GPIF_INTERFACE s_dbus_out<6> |
Project.unit<0>.dataChannel<9>=GPIF_INTERFACE s_dbus_out<7> |
Project.unit<0>.dataChannel<47>= |
Project.unit<0>.dataChannel<4>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd3 |
Project.unit<0>.dataChannel<5>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd4 |
Project.unit<0>.dataChannel<6>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd5 |
Project.unit<0>.dataChannel<7>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd6 |
Project.unit<0>.dataChannel<8>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd7 |
Project.unit<0>.dataChannel<9>=GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd8 |
Project.unit<0>.dataDepth=512 |
Project.unit<0>.dataEqualsTrigger=false |
Project.unit<0>.dataPortWidth=47 |
/gpif_com_fsm.vhd
149,6 → 149,7
-- comb logic |
transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL, |
i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM) |
variable state_number : std_logic_vector(3 downto 0); -- debug information |
begin -- process transaction |
|
-- default signal values to avoid latches: |
167,6 → 168,7
-- controll |
|
when rst => |
state_number := x"1"; |
-- output signal values: |
s_FIFOrst <= '1'; |
s_WRX <= '0'; |
186,6 → 188,7
end if; |
|
when idle => |
state_number := x"2"; |
-- output signal values: |
s_FIFOrst <= '0'; |
s_WRX <= '0'; |
209,6 → 212,7
----------------------------------------------------------------------- |
-- in trans |
when inRQ => |
state_number := x"3"; |
-- output signal values: |
s_WRX <= '0'; |
s_RDYX <= '0'; |
225,6 → 229,7
end if; |
|
when inACK => |
state_number := x"4"; |
-- output signal values: |
s_WRX <= '0'; |
s_RDYX <= '1'; |
242,6 → 247,7
end if; |
|
when inWait => |
state_number := x"5"; |
-- output signal values: |
s_WRX <= '0'; |
s_RDYX <= '1'; |
252,6 → 258,7
nx_state <= inTrans; |
|
when inTrans => |
state_number := x"6"; |
-- output signal values: |
s_WRX <= '0'; |
s_RDYX <= '1'; |
270,6 → 277,7
end if; |
|
when inThrot => |
state_number := x"7"; |
-- output signal values: |
s_WRX <= '0'; |
s_RDYX <= '0'; |
289,6 → 297,7
end if; |
|
when inThrotBreak => |
state_number := x"8"; |
-- this is a one clock delay to help the fx2 to see the RDYX signal. |
|
-- output signal values: |
314,6 → 323,7
-- nx_state <= inThrotEnd; |
|
when inThrotEnd => |
state_number := x"9"; |
-- this is a one clock delay to help the fx2 to see the RDYX signal. |
|
-- output signal values: |
326,6 → 336,7
nx_state <= inTrans; |
|
when endInTrans => |
state_number := x"A"; |
-- output signal values: |
s_WRX <= '0'; |
s_RDYX <= '0'; |
338,6 → 349,7
----------------------------------------------------------------------- |
-- out trans |
when outRQ => |
state_number := x"B"; |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '0'; |
353,6 → 365,7
end if; |
|
when outACK => |
state_number := x"C"; |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '0'; |
369,6 → 382,7
end if; |
|
when outTrans => |
state_number := x"D"; |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '0'; |
390,6 → 404,7
end if; |
|
when outUSBwait => |
state_number := x"E"; |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '0'; |
407,6 → 422,7
end if; |
|
when outFIFOwait => |
state_number := x"F"; |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '1'; |
426,6 → 442,7
end if; |
|
when endOutTrans => |
state_number := x"9"; |
-- output signal values: |
s_RDYX <= '0'; |
s_WRX <= '0'; |
/chipscope-analyzer.cpj
1,5 → 1,5
#ChipScope Pro Analyzer Project File, Version 3.0 |
#Tue Jan 26 21:37:40 CET 2010 |
#Wed Jan 27 19:37:15 CET 2010 |
deviceChain.deviceName0=XC3S1500 |
deviceChain.iRLength0=6 |
deviceChain.name0=MyDevice0 |
33,7 → 33,7
unit.0.0.1.WIDTH1=0.9352014 |
unit.0.0.1.X1=0.030647986 |
unit.0.0.1.Y1=0.15781711 |
unit.0.0.MFBitsA0=X1XXXXX |
unit.0.0.MFBitsA0=1XXXXXX |
unit.0.0.MFBitsB0=0000000 |
unit.0.0.MFCompareA0=0 |
unit.0.0.MFCompareB0=999 |
63,7 → 63,7
unit.0.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.-1.b.0.name=/GPIF_INTERFACE/s_dbus_out |
unit.0.0.port.-1.b.0.orderindex=-1 |
unit.0.0.port.-1.b.0.radix=Hex |
unit.0.0.port.-1.b.0.radix=Bin |
unit.0.0.port.-1.b.0.signedOffset=0.0 |
unit.0.0.port.-1.b.0.signedPrecision=0 |
unit.0.0.port.-1.b.0.signedScaleFactor=1.0 |
410,7 → 410,7
unit.0.0.waveform.posn.14.type=signal |
unit.0.0.waveform.posn.15.channel=2147483646 |
unit.0.0.waveform.posn.15.name=/GPIF_INTERFACE/s_dbus_out |
unit.0.0.waveform.posn.15.radix=1 |
unit.0.0.waveform.posn.15.radix=0 |
unit.0.0.waveform.posn.15.type=bus |
unit.0.0.waveform.posn.16.channel=2147483646 |
unit.0.0.waveform.posn.16.name=/s_RX_DATA |