OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /gecko3/trunk/GECKO3COM/gecko3com-ip
    from Rev 27 to Rev 28
    ↔ Reverse comparison
  •

Rev 27 → Rev 28

/core/GECKO3COM_simple_prototype.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/core/GECKO3COM_simple.xise
19,7 → 19,6
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_dualclock.xco" xil_pn:type="FILE_COREGEN"/>
<file xil_pn:name="fifo_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
46,9 → 45,6
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="gecko3com_test_chipscope.cdc" xil_pn:type="FILE_CDC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_simple.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
81,10 → 77,19
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_dualclock.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_simple_test.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_simple_test.cdc" xil_pn:type="FILE_CDC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3main_v1.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_dualclock.ise" xil_pn:type="FILE_COREGENISE"/>
<file xil_pn:name="coregenerator/coregenerator_fifo_receive.ise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
91,6 → 96,9
<file xil_pn:name="coregenerator/coregenerator_fifo_send.ise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_dualclock.ise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
</files>
 
<properties>
102,25 → 110,43
<property xil_pn:name="Device" xil_pn:value="xc3s4000"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="Editor" xil_pn:value="Custom"/>
<property xil_pn:name="Extra Effort" xil_pn:value="Normal" xil_pn:x_locked="true"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:x_locked="true"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gpif_com_test|behaviour"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gpif_com_test"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|GECKO3COM_simple_test|behavour"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/GECKO3COM_simple_test"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance without IOB Packing;/home/chrigi/bin/11.1/ISE/spartan3/data/spartan3_performance_without_iobpacking.xds"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:x_locked="true"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|GECKO3COM_simple|Behavioral"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="usb_tmc_com"/>
<property xil_pn:name="PROP_mapSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="PROP_parSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:x_locked="true"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:x_locked="true"/>
<property xil_pn:name="Package" xil_pn:value="fg676"/>
<property xil_pn:name="Perform Timing-Driven Packing" xil_pn:value="true" xil_pn:x_locked="true"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:x_locked="true"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:x_locked="true"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:x_locked="true"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:x_locked="true"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false"/>
<property xil_pn:name="Report Type" xil_pn:value="Error Report"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="yes"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:x_locked="true"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="Yes"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Architecture|GECKO3COM_simple|Behavioral"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Architecture|gpif_com_test_tb|simulation"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="DUT"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="1 ns"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="2000ns"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
127,6 → 153,7
<property xil_pn:name="Simulator Path" xil_pn:value="/opt/mentorGraphics/modeltech/bin/"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="GECKO3COM_simple_test.ucf"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="GECKO3COM.ipf"/>
133,14 → 160,15
</properties>
 
<bindings>
<binding xil_pn:location="/gpif_com_test" xil_pn:name="gecko3com_test_chipscope.cdc"/>
<binding xil_pn:location="/gpif_com_test" xil_pn:name="GECKO3main_v1.ucf"/>
<binding xil_pn:location="/gpif_com_test" xil_pn:name="GECKO3COM_simple_test.ucf"/>
<binding xil_pn:location="/GECKO3COM_simple_test" xil_pn:name="GECKO3COM_simple_test.cdc"/>
<binding xil_pn:location="/GECKO3COM_simple_test" xil_pn:name="GECKO3main_v1.ucf"/>
</bindings>
 
<libraries/>
 
<partitions>
<partition xil_pn:name="/gpif_com_test"/>
<partition xil_pn:name="/GECKO3COM_simple_test"/>
</partitions>
 
</project>
/core/GECKO3main_v1.ucf
74,10 → 74,10
 
 
# switches
net "i_mode_switch<0>" loc = "C5";
net "i_mode_switch<1>" loc = "D5";
net "i_mode_switch<2>" loc = "E5";
#net "i_mode_switch<3>" loc = "C4";
net "i_mode_switch<0>" loc = "D7";
net "i_mode_switch<1>" loc = "F7";
net "i_mode_switch<2>" loc = "C6";
#net "i_mode_switch<3>" loc = "D6";
 
# LEDs
 
/core/GECKO3COM_simple.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/core/gpif_com_fsm.vhd
91,11 → 91,13
 
type t_fsmState is (rst, idle, -- controll states
-- in com states
inRQ, inACK, inWait, inTrans, inThrot,
inThrotBreak,inThrotBreak2, inThrotEnd,
endInTrans, -- in com states
outRQ, outRQdelay, outTrans, outACK, outUSBwait,
outFIFOwait, endOutTrans); -- out com states
inThrotBreak, inThrotEnd,
endInTrans,
-- out com states
outRQ, outRQdelay, outTrans, outACK, outACKwait,
outUSBwait, outUSBwaitEnd, outFIFOwait, endOutTrans);
 
147,7 → 149,6
-- comb logic
transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
variable state_number : std_logic_vector(3 downto 0); -- debug information
begin -- process transaction
 
-- default signal values to avoid latches:
166,7 → 167,6
-- controll
 
when rst =>
state_number := x"1";
-- output signal values:
s_FIFOrst <= '1';
s_WRX <= '0';
186,7 → 186,6
end if;
when idle =>
state_number := x"2";
-- output signal values:
s_FIFOrst <= '0';
s_WRX <= '0';
209,11 → 208,10
 
-----------------------------------------------------------------------
-- in trans
when inRQ =>
state_number := x"3";
when inRQ =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
o_RX <= '0';
227,7 → 225,6
end if;
 
when inACK =>
state_number := x"4";
-- output signal values:
s_WRX <= '0';
s_RDYX <= '1';
238,7 → 235,6
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '1' then
--nx_state <= inTrans;
nx_state <= inWait;
else
nx_state <= endInTrans;
245,7 → 241,6
end if;
 
when inWait =>
state_number := x"5";
-- output signal values:
s_WRX <= '0';
s_RDYX <= '1';
256,7 → 251,6
nx_state <= inTrans;
when inTrans =>
state_number := x"6";
-- output signal values:
s_WRX <= '0';
s_RDYX <= '1';
275,7 → 269,6
end if;
 
when inThrot =>
state_number := x"7";
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
295,7 → 288,6
end if;
 
when inThrotBreak =>
state_number := x"8";
-- this is a one clock delay to help the fx2 to see the RDYX signal.
-- output signal values:
305,23 → 297,9
o_RX <= '1';
 
-- state decisions
--nx_state <= inThrotBreak2;
nx_state <= inThrotEnd;
 
--when inThrotBreak2 =>
-- -- this is a one clock delay to help the fx2 to see the RDYX signal.
-- -- output signal values:
-- s_WRX <= '0';
-- s_RDYX <= '1';
-- s_U2X_WR_EN <= '0';
-- o_RX <= '1';
 
-- -- state decisions
-- nx_state <= inThrotEnd;
when inThrotEnd =>
state_number := x"9";
-- this is a one clock delay to help the fx2 to see the RDYX signal.
-- output signal values:
334,7 → 312,6
nx_state <= inTrans;
when endInTrans =>
state_number := x"A";
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
347,7 → 324,6
-----------------------------------------------------------------------
-- out trans
when outRQ =>
state_number := x"B";
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
377,8 → 353,7
nx_state <= outACK;
end if;
 
when outACK =>
state_number := x"C";
when outACK =>
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
391,11 → 366,26
elsif i_WRU = '0' and i_RDYU = '1' then
nx_state <= outTrans;
else
nx_state <= outUSBwait;
nx_state <= outACKwait;
end if;
 
when outACKwait =>
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
s_X2U_RD_EN <= '0';
o_TX <= '1';
 
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '0' and i_RDYU = '1' then
nx_state <= outTrans;
else
nx_state <= outACKwait;
end if;
 
when outTrans =>
state_number := x"D";
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
413,11 → 403,10
elsif i_WRU = '0' and i_RDYU = '1' then
nx_state <= outTrans;
else
nx_state <= outUSBwait;
nx_state <= outUSBwait;
end if;
 
when outUSBwait =>
state_number := x"E";
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
431,13 → 420,23
elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
nx_state <= endOutTrans;
elsif i_WRU = '0' and i_RDYU = '1' then
nx_state <= outTrans;
nx_state <= outUSBwaitEnd;
else
nx_state <= outUSBwait;
end if;
 
when outUSBwaitEnd =>
-- output signal values:
s_WRX <= '1';
s_RDYX <= '1';
s_X2U_RD_EN <= '0';
o_TX <= '1';
s_bus_trans_dir <= writeToGPIF;
 
-- state decisions
nx_state <= outTrans;
when outFIFOwait =>
state_number := x"F";
-- output signal values:
s_WRX <= '1';
s_RDYX <= '1';
457,7 → 456,6
end if;
when endOutTrans =>
state_number := x"9";
-- output signal values:
s_RDYX <= '0';
s_WRX <= '0';
/core/GECKO3COM_simple_fsm.vhd
142,7 → 142,6
begin -- fsm
 
o_receive_fifo_wr_en <= s_receive_fifo_wr_en;
o_receive_fifo_reset <= s_receive_fifo_reset;
o_receive_transfersize_en <= s_receive_transfersize_en;
o_receive_counter_load <= s_receive_counter_load;
o_receive_counter_en <= s_receive_counter_en;
149,7 → 148,6
o_btag_reg_en <= s_btag_reg_en;
o_nbtag_reg_en <= s_nbtag_reg_en;
o_send_fifo_rd_en <= s_send_fifo_rd_en;
o_send_fifo_reset <= s_send_fifo_reset;
o_send_counter_load <= s_send_counter_load;
o_send_counter_en <= s_send_counter_en;
o_send_mux_sel <= s_send_mux_sel;
167,8 → 165,14
if (i_sysclk'event and i_sysclk = '1') then
if (i_nReset = '0') then
state <= st1_idle;
 
o_receive_fifo_reset <= '0';
o_send_fifo_reset <= '0';
else
state <= next_state;
 
o_receive_fifo_reset <= s_receive_fifo_reset;
o_send_fifo_reset <= s_send_fifo_reset;
end if;
end if;
end process;
272,9 → 276,9
s_send_counter_load <= '1';
end if;
 
if (state = st21_send_reserved and i_gpif_tx_full = '0' and
i_send_fifo_empty = '0')
or (state = st22_send_data and
if --(state = st21_send_reserved and i_gpif_tx_full = '0' and
--i_send_fifo_empty = '0')
(state = st22_send_data and
i_gpif_tx_full = '0' and
i_send_fifo_empty = '0' and
i_send_counter_zero = '0')
/core/GECKO3COM_simple_test.cdc
1,5 → 1,5
#ChipScope Core Inserter Project File Version 3.0
#Mon Feb 22 22:07:31 CET 2010
#Wed Feb 24 16:47:27 CET 2010
Project.device.designInputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_test_cs.ngc
Project.device.designOutputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_test_cs.ngc
Project.device.deviceFamily=6
104,35 → 104,35
Project.unit<0>.dataChannel<44>=GECKO3COM_simple_1 GECKO3COM_simple_fsm_1 state_FSM_FFd3
Project.unit<0>.dataChannel<45>=GECKO3COM_simple_1 GECKO3COM_simple_fsm_1 state_FSM_FFd4
Project.unit<0>.dataChannel<46>=GECKO3COM_simple_1 GECKO3COM_simple_fsm_1 state_FSM_FFd5
Project.unit<0>.dataChannel<47>=s_send_counter_equals_transfer_size
Project.unit<0>.dataChannel<47>=s_transfer_size_reg_en
Project.unit<0>.dataChannel<48>=s_send_transfersize_en
Project.unit<0>.dataChannel<49>=s_send_fifo_data<0>
Project.unit<0>.dataChannel<49>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<0>
Project.unit<0>.dataChannel<4>=GECKO3COM_simple_1 o_receive_end_of_message
Project.unit<0>.dataChannel<50>=s_send_fifo_data<1>
Project.unit<0>.dataChannel<51>=s_send_fifo_data<2>
Project.unit<0>.dataChannel<52>=s_send_fifo_data<3>
Project.unit<0>.dataChannel<53>=s_send_fifo_data<4>
Project.unit<0>.dataChannel<54>=s_send_fifo_data<5>
Project.unit<0>.dataChannel<55>=s_send_fifo_data<6>
Project.unit<0>.dataChannel<56>=s_send_fifo_data<7>
Project.unit<0>.dataChannel<57>=s_send_fifo_data<8>
Project.unit<0>.dataChannel<58>=s_send_fifo_data<9>
Project.unit<0>.dataChannel<59>=s_send_fifo_data<10>
Project.unit<0>.dataChannel<50>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<1>
Project.unit<0>.dataChannel<51>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<2>
Project.unit<0>.dataChannel<52>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<3>
Project.unit<0>.dataChannel<53>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<4>
Project.unit<0>.dataChannel<54>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<5>
Project.unit<0>.dataChannel<55>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<6>
Project.unit<0>.dataChannel<56>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<7>
Project.unit<0>.dataChannel<57>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<8>
Project.unit<0>.dataChannel<58>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<9>
Project.unit<0>.dataChannel<59>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<10>
Project.unit<0>.dataChannel<5>=GECKO3COM_simple_1 o_receive_fifo_empty
Project.unit<0>.dataChannel<60>=s_send_fifo_data<11>
Project.unit<0>.dataChannel<61>=s_send_fifo_data<12>
Project.unit<0>.dataChannel<62>=s_send_fifo_data<13>
Project.unit<0>.dataChannel<63>=s_send_fifo_data<14>
Project.unit<0>.dataChannel<64>=s_send_fifo_data<15>
Project.unit<0>.dataChannel<65>=s_send_fifo_data<16>
Project.unit<0>.dataChannel<66>=s_send_fifo_data<17>
Project.unit<0>.dataChannel<67>=s_send_fifo_data<18>
Project.unit<0>.dataChannel<68>=s_send_fifo_data<19>
Project.unit<0>.dataChannel<69>=s_send_fifo_data<20>
Project.unit<0>.dataChannel<60>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<11>
Project.unit<0>.dataChannel<61>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<12>
Project.unit<0>.dataChannel<62>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<13>
Project.unit<0>.dataChannel<63>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<14>
Project.unit<0>.dataChannel<64>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 s_send_fifo_data<15>
Project.unit<0>.dataChannel<65>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 i_rx_data<0>
Project.unit<0>.dataChannel<66>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 i_rx_data<1>
Project.unit<0>.dataChannel<67>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 i_rx_data<2>
Project.unit<0>.dataChannel<68>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 i_rx_data<3>
Project.unit<0>.dataChannel<69>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 i_rx_data<4>
Project.unit<0>.dataChannel<6>=GECKO3COM_simple_1 o_receive_newdata
Project.unit<0>.dataChannel<70>=s_send_fifo_data<21>
Project.unit<0>.dataChannel<71>=s_send_fifo_data<22>
Project.unit<0>.dataChannel<72>=s_send_fifo_data<23>
Project.unit<0>.dataChannel<70>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 i_rx_data<5>
Project.unit<0>.dataChannel<71>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 i_rx_data<6>
Project.unit<0>.dataChannel<72>=GECKO3COM_simple_1 GECKO3COM_simple_datapath_1 i_rx_data<7>
Project.unit<0>.dataChannel<73>=s_send_have_more_data
Project.unit<0>.dataChannel<74>=GECKO3COM_simple_1 GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd1
Project.unit<0>.dataChannel<75>=GECKO3COM_simple_1 GPIF_INTERFACE FSM_GPIF pr_state_FSM_FFd2
178,7 → 178,7
Project.unit<0>.triggerChannel<0><2>=GECKO3COM_simple_1 s_request_dev_dep_msg_in
Project.unit<0>.triggerChannel<0><3>=GECKO3COM_simple_1 s_gpif_rx_rd_en
Project.unit<0>.triggerChannel<0><4>=GECKO3COM_simple_1 s_btag_reg_en
Project.unit<0>.triggerChannel<0><5>=GECKO3COM_simple_1 s_gpif_abort
Project.unit<0>.triggerChannel<0><5>=i_RDYU_IBUF
Project.unit<0>.triggerChannel<0><6>=s_send_data_request
Project.unit<0>.triggerChannel<0><7>=s_send_fifo_full
Project.unit<0>.triggerChannel<0><8>=GECKO3COM_simple_1 i_send_fifo_wr_en
/core/GECKO3COM_simple_prototype.xise
140,8 → 140,6
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false"/>
<property xil_pn:name="Report Type" xil_pn:value="Error Report"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="yes"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:x_locked="true"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="Yes"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Architecture|GECKO3COM_simple|Behavioral"/>
/core/GECKO3main_prototype.ucf
42,12 → 42,12
#net "i_SYSCLK" loc = "AA11"; # IFCLK, to test as a synchronus system
#net "i_SYSCLK" CLOCK_DEDICATED_ROUTE = FALSE; # also needed when IFCLK used as SYSCLK
net "i_SYSCLK" tnm_net = "SYSCLK";
timespec "TS_SYSCLK" = period "SYSCLK" 20.0 ns HIGH 50%; # 50 MHz system clock
timespec "TS_SYSCLK" = period "SYSCLK" 15.0 ns HIGH 50%; # 50 MHz system clock
 
net "i_IFCLK" loc = "AA11";
net "i_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
net "i_IFCLK" tnm_net = "IFCLK";
timespec "TS_IFCLK" = period "IFCLK" 20.83 ns HIGH 50%; # 48 MHz interface clock
timespec "TS_IFCLK" = period "IFCLK" 15.0 ns HIGH 50%; # 48 MHz interface clock
 
# connection of controll bus signals
net "i_WRU" loc = "AC5";
/core/GECKO3COM_simple_test.cpj
1,9 → 1,9
#ChipScope Pro Analyzer Project File, Version 3.0
#Mon Feb 22 18:02:47 CET 2010
deviceChain.deviceName0=XC3S1500
#Wed Feb 24 00:29:25 CET 2010
deviceChain.deviceName0=XC3S4000
deviceChain.iRLength0=6
deviceChain.name0=MyDevice0
deviceIds=01434093
deviceIds=01448093
import.certifyIdx=-1
import.dir=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/
import.filename=GECKO3COM_simple_test.cdc
34,7 → 34,7
unit.0.0.1.WIDTH1=1.0563822
unit.0.0.1.X1=-0.0031323414
unit.0.0.1.Y1=0.10463734
unit.0.0.MFBitsA0=XXXXX1XXXXXX
unit.0.0.MFBitsA0=XXXX1XXXXXXX
unit.0.0.MFBitsA1=XXXXXXXXXXXX
unit.0.0.MFBitsB0=000000000000
unit.0.0.MFBitsB1=000000000000
53,8 → 53,8
unit.0.0.TCActive=0
unit.0.0.TCAdvanced0=0
unit.0.0.TCCondition0_0=M0
unit.0.0.TCCondition0_1=M0
unit.0.0.TCConditionType0=0
unit.0.0.TCCondition0_1=M0 --> M0 --> M0 --> M0
unit.0.0.TCConditionType0=1
unit.0.0.TCCount=1
unit.0.0.TCEventCount0=1
unit.0.0.TCEventType0=3
77,7 → 77,7
unit.0.0.coretype=ILA
unit.0.0.eventCount0=1
unit.0.0.eventCount1=1
unit.0.0.port.-1.b.0.alias=/GECKO3COM_simple_1/s_gpif_rx_data
unit.0.0.port.-1.b.0.alias=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM
unit.0.0.port.-1.b.0.channellist=74 81 82 83 84 85 86 87 88 89 75 76 77 78 79 80
unit.0.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.b.0.name=/GECKO3COM_simple_1/s_gpif_rx_data
134,7 → 134,7
unit.0.0.port.-1.b.2.unsignedScaleFactor=1.0
unit.0.0.port.-1.b.2.visible=1
unit.0.0.port.-1.b.3.alias=GECKO3COM_simple_fsm_1/state_FSM_FFd1
unit.0.0.port.-1.b.3.channellist=46 45 44 43 42
unit.0.0.port.-1.b.3.channellist=42 43 44 45 46
unit.0.0.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.b.3.name=/GECKO3COM_simple_1/o_receive_transfersize
unit.0.0.port.-1.b.3.orderindex=-1
675,7 → 675,7
unit.0.0.port.-1.s.46.visible=1
unit.0.0.port.-1.s.47.alias=
unit.0.0.port.-1.s.47.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.47.name=/s_send_counter_equals_transfer_size
unit.0.0.port.-1.s.47.name=/s_transfer_size_reg_en
unit.0.0.port.-1.s.47.orderindex=-1
unit.0.0.port.-1.s.47.visible=1
unit.0.0.port.-1.s.48.alias=
825,32 → 825,32
unit.0.0.port.-1.s.73.visible=1
unit.0.0.port.-1.s.74.alias=
unit.0.0.port.-1.s.74.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.74.name=/GECKO3COM_simple_1/s_gpif_rx_data<0>
unit.0.0.port.-1.s.74.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd1
unit.0.0.port.-1.s.74.orderindex=-1
unit.0.0.port.-1.s.74.visible=0
unit.0.0.port.-1.s.75.alias=
unit.0.0.port.-1.s.75.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.75.name=/GECKO3COM_simple_1/s_gpif_rx_data<10>
unit.0.0.port.-1.s.75.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd2
unit.0.0.port.-1.s.75.orderindex=-1
unit.0.0.port.-1.s.75.visible=0
unit.0.0.port.-1.s.76.alias=
unit.0.0.port.-1.s.76.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.76.name=/GECKO3COM_simple_1/s_gpif_rx_data<11>
unit.0.0.port.-1.s.76.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd3
unit.0.0.port.-1.s.76.orderindex=-1
unit.0.0.port.-1.s.76.visible=0
unit.0.0.port.-1.s.77.alias=
unit.0.0.port.-1.s.77.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.77.name=/GECKO3COM_simple_1/s_gpif_rx_data<12>
unit.0.0.port.-1.s.77.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd4
unit.0.0.port.-1.s.77.orderindex=-1
unit.0.0.port.-1.s.77.visible=0
unit.0.0.port.-1.s.78.alias=
unit.0.0.port.-1.s.78.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.78.name=/GECKO3COM_simple_1/s_gpif_rx_data<13>
unit.0.0.port.-1.s.78.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd5
unit.0.0.port.-1.s.78.orderindex=-1
unit.0.0.port.-1.s.78.visible=0
unit.0.0.port.-1.s.79.alias=
unit.0.0.port.-1.s.79.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.79.name=/GECKO3COM_simple_1/s_gpif_rx_data<14>
unit.0.0.port.-1.s.79.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd6
unit.0.0.port.-1.s.79.orderindex=-1
unit.0.0.port.-1.s.79.visible=0
unit.0.0.port.-1.s.8.alias=
860,52 → 860,52
unit.0.0.port.-1.s.8.visible=1
unit.0.0.port.-1.s.80.alias=
unit.0.0.port.-1.s.80.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.80.name=/GECKO3COM_simple_1/s_gpif_rx_data<15>
unit.0.0.port.-1.s.80.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd7
unit.0.0.port.-1.s.80.orderindex=-1
unit.0.0.port.-1.s.80.visible=0
unit.0.0.port.-1.s.81.alias=
unit.0.0.port.-1.s.81.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.81.name=/GECKO3COM_simple_1/s_gpif_rx_data<1>
unit.0.0.port.-1.s.81.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd8
unit.0.0.port.-1.s.81.orderindex=-1
unit.0.0.port.-1.s.81.visible=0
unit.0.0.port.-1.s.82.alias=
unit.0.0.port.-1.s.82.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.82.name=/GECKO3COM_simple_1/s_gpif_rx_data<2>
unit.0.0.port.-1.s.82.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd9
unit.0.0.port.-1.s.82.orderindex=-1
unit.0.0.port.-1.s.82.visible=0
unit.0.0.port.-1.s.83.alias=
unit.0.0.port.-1.s.83.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.83.name=/GECKO3COM_simple_1/s_gpif_rx_data<3>
unit.0.0.port.-1.s.83.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd10
unit.0.0.port.-1.s.83.orderindex=-1
unit.0.0.port.-1.s.83.visible=0
unit.0.0.port.-1.s.84.alias=
unit.0.0.port.-1.s.84.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.84.name=/GECKO3COM_simple_1/s_gpif_rx_data<4>
unit.0.0.port.-1.s.84.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd11
unit.0.0.port.-1.s.84.orderindex=-1
unit.0.0.port.-1.s.84.visible=0
unit.0.0.port.-1.s.85.alias=
unit.0.0.port.-1.s.85.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.85.name=/GECKO3COM_simple_1/s_gpif_rx_data<5>
unit.0.0.port.-1.s.85.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd12
unit.0.0.port.-1.s.85.orderindex=-1
unit.0.0.port.-1.s.85.visible=0
unit.0.0.port.-1.s.86.alias=
unit.0.0.port.-1.s.86.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.86.name=/GECKO3COM_simple_1/s_gpif_rx_data<6>
unit.0.0.port.-1.s.86.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd13
unit.0.0.port.-1.s.86.orderindex=-1
unit.0.0.port.-1.s.86.visible=0
unit.0.0.port.-1.s.87.alias=
unit.0.0.port.-1.s.87.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.87.name=/GECKO3COM_simple_1/s_gpif_rx_data<7>
unit.0.0.port.-1.s.87.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd14
unit.0.0.port.-1.s.87.orderindex=-1
unit.0.0.port.-1.s.87.visible=0
unit.0.0.port.-1.s.88.alias=
unit.0.0.port.-1.s.88.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.88.name=/GECKO3COM_simple_1/s_gpif_rx_data<8>
unit.0.0.port.-1.s.88.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd15
unit.0.0.port.-1.s.88.orderindex=-1
unit.0.0.port.-1.s.88.visible=0
unit.0.0.port.-1.s.89.alias=
unit.0.0.port.-1.s.89.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.89.name=/GECKO3COM_simple_1/s_gpif_rx_data<9>
unit.0.0.port.-1.s.89.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM_FFd16
unit.0.0.port.-1.s.89.orderindex=-1
unit.0.0.port.-1.s.89.visible=0
unit.0.0.port.-1.s.9.alias=
985,7 → 985,7
unit.0.0.port.0.s.0.visible=1
unit.0.0.port.0.s.1.alias=
unit.0.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.1.name=/GECKO3COM_simple_1/s_btag_correct
unit.0.0.port.0.s.1.name=/GECKO3COM_simple_1/s_gpif_tx_full
unit.0.0.port.0.s.1.orderindex=-1
unit.0.0.port.0.s.1.visible=1
unit.0.0.port.0.s.10.alias=
1325,7 → 1325,7
unit.0.0.waveform.posn.36.name=/GECKO3COM_simple_1/s_send_fifo_reset
unit.0.0.waveform.posn.36.type=signal
unit.0.0.waveform.posn.37.channel=47
unit.0.0.waveform.posn.37.name=/s_send_counter_equals_transfer_size
unit.0.0.waveform.posn.37.name=/s_transfer_size_reg_en
unit.0.0.waveform.posn.37.radix=1
unit.0.0.waveform.posn.37.type=signal
unit.0.0.waveform.posn.38.channel=48
1344,7 → 1344,7
unit.0.0.waveform.posn.40.radix=1
unit.0.0.waveform.posn.40.type=bus
unit.0.0.waveform.posn.41.channel=2147483646
unit.0.0.waveform.posn.41.name=/GECKO3COM_simple_1/s_gpif_rx_data
unit.0.0.waveform.posn.41.name=/GECKO3COM_simple_1/GPIF_INTERFACE/FSM_GPIF/pr_state_FSM
unit.0.0.waveform.posn.41.radix=1
unit.0.0.waveform.posn.41.type=bus
unit.0.0.waveform.posn.42.channel=2147483646
/core/coregenerator/coregenerator_fifo_dualclock.xise
41,7 → 41,7
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Command line syntax" xil_pn:value="emacsclient +$2 $1"/>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1500"/>
<property xil_pn:name="Device" xil_pn:value="xc3s4000"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="Editor" xil_pn:value="Custom"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
/core/coregenerator/coregenerator_fifo_dualclock.gise
38,6 → 38,7
<transform xil_pn:end_ts="1266873172" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4335293426568460978" xil_pn:start_ts="1266873172">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1266873172" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1266873172">
<status xil_pn:value="SuccessfullyRun"/>
/core/coregenerator/coregenerator_fifo_receive.xise
39,7 → 39,7
 
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1500"/>
<property xil_pn:name="Device" xil_pn:value="xc3s4000"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|coregenerator_fifo_receive"/>
/core/coregenerator/coregenerator_fifo_send.xise
39,7 → 39,7
 
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1500"/>
<property xil_pn:name="Device" xil_pn:value="xc3s4000"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|coregenerator_fifo_send"/>
/core/coregenerator/coregenerator_fifo_receive.gise
38,6 → 38,7
<transform xil_pn:end_ts="1266873170" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4335293426568460978" xil_pn:start_ts="1266873170">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1266873170" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1266873170">
<status xil_pn:value="SuccessfullyRun"/>
/core/coregenerator/coregenerator_fifo_send.gise
38,6 → 38,7
<transform xil_pn:end_ts="1266873171" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4335293426568460978" xil_pn:start_ts="1266873171">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1266873171" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1266873171">
<status xil_pn:value="SuccessfullyRun"/>
/core/GECKO3COM_simple_test.vhd
83,7 → 83,7
-- we will transmitt 1 MiB data when the pseude random number generator
-- is used:
--signal c_transfer_size_prng : std_logic_vector(31 downto 0) := x"00100000";
signal c_transfer_size_prng : std_logic_vector(31 downto 0) := x"00000FA0";
signal c_transfer_size_prng : std_logic_vector(31 downto 0) := x"00000001";
 
-----------------------------------------------------------------------------
336,10 → 336,10
if i_nReset = '0' then -- asynchronous reset (active low)
s_send_counter_value <= (others => '0');
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
if s_send_counter_reset = '1' then
if s_send_counter_reset = '1' and s_send_counter_en = '0' then
s_send_counter_value <= (others => '0');
end if;
if s_send_counter_en = '1' then
if s_send_counter_reset = '0' and s_send_counter_en = '1' then
s_send_counter_value(31 downto 2) <=
s_send_counter_value(31 downto 2) + 1;
s_send_counter_value(1 downto 0) <= "00"; -- every fifo write (32bit)
350,7 → 350,7
-- transfer size counter comparator
s_send_counter_equals_transfer_size <=
'1' when s_send_counter_value >= s_send_transfersize else
'1' when s_send_counter_value > s_send_transfersize else
'0';
 
 
505,13 → 505,13
end if;
 
when st6_send_wait =>
 
if s_send_fifo_full = '0' then
next_state <= st5_send_data;
end if;
 
when st7_subtract_transfered_data =>
s_transfer_size_reg_select <= '0';
s_transfer_size_reg_select <= '0';
s_transfer_size_reg_en <= '1';
 
if s_send_data_request = '1' then
/core/gpif_com.vhd
280,7 → 280,7
if s_EOM = '1' then
s_EOM_FF <= '1';
end if;
if s_X2U_EMPTY = '1' then
if s_X2U_EMPTY = '1' and s_TX_FSM = '0' then
s_EOM_FF <= '0';
end if;
end if;

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