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URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

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  • This comparison shows the changes necessary to convert path 
    /gecko3/trunk
    from Rev 18 to Rev 19
    ↔ Reverse comparison
  •

Rev 18 → Rev 19

/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/GECKO3COM/gecko3com-ip/core/GECKO3main_v1.ucf
43,7 → 43,7
net "i_SYSCLK" tnm_net = "SYSCLK";
timespec "TS_SYSCLK" = period "SYSCLK" 20.0 ns HIGH 50%; # 50 MHz system clock
 
net "i_IFCLK" loc = "AA17";
net "i_IFCLK" loc = "AA7";
net "i_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
net "i_IFCLK" tnm_net = "IFCLK";
timespec "TS_IFCLK" = period "IFCLK" 20.83 ns HIGH 50%; # 48 MHz interface clock
/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/GECKO3COM/gecko3com-ip/core/gpif_com_fsm.vhd
69,12 → 69,6
o_TX : out std_logic --
);
 
-- XST specific synthesize attributes
attribute safe_implementation: string;
attribute safe_recovery_state: string;
 
attribute safe_implementation of gpif_com_fsm : entity is "yes";
 
end gpif_com_fsm;
 
 
81,6 → 75,11
 
architecture fsm of gpif_com_fsm is
 
-- XST specific synthesize attributes
attribute safe_implementation: string;
attribute safe_recovery_state: string;
-----------------------------------------------------------------------------
-- FSM
-----------------------------------------------------------------------------
90,8 → 89,8
 
type t_fsmState is (rst, idle, -- controll states
inRQ, inACK, inTrans, inThrot,
inThrotEnd, endInTrans, -- in com states
inRQ, inACK, inWait, inTrans, inThrot,
inThrotBreak,inThrotBreak2, inThrotEnd, endInTrans, -- in com states
outRQ, outTrans, outWait, endOutTrans); -- out com states
 
99,7 → 98,8
signal pr_state, nx_state : t_fsmState;
-- XST specific synthesize attributes
attribute safe_recovery_state of pr_state : signal is "idle";
attribute safe_recovery_state of nx_state : signal is "idle";
attribute safe_implementation of pr_state : signal is "yes";
 
-- interconection signals
113,6 → 113,8
begin
 
 
o_FIFOrst <= s_FIFOrst;
o_X2U_RD_EN <= s_X2U_RD_EN;
o_WRX <= s_WRX;
128,7 → 130,6
 
-- state reg
action : process(i_IFCLK, i_nReset)
variable v_setup : integer range 0 to 15;
begin
 
if i_nReset = '0' then
141,7 → 142,8
 
 
-- comb logic
transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_AM_FULL, i_X2U_EMPTY)
transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL,
i_U2X_AM_FULL, i_X2U_EMPTY)
begin -- process transaction
 
-- default signal values to avoid latches:
204,6 → 206,9
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
o_RX <= '0';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
217,7 → 222,7
-- output signal values:
s_WRX <= '0';
s_RDYX <= '1';
s_U2X_WR_EN <= '1';
s_U2X_WR_EN <= '0';
o_RX <= '1';
 
-- state decisions
224,11 → 229,21
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '1' then
nx_state <= inTrans;
--nx_state <= inDummy;
--nx_state <= inTrans;
nx_state <= inWait;
else
nx_state <= endInTrans;
end if;
 
when inWait =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '1';
s_U2X_WR_EN <= '0';
o_RX <= '1';
 
-- state decisions
nx_state <= inTrans;
when inTrans =>
-- output signal values:
259,8 → 274,8
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_U2X_FULL = '0' then
--nx_state <= inThrotEnd;
nx_state <= inACK;
nx_state <= inThrotBreak;
--nx_state <= inACK;
elsif i_WRU = '0' then
nx_state <= endInTrans;
else
267,9 → 282,22
nx_state <= inThrot;
end if;
 
--when inThrotEnd =>
when inThrotBreak =>
-- this is a one clock delay to help the fx2 to see the RDYX signal.
-- output signal values:
s_WRX <= '0';
s_RDYX <= '1';
s_U2X_WR_EN <= '0';
o_RX <= '1';
 
-- state decisions
--nx_state <= inThrotBreak2;
nx_state <= inThrotEnd;
 
--when inThrotBreak2 =>
-- -- this is a one clock delay to help the fx2 to see the RDYX signal.
-- -- output signal values:
-- s_WRX <= '0';
-- s_RDYX <= '1';
277,13 → 305,26
-- o_RX <= '1';
 
-- -- state decisions
-- nx_state <= inACK;
-- nx_state <= inThrotEnd;
when inThrotEnd =>
-- this is a one clock delay to help the fx2 to see the RDYX signal.
-- output signal values:
s_WRX <= '0';
s_RDYX <= '1';
s_U2X_WR_EN <= '0';
o_RX <= '1';
 
-- state decisions
nx_state <= inTrans;
when endInTrans =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '1';
s_U2X_WR_EN <= '0';
o_RX <= '0';
 
-- state decisions
nx_state <= idle;
/GECKO3COM/gecko3com-ip/core/chipscope-analyzer.cpj
1,5 → 1,5
#ChipScope Pro Analyzer Project File, Version 3.0
#Wed Jan 13 21:31:08 CET 2010
#Sat Jan 16 00:54:10 CET 2010
deviceChain.deviceName0=XC3S1500
deviceChain.iRLength0=6
deviceChain.name0=MyDevice0
33,7 → 33,7
unit.0.0.1.WIDTH1=1.0574257
unit.0.0.1.X1=0.0
unit.0.0.1.Y1=0.3038348
unit.0.0.MFBitsA0=1XXX
unit.0.0.MFBitsA0=1XX0
unit.0.0.MFBitsB0=0000
unit.0.0.MFCompareA0=0
unit.0.0.MFCompareB0=999
/GECKO3COM/gecko3com-ip/core/gpif_com_test.vhd
81,7 → 81,6
signal s_RX_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_RD_EN, s_WR_EN : std_logic;
signal s_TX_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_RDYX : std_logic;
 
signal s_ABORT, s_ABORT_TMP : std_logic;
160,13 → 159,14
-- inputs : i_SYSCLK
-- outputs: s_RX_DATA_TMP
rx_throtling: process (i_SYSCLK, i_nReset)
variable v_rx_throtle_count : std_logic_vector(6 downto 0); -- counter variable
-- counter variable
variable v_rx_throtle_count : std_logic_vector(6 downto 0);
begin
if i_nReset = '0' then
v_rx_throtle_count := (others => '0');
s_RD_EN <= '0';
elsif i_SYSCLK = '1' and i_SYSCLK'event then
if v_rx_throtle_count >= 63 then
if v_rx_throtle_count >= 2 then
s_RD_EN <= '1';
v_rx_throtle_count := (others => '0');
else
193,7 → 193,7
 
-- dummy logic to "use" these signals and avoid that they are removed by
-- the optimizer
process(s_RX_DATA_TMP, s_EMPTY_TMP, s_FULL_TMP, s_ABORT_TMP, s_RDYX)
process(s_RX_DATA_TMP, s_EMPTY_TMP, s_FULL_TMP, s_ABORT_TMP)
variable result : std_logic := '0';
begin
result := '0';
220,7 → 220,7
begin
if i_nReset = '0' then
s_rom_adress <= (others => '0');
--DEBUG s_WR_EN <= '1';
--s_WR_EN <= '1';
s_WR_EN <= '0';
elsif i_SYSCLK = '1' and i_SYSCLK'event then
if s_rom_adress = 24 then
228,7 → 228,7
s_WR_EN <= '0';
else
s_rom_adress <= s_rom_adress + 1;
--DEBUG s_WR_EN <= '1';
--s_WR_EN <= '1';
s_WR_EN <= '0';
end if;
end if;
/GECKO3COM/gecko3com-ip/core/gpif_com.vhd
265,6 → 265,14
end if;
end process bus_access;
 
s_dbus_in <= b_gpif_bus;
-- buffer the gpif bus input signals to avoid that the last word in the
-- usb to xilinx transfer is read twice.
buf_input : process (i_IFCLK)
begin
if rising_edge(i_IFCLK) then
s_dbus_in <= b_gpif_bus;
end if;
end process buf_input;
 
end structure;
/GECKO3COM/gecko3com-fw/firmware/include/gecko3com_gpif.h
41,6 → 41,9
#define bmGPIF_READ_IN_PROGRESS 1
#define bmGPIF_PENDING_DATA 2
 
/** flag to signal, that the GPIF receives data from the FPGA */
volatile static idata uint8_t flGPIF;
 
/** \brief initialize GPIF system
*
* initialize GPIF with waveform data.
/GECKO3COM/gecko3com-fw/firmware/src/gecko3com_main.c
848,13 → 848,6
}
} /* end of IN Transfer clause */
 
/* if(!(EP2468STAT & bmEP2EMPTY) && flLOCAL == GECKO3COM_REMOTE) { */
/* flGPIF &= ~bmGPIF_PENDING_DATA; */
/* OUTPKTEND = USB_TMC_EP_OUT; */
/* gpif_trigger_write(); */
/* EP2FIFOCFG |= bmAUTOOUT; */
/* } */
 
/* if the LED flag is set to off, disable the external LED */
if(flLED == LEDS_OFF) {
set_led_ext(LEDS_OFF);
/GECKO3COM/gecko3com-fw/firmware/src/gecko3com_gpif.c
77,8 → 77,8
extern const char InitData[7];
 
 
/** private flag to signal, that the GPIF receives data from the FPGA */
volatile static uint8_t flGPIF;
//** private flag to signal, that the GPIF receives data from the FPGA */
//volatile static uint8_t flGPIF;
 
 
 
90,23 → 90,22
{
ISR_DEBUG_PORT |= bmGPIF_DONE;
 
clear_fifo_gpif_irq();
 
//EA = 0; /* disable all interrupts */
 
/* check if there is data available for an OUT transfer */
if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
//if(!(EP2468STAT & bmEP2EMPTY)) {
/*if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
//if(!(EP2468STAT & bmEP2EMPTY)) {
flGPIF &= ~bmGPIF_PENDING_DATA;
GPIFABORT = 0xFF;
SYNCDELAY;
gpif_trigger_write();
}
else {
INPKTEND = USB_TMC_EP_IN;
else*/ {
/* check if this is a end of a IN transfer */
//INPKTEND = USB_TMC_EP_IN;
while(!(GPIFTRIG & bmGPIF_IDLE));
gpif_trigger_read();
}
//EA = 1; /* global interrupt enable */
 
clear_fifo_gpif_irq();
ISR_DEBUG_PORT &= ~bmGPIF_DONE;
}
120,21 → 119,19
{
ISR_DEBUG_PORT |= bmFIFO_PF;
 
clear_fifo_gpif_irq();
 
/* check if there is a active IN transfer */
if((GPIFIDLECTL & bmBIT3) == bmBIT3) {
/*if((GPIFIDLECTL & bmBIT3) == bmBIT3) {
flGPIF |= bmGPIF_PENDING_DATA;
}
else {
//EA = 0; /* disable all interrupts */
else*/ {
GPIFABORT = 0xFF;
SYNCDELAY;
while(!(GPIFTRIG & bmGPIF_IDLE));
gpif_trigger_write();
//EA = 1; /* global interrupt enable */
}
 
clear_fifo_gpif_irq();
 
ISR_DEBUG_PORT &= ~bmFIFO_PF;
}
 
145,8 → 142,9
uint8_t i;
 
#ifdef GECKO3MAIN
/* IFCLK is generated internally and runs at 48 MHz; GPIF "master mode" */
IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmGSTATE | bmIFGPIF;
/* IFCLK is generated internally and runs at 30 MHz; GPIF "master mode" */
//IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmGSTATE | bmIFGPIF;
IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmGSTATE | bmIFGPIF;
SYNCDELAY;
 
/* we have to commit the currently processed packet BEFORE we switch to auto out mode */
168,11 → 166,11
* flag has to change one cycle before the FIFO is completly empty, else we
* transfer one word too much */
EP2FIFOPFH = bmDECIS;
EP2FIFOPFL = 1;
EP2FIFOPFL = 4;
SYNCDELAY;
 
//EP2GPIFFLGSEL = bmFLAG_PROGRAMMABLE;
EP2GPIFFLGSEL = bmFLAG_EMPTY;
EP2GPIFFLGSEL = bmFLAG_PROGRAMMABLE;
//EP2GPIFFLGSEL = bmFLAG_EMPTY;
SYNCDELAY;
EP6GPIFFLGSEL = bmFLAG_FULL;
SYNCDELAY;
286,7 → 284,6
 
 
#ifdef GECKO3MAIN
//EP2FIFOCFG &= ~bmOEP;
EP2FIFOCFG &= ~bmAUTOOUT; /* disable AutoOUT feature */
SYNCDELAY;
//EP6FIFOCFG &= ~bmINFM;
/GECKO3COM/gecko3com-fw/firmware/gpif-design/gecko3main_fifo_transfer.gpf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/GECKO3COM/gecko3com-fw/firmware/gpif-design/gecko3main_gpif.c
103,18 → 103,18
// DataMode NO Data NO Data NO Data Activate Activate NO Data NO Data
// NextData SameData SameData SameData SameData NextData SameData SameData
// Int Trig No Int No Int No Int No Int Trig Int No Int No Int
// IF/Wait IF Wait 2 Wait 1 IF Wait 1 IF IF
// Term A WRX WRX WRX WRX
// LFunc AND AND AND AND
// Term B WRX WRX WRX WRX
// Branch1 Then 1 Then 3 ThenIdle ThenIdle
// Branch0 Else 0 Else 4 ElseIdle ElseIdle
// Re-Exec No Yes No Yes
// IF/Wait IF IF Wait 1 IF Wait 1 IF IF
// Term A WRX WRX RDYX WRX WRX
// LFunc AND AND !A AND B AND AND
// Term B WRX RDYX WRX WRX WRX
// Branch1 Then 1 Then 0 Then 3 ThenIdle ThenIdle
// Branch0 Else 0 Else 2 Else 4 ElseIdle ElseIdle
// Re-Exec No Yes Yes No Yes
// Sngl/CRC Default Default Default Default Default Default Default
// RDYU 0 0 0 0 0 0 0 0
// WRU 0 0 0 0 0 0 0 0
// RDYU 0 0 1 1 1 0 0 0
// X2U_ex 0 1 1 1 1 0 0 0
// X2U_ex 0 0 1 1 1 0 0 0
// U2X_th 0 0 0 0 0 0 0 0
// unused 0 0 0 0 0 0 0 0
//
130,13 → 130,13
// DataMode NO Data NO Data NO Data Activate Activate Activate NO Data
// NextData SameData SameData SameData SameData NextData NextData SameData
// Int Trig No Int No Int No Int No Int No Int Trig Int No Int
// IF/Wait IF Wait 1 IF Wait 1 IF IF IF
// Term A WRX WRX FIFOFlag RDYX WRX
// LFunc AND AND AND AND AND
// Term B WRX WRX FIFOFlag RDYX WRX
// Branch1 ThenIdle Then 2 Then 5 Then 5 ThenIdle
// Branch0 Else 1 Else 3 Else 4 ElseIdle ElseIdle
// Re-Exec No No Yes No No
// IF/Wait IF Wait 1 IF IF IF IF IF
// Term A WRX WRX RDYX FIFOFlag RDYX WRX
// LFunc AND AND AND AND AND AND
// Term B WRX WRX RDYX FIFOFlag RDYX WRX
// Branch1 ThenIdle Then 2 Then 4 Then 4 Then 5 ThenIdle
// Branch0 Else 1 Else 3 Else 3 Else 5 ElseIdle ElseIdle
// Re-Exec No No No Yes No No
// Sngl/CRC Default Default Default Default Default Default Default
// RDYU 0 0 0 0 0 0 0 0
// WRU 0 1 1 1 1 0 0 0
169,15 → 169,15
/* Output*/ 0x00, 0x02, 0x02, 0x06, 0x06, 0x06, 0x06, 0x00,
/* LFun */ 0x40, 0x09, 0x0F, 0x09, 0x00, 0x00, 0x00, 0x3F,
// Wave 2
/* LenBr */ 0x08, 0x02, 0x01, 0x9C, 0x01, 0x3F, 0xBF, 0x07,
/* Opcode*/ 0x01, 0x00, 0x00, 0x03, 0x16, 0x01, 0x01, 0x00,
/* Output*/ 0x00, 0x08, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00,
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
/* LenBr */ 0x08, 0x82, 0x01, 0x9C, 0x01, 0x3F, 0xBF, 0x07,
/* Opcode*/ 0x01, 0x01, 0x00, 0x03, 0x16, 0x01, 0x01, 0x00,
/* Output*/ 0x00, 0x00, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00,
/* LFun */ 0x00, 0x01, 0x00, 0xC8, 0x00, 0x00, 0x00, 0x3F,
// Wave 3
/* LenBr */ 0x39, 0x01, 0x13, 0x01, 0xAC, 0x2F, 0x3F, 0x07,
/* Opcode*/ 0x01, 0x00, 0x01, 0x02, 0x07, 0x17, 0x01, 0x00,
/* LenBr */ 0x39, 0x01, 0x13, 0x23, 0xA5, 0x2F, 0x3F, 0x07,
/* Opcode*/ 0x01, 0x00, 0x01, 0x03, 0x07, 0x17, 0x01, 0x00,
/* Output*/ 0x00, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00,
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x36, 0x09, 0x00, 0x3F,
/* LFun */ 0x00, 0x00, 0x00, 0x09, 0x36, 0x09, 0x00, 0x3F,
};
// END DO NOT EDIT
187,7 → 187,7
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 2 FlowStates */ 0x83,0x36,0x04,0x00,0x03,0x23,0x03,0x02,0x00,
/* Wave 3 FlowStates */ 0x84,0x09,0x02,0x02,0x04,0x23,0x03,0x02,0x00,
/* Wave 3 FlowStates */ 0x84,0x09,0x02,0x02,0x04,0x24,0x03,0x02,0x00,
};
// END DO NOT EDIT
/GECKO3COM/gecko3com-fw/gecko3com.iic Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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