URL
https://opencores.org/ocsvn/generic_booth_multipler/generic_booth_multipler/trunk
Subversion Repositories generic_booth_multipler
Compare Revisions
- This comparison shows the changes necessary to convert path
/generic_booth_multipler/tags/P0
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/rtl/benches/TB_ALU.vhd
0,0 → 1,41
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
|
ENTITY TB_ALU IS |
END TB_ALU; |
|
ARCHITECTURE behavior OF TB_ALU IS |
|
COMPONENT Alu |
PORT( |
A : IN std_logic_vector(7 downto 0); |
B : IN std_logic_vector(7 downto 0); |
op : IN std_logic; |
S : OUT std_logic_vector(7 downto 0) |
); |
END COMPONENT; |
|
|
--Inputs |
signal A : std_logic_vector(7 downto 0) := (others => '0'); |
signal B : std_logic_vector(7 downto 0) := (others => '0'); |
signal op : std_logic := '0'; |
|
--Outputs |
signal S : std_logic_vector(7 downto 0); |
|
BEGIN |
|
uut: Alu PORT MAP ( |
A => A, |
B => B, |
op => op, |
S => S |
); |
A <= X"05" after 10 ns , X"0F" after 30 ns; |
B <= X"0A" after 10 ns , X"08" after 30 ns; |
op <= '1' after 20 ns , '0' after 40 ns; |
|
END; |
/rtl/benches/TB_Adder.vhd
0,0 → 1,47
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
ENTITY TB_Adder IS |
END TB_Adder; |
|
ARCHITECTURE behavior OF TB_Adder IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT Adder |
PORT( |
A : IN std_logic_vector(7 downto 0); |
B : IN std_logic_vector(7 downto 0); |
Cin : IN std_logic; |
S : OUT std_logic_vector(7 downto 0); |
Cout : OUT std_logic |
); |
END COMPONENT; |
|
|
--Inputs |
signal A : std_logic_vector(7 downto 0) := (others =>'0'); |
signal B : std_logic_vector(7 downto 0) := (others =>'0'); |
signal Cin : std_logic := '0'; |
|
--Outputs |
signal S : std_logic_vector(7 downto 0); |
signal Cout : std_logic; |
-- No clocks detected in port list. Replace <clock> below with |
-- appropriate port name |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: Adder PORT MAP ( |
A => A, |
B => B, |
Cin => Cin, |
S => S, |
Cout => Cout |
); |
cin <= '1' after 20 ns , '0' after 40 ns; |
A <= X"05" after 10 ns , X"06" after 20 ns , X"F8" after 30 ns ; |
B <= X"0F" after 10 ns , X"0A" after 20 ns , X"F3" after 30 ns ; |
END; |
/rtl/benches/TB_Ander.vhd
0,0 → 1,40
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
ENTITY TB_Ander IS |
END TB_Ander; |
|
ARCHITECTURE behavior OF TB_Ander IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT Ander |
PORT( |
input1 : IN std_logic; |
input2 : IN std_logic_vector(7 downto 0); |
result : OUT std_logic_vector(7 downto 0) |
); |
END COMPONENT; |
|
|
--Inputs |
signal input1 : std_logic := '0'; |
signal input2 : std_logic_vector(7 downto 0) := (others=>'0'); |
|
--Outputs |
signal result : std_logic_vector(7 downto 0); |
-- No clocks detected in port list. Replace <clock> below with |
-- appropriate port name |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: Ander PORT MAP ( |
input1 => input1, |
input2 => input2, |
result => result |
); |
input2 <= X"58"; |
input1 <= '1' after 20 ns; |
END; |
/rtl/benches/TB_BoothDatapath.vhd
0,0 → 1,68
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
|
entity TB_BoothDatapath is |
end TB_BoothDatapath; |
|
architecture Behavioral of TB_BoothDatapath is |
|
component BoothDatapath is |
port( |
clock :in std_logic; |
reset :in std_logic; |
load :in std_logic; |
shift :in std_logic; |
X :in std_logic_vector; |
Y :in std_logic_vector; |
P :out std_logic_vector); |
end component; |
|
|
signal clock: std_logic := '0'; |
signal load: std_logic := '0'; |
signal reset: std_logic := '0'; |
signal shift: std_logic := '0'; |
|
signal X4: std_logic_vector(3 downto 0); |
signal Y4: std_logic_vector(3 downto 0); |
signal P8: std_logic_vector(7 downto 0); |
|
signal X8: std_logic_vector(7 downto 0); |
signal Y8: std_logic_vector(7 downto 0); |
signal P16: std_logic_vector(15 downto 0); |
begin |
uut4: BoothDatapath |
port map( |
clock => clock, |
reset => reset, |
load => load, |
shift => shift, |
X => X4, |
Y => Y4, |
P => P8); |
|
uut8: BoothDatapath |
port map( |
clock => clock, |
reset => reset, |
load => load, |
shift => shift, |
X => X8, |
Y => Y8, |
P => P16); |
|
clock <= not clock after 5 ns; |
reset<= '1' after 10 ns, '0' after 20 ns; |
load <= '1' after 30 ns, '0' after 40 ns; |
shift <= '1' after 40 ns; |
|
Y4 <= X"B"; |
X4 <= X"A"; |
Y8 <= X"BA"; |
X8 <= X"A7"; |
|
|
|
end Behavioral; |
/rtl/benches/TB_BoothMultiplier.vhd
0,0 → 1,90
-- TestBench Template |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
|
ENTITY TB_BoothMultiplier IS |
END TB_BoothMultiplier; |
|
ARCHITECTURE behavior OF TB_BoothMultiplier IS |
|
-- Component Declaration |
component BoothMultiplier is |
generic(COUNTER_SIZE : positive := 2); |
port( |
clock : in std_logic; |
clear : in std_logic; |
start : in std_logic; |
X_data: in std_logic_vector(2**COUNTER_SIZE-1 downto 0); |
Y_data: in std_logic_vector(2**COUNTER_SIZE-1 downto 0); |
ready : out std_logic; |
Result: out std_logic_vector(2*(2**COUNTER_SIZE)-1 downto 0)); |
end component; |
|
signal clock :std_logic := '0'; |
signal reset :std_logic := '0'; |
signal start :std_logic := '0'; |
signal ready4 :std_logic := '0'; |
signal ready8 :std_logic := '0'; |
|
signal X_data4 :std_logic_vector(3 downto 0); |
signal Y_data4 :std_logic_vector(3 downto 0); |
signal Result8 :std_logic_vector(7 downto 0); |
signal X_data8 :std_logic_vector(7 downto 0); |
signal Y_data8 :std_logic_vector(7 downto 0); |
signal Result16 :std_logic_vector(15 downto 0); |
|
begin |
desing_under_test4bit: BoothMultiplier |
generic map( |
COUNTER_SIZE => 2) |
port map( |
clock => clock, |
clear => reset, |
start => start, |
X_data => X_data4, |
Y_data => Y_data4, |
ready => ready4, |
Result => Result8); |
|
desing_under_test8bit: BoothMultiplier |
generic map( |
COUNTER_SIZE => 3) |
port map( |
clock => clock, |
clear => reset, |
start => start, |
X_data => X_data8, |
Y_data => Y_data8, |
ready => ready8, |
Result => Result16); |
|
clock <= not clock after 5 ns; |
start <= '1' after 10 ns ; |
|
reset <= '1' after 0010 ns ,'0' after 0020 ns; |
-- '1' after 0410 ns, '0' after 0420 ns, |
-- '1' after 0810 ns, '0' after 0820 ns, |
-- '1' after 1210 ns, '0' after 1220 ns; |
-- |
X_data8 <= X"23" , -- 35 |
X"03" after 0400 ns, -- 3 |
X"FA" after 0800 ns, -- -8 |
X"F5" after 1200 ns; -- -10 |
|
Y_data8 <= X"03" , -- 3 |
X"23" after 0400 ns, -- 35 |
X"F5" after 0800 ns, -- -10 |
X"FA" after 1200 ns; -- -8 |
X_data4 <= X"3" , -- 35 |
X"3" after 0400 ns, -- 3 |
X"A" after 0800 ns, -- -8 |
X"5" after 1200 ns; -- -10 |
|
Y_data4 <= X"3" , -- 3 |
X"3" after 0400 ns, -- 35 |
X"5" after 0800 ns, -- -10 |
X"A" after 1200 ns; -- -8 |
|
end; |
/rtl/benches/TB_Register.vhd
0,0 → 1,59
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
ENTITY TB_Register IS |
END TB_Register; |
|
ARCHITECTURE behavior OF TB_Register IS |
|
COMPONENT Regeister |
PORT( |
clock : IN std_logic; |
enable : IN std_logic; |
reset : IN std_logic; |
din : IN std_logic_vector(7 downto 0); |
dout : OUT std_logic_vector(7 downto 0) |
); |
END COMPONENT; |
|
|
signal clock : std_logic := '0'; |
signal enable : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal din : std_logic_vector(7 downto 0) ; |
|
signal dout : std_logic_vector(7 downto 0); |
|
constant clock_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: Regeister PORT MAP ( |
clock => clock, |
enable => enable, |
reset => reset, |
din => din, |
dout => dout |
); |
|
-- Clock process definitions |
clock_process :process |
begin |
clock <= '0'; |
wait for clock_period/2; |
clock <= '1'; |
wait for clock_period/2; |
end process; |
reset <= '1' after clock_period/2 ,'0' after clock_period*3/2; |
enable<= '1' after clock_period*2 ,'0' after clock_period*7; |
din <= X"05" after clock_period , |
X"0A" after clock_period*2, |
X"1A" after clock_period*3, |
X"2A" after clock_period*4, |
X"3A" after clock_period*5, |
X"4A" after clock_period*6, |
X"5A" after clock_period*7, |
X"6B" after clock_period*8; |
END; |
/rtl/benches/TB_RightShiftReg.vhd
0,0 → 1,59
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
|
ENTITY TB_RightShiftReg IS |
END TB_RightShiftReg; |
|
ARCHITECTURE behavior OF TB_RightShiftReg IS |
|
|
|
COMPONENT RightShiftReg |
PORT( |
clock : IN std_logic; |
enable : IN std_logic; |
shift : IN std_logic; |
din : IN std_logic_vector(8 downto 0); |
dout : OUT std_logic_vector(1 downto 0) |
); |
END COMPONENT; |
|
|
--Inputs |
signal clock : std_logic := '0'; |
signal enable : std_logic := '0'; |
signal shift : std_logic := '0'; |
signal din : std_logic_vector(8 downto 0) := (others => '0'); |
|
--Outputs |
signal dout : std_logic_vector(1 downto 0); |
|
-- Clock period definitions |
constant clock_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: RightShiftReg PORT MAP ( |
clock => clock, |
enable => enable, |
shift => shift, |
din => din, |
dout => dout |
); |
|
-- Clock process definitions |
clock_process :process |
begin |
clock <= '0'; |
wait for clock_period/2; |
clock <= '1'; |
wait for clock_period/2; |
end process; |
|
enable <= '1' after clock_period*2 ,'0' after clock_period*3; |
shift <= '1' after clock_period*3 ,'0' after clock_period*7; |
din <= "011001101" after clock_period/2; |
END; |
/rtl/modules/00.Adder.vhd
0,0 → 1,32
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity Adder is |
port( |
A : in std_logic_vector; |
B : in std_logic_vector; |
Cin : in std_logic; |
S : out std_logic_vector; |
Cout : out std_logic); |
end Adder; |
|
architecture Behavioral of Adder is |
component FullAdder is |
port( |
A :in std_logic; |
B :in std_logic; |
Cin :in std_logic; |
Sum :out std_logic; |
Cout:out std_logic); |
end component; |
signal carry : std_logic_vector(A'length downto 0); |
begin |
carry(0) <= cin; |
cout <= carry(A'length); |
AdderGen : for i in A'range generate |
FA : FullAdder port map(A(i),B(i),carry(i),S(i),carry(i+1)); |
end generate; |
|
|
end Behavioral; |
|
/rtl/modules/00.Alu.vhd
0,0 → 1,36
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity Alu is |
port( |
A : in std_logic_vector; |
B : in std_logic_vector; |
op : in std_logic; |
S : out std_logic_vector); |
end Alu; |
|
architecture Behavioral of Alu is |
component Adder is |
port( |
A : in std_logic_vector; |
B : in std_logic_vector; |
Cin : in std_logic; |
S : out std_logic_vector; |
Cout : out std_logic); |
end component; |
|
component XorCrearor is |
port( |
input1 : in std_logic; |
input2 : in std_logic_vector; |
result : out std_logic_vector); |
end component; |
signal xored: std_logic_vector(A'range); |
begin |
XO :XorCrearor port map(op,B,xored); |
ADD:ADDER port map(A,xored,op,S,open); |
|
|
end Behavioral; |
|
/rtl/modules/00.Ander.vhd
0,0 → 1,23
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity Ander is |
port( |
input1 : in std_logic; |
input2 : in std_logic_vector; |
result : out std_logic_vector); |
end Ander; |
|
architecture Behavioral of Ander is |
|
begin |
process(input1,input2) |
begin |
for i in input2'range loop |
result(i) <= input1 and input2(i); |
end loop; |
end process; |
|
end Behavioral; |
|
/rtl/modules/00.BoothEncoder.vhd
0,0 → 1,20
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity BoothEncoder is |
port( |
input1 : in std_logic; |
input0 : in std_logic; |
operator : out std_logic; |
product : out std_logic |
); |
end BoothEncoder; |
|
architecture Behavioral of BoothEncoder is |
|
begin |
product <= input1 xor input0 ; |
operator <= input1; |
end Behavioral; |
|
/rtl/modules/00.COUNTER.vhd
0,0 → 1,32
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
entity counter is |
port( |
clock : in std_logic; |
reset : in std_logic; |
value : out std_logic_vector); |
end counter; |
|
architecture behavioral of counter is |
|
signal internal_value : std_logic_vector(value'range):= (others => '0'); |
|
begin |
|
counter_proc: |
process(clock) |
begin |
if (rising_edge(clock)) then |
if (reset = '1') then |
internal_value <= (others => '0'); |
else |
internal_value <= internal_value + '1'; |
end if; |
end if; |
end process; |
|
value <= internal_value; |
|
end; |
/rtl/modules/00.FullAdder.vhd
0,0 → 1,19
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity FullAdder is |
port( |
A :in std_logic; |
B :in std_logic; |
Cin :in std_logic; |
Sum :out std_logic; |
Cout:out std_logic); |
end FullAdder; |
|
architecture Behavioral of FullAdder is |
|
begin |
Cout <= (A AND B)OR(B AND Cin)OR(Cin AND A); |
Sum <= A XOR B XOR Cin; |
|
end Behavioral; |
/rtl/modules/00.LeftShiftReg.vhd
0,0 → 1,32
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity LeftShiftReg is |
port( |
clock :in std_logic; |
enable :in std_logic; |
shift :in std_logic; |
din :in std_logic_vector; |
dout :out std_logic_vector); |
end LeftShiftReg; |
|
architecture Behavioral of LeftShiftReg is |
signal data : std_logic_vector(din'range); |
begin |
process(clock,enable,shift) |
begin |
if(clock'event and clock = '1')then |
if(enable = '1')then |
data <= din; |
elsif(shift = '1') then |
data <= data(din'length-2 downto 0) & '0'; |
else |
data <= data; |
end if; |
end if; |
end process; |
dout <= data; |
|
end Behavioral; |
|
/rtl/modules/00.Regeister.vhd
0,0 → 1,32
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity Regeister is |
port( |
clock :in std_logic; |
enable :in std_logic; |
reset :in std_logic; |
din :in std_logic_vector; |
dout :out std_logic_vector); |
end Regeister; |
|
architecture Behavioral of Regeister is |
signal data :std_logic_vector(din'range):=(OTHERS=>'0'); |
begin |
process(clock) |
begin |
if(clock'event and clock='1')then |
if(reset ='1' )then |
data <=(others =>'0'); |
elsif(enable = '1')then |
data <= din; |
else |
data <= data; |
end if; |
end if; |
end process; |
dout <= data; |
|
end Behavioral; |
|
/rtl/modules/00.RightShiftReg.vhd
0,0 → 1,30
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity RightShiftReg is |
port( |
clock :in std_logic; |
enable :in std_logic; |
shift :in std_logic; |
din :in std_logic_vector; |
dout :out std_logic_vector(1 downto 0)); |
end RightShiftReg; |
|
architecture Behavioral of RightShiftReg is |
signal data : std_logic_vector(din'length-1 downto 0); |
begin |
process(clock,enable,shift) |
begin |
if(clock'event and clock = '1')then |
if(enable = '1')then |
data <= din; |
elsif(shift = '1') then |
data <= '0' & data(din'length-1 downto 1); |
else |
data <= data; |
end if; |
end if; |
end process; |
dout <= data(1 downto 0); |
end Behavioral; |
|
/rtl/modules/00.XorCrearor.vhd
0,0 → 1,24
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity XorCrearor is |
port( |
input1 : in std_logic; |
input2 : in std_logic_vector; |
result : out std_logic_vector); |
end XorCrearor; |
|
architecture Behavioral of XorCrearor is |
|
begin |
process(input1,input2) |
begin |
for i in input2'range loop |
result(i) <= input1 xor input2(i); |
end loop; |
end process; |
|
|
end Behavioral; |
|
/rtl/modules/01.BoothController.vhd
0,0 → 1,76
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
|
entity BoothController is |
Port ( |
clock : in std_logic; |
reset : in std_logic; |
start : in std_logic; |
interrupt : in std_logic; |
load : out std_logic; |
shift : out std_logic; |
cnt_clear : out std_logic; |
reg_clear : out std_logic; |
ready : out std_logic); |
end BoothController; |
|
|
architecture Behavioral of BoothController is |
|
type state_t is (reset_st,reset_and_load_st,calculating_st, calculated_st, done_st); |
signal current_state : state_t := reset_st; |
signal next_state : state_t := reset_st; |
|
begin |
process(clock, reset) |
begin |
if(reset = '1') then |
current_state <= reset_st; |
elsif (rising_edge(clock)) then |
current_state <= next_state; |
end if; |
end process; |
|
process(current_state, start, interrupt) |
begin |
load <= '0'; |
shift <= '0'; |
cnt_clear <= '0'; |
reg_clear <= '0'; |
|
case current_state is |
|
when reset_st => |
if(start = '1') then |
load <= '1'; |
reg_clear <= '1'; |
next_state <= reset_and_load_st; |
else |
next_state <= reset_st; |
end if; |
|
when reset_and_load_st => |
shift <= '1'; |
cnt_clear <= '1'; |
next_state <= calculating_st; |
|
when calculating_st => |
if(interrupt = '1') then |
next_state <= calculated_st; |
else |
shift <= '1'; |
next_state <= calculating_st; |
end if; |
|
when calculated_st => |
next_state <= done_st; |
|
when done_st => |
next_state <= done_st; |
|
end case; |
|
end process; |
ready <= '1' when current_state = done_st else '0'; |
end Behavioral; |
/rtl/modules/01.BoothDatapath.vhd
0,0 → 1,119
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity BoothDatapath is |
port( |
clock :in std_logic; |
reset :in std_logic; |
load :in std_logic; |
shift :in std_logic; |
X : in std_logic_vector; |
Y : in std_logic_vector; |
P : out std_logic_vector); |
end BoothDatapath; |
|
architecture Behavioral of BoothDatapath is |
|
component Regeister is |
port( |
clock :in std_logic; |
enable :in std_logic; |
reset :in std_logic; |
din :in std_logic_vector; |
dout :out std_logic_vector); |
end component; |
|
component LeftShiftReg is |
port( |
clock :in std_logic; |
enable :in std_logic; |
shift :in std_logic; |
din :in std_logic_vector; |
dout :out std_logic_vector); |
end component; |
|
component RightShiftReg is |
port( |
clock : in std_logic; |
enable : in std_logic; |
shift : in std_logic; |
din : in std_logic_vector; |
dout : out std_logic_vector(1 downto 0)); |
end component; |
component BoothEncoder is |
port( |
input1 : in std_logic; |
input0 : in std_logic; |
operator : out std_logic; |
product : out std_logic |
); |
end component; |
|
component Alu is |
port( |
A : in std_logic_vector; |
B : in std_logic_vector; |
op : in std_logic; |
S : out std_logic_vector); |
end component; |
component Ander is |
port( |
input1 : in std_logic; |
input2 : in std_logic_vector; |
result : out std_logic_vector); |
end component; |
signal sign_extended_x,andout,alu_out,p_out,X_reg_dout: std_logic_vector(2*X'length -1 downto 0); |
signal lessTwoBits : std_logic_vector(1 downto 0); |
signal operator,product : std_logic; |
signal Y_concat_zero : std_logic_vector(y'length downto 0); |
begin |
Y_concat_zero <= Y & '0'; |
sign_extended_x(X'range) <= X; |
sign_extended_x(sign_extended_x'length - 1 downto X'length) <= (others=> X(X'length-1)); |
|
Booth_ENC: BoothEncoder |
port map(input1 => lessTwoBits(1), |
input0=>lessTwoBits(0), |
operator => operator, |
product => product); |
|
Y_REG : RightShiftReg |
port map( |
clock => clock, |
enable => load, |
shift =>shift, |
din => Y_concat_zero, |
dout => lessTwoBits); |
|
X_REG : LeftShiftReg |
port map( |
clock => clock, |
enable => load, |
shift => shift, |
din => sign_extended_x, |
dout => X_reg_dout); |
|
ANDing : Ander |
port map( |
input1 => product, |
input2 => X_reg_dout, |
result => AndOut); |
|
Add_Sub : ALU |
port map( |
A => P_out, |
B => AndOut, |
op => operator, |
S => ALU_Out); |
|
P_REG : Regeister |
port map( |
clock => clock, |
enable => shift, |
reset => reset, |
din => ALU_Out, |
dout => P_out); |
P <= P_out; |
|
end Behavioral; |
|
/rtl/modules/02.BoothMultiplier.vhd
0,0 → 1,91
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity BoothMultiplier is |
generic(COUNTER_SIZE : positive := 2); |
port( |
clock : in std_logic; |
clear : in std_logic; |
start : in std_logic; |
X_data: in std_logic_vector(2**COUNTER_SIZE-1 downto 0); |
Y_data: in std_logic_vector(2**COUNTER_SIZE-1 downto 0); |
ready : out std_logic; |
Result: out std_logic_vector(2*(2**COUNTER_SIZE)-1 downto 0)); |
end BoothMultiplier; |
|
architecture Behavioral of BoothMultiplier is |
|
component counter is |
port( clock : in std_logic; |
reset : in std_logic; |
value : out std_logic_vector); |
end component counter; |
|
component BoothDatapath is |
port( |
clock :in std_logic; |
reset :in std_logic; |
load :in std_logic; |
shift :in std_logic; |
X :in std_logic_vector; |
Y :in std_logic_vector; |
P :out std_logic_vector); |
end component BoothDatapath; |
|
component BoothController is |
Port ( |
clock : in std_logic; |
reset : in std_logic; |
start : in std_logic; |
interrupt : in std_logic; |
load : out std_logic; |
shift : out std_logic; |
cnt_clear : out std_logic; |
reg_clear : out std_logic; |
ready : out std_logic); |
end component BoothController; |
|
signal load : std_logic; |
signal counter_value : std_logic_vector(COUNTER_SIZE - 1 downto 0); |
signal shift : std_logic; |
signal counter_interrupt : std_logic; |
signal cnt_clear : std_logic; |
signal reg_clear : std_logic; |
|
CONSTANT ONES : std_logic_vector(COUNTER_SIZE - 1 downto 0) := (others => '1'); |
|
begin |
|
datapath: BoothDatapath |
port map( |
clock => clock, |
reset => reg_clear, |
load => load, |
shift => shift, |
X => X_data, |
Y => Y_data, |
P => Result); |
|
counter_unit: counter |
port map( |
clock => clock, |
reset => cnt_clear, |
value => counter_value); |
|
counter_interrupt <= '1' when (counter_value = ONES) else '0'; |
|
controller: BoothController |
port map( |
clock => clock, |
reset => clear, |
start => start, |
interrupt => counter_interrupt, |
load => load, |
shift => shift, |
cnt_clear => cnt_clear, |
reg_clear => reg_clear, |
ready => ready); |
|
end Behavioral; |
|