Subversion Repositories gost28147

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trunk/BUGS Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/verilog/gost28147-89.sv =================================================================== --- trunk/rtl/verilog/gost28147-89.sv (nonexistent) +++ trunk/rtl/verilog/gost28147-89.sv (revision 2) @@ -0,0 +1,130 @@ +// $Id: $ From Russia with love + +///////////////////////////////////////////////////////////////////// +// This file is part of the GOST 28147-89 CryptoCore project // +// // +// Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com) // +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 100ps + +//`define GOST_R_3411_TESTPARAM (1) +//`define GOST_R_3411_CRYPTOPRO (1) +//`define GOST_R_3411_BOTH (1) + +module gost_28147_89 (clk, rst, mode, select, load, done, kload, key, pdata, cdata); + input clk; // Input clock signal for synchronous design + input rst; // Syncronous Reset input + input mode; // 0 - encrypt, 1 - decrypt + input select; // if GOST_R_3411_BOTH defined: 0 - Using the GOST R 34.11-94 TestParameter S-boxes; 1 - Using the CryptoPro S-boxes + input load; // load plain text and start cipher cycles + output done; // cipher text ready for output read + input kload; // load cipher key + input [255:0] key; // cipher key input + input [63:0] pdata; // plain text input + output [63:0] cdata; // cipher text output + +`ifdef GOST_R_3411_TESTPARAM +// Using the GOST R 34.11-94 TestParameter S-boxes +const logic [3:0] S1 [0:15] = { 4, 10, 9, 2, 13, 8, 0, 14, 6, 11, 1, 12, 7, 15, 5, 3}; +const logic [3:0] S2 [0:15] = { 14, 11, 4, 12, 6, 13, 15, 10, 2, 3, 8, 1, 0, 7, 5, 9}; +const logic [3:0] S3 [0:15] = { 5, 8, 1, 13, 10, 3, 4, 2, 14, 15, 12, 7, 6, 0, 9, 11}; +const logic [3:0] S4 [0:15] = { 7, 13, 10, 1, 0, 8, 9, 15, 14, 4, 6, 12, 11, 2, 5, 3}; +const logic [3:0] S5 [0:15] = { 6, 12, 7, 1, 5, 15, 13, 8, 4, 10, 9, 14, 0, 3, 11, 2}; +const logic [3:0] S6 [0:15] = { 4, 11, 10, 0, 7, 2, 1, 13, 3, 6, 8, 5, 9, 12, 15, 14}; +const logic [3:0] S7 [0:15] = { 13, 11, 4, 1, 3, 15, 5, 9, 0, 10, 14, 7, 6, 8, 2, 12}; +const logic [3:0] S8 [0:15] = { 1, 15, 13, 0, 5, 7, 10, 4, 9, 2, 3, 14, 6, 11, 8, 12}; +`endif +`ifdef GOST_R_3411_CRYPTOPRO +// Using the CryptoPro S-boxes +const logic [3:0] S1 [0:15] = { 10, 4, 5, 6, 8, 1, 3, 7, 13, 12, 14, 0, 9, 2, 11, 15}; +const logic [3:0] S2 [0:15] = { 5, 15, 4, 0, 2, 13, 11, 9, 1, 7, 6, 3, 12, 14, 10, 8}; +const logic [3:0] S3 [0:15] = { 7, 15, 12, 14, 9, 4, 1, 0, 3, 11, 5, 2, 6, 10, 8, 13}; +const logic [3:0] S4 [0:15] = { 4, 10, 7, 12, 0, 15, 2, 8, 14, 1, 6, 5, 13, 11, 9, 3}; +const logic [3:0] S5 [0:15] = { 7, 6, 4, 11, 9, 12, 2, 10, 1, 8, 0, 14, 15, 13, 3, 5}; +const logic [3:0] S6 [0:15] = { 7, 6, 2, 4, 13, 9, 15, 0, 10, 1, 5, 11, 8, 14, 12, 3}; +const logic [3:0] S7 [0:15] = { 13, 14, 4, 1, 7, 0, 5, 10, 3, 12, 8, 15, 6, 2, 9, 11}; +const logic [3:0] S8 [0:15] = { 1, 3, 10, 9, 5, 11, 4, 15, 8, 6, 7, 14, 13, 0, 2, 12}; +`endif +`ifdef GOST_R_3411_BOTH +// Using both parameter's Set S-Boxes: GOST R 34.11-94 TestParameter and CryptoPro +// GOST R 34.11-94 TestParameter S-boxes +const logic [3:0] S1_TESTPARAM [0:15] = { 4, 10, 9, 2, 13, 8, 0, 14, 6, 11, 1, 12, 7, 15, 5, 3}; +const logic [3:0] S2_TESTPARAM [0:15] = { 14, 11, 4, 12, 6, 13, 15, 10, 2, 3, 8, 1, 0, 7, 5, 9}; +const logic [3:0] S3_TESTPARAM [0:15] = { 5, 8, 1, 13, 10, 3, 4, 2, 14, 15, 12, 7, 6, 0, 9, 11}; +const logic [3:0] S4_TESTPARAM [0:15] = { 7, 13, 10, 1, 0, 8, 9, 15, 14, 4, 6, 12, 11, 2, 5, 3}; +const logic [3:0] S5_TESTPARAM [0:15] = { 6, 12, 7, 1, 5, 15, 13, 8, 4, 10, 9, 14, 0, 3, 11, 2}; +const logic [3:0] S6_TESTPARAM [0:15] = { 4, 11, 10, 0, 7, 2, 1, 13, 3, 6, 8, 5, 9, 12, 15, 14}; +const logic [3:0] S7_TESTPARAM [0:15] = { 13, 11, 4, 1, 3, 15, 5, 9, 0, 10, 14, 7, 6, 8, 2, 12}; +const logic [3:0] S8_TESTPARAM [0:15] = { 1, 15, 13, 0, 5, 7, 10, 4, 9, 2, 3, 14, 6, 11, 8, 12}; +// CryptoPro S-boxes +const logic [3:0] S1_CRYPTOPRO [0:15] = { 10, 4, 5, 6, 8, 1, 3, 7, 13, 12, 14, 0, 9, 2, 11, 15}; +const logic [3:0] S2_CRYPTOPRO [0:15] = { 5, 15, 4, 0, 2, 13, 11, 9, 1, 7, 6, 3, 12, 14, 10, 8}; +const logic [3:0] S3_CRYPTOPRO [0:15] = { 7, 15, 12, 14, 9, 4, 1, 0, 3, 11, 5, 2, 6, 10, 8, 13}; +const logic [3:0] S4_CRYPTOPRO [0:15] = { 4, 10, 7, 12, 0, 15, 2, 8, 14, 1, 6, 5, 13, 11, 9, 3}; +const logic [3:0] S5_CRYPTOPRO [0:15] = { 7, 6, 4, 11, 9, 12, 2, 10, 1, 8, 0, 14, 15, 13, 3, 5}; +const logic [3:0] S6_CRYPTOPRO [0:15] = { 7, 6, 2, 4, 13, 9, 15, 0, 10, 1, 5, 11, 8, 14, 12, 3}; +const logic [3:0] S7_CRYPTOPRO [0:15] = { 13, 14, 4, 1, 7, 0, 5, 10, 3, 12, 8, 15, 6, 2, 9, 11}; +const logic [3:0] S8_CRYPTOPRO [0:15] = { 1, 3, 10, 9, 5, 11, 4, 15, 8, 6, 7, 14, 13, 0, 2, 12}; +// define Sbox() function +`define Sbox(x,sel) ( sel ? {S8_CRYPTOPRO[x[31:28]],S7_CRYPTOPRO[x[27:24]],S6_CRYPTOPRO[x[23:20]],S5_CRYPTOPRO[x[19:16]], \ + S4_CRYPTOPRO[x[15:12]],S3_CRYPTOPRO[x[11:8]],S2_CRYPTOPRO[x[7:4]],S1_CRYPTOPRO[x[3:0]]} : \ + {S8_TESTPARAM[x[31:28]],S7_TESTPARAM[x[27:24]],S6_TESTPARAM[x[23:20]],S5_TESTPARAM[x[19:16]], \ + S4_TESTPARAM[x[15:12]],S3_TESTPARAM[x[11:8]],S2_TESTPARAM[x[7:4]],S1_TESTPARAM[x[3:0]]}) +`endif +`ifndef GOST_R_3411_BOTH +// define Sbox() function +`define Sbox(x,sel) {S8[x[31:28]],S7[x[27:24]],S6[x[23:20]],S5[x[19:16]],S4[x[15:12]],S3[x[11:8]],S2[x[7:4]],S1[x[3:0]]} +`endif + + +reg [4:0] i; // cipher cycles counter: 0..31; + +always_ff @(posedge clk) + if(rst || load) + i <= 5'h0; + else //if(~&i) + i <= i + 1; + +//reg run; //running cipher cycles flag + +wire [2:0] enc_index = (&i[4:3]) ? ~i[2:0] : i[2:0]; // cipher key index for encrypt +wire [2:0] dec_index = (|i[4:3]) ? ~i[2:0] : i[2:0]; // cipher key index for decrypt +wire [2:0] kindex = mode ? dec_index : enc_index; // cipher key index + +reg [31:0] K [0:7]; // cipher key storage + +always_ff @(posedge clk) + if(rst) + {K[0],K[1],K[2],K[3],K[4],K[5],K[6],K[7]} <= {256{1'b0}}; + else if(kload) + {K[0],K[1],K[2],K[3],K[4],K[5],K[6],K[7]} <= key; + + +reg [31:0] b, a; // MSB, LSB of input data +wire [31:0] state_addmod32 = a + K[kindex]; // Adding by module 32 +wire [31:0] state_sbox = `Sbox(state_addmod32,select); // S-box replacing +wire [31:0] state_shift11 = {state_sbox[20:0],state_sbox[31:21]}; // <<11 + +always_ff @(posedge clk) + if(rst) + {b,a} <= {64{1'b0}}; + else if(load) + {b,a} <= pdata; + else /*if(~&i)*/ begin + a <= b ^ state_shift11; + b <= a; + end + +reg r_done; +always_ff @(posedge clk) + if(rst) + r_done <= 1'b0; + else + r_done <= &i; + +assign done = r_done; //ready flag for output data +assign cdata = {a,b}; + +endmodule +

trunk/rtl/verilog/gost28147-89.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/TODO =================================================================== --- trunk/TODO (nonexistent) +++ trunk/TODO (revision 2) @@ -0,0 +1,23 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// TODO //// +//// //// +//// This file is part of the GOST 28147-89 CryptoCore project //// +//// //// +//// Author(s): //// +//// - Dmitry Murzinov (kakstattakim@gmail.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// + +// SVN Revision History +// +// $Log: $ +// +// + + +TODO: + + - Implementation testing with support Botan crypto-lib (VPI-based testbench). +

trunk/TODO Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/src/gost28147-89_tb.sv =================================================================== --- trunk/sim/src/gost28147-89_tb.sv (nonexistent) +++ trunk/sim/src/gost28147-89_tb.sv (revision 2) @@ -0,0 +1,137 @@ +// $Id: $ from Russia with love + +///////////////////////////////////////////////////////////////////// +// This file is part of the GOST 28147-89 CryptoCore project // +// // +// Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com) // +///////////////////////////////////////////////////////////////////// + +`timescale 1ns / 100ps + +module tb (); + +// clock generator settings: +parameter cycles_reset = 2; // rst active (clk) +parameter clk_period = 10; // clk period ns +parameter clk_delay = 0; // clk initial delay + +reg clk; // clock +reg rst; // sync reset +reg mode; // 0 - encrypt, 1 - decrypt +reg select; // if GOST_R_3411_BOTH defined: 0 - Using the GOST R 34.11-94 TestParameter S-boxes; 1 - Using the CryptoPro S-boxes +reg load; // load plain text and start cipher cycles +wire done; // cipher text ready for output read +reg kload; // load cipher key + +reg [255:0] key; // cipher key input +reg [63:0] pdata; // plain text input +wire [63:0] cdata; // cipher text output + +reg [63:0] pdata_d; // plain text input +wire [63:0] cdata_d; // cipher text output + +reg [63:0] reference_data; // reference data for verify + +wire EQUAL = cdata == reference_data; +wire [8*4-1:0] STATUS = EQUAL ? "OK" : "FAIL"; + +// instance connect +gost_28147_89 + u_cipher (.clk(clk), .rst(rst), .mode(mode), .select(select), .load(load), .done(done), .kload(kload), .key(key), .pdata(pdata), .cdata(cdata)); + + + reg [24:0] clk_counter; // just clock counter for debug + +// Clock generation + always begin + # (clk_delay); + forever # (clk_period/2) clk = ~clk; + end + +// Initial statement +initial begin + #0 clk = 1'b0; + load = 0; + kload = 0; + mode = 0; + select = 0; + key = 256'h0; + pdata = 64'h0; + clk_counter = 0; + + // Reset + #0 rst = 1'bX; + #0 rst = 1'b0; + # ( 2*clk_period *cycles_reset) rst = 1'b1; + # ( 2*clk_period *cycles_reset) rst = 1'b0; + + // key load + @ ( posedge clk ) #1 kload = 1; + key = swapkey(256'hBE5EC200_6CFF9DCF_52354959_F1FF0CBF_E95061B5_A648C103_87069C25_997C0672); + @ ( posedge clk ) #1 kload = 0; + + + // Crypt mode + @ ( posedge clk ) #1 load = 1; mode = 0; + pdata = swapdata(64'h0DF82802_B741A292); + reference_data = swapdata(64'h07F9027D_F7F7DF89); + @ ( posedge clk ) #1 load = 0; + + + // Decrypt mode + @ ( posedge done ); + @ ( posedge clk ) #1 load = 1; mode = 1; + pdata = swapdata(64'h07F9027D_F7F7DF89); + reference_data = swapdata(64'h0DF82802_B741A292); + @ ( posedge clk ) #1 load = 0; + + //$finish; + @ ( posedge done ); + @ ( posedge clk ) + #1 $stop; +end + +always begin + @( posedge clk ); + clk_counter <= clk_counter + 1; +end // always + +always @( posedge done ) + if (mode == 0) + #1 $display("KEY: %H \nCRYPT IN: %H \t REFOUT: %H \t OUT: %H ....%s\n", key, pdata, reference_data, cdata, STATUS); + else if (mode == 1) + #1 $display("KEY: %H \nDECRYPT IN: %H \t REFOUT: %H \t OUT: %H ....%s\n", key, pdata, reference_data, cdata, STATUS); + + +// ======= swap4(x) ======= +function [31:0] swap4( input [31:0] x ); +begin + swap4 = {x[7:0],x[15:8],x[23:16],x[31:24]}; +end +endfunction + +// ======= swapdate(data) ======= +function [63:0] swapdata( input [63:0] data ); +begin + swapdata = {swap4(data[31:0]),swap4(data[63:32])}; +end +endfunction + +// ======= swapkey(key) ======= +function [255:0] swapkey( input [255:0] key ); +logic [31:0] K [0:7]; +begin + K[0] = swap4(key[255:224]); + K[1] = swap4(key[223:192]); + K[2] = swap4(key[191:160]); + K[3] = swap4(key[159:128]); + K[4] = swap4(key[127:96]); + K[5] = swap4(key[95:64]); + K[6] = swap4(key[63:32]); + K[7] = swap4(key[31:0]); + swapkey = {K[0],K[1],K[2],K[3],K[4],K[5],K[6],K[7]}; +end +endfunction + +endmodule +// eof

trunk/sim/src/gost28147-89_tb.sv Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/bin/gost28147-89.tcl =================================================================== --- trunk/sim/bin/gost28147-89.tcl (nonexistent) +++ trunk/sim/bin/gost28147-89.tcl (revision 2) @@ -0,0 +1,39 @@ +## $Id: gost28147-89.tcl 13 2012-03-22 11:02:55Z Doka $ from Russia with love + +#################################################################### +# This file is part of the GOST 28147-89 CryptoCore project # +# # +# Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com) # +#################################################################### + +## Run this file with command: cd proj/gost28147/sim/bin; source gost28147-89.tcl + +set name_tb "gost28147-89_tb" +set timesim 2500ns + +##################################################### +## path to verilog source code +set dir_src ../../rtl/verilog +## path to testbenches dir +set dir_sim ../../sim/src +## path to script dir +set dir_script ../bin +## path to work dir +set dir_work ../run + +## set include file dirs +set dir_inc $dir_src+$dir_sim+../../rtl/tech + +## set project defines +set DEFINE GOST_R_3411_TESTPARAM + +##################################################### +quit -sim + +vlib work +vlog +define+$DEFINE +incdir+$dir_inc -sv $dir_src/gost28147-89.sv +vlog +define+$DEFINE +incdir+$dir_inc -sv $dir_sim/$name_tb.sv +vsim -novopt +notimingchecks -wlfdeleteonquit -t 1ns work.tb + +run $timesim +quit

trunk/sim/bin/gost28147-89.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/bin/gost28147-89_gui.tcl =================================================================== --- trunk/sim/bin/gost28147-89_gui.tcl (nonexistent) +++ trunk/sim/bin/gost28147-89_gui.tcl (revision 2) @@ -0,0 +1,86 @@ +## $Id: gost28147-89.tcl 13 2012-03-22 11:02:55Z Doka $ +## From Russia with love + +#################################################################### +# This file is part of the GOST 28147-89 CryptoCore project # +# # +# Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com) # +#################################################################### + +set name_tb "gost28147-89_tb" +set timesim 2500ns +#set timesim 1000us + +##################################################### +## path to verilog source code +set dir_src ../../rtl/verilog + +## path to testbenches dir +set dir_sim ../../sim/src + +## path to script dir +set dir_script ../bin + +## path to work dir +set dir_work ../run + +## set include file dirs +set dir_inc $dir_src+$dir_sim+../../rtl/tech + +## set project defines +set DEFINE GOST_R_3411_TESTPARAM + +##################################################### +quit -sim +vlib work +vlog +define+$DEFINE +incdir+$dir_inc -sv $dir_src/gost28147-89.sv +vlog +define+$DEFINE +incdir+$dir_inc -sv $dir_sim/$name_tb.sv +vsim -novopt +notimingchecks -wlfdeleteonquit -t 1ns work.tb + +##################################################### +radix -decimal +radix -unsigned +view wave + +add wave -color {indian red} -binary clk rst +add wave -color {violet} -hex clk_counter(7:0) +add wave -divider { - key - } +add wave -color {orange} -hex key kload + +add wave -divider { - u - } +add wave -color {aquamarine} -hex /u_cipher/a /u_cipher/b +add wave -color {pink} -hex /u_cipher/state_* + +add wave -divider { - state cycles - } +add wave -color {cyan} -dec -unsigned /u_cipher/i /u_cipher/kindex +add wave /u_cipher/mode + +add wave -divider { - IN - } +add wave -color {violet} -hex load pdata + +add wave -divider { - OUT - } +add wave -color {cyan} -hex done cdata reference_data + +add wave -divider { - EQUAL - } +add wave EQUAL +add wave -color {aquamarine} -ascii STATUS + +add wave -divider { - KEY - } +add wave -color {indian red} -hex /u_cipher/K(0) /u_cipher/K(1) /u_cipher/K(2) /u_cipher/K(3) /u_cipher/K(4) /u_cipher/K(5) /u_cipher/K(6) /u_cipher/K(7) + +add wave -divider { - data - } +add wave -color {orange} -hex pdata +add wave -color {orange} -hex cdata + +##################################################### +run $timesim +#WaveRestoreZoom 400ns $timesim +WaveRestoreZoom 0ns 800ns + + + + + + + +

trunk/sim/bin/gost28147-89_gui.tcl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/bin/synplify.tcl =================================================================== --- trunk/syn/bin/synplify.tcl (nonexistent) +++ trunk/syn/bin/synplify.tcl (revision 2) @@ -0,0 +1,76 @@ +# $Id: $ From Russia with love +# synplify -enable64bit -batch synplify.tcl + +#################################################################### +# This file is part of the GOST 28147-89 CryptoCore project # +# # +# Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com) # +#################################################################### + + +######## generic synthesis procedures for Synplif FPGA-Compiler ######## + + + +#add_file options +add_file -verilog -vlog_std sysv ../../rtl/verilog/gost28147-89.sv + +#implementation: "xilinx" +impl -add xilinx -type fpga + +#device options +set_option -technology SPARTAN3E +set_option -part XC3S100E +set_option -package VQ100 +set_option -speed_grade -4 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "gost_28147_89" +set_option -vlog_std sysv +set_option -project_relative_includes 1 +set_option -enable64bit 1 +set_option -hdl_define -set GOST_R_3411_TESTPARAM +set_option -include_path "../../rtl/verilog" +set_option -default_enum_encoding default +set_option -resource_sharing 1 +set_option -use_fsm_explorer 0 +set_option -compiler_compatible 0 +set_option -multi_file_compilation_unit 1 + + +#map options +set_option -frequency 100.000 +#set_option -frequency auto +set_option -vendor_xcompatible_mode 0 +set_option -run_prop_extract 1 +set_option -fanout_limit 10000 +set_option -disable_io_insertion 1 +set_option -pipe 1 +set_option -update_models_cp 0 +set_option -verification_mode 0 +set_option -retiming 1 +set_option -no_sequential_opt 0 +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -num_critical_paths 10 +set_option -num_startend_points 10 +set_option -dup 0 +set_option -symbolic_fsm_compiler 1 + +#simulation options +set_option -write_verilog 1 +set_option -write_vhdl 0 + +#VIF options +set_option -write_vif 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "../out/gost28147.edf" + +impl -active "xilinx" + +run Index: trunk/Makefile =================================================================== --- trunk/Makefile (nonexistent) +++ trunk/Makefile (revision 2) @@ -0,0 +1,69 @@ +# $Id: $ From Russia with love + +# ====================================================================== # +# # +# Makefile for GOST 28147-89 CryptoCore project # +# # +# Copyright (c) 2014 Dmitry Murzinov (kakstattakim@gmail.com) # +# # +# ====================================================================== # + + +# project name +PROJECT=gost28147_89 +SOURCES=$(PROJECT).sv + +SIM_DIR=./sim/bin +SYN_DIR=./syn/bin +CUR_DIR=$(shell pwd) + +#ICARUS_SETUP:=. /soft/icarus.setup +#MENTOR_SETUP:=. /soft/mentor.setup +MENTOR_SETUP:=date +#SYNPLIFY_SETUP:=. /soft/synplify.setup +SYNPLIFY_SETUP:=date + +####################################################################### +all: synthesis +default_target: help + +synthesis: syn + +##### HELP target ##### +help: + @echo "" + @echo " Current project: $(PROJECT)" + @echo " Current directory: $(CUR_DIR)" + @echo "" + @echo " Available targets :" + @echo " ==================" + @echo " make : print this text" + @echo " make synthesis : synthesize design using Synplify to get netlist" + @echo " make sim : compile and run simulation RTL-design using ModelSim" + @echo " make sim-gui : compile and run simulation RTL-design using ModelSim with GUI" + @echo " make clean : remove all temporary files" + @echo "" + +##### SIM target ##### +sim: + @cd $(SIM_DIR);\ + $(MENTOR_SETUP);\ + vsim -c -quiet -do gost28147-89.tcl;\ + cd $(CUR_DIR); +sim-gui: + @cd $(SIM_DIR);\ + $(MENTOR_SETUP);\ + vsim -do gost28147-89_gui.tcl;\ + cd $(CUR_DIR); + + +##### SYN target ##### +syn: + @cd $(SYN_DIR);\ + $(SYNPLIFY_SETUP);\ + synplify_pro -enable64bit -batch synplify.tcl;\ + cd $(CUR_DIR); + +##### PHONY target ##### +.PHONY : clean syn sim + \ No newline at end of file

trunk/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/README =================================================================== --- trunk/README (nonexistent) +++ trunk/README (revision 2) @@ -0,0 +1,18 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// README //// +//// //// +//// This file is part of the GOST 28147-89 CryptoCore project //// +//// //// +//// Author(s): //// +//// - Dmitry Murzinov (kakstattakim@gmail.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// SVN Revision History +// +// $Log: $ +// +// +//

trunk/README Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property