URL
https://opencores.org/ocsvn/gpib_controller/gpib_controller/trunk
Subversion Repositories gpib_controller
Compare Revisions
- This comparison shows the changes necessary to convert path
/gpib_controller/trunk/prototype_1/fpga/xilinx_prj/iseconfig
- from Rev 5 to Rev 8
- ↔ Reverse comparison
Rev 5 → Rev 8
/proto1.projectmgr
6,7 → 6,6
<!--This is an ISE project configuration file.--> |
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > |
<ClosedNodes> |
<ClosedNode></ClosedNode> |
<ClosedNode>/EdgeDetector - arch</ClosedNode> |
<ClosedNode>/Fifo8b - arch</ClosedNode> |
<ClosedNode>/Fifo8b_Test_vhd - behavior</ClosedNode> |
15,6 → 14,7
<ClosedNode>/Uart - arch</ClosedNode> |
<ClosedNode>/gpibInterface - Behavioral</ClosedNode> |
<ClosedNode>/main - Behavioral</ClosedNode> |
<ClosedNode>/main - Behavioral/gpib0 - RegsGpibFasade - arch</ClosedNode> |
<ClosedNode>/main - Behavioral/gpib0 - RegsGpibFasade - arch/ev - EventReg - arch</ClosedNode> |
<ClosedNode>/main - Behavioral/gpib0 - RegsGpibFasade - arch/gpib - gpibInterface - Behavioral</ClosedNode> |
<ClosedNode>/main - Behavioral/gpib0 - RegsGpibFasade - arch/ig - InterruptGenerator - arch</ClosedNode> |
24,26 → 24,28
<ClosedNode>/main - Behavioral/gpib0 - RegsGpibFasade - arch/writerFifo - Fifo8b - arch</ClosedNode> |
</ClosedNodes> |
<SelectedItems> |
<SelectedItem>gpib - gpibInterface - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/src/gpib/gpibInterface.vhd)</SelectedItem> |
<SelectedItem>main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/src/main.vhd)</SelectedItem> |
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<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> |
<CurrentItem>gpib - gpibInterface - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB/vhdl/src/gpib/gpibInterface.vhd)</CurrentItem> |
<CurrentItem>main - Behavioral (/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/src/main.vhd)</CurrentItem> |
</ItemView> |
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > |
<ClosedNodes> |
<ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode> |
<ClosedNode>Implement Design</ClosedNode> |
<ClosedNode>Synthesize - XST</ClosedNode> |
</ClosedNodes> |
<SelectedItems> |
<SelectedItem>Add Existing Source</SelectedItem> |
<SelectedItem></SelectedItem> |
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>Add Existing Source</CurrentItem> |
<CurrentItem></CurrentItem> |
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<ItemView guiview="File" > |
<ClosedNodes/> |
50,35 → 52,33
<SelectedItems/> |
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>commandDecoder.vhd</CurrentItem> |
<CurrentItem>main.ucf</CurrentItem> |
</ItemView> |
<ItemView guiview="Library" > |
<ClosedNodes> |
<ClosedNode>work</ClosedNode> |
</ClosedNodes> |
<ClosedNodes/> |
<SelectedItems/> |
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>work</CurrentItem> |
</ItemView> |
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" > |
<ClosedNodes> |
<ClosedNode>Design Utilities</ClosedNode> |
<ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode> |
<ClosedNode>Implement Design</ClosedNode> |
<ClosedNode>Synthesize - XST</ClosedNode> |
</ClosedNodes> |
<SelectedItems> |
<SelectedItem>Add Existing Source</SelectedItem> |
<SelectedItem>Generate Programming File</SelectedItem> |
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> |
<ScrollbarPosition orientation="vertical" >6</ScrollbarPosition> |
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>Add Existing Source</CurrentItem> |
<CurrentItem>Generate Programming File</CurrentItem> |
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" > |
<ClosedNodes> |
89,7 → 89,7
</SelectedItems> |
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> |
<CurrentItem>Add Existing Source</CurrentItem> |
</ItemView> |
/main.xreport
1,11 → 1,11
<?xml version='1.0' encoding='UTF-8'?> |
<report-views version="2.0" > |
<header> |
<DateModified>2013-01-05T20:16:41</DateModified> |
<DateModified>2013-01-05T23:24:20</DateModified> |
<ModuleName>main</ModuleName> |
<SummaryTimeStamp>2012-02-13T21:38:35</SummaryTimeStamp> |
<SavedFilePath>/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/iseconfig/main.xreport</SavedFilePath> |
<ImplementationReportsDirectory>/home/andrzej/apaluch/projects/elektronika/GPIB/prototype_1/fpga/proto1/</ImplementationReportsDirectory> |
<SavedFilePath>/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/iseconfig/main.xreport</SavedFilePath> |
<ImplementationReportsDirectory>/home/andrzej/apaluch/projects/elektronika/GPIB_fpga/xilinx_prj/</ImplementationReportsDirectory> |
<DateInitialized>2012-01-25T02:08:45</DateInitialized> |
<EnableMessageFiltering>true</EnableMessageFiltering> |
</header> |