OpenCores
URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /gpio/tags/rel_11/sim
    from Rev 51 to Rev 65
    ↔ Reverse comparison
  •

Rev 51 → Rev 65

/rtl_sim/log/ncelab.log
0,0 → 1,45
TOOL: ncelab 04.10-b001: Started on Dec 01, 2003 at 15:32:24
ncelab
-f ncelab.args
-MESSAGES
-NOCOPYRIGHT
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-LOGFILE ../log/ncelab.log
-SNAPSHOT worklib.bench:rtl
-NO_TCHK_MSG
-ACCESS +RWC
worklib.tb_tasks
worklib.gpio_testbench
 
Elaborating the design hierarchy:
Caching library 'worklib' ....... Done
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.clkrst:v <0x67faf15a>
streams: 2, words: 1034
worklib.gpio_mon:v <0x50b5485b>
streams: 6, words: 1408
worklib.gpio_testbench:v <0x2b2f512c>
streams: 2, words: 300
worklib.gpio_top:v <0x2a4cd65a>
streams: 72, words: 55544
worklib.tb_tasks:v <0x3e6d21f9>
streams: 33, words: 52966
worklib.wb_master:v <0x2119db6d>
streams: 38, words: 21648
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 6 6
Registers: 122 122
Scalar wires: 23 -
Vectored wires: 14 -
Always blocks: 24 24
Initial blocks: 3 3
Cont. assignments: 10 17
Pseudo assignments: 2 43
Simulation timescale: 10ps
Writing initial simulation snapshot: worklib.bench:rtl
TOOL: ncelab 04.10-b001: Exiting on Dec 01, 2003 at 15:32:26 (total: 00:00:02)
/rtl_sim/log/ncvlog.log
0,0 → 1,36
TOOL: ncvlog 04.10-b001: Started on Dec 01, 2003 at 15:32:23
ncvlog
-f ncvlog.args
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-MESSAGES
-INCDIR ../../../bench/verilog
-INCDIR ../../../rtl/verilog
-NOCOPYRIGHT
-LOGFILE ../log/ncvlog.log
../../../rtl/verilog/gpio_top.v
../../../bench/verilog/clkrst.v
../../../bench/verilog/gpio_mon.v
../../../bench/verilog/wb_master.v
../../../bench/verilog/tb_tasks.v
../../../bench/verilog/gpio_testbench.v
 
file: ../../../rtl/verilog/gpio_top.v
module worklib.gpio_top:v
errors: 0, warnings: 0
file: ../../../bench/verilog/clkrst.v
module worklib.clkrst:v
errors: 0, warnings: 0
file: ../../../bench/verilog/gpio_mon.v
module worklib.gpio_mon:v
errors: 0, warnings: 0
file: ../../../bench/verilog/wb_master.v
module worklib.wb_master:v
errors: 0, warnings: 0
file: ../../../bench/verilog/tb_tasks.v
module worklib.tb_tasks:v
errors: 0, warnings: 0
file: ../../../bench/verilog/gpio_testbench.v
module worklib.gpio_testbench:v
errors: 0, warnings: 0
TOOL: ncvlog 04.10-b001: Exiting on Dec 01, 2003 at 15:32:24 (total: 00:00:01)
/rtl_sim/log/ncsim.log
0,0 → 1,43
TOOL: ncsim 04.10-b001: Started on Dec 01, 2003 at 15:32:26
ncsim
-LICQUEUE
-f ./ncsim.args
-MESSAGES
-NOCOPYRIGHT
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-INPUT ncsim.tcl
-LOGFILE ../log/ncsim.log
worklib.bench:rtl
 
Loading snapshot worklib.bench:rtl .................... Done
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
ncsim> run
 
###
### GPIO IP Core Verification ###
###
 
I. Testing correct operation of RGPIO_CTRL control bits
 
Testing control bit RGPIO_CTRL[ECLK] ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... OK
Testing control bit RGPIO_CTRL[NEC] ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... OK
Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ... OK
 
II. Testing modes of operation ...
 
Testing input mode ... OK
Testing output mode ... OK
Testing bidirectional I/O ... OK
Testing auxiliary feature ... OK
Testing ptrig features ... OK
 
###
### FAILED TESTS: 0 ###
###
 
report (deaddead)
exit (00000000)
/projects/highland/gorand/ttt/gpio/bench/verilog/tb_tasks.v:1009 $finish(0);
ncsim> quit
TOOL: ncsim 04.10-b001: Exiting on Dec 01, 2003 at 15:35:23 (total: 00:02:57)
/rtl_sim/run/ncsim.tcl
0,0 → 1,2
run
quit
/rtl_sim/run/run_sim_gpio
0,0 → 1,102
#!/bin/csh -f
 
if ( $# < 1 ) then
echo "First argument must be a top level module name!"
exit
else
set SIM_TOP = $1
endif
 
set current_par = 1
set output_waveform = 0
while ( $current_par < $# )
@ current_par = $current_par + 1
case wave:
@ output_waveform = 1
breaksw
default:
echo 'Unknown option "'$argv[$current_par]'"!'
exit
breaksw
endsw
end
 
echo "-CDSLIB ../bin/cds.lib" > ncvlog.args
echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args
echo "-MESSAGES" >> ncvlog.args
echo "-INCDIR ../../../bench/verilog" >> ncvlog.args
echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args
echo "-NOCOPYRIGHT" >> ncvlog.args
echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args
 
foreach filename ( `cat ../bin/rtl_file_list` )
echo "../../../rtl/verilog/"$filename >> ncvlog.args
end
 
foreach filename ( `cat ../bin/sim_file_list` )
echo "../../../bench/verilog/"$filename >> ncvlog.args
end
 
ncvlog -f ncvlog.args
 
echo "-MESSAGES" > ncelab.args
echo "-NOCOPYRIGHT" >> ncelab.args
echo "-CDSLIB ../bin/cds.lib" >> ncelab.args
echo "-HDLVAR ../bin/hdl.var" >> ncelab.args
echo "-LOGFILE ../log/ncelab.log" >> ncelab.args
echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args
echo "-NO_TCHK_MSG" >> ncelab.args
echo "-ACCESS +RWC" >> ncelab.args
echo "worklib.tb_tasks" >> ncelab.args
echo worklib.$SIM_TOP >> ncelab.args
 
ncelab -f ncelab.args
 
echo "-MESSAGES" > ncsim.args
echo "-NOCOPYRIGHT" >> ncsim.args
echo "-CDSLIB ../bin/cds.lib" >> ncsim.args
echo "-HDLVAR ../bin/hdl.var" >> ncsim.args
echo "-INPUT ncsim.tcl" >> ncsim.args
echo "-LOGFILE ../log/ncsim.log" >> ncsim.args
echo "worklib.bench:rtl" >> ncsim.args
 
if ( $output_waveform ) then
echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl
echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl
echo "run" >> ./ncsim.tcl
else
echo "run" > ./ncsim.tcl
endif
 
echo "quit" >> ncsim.tcl
 
ncsim -LICQUEUE -f ./ncsim.args
 
set exit_line_nb = `sed -n '/exit/=' < ../log/ncsim.log`
 
#echo "$exit_line_nb"
 
set dead_line_nb = 0
 
if ( $exit_line_nb ) then
 
@ dead_line_nb = $exit_line_nb - 1
set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ../log/ncsim.log`
set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ../log/ncsim.log`
 
echo "$dead_line"
echo "$exit_line"
 
echo "TEST: gpio"
if ( "$dead_line" == "report (deaddead)" ) then
if ( "$exit_line" == "exit (00000000)" ) then
echo "STATUS: passed" #|tee -a ../log/run_sim.log 2>&1
else
echo "STATUS: failed" #|tee -a ../log/run_sim.log 2>&1
endif
else
echo "STATUS: failed"
endif
 
endif
 
rtl_sim/run/run_sim_gpio Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/run/run_sim =================================================================== --- rtl_sim/run/run_sim (nonexistent) +++ rtl_sim/run/run_sim (revision 65) @@ -0,0 +1,3 @@ +#!/bin/sh +./run_sim_gpio gpio_testbench +
rtl_sim/run/run_sim Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/run/ncelab.args =================================================================== --- rtl_sim/run/ncelab.args (nonexistent) +++ rtl_sim/run/ncelab.args (revision 65) @@ -0,0 +1,10 @@ +-MESSAGES +-NOCOPYRIGHT +-CDSLIB ../bin/cds.lib +-HDLVAR ../bin/hdl.var +-LOGFILE ../log/ncelab.log +-SNAPSHOT worklib.bench:rtl +-NO_TCHK_MSG +-ACCESS +RWC +worklib.tb_tasks +worklib.gpio_testbench Index: rtl_sim/run/ncvlog.args =================================================================== --- rtl_sim/run/ncvlog.args (nonexistent) +++ rtl_sim/run/ncvlog.args (revision 65) @@ -0,0 +1,13 @@ +-CDSLIB ../bin/cds.lib +-HDLVAR ../bin/hdl.var +-MESSAGES +-INCDIR ../../../bench/verilog +-INCDIR ../../../rtl/verilog +-NOCOPYRIGHT +-LOGFILE ../log/ncvlog.log +../../../rtl/verilog/gpio_top.v +../../../bench/verilog/clkrst.v +../../../bench/verilog/gpio_mon.v +../../../bench/verilog/wb_master.v +../../../bench/verilog/tb_tasks.v +../../../bench/verilog/gpio_testbench.v Index: rtl_sim/run/ncsim.args =================================================================== --- rtl_sim/run/ncsim.args (nonexistent) +++ rtl_sim/run/ncsim.args (revision 65) @@ -0,0 +1,7 @@ +-MESSAGES +-NOCOPYRIGHT +-CDSLIB ../bin/cds.lib +-HDLVAR ../bin/hdl.var +-INPUT ncsim.tcl +-LOGFILE ../log/ncsim.log +worklib.bench:rtl Index: rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak =================================================================== --- rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak (nonexistent) +++ rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak (revision 65) @@ -0,0 +1,3266 @@ +ӵۀ՝ٛ• jDkX=J%WW:_,O.B' X?$(H.5?GO(8(((Ղ;Ղ;|lNr@@`f>`>(>>`D @X@|@CD@xDC ޱèĭ @CAC @뿿-A-(A(A@@ PA@@ xA@ `@ C@ p@ C A-A}0BAAB.  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A. + BEE+(GE F@E'xFEF-B}HF pFF- +F F0HE@@FhG@GGxG..P A. +P BGG4`HFP F@(G0x@GF`G-p0B}xG +pGG-p@G @G4XIF@GHxH@ؘ>0BXDBDBEI0J0B@B@BAXC0ACPAӵٞӛۙēﴰϲq>hjDkX^phqt8l.q%d7|/Lb:L O(kE)@.[# +<7ohhewwZRRTBBo:j)h;~~STSHHiHfI9K$N+HN'Hg`m*\9K"N!FgFhFiGiFhFiGiFhFi nc $R7E,@/HiHH<^efawY//.^,C)L/[(oa ej!F)[:T0xa!C&H+Cl +dg.//.//./M(F%MbqjizG3R!J9aa|tdi "TT3C*E~}zlB445E7X2W4@3tz~q:]2@!O+cz:H`>==(>>p @X@|@@@98BBB ޱèĭ@@ @$쿿(!A@0@8!PA@@@4!A@P KHtD@@I:xXIH@J. E .`)I-2B]+IJ-7XI. :xFIHp<p+Jp7( Jp:h0JiI@J XI$L@ 0J`K8KLpKA.@ PB. +@ PDKKGMJ@tD@ KCx8KJ` L.p E ppp.`*pK-3pB],pKK-8p8K. ;pxFpKpXpLp,pKp8p(Lp;phLipK L 8KNH@ +L@MMtNPMJ`. PB. + PDLLPNLtD@MLxML N.0 E 000.`(0M-10B]*0MM-60M. 90xFPM0hp\p*0Mp60(Mp90hMi0xMN M pPA@ N ONTP0OS . PB. + PDNNYPNtD@NUxNNO. E .`)O-2B]+OO-7N. :xF0Oxplp+Op7(Op:hOiXOO N PR@@ pdPQP4RQ\. PB. + PDPPbRpPtD@P^xPpPQ. E .`)xQ-2B]+`QQ-7P. :xFQp|p+Qp7(Qp:hQi8QQ P䪪TXB@ +0DRRTRe.P PB.P PD@RRkUPR +PRRgPR`S.p E  ppp.`'pXS-0pB])p@S`S-5pRSRpp)ppSp5pHSipSSR8V0hhTPT RGPIO_IN: %h h% :NI_OIPGR -R R VpP@ T UVHUr.  PB.  PD@TTx@WT + RUtT0U.@ E @@@.`(@E-1@B]*@UU-6@ U8VHU@p*@Up6@HUi@pUUHUPpX0PpVV RGPIO_OUT: %h h% :TUO_OIPGR -P U U⧧ YG@ +VXWYW` . PB. PD@ W0WpYV + R@WV X. E   .`' H-0 B]) WW-5 XWpXW p) Wp5 HXi WXW0 Z00 `XX + RGPIO_OE:%hh%:EO_OIPGR -0 XW XW$X[T@ YY<[Y0 +. PB. PD@PY`Y[ Y + RpY Y @Z. E   .`) I-2 B]+ ZZ-7 YZY p+  Zp7 H0Zi Y@ZY +\0 +p[Z RGPIO_INTE:%h h%:ETNI_OIPGR - +Y Y(] Y@ + +L[[t][ . + PB. + PD@[[]X[ + +R[X[ +x\. + E + + +.`* +K-3 +B], +8\H\-8 +[\[ +p, +X\p8 +Hh\i +\x\[ +_0 +x@](] RGPIO_PTRIG:%h h%:GIRTP_OIPGR - +[ [ _@ P ]]_ ^ .p PB.p PD@]]`] +p R]] ^. E   .`( M-1 B]* p^^-6 ]_ ^ p* ^p6 H^i H^^ ^ Ha0 hx_`_ RGPIO_AUX:%h h%:XUA_OIPGR - ] ]$b@ _0`aX` .@ PB.@ PD@_`Pb_ +@ R`_P `.` E ` ` ` .`)` O-2` B]+` ``-7` 0`HaX`` p+` `p7` H`i` ``X`p c0p xaa RGPIO_CTRL: %h h% :LRTC_OIPGR -p 0` 0`$8d@ ahbdbp +. + PB. + PD@0b@bdb + +RPbb + c.0 + E 0 +0 +0 +.`)0 +xQ-20 +B]+0 +bb-70 +hbcb0 + p+0 +cp70 +Hci0 +b cb@ +$(v0@ +pcc RGPIO_INTS:%h h%:STNI_OIPGR -@ +hb hb g_@ +,ddd|ge. + PB. + + PDhdxd8ed8d +tD@dxedPe8ddxd. PB. PD@e(egxed8d +R8e8d + +d8d 0f.0 E 000.`'0XS-00B])0ef-50PePge04,p)0fp50H fi0e0f-PPe-PdO +Pff-`d}Pg`ff.` A-d}Pgg@g. PDePffg PedHiC@ g(hh,i8hp.  PB.  PDggigRgxhg0h.@ E @@@.`'@XS-0@B])@hh-5@h8h@@8p)@hp5@Hhi@`hh hⶶjX[@ +0 A])0(Z$080Np$0NH-`H `u p`uppp-pHxpppx. Apph -k Ї|Pj -k 0|j@P. PD pp -k |x$j -k X|(jhx- p u,p u000-0p00p0x```.` PD`4p`pp pp-pk p؊|Xp8jp -k 8|<jHX. A @pp -k |Dj  -k `|Hjp- gLph. APpp   - k x| Tj  00-0k 0؍|H0Xj0@@@.@ PD@\p@p8 PP-Pk P| P`jP ``-`k `|X`dj` - ؐghphH-- HO - -pOȏ؏Sؐ lؒ0 hX..- @A}ؐ +@pȐ-@A.@ AJ@ pH0`g@Dh)-XB. AKP`. + PD@pnБ Twj wq( wu X $y! T}!(  ؒp00!P( Testing input mode ...0... edom tupni gnitseT . PD Ntp N- } Г. PD- X} P. + PD- + X.  +.* L pU `-- X}/ Д(-1 X.4 AJ3 ; p- ؕ8 uxp u`   - P8 |p xȕ !!-!k +!0|8!j!@P  ! !- !k + !|8 !j !- P!Б8P!gp P!hؖ-!- +!БP +!(8-!}!X- !.! AJ +!8!HhȘ (8-"="Ș "80" OKKO Ș0"B" 0P"H0"P"h@ Testing output mode ...8... edom tuptuo gnitseT -"}"ؙ." PD-"X}" . +" PD- +"X." .*" L"@PU"0`--"X}/"ؚ-1"X.4" AJ3"Ț;" -#}x#H6 +# - +##Cp +#xDh @#@#-@#k +@#Л|P@#j@# P#P#-P#k +P#0|P#jP#@P0###-#Б#p#(-#- +#БP +#-#}# x- #.# AJ +#Xh#0"p-0$=0$؝ @$80@$XH OKKO `$B0$`$0($0 Testing bidirectional I/O ...@... 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DXl ??XX0??XlH?@D0@(@HBB'V}7<8_<С0@Pr@ @bpa??X;@ @X7< @@@H!c!0 HH@!0 HI@!0 v8IhIA!0 vII@A!0Њ vIJA!0 v@JpJA!0 vxJJB!0p vJ K@B!0Ph`KKB!0 K@LB!0 +"LLC!0  %Б(MpM@C!0X %MNC!0 +% `NNC!0ȟ%HOHOD!0%pOO@D!08  PHPD!0 gpPPD!0H hPPE!0 hx QPQ@E!0 hxQQE!0X hHQRE!0 h(RXRF!0 hRR@F!0h hRSF!00SHSF!0ȶ  pSTG!0 UpW@G!0  pXY[G!0` H]x^G!0 X_`H! +G`aa@H!  +dHfg,FAILED !!!" HKDE% K 0 p",2EQyЅ% @LPp",{26Bjv%v @=P`qp",{26Bjv%v @=P@qp",{26Bjv%v @=P qpъ",{26Bjv%v `@`=Pqp",{26Bjv%v @@@=Pqp",{26Bjv%v @ =Pqpqg0H RGPIO_IN: " ,{2 +9 PKjDK%v @Pj 0 pQg4HK RGPIO_OUT: " ,{2: KkDK%v (@(Pؕk h pg,K RGPIO_OE:" ,{2= LnDK"%v `@`Pn  pg4xL RGPIO_INTE:" ,{2@ MqDK%%v @P@q К ( p!g8M RGPIO_PTRIG:" ,{2@ MqDK%%v Ȝ@ȜPxq  ` pYg0M RGPIO_AUX:" ,{2@ PNqDK%%v @Pq @  pg8HN RGPIO_CTRL: " ,{2@ NqDK%%v 8@8Pq x С pɟg4N RGPIO_INTS:" ,{2@ OqDK%%v p@pP q   p",{2 + %v @P0p9",{2 +[g%v @PȨbp",{2\h%v Ȫ@ȪPxcpI",{2\h%v x@xP(cp",{2\h%v (@(Pحcp",{2\h%v د@دPcpY",{2\h%v @P8cp ",{2\h%v 8@8Pcp",{2\h%v @Pcpi"X@Ы%X pgO.",Џ,BNFSaкA#9H~ДDгAF[gМ +9 +O +| +Ј + % +; +G +DL +Z +} +F +А + + ++APМDл hSD %hP@@ع=@8\PXPкP 4@@P0P PbPXP@PJ +@ +P @x6 +@ؿU +P +PH +P<@@@P pɶg`S.",Џ,B]AbpsFxІ +CYhд.DS П F о  +, +8 +D z А  +$ +0f|D2>JЖ)5kЁD UIDи%xP@x=@kPXPPPxT@@hP?@0 @ P P3 +P @ @p +Pw@8@P9P @@$PH|@@8PXI 8pgdU Testing input mode ...ghX OKghX Testing output mode ...gX OKgX Testing bidirectional I/O ...gX OKgY Testing auxiliary feature ...gY OK",` pXDAF[gsп&D+9 XDgE@@Н XDO@@Х +? +U +n +z +4 Xe D E @@ X +D +@ +@ + +-CRО YD +E0@@5CC YtD@JV@A+@n@sЁ1JV PYD?Eb@@guУ% P PpbP@h@4P `g P O Px@P +@hu +Pe ( P` +  + +PH>@@8P  + >P@t  QPP P+ |P@0,@QP ? pPp!gHY Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...g\ OK",` \D"9@A>L]BbpAЕAн!Wm$3i A . 7 +m +Ѓ +  @F $  @]DGEj@@o}Ы%P 0PGPkPPPP  +@h@P@Xz@@) P~ +@( @ P `G xPpagt8] Testing ptrig features ...g _ OK",` (_D&=BBPb@AguAКA&\r*9oЅ! A& 4 E BJ X a + +Э +   P_ODE@@%P !PKPpPXPP@m@P%@0@@/ PpS P +@P @O  PpgxH_Spurious interrupt detected. " РJ 8a{DE@@'E%@x +{   P ' i0adcv.pot_bt/tuo/..ga###gb### GPIO IP Core Verification ###g b###gPbI. Testing correct operation of RGPIO_CTRL control bitsg`b Testing control bit RGPIO_CTRL[ECLK] ...gb OKgb Testing control bit RGPIO_CTRL[NEC] ...gb OKg(cII. Testing modes of operation ...g8c###gLhc### FAILED TESTS: gxc ###gc###gc/projects/highland/gorand/gpio/bench/verilog/tb_tasks.v:989 $finish; +" = aSP +TP U>JsдE b3D~E (bDE0 XbaDEE hbCDEE b%D_Fdr bDiE@@П bD +G 0cDE7@@<JMGR`E @cD' Er E @G У G й E + pc5 +D +E + c +D: GU c D E c Dh E E c  + +м +% + EP zPX +P + 3 `~   a   C (  % XmPP i P@ P x EP[P  ' r P` P 5 +  + + :    @h  +@0X;?@X@, +, +FlGFDGFDVHvpvtvHvDFtDhdžEdžFDFtFpFDFH +vpvtvHvDFtDhdžFdžFDFtFp] U؃FËV ډ]U 0 +, +4 +FlᐐFDFlFDFD$dždžFD8NjFDFlGFDGE8U4FxFDF|FHqFtxhFh@FtFP@$F<FFtFhS^PC$[FS^hC[FhS^C[FlFlS^h[ᐐFtxhCE,F]0ZCnDiI FlᐐFthOo~Fl?S^[FFtxFlᐐFDFlFDFD$dždžFD8NjFDFlGFDGFxFDF|FHqFtxhFh@FtFP@$F<FFtFhS^PC$[FS^hC[FhS^C[FlFlS^h[ᐐFtxhCEs]+sp9Tzd20&P#WW0G(Z1]4Vx,n1e*zT7Aou}S> Xl +:;n +#O&H=EkZiQ eKe}da-y;d0/Lb:L O(kEu +9_oZn];Xvsh><*I&BBcX?DXl ??XX.??XlgDPgDDgDD(DHD*{7< 8<0@8@ @@Dm??X;@ @X7< @@@@!p [ @@"Д%@p 0X;?@X@Vt1B FHBFDFlflfl NlNlFH9)FDFH@FDFHPFDBJ FtFh@ FtFh@ FtFlᐐX;@X?  @ԁ@@ӵƟҘږ߉㭠ۡv -] jDkXMc{ bg+|>a,m>j/}S0FhrzT9{| q_n]eK=N::s]*E7\0Y;B_STCm xV L#Dj)aU6R3cV7urQ`SkE6_88q_(G5^2[9@]QVAo" zT"N!Fh+cW4P1aT5wp}SbQiG$K//iX? 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A0FXM 0p20Mp>0XMpA0Mi0MN M ڿ˨ܮxPH@ N(OO\P8OS . PB. + PDNNYPNtD@NUxONO. E .`1O-:B]3OO-?O. BF8O p3Op?XOpBOi`OO O ڿˢ̸XRC@ plPQP@(U@VPU @p2@HUp>@Ui@xUUPUPxX0PpVV RGPIO_OUT: %h h% :TUO_OIPGR -P(U (Uݵڭ§(Y@@ +V`W YW` . PB. PD@(W8WxYV + RHWV X. E  .`/  H-8 B]1 WW-= `WxXW ,$p1 HWp= Xi WXW0 0Z00 `XX + RGPIO_OE:%hh%:EO_OIPGR -0 `W `W$۳ܫ¬ؽ`[A@ YYD[Y0 +. PB. PD@XYhY[(Y + RxY(Y HZ. E  .`1 J-: B]3 ZZ-? YZY @8p3 H(Zp? 8Zi YHZY +D\0 +p[Z RGPIO_INTE:%h h%:ETNI_OIPGR - +Y Y(ذߨج޷]V@ + +T[[|][ . + PB. + PD@[[]`[ + +R[`[ +\. + E + + +.`2 +K-; +B]4 +@\P\-@ +[\[ +TLp4 +H`\p@ +p\i +\\[ +X_0 +xH]0] RGPIO_PTRIG:%h h%:GIRTP_OIPGR - +[ [ ڲݪ˾_`[@ P ]^_(^ .p PB.p PD@]] `] +p R]] ^. E  .`0 M-9 B]2 x^^-> ^_(^ h`p2 H^p> ^i P^^(^ lPa0 h_h_ RGPIO_AUX:%h h%:XUA_OIPGR - ^ ^$۳ܫȼ΢bT@ _8`a`` .@ PB.@ PD@``Xb_ +@ R `_P `.` E` ` ` .`1` O-:` B]3` ``-?` 8`Pa`` ` |tp3` H`p?` `i` ````p c0p xaa RGPIO_CTRL: %h h% :LRTC_OIPGR -p 8` 8`$۳ܫ¬ث@d@ apb$dbp +. + PB. + PD@8bHbdb + +RXbb +(c.0 + E0 +0 + 0 +.`10 +Q-:0 +B]30 +bb-?0 +pbcb 0 +p30 +Hcp?0 +ci0 +b(cb@ +0v0@ +pcc RGPIO_INTS:%h h%:STNI_OIPGR -@ +pb pb ʥȸgxP@ +4dddge. + PB. + + PDpdd@ed@d +tD@dxedߺXe@ddxd. PB. PD@ e0eged@d +R@e@d + +d@d 8f.0 E00 0.`/0`S-80B]10ef-=0XeXge 0p10Hfp=0(fi0e8f-PXe-PdO +Pff-`d}Xg`fg.` A-d}XggHg. PDePff g XedȭٰPiB@ g0hh4i@hp.  PB.  PDggigRgxhg0h.@ E@@ @.`/@`S-8@B]1@hh-=@h@h @p1@Hhp=@hi@hhh hɬط¶k(Y@ +Diiiji0.  PB.  PDiiPkPiRixiPij. E .`0E-9B]2@jPj->ii p2H`jp>pjijj iȭٶl@d@ jkhklk.  PB.  PD0k@kmkRPkxhkk0l. E .`/ H-8B]1kl-=hkk p1Hlp= lik0l hk Ϋ߶ج`nk@ @l@mmDnPm. P PB. P PDllnlPRmxmlpm. E .`1J-:B]3mm-?mPm p3Hmp?mixmm m$Ϫޮڨpb@ Tnnnoop.  PB.  PDnn `p`nRnxn`n0o.@ E@@ @.`2@K-;@B]4@Po`o-@@no @p4@Hpop@@oi@(oo nɬع̴q@ +ppxpqp0.  PB.  PD@pPprpR`pxxpp@q. E .`0M-9B]2qq->xpp p2H qp>0qip@q xp Ϋ߼Ⱥpsl@ qPr(rTs`r.  PB.  PDqrsqRrx(rqr. E .`1O-:B]3rr-?(r`r p3Hrp?rirr (r Ϋ߶ج u`n@ @dstsut . P PB. P PDss&pupsPRs"xspspt. E .`1Q-:B]3`tpt-?st p3Htp?ti8tt s0ǦȬîvL@uuuvu)p.  PB.  PDPu`u/@w uRpu+xu u0u-@u}u@uv 6 +@ u.@ A.@ PB]@Pv`v.!@ AK @pvvY@0vv u(ߺɽЃg@ +v`wx2-XB. AKww. + PD@ w0w8(x wv\w@w4 wvw@w; Hxvw@w?-XB. AKww. + PD@xxG xx`wvDx(xC xwvtx(xJ wvx(xNvHy$Ͽֹ䊊4Ǣ։  $ .&  PDyx$ (p& 8y΢ 00-0k 0y|(zx0 j0yy @@-@k @z|`zx@j@z(z-Hxzx  upuPz,ټȗ"-%Hx({x"Hp%z.  PD{xNp O{ @@-@k @{||x@ j@{{ PP-Pk P{|8|xP$jP{|-`w|xg(ph(|.  A." PD] x|||xN,p O|-@xx`}x @ u0p@u|PP"P-%Pxx}x"PH4p%PP}$.& PD@~x$(8p&} -k  ~|~x<j0~@~ -k ~|~x@j~~$.& Ahx$(Dp&~ -k H|xHjXh -k |xLj-wPxgPph-xx  uTpu@"-%x0x"HXp% -k |x\j 0 -k p|ȁx`j- wx gdp h-`w- HxO -w-xxO8HS(X-w-$wO!xShh0 ..- A} + x-A. AJXhx0 xHxxx$ܹʾꉉ(q@ 0ă T`!(Ѓ +@\wV!PЃ@wZ!xЃ +PDx^!(ЃPtxbЃ`$.& PDh$(lp& -k H|ȅpjXh -k |`tjȅ. 0 A."0 PD] 0.&0 A.>0 A])0 0Z$0@0Nxp$0OP-`P ` u|p`upp"p-%pP"pHp%p$.& A$(p&p -k ؇|Xj -k 8|jHX$.& PD $(p& -k |j  -k `|jp- x  up u00"0-%0x"0Hp%0``$`.&` PD$`(p&`x pp-pk p|`pjp -k @|jP`$.& A($(p& -k |j( -k h|jx-(gph$.& A$(p&   - k | j  00-0k 0|P0j0@@$@.&@ PDȎ$@(p&@@ PP-Pk P|(PjPȎ ``-`k `|``j`(-(gphP-- PO -(-xOЏS 0 p`..- @A} +@xА-@A.@ AJ@ Px0ףh_@Lh)-XB. AKXh. + PD@xnؑ(\wj(wq0(wu `(,y!( \}Ⱥ!ؑ((80!X0 Testing input mode ...0... edom tupni gnitseT . PD Np O- } ؓ. PD- `} X. + PD- + `.  +.* L xU h-- `}/ ؔ0-1 `.4 AJ3  ; x- @ up uh  # -& X@# Hp& Е !!-!k +!8|@!j!HX  ! !- !k + !|@ !j !- P!ؑȗ@P!gp P!h-!- +!ؑP +!0@-!}ȗ!`- !.! AJ +!@!PpИ 0Ȕ@-"="И "`0" OKKO И0"B"(8P"P0"P"pH Testing output mode ...8... edom tuptuo gnitseT -"}"." PD-"`}"(. +" PD- +"`." .*" L"HXU"8h--"`}/"-1"`.4" AJ3"К;"(-#}#P6 +#(- +##Cp +#xDp @#@#-@#k +@#؛|X@#j@# P#P#-P#k +P#8|P# jP#HX0ҷÜ##$#-'#ؑ$#p'#-#- +#ؑP +#-#}#(- #.# AJ +#`p#8"x-0$=0$ @$`0@$`P OKKO `$B0$h$ 0($8 Testing bidirectional I/O ...@... O/I lanoitceridib gnitseT -%}%x.% PD-%`}%. +% PD- +%`.% .*% L%(U%8--%`}/%X-1%`.4% AJ3%;%-0%}P0% 6 +0%(- @%ȡ@%Gp @%G@ p%p%-p%k +p%|(p% jp%ȡ %%-%k +%|%$j%(0ҷÜ%%$%-'%ؑp$%(p'%8x-%-%ؑ> %آP +%Ȣ-%}p%`- %.% AJ +%@P%x%ПHh-`&=`&x p&`,0p&@0 OKKO x&B`&УHh&00(& Testing auxiliary feature ...@... erutaef yrailixua gnitseT -0'}@0'X.0' PD-@'`}@@'إ. +@' PD- +@'`.@' .*@' L@'U@'--@'`}@/@'8-1@'`.4@' AJ3@'p@;@'ئ-`'}X`'Ȧ6 +`'Ч(0ƣ׈p'p'$p'-'p'$p'p4p'p'H-'ؑ}'Ч6 +'x(- +'ؑP'L8p +' M-'}'@x6 +'(- +' 'C<p +'xD  ( (- (k + (| (@j (  0(0(-0(k +0(`|Щ0(Dj0(p`(`($`(-'`(0$`(Hp'`(-(- +(ؑY +( -(-(ؑ>(PY(@`Z(0p-(0P(-(}(- (.( AJ +(( @'(H-0)=0)h @)`L0@)ث OKKO  `)B0)x `0(ߺɽv@ +)\0/!h +)\w!h)w!h)w!8h),!hh *\߱!8h*d!h*!h +*Dxh *0@*P80G@*X? Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...... ]TNI[LRTC_OIPGR dna ]ETNI[LRTC_OIPGR tib lortnoc gnitseT - +*A}x* X.* PD-*}*h.* PD-+8}+. ++ PD- ++8.+ .*+ L+U+(--+8}/+H-1+8.5+ AJ3+<+-0+}0+ذ. 0+ A.0+ PB] 0+ .0+ AK0+0@.d%0+ xY0+P`@+@+#@+-&@+#@+HTp&@+. p+ PDX p+JXp p+@K. ++ PDز+xP\p ++PH. ++ A.#+ ] ++(+N`p ++OȲ- ,,Hdp ,`I 0,0,-0,k +0,|0,hj0, @,@,-@,k +@,|8@,lj@,-p,}дp,($Ͽֹ(ܾp,p,'p,-'p,(,,#,.%, PDH#,Hpp%, ,,-,k +,(|,tj,8H ,,-,k +,|,xj, ,,-,k +,|@,|j,- -} -0 - -' --' -(. +P- PDP-Np +P-O ----k +-|x-j- ----k +-X|-j-hx--}---'--'-(- --psp -s- .- .= .`T + .Pp- .T .- .-! .P .T .и) .(-0.}0.p- 0..0. AJ +0.P` .+8X- +.A}к.й.. A-.=.к .`0. OKKO к/B.(8 h,޻ȼ(@/ Hl`4!p +/\w!/w!/w! /\!/d!8p/!H +/Dx/H`/0%/ؼ Testing ptrig features ...8... serutaef girtp gnitseT - +`0A}``08p.`0 PD-0}`0.0 PD-0}0Ƚ. +0 PD- +0.0 .*0 L0 0U0@--0}/0`-10.50 AJ30<0-08}Ⱦ0. 0 A.0 PB] 0(8.0 AK0HX.d%0 xY0hx00#0.d.0 PDȾ#0Hp.0. + 1 PD`Ⱦ 1xPp + 1P.dP1 xȾ P1JpP1@KP. +1 A.#1 ] +1 Ⱦ1Np +1O- 18Ⱦ1Hp 1`I 11-1k +1x|Ⱦ1j1 11-1k +1|0Ⱦ1j1- 2H}Ⱦ 2 p 2 2' 2-' 2(P2P2#P2.d.P2 x Ⱦ#P2Hp.P2 22-2k +2|Ⱦ2j2  22-2k +2`|Ⱦ2j2p 22-2k +2|Ⱦ2j2-2p}xȾ2X22'2-'2(. +3 PDȾ3Np +3Oh. +3 PD@Ⱦ3xPp +3P @3@3-@3k +@3 |Ⱦ@3j@30@ P3P3-P3k +P3|ȾP3jP3-3}Ⱦ333'3-'3(-3H-3p= 38T +3(H-3T3Xh-3}3- 3.3 AJ +3Ⱦ3xP`0ؽPpȾ- +4A}@`4@x.4 A-`4=`4@ p4`0p4 OKKO @4B``4 85'515-15(k5-5AX5 5`(0) 5`8Spurious interrupt detected. @ .detceted tpurretni suoirupS05B- +@5PA}(@5.@5 & P5`5j5X@5X!ps@ 5\ 5 5(0%5`../out/gpio_testbench.vcd8dcv.hcnebtset_oipg/tuo/.. 5 (敕. 5 PD- 6@}h 6H. +6 PD- + 6A} 6X. 6 A- 06PA}06.06 PD@6@6"@6.$@6 PDx"@6Hp$@6P6P6#P6.%P6 PD#P6pp%P6h`6`6$`6.&`6 PD $`6(p&`6Pp6`P6`06######6`0,68"### GPIO IP Core Verification ###H### noitacifireV eroC PI OIPG ###6`06######6`6`0B6h8I. Testing correct operation of RGPIO_CTRL control bitspstib lortnoc LRTC_OIPGR fo noitarepo tcerroc gnitseT .IH6`H87037P+ Testing control bit RGPIO_CTRL[ECLK] ...X... ]KLCE[LRTC_OIPGR tib lortnoc gnitseT - +7A} 7(`.7 PD- 7} 7p. + 7 PD- + 7. 7 .* 7 L 7U 7-- 7}/ 7`-1 7.5 7 AJ3 7@P +07v 7p-@7A.@7 PDO@7 P7`0P7XH OKKO p7B@7`7 h027H@* Testing control bit RGPIO_CTRL[NEC] ...X... ]CEN[LRTC_OIPGR tib lortnoc gnitseT - +7A} 7.7 PD-7}7. +7 PD- +7.7 .*7 L78HU7(X--7}/7x-17.57 AJ37 7Ѓ7h-7A.7 PDO78H 7`X07 OKKO 8B(7XhX 08hP8`P`8`P0-`8#II. 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ЉGGG3F F3^ ډӁ WkWGFDFHFtxFpS^tC [S^tC[FlᐐFtx@ FpFt@Ft@1ҊFpFpPFt<@F5!ډՁVЃ5!Ӊ ډكЃ, +F , + , +, +4Ft040 +4 +, +wdž8 +dž< +, +<4 + < +0 +38 +< + < +0 + 8 +8 + 8 +8 +0 +< +4 +Vt1B FHBFD0 +4 +Flfl NlNl)ȹ NlFH9)FDFH@FDFHPFDBJ Ft@FFtFhFFtFh@@FphFtxډ=@E(F],E0V ډӃ 5U0FDFHFtxFpS^tC [S^tC[FlᐐFtx@ FpFt@Ft@G](U,E0G1؉F_1Ӊ ډӃ WuWU0FDGFHFtxFpS^tC [S^tC[FlᐐFtx@ FpFt@Ft@1ҊFpFpPFtF FtFFtFFtFF5‹F Љŋ^ ^V V^ !n F !ЉFF Fŋ^ ^V Vn!^F!ЉŋF5#^ 5#VF F Љʼn5#^V ntVD^HE$FlE(FMfDfHFD1FlFH1FFl FF&AFiEFDE$FHE(Ft@FFtFhFFtFh@@FphFtxډ=@E4F]8E<V ډӁ UZhY?(D-C6N`QbZtn @nvoj&R0oz b?r\*rq8U{K3eS74RkE)@.[# +<7zqqgXP? ,DXl P?P?XX0P?P?Xl@@D@@BB;1h-:<Hv<0@p@  +^#y?p@EPE;@ @X:< @@@H!Xi!08 HH@!0^XHI@!0#`IIA!0#IJ@A!0#@JpJA!0#0JJA!0#X KPKB!0x#KK@B!0XL`LB!0 0LMB!0 +hMMC!0( `NXN@C!0` NOC!0 +hOOC!0@P`PD!0PQ@D!0@PQQD!0xQQD!0PP0R`RE!00RR@E!0S0SE!0`hSSE!0бSTF!08ThT@F!0pTTF!0 pU UF!0`PUVG!0 (XY@G!0($@(\`^G!0h,( aPbG!0;#cdH!J7Xff@H!_ *h:ilg,FAILED !!!" HKDE,8%K 0  3p",2*R^% H @_   %PYp",{2#%v @$   Php",{2#%v @$ x  PHp",{2#%v @$ X h xP(p",{2#%v h@h$ 8 H XPp",{2#%v H@H$  ( 8Pp",{2#%v (@($   Ppyg0H RGPIO_IN: " ,{2:F LD:KwЃ% v @! AP  8: ~pYg4L RGPIO_OUT: " ,{2=I LDFKЏ% v 0@0$ DP  pF pg,L RGPIO_OE:" ,{2=I XMDQKК% v h@h$ HDP  Q pg4PM RGPIO_INTE:" ,{2=I NDQKК% v @$ xDPH 8 Q 0p)g8M RGPIO_PTRIG:" ,{2=I NDQKК% v @$ DP p Q hpag0N RGPIO_AUX:" ,{2=I XODQKК% v @$ DP  HQ pg8PO RGPIO_CTRL: " ,{2=I PDQKК% v @@@$ DP  Q pg4O RGPIO_INTS:" ,{2=I PDQKК% v x@x$ XDP(  Q p ",{2:F% v @! hAP8 (v  pA",{2:F%v @ ! AP p",{2=I%v @$ DP ppQ",{2=I%v @$ `DP0 p",{2=I%v 0@0$ DP p",{2=I%v @$ DP pa",{2=I%v @$ pDP@ 0p",{2=I%v @@@$ DP p",{2=I%v @$ DP pq"X@% X p!gP.",м#Yo{FЎp|A !0f|DЛ;A@NQFVdF R д + +  Q g +'6lЂDСF I_nкD HUDл% xPH@j@@P` PW wP XP(@w@P8 (/ IP_P - M P`  P @Xb @  P"@}@P PPr @ PZ@H@P2   pg@U.",м#YoAFл ,bx,8D z А + + + +F + + < H T + +Р +Wcoл"D'54JYХ +LbqнDH XyD% P@j@ P`P4  HP Ps@@p 3P @8  +@  P _  P + P +# +C P + +@ @x > ^P @@ @ 0P   X +P( +E@ +@ PP]@@@P`1 Py @ xpgdX Testing input mode ...g8[ OKgh`[ Testing output mode ...gp[ OKg[ Testing bidirectional I/O ...g[ OKg[ Testing auxiliary feature ...g[ OK",` @[DAF%4jЀDП h[LDE@@ x[D* +@ +@ + +  I _ n + +к + + +c [DE@@ [FDr@?@DR[Ч' [D9E\@@aoo [D@@A#@@ BXg г $ \9$D$E$@@$к$$$%,  P/ q Px8 h P @p{@P  `Q L h P (R  * + +  +  PZ @ +@p +P@ 7 (  0 PhF  x r  3 !MPP!@!@@""P" x" # X  $9 jPH$ $ X%6 % / & 'PX' h ' 0(P(#  @( (P(S@8) @) P)9! )" *># 8&9$ +$ $P+$p)g\ Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...g` OK",` `DvЂ@A BZA_mA(7mЃFR^Ъ  + J ` + A  & +\ +r +C@FHV aDjE@@Р% 8. / h/[ / 0] 1}P1 82P2 2PX2N 3hP2 X3P(3#@3~@4 (4- 5MP4@`5 +@5[ @ 6 06 6 P6m +@07@77 7QP8 8 9 H0s 9 h:j P:pi,gta Testing ptrig features ...gc OK",` cDT`Bа@ABAGUAлUk4@LИ  8 N A B BG U ^ + +Ъ + c3D~E@@д% < 8= =[ = >; ?[P? @@P@ @P`@6 APP@ PAP A @Af@B B B;PB@8C @CI @C D D PxD6 DP PD +@XE@Eo E F `> @G3 G~ PHp;gxcSpurious interrupt detected. " РJ 0f{DE@@eE%@J{ I PI, Ie i(fdcv.hcnebtset_oipg/tuo/..gf###g g### GPIO IP Core Verification ###g0g###g`gI. Testing correct operation of RGPIO_CTRL control bitsgpg Testing control bit RGPIO_CTRL[ECLK] ...gg OKgg Testing control bit RGPIO_CTRL[NEC] ...gh OKg8hII. Testing modes of operation ...gHh###gLxh### FAILED TESTS: gh ###gh###g$hreport (gh)g@hexit (00000000)g$hreport (gi)g@(iexit (00000000)g@8i/projects/highland/gorand/ttt/gpio/bench/verilog/tb_tasks.v:1009 $finish(0); +"` = fSPKTPKUMYиE (g7DE 8gDE4 hgeDEE xgGDEE g)DF   g:DE@@л hD G + @h +DH Ek @@p ~ G Д E Ph D[ E E @G G  +E8 + hi +D +E + hDwG hDE) hZDEEh hDK" hSDE hD5EU iDK 0i@DE @iD"E= `igs*% K K) Ld XL L @MPM4 MTPxM NPM 7 N  N e O  G HP  ) xQo (R pRPpSS S: (T P`T T2 Uf U PV + xV + WH y PW P(X  X[ PY PY + i + @Z +  Zw [ Z Z `[   P\ \S P\  \5  ] ]@ ]  @^" a ^%@_ 1;1:;;  ܄,T|<܄ +,5T]| 8`؍<8A`i؍  ]҉"J<]f҉ۉ"+JSHɑT$ĞdtT4ԴɑґT]$-Ğ͞dm +t}T]4=Դݴ: :C˔ ˔Ԕc cl   C CL    ) AJAJ ! ӭ ӭܭ  s s|S S\3 3<7 7@0 +3C^<\ +$3<CL^g<=G GP0BU3&+=<\BKU^3&<&++=<F<$ +v&.'/D + v&/.'7'//T T] &Z Zc  @C$ +@@CCT T]  Q QZ$o/w4 +Dox/8w4= +% +$3v~ +D%3<v~ + +xo$xox8$8A +$+4$-s s| <<<  y  y  "$6;,""$$66;; A!AJ!! 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JmVVM| P?W\z Y  mV mV,Q/CMH ?mV,Q/GM|  ?D$MbmVVM?7. `l + mV mVuѺCM + ?KJmVuѺGM8 + +? mVVM +?$7yMi( | +mV +mVZoCM +H ?bmVZoGM + +?& +mVVM ?oGs 8 mVH mVCCM| 8 ?gmVCGM 8 +l ?MmVVM ?\2 z mV sFSS8 +?7& +mVwCMl  ?mVwGM 8 +?rmVVM\ +?| + + mV mV帝CM( + +?2 H +mV帝GM\ + +?mVVM? + +mVOуCM +( +?rmVOуGM| ? +mVVM?>>I&T?S:XX4]3F>>L8TT""@%K(@@'W>Qzlzqzzl3G&U>MM:Xj x i| e +U8W99Z6]/\((O?V9f} + +yD0_//h8q>a5z**}?`-l?k.||(j5a.~~*h7c"q:ii.~7x'j%kk(d/}.zz#| \ No newline at end of file Index: rtl_sim/bin/sim_file_list =================================================================== --- rtl_sim/bin/sim_file_list (nonexistent) +++ rtl_sim/bin/sim_file_list (revision 65) @@ -0,0 +1,7 @@ +clkrst.v +gpio_mon.v +wb_master.v +tb_tasks.v +gpio_testbench.v + +
rtl_sim/bin/sim_file_list Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/bin/sim.sh =================================================================== --- rtl_sim/bin/sim.sh (nonexistent) +++ rtl_sim/bin/sim.sh (revision 65) @@ -0,0 +1,125 @@ +#!/bin/bash + +# +# This script runs RTL and gate-level simulation using different simultion tools. +# Right now Cadence Verilog-XL and NCSim are supported. +# +# Author: Damjan Lampret +# + +# +# User definitions +# + +# Set simulation tool you are using (xl, ncsim, ncver) +SIMTOOL=ncsim + +# Set test bench top module(s) +TB_TOP="tb_tasks" + +# Set include directories +INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/" + +# Set test bench files +BENCH_FILES="../../../bench/verilog/*.v" + +# Set RTL source files +RTL_FILES="../../../rtl/verilog/*.v" + +# Set gate-level netlist files +GATE_FILES="../syn/out/final_gpio.v" + +# Set libraries (standard cell etc.) +LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v" + +# Set parameters for simulation tool +if [ $SIMTOOL == xl ]; then + PARAM="+turbo+3 -q" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +elif [ $SIMTOOL == ncver ]; then + NCVER_PARAM="" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +elif [ $SIMTOOL == ncsim ]; then + NCPREP_PARAM="-UPDATE +overwrite" + NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0 +fi + +# +# Don't change anything below unless you know what you are doing +# + +# Run simulation in sim directory +#cd ../sim + +# Run actual simulation + +# Cadence Verilog-XL +if [ $SIMTOOL == xl ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES + + # Gate-level simulation + elif [ "$1" == gate ]; then + verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Cadence Ncverilog +elif [ $SIMTOOL == ncver ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES + cp ncverilog.log ../log + + # Gate-level simulation + elif [ "$1" == gate ]; then + ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + cp ncverilog.log ../log + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Cadence Ncsim +elif [ $SIMTOOL == ncsim ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES + ./RUN_NC + + # Gate-level simulation + elif [ "$1" == gate ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + ./RUN_NC + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Unsupported simulation tool +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0; +fi
rtl_sim/bin/sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/bin/rtl_file_list =================================================================== --- rtl_sim/bin/rtl_file_list (nonexistent) +++ rtl_sim/bin/rtl_file_list (revision 65) @@ -0,0 +1 @@ +gpio_top.v
rtl_sim/bin/rtl_file_list Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl_sim/bin/cds.lib =================================================================== --- rtl_sim/bin/cds.lib (nonexistent) +++ rtl_sim/bin/cds.lib (revision 65) @@ -0,0 +1,6 @@ +# +# cds.lib: Defines the locations of compiled libraries. +# Created by ncprep on Tue Nov 11 00:24:06 2003 +# + +define worklib ./INCA_libs/worklib Index: rtl_sim/bin/hdl.var =================================================================== --- rtl_sim/bin/hdl.var (nonexistent) +++ rtl_sim/bin/hdl.var (revision 65) @@ -0,0 +1,9 @@ +# +# hdl.var: Defines variables used by the INCA tools. +# Created by ncprep on Tue Nov 11 00:24:06 2003 +# + +softinclude $CDS_INST_DIR/tools/inca/files/hdl.var + +define LIB_MAP ( $LIB_MAP, + => worklib ) +define VIEW_MAP ( $VIEW_MAP, .v => v)

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