URL
https://opencores.org/ocsvn/gpio/gpio/trunk
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/gpio/tags/rel_6/bench/verilog
- from Rev 38 to Rev 65
- ↔ Reverse comparison
Rev 38 → Rev 65
/wb_master.v
0,0 → 1,308
`include "timescale.v" |
`include "gpio_defines.v" |
|
// -*- Mode: Verilog -*- |
// Filename : wb_master.v |
// Description : Wishbone Master Behavorial |
// Author : Winefred Washington |
// Created On : Thu Jan 11 21:18:41 2001 |
// Last Modified By: . |
// Last Modified On: . |
// Update Count : 0 |
// Status : Unknown, Use with caution! |
|
// Description Specification |
// General Description: 8, 16, 32-bit WISHBONE Master |
// Supported cycles: MASTER, READ/WRITE |
// MASTER, BLOCK READ/WRITE |
// MASTER, RMW |
// Data port, size: 8, 16, 32-bit |
// Data port, granularity 8-bit |
// Data port, Max. operand size 32-bit |
// Data transfer ordering: little endian |
// Data transfer sequencing: undefined |
// |
|
module wb_master(CLK_I, RST_I, TAG_I, TAG_O, |
ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); |
|
parameter aw = `GPIO_ADDRHH+1 ; |
input CLK_I; |
input RST_I; |
input [3:0] TAG_I; |
output [3:0] TAG_O; |
input ACK_I; |
output [aw-1:0] ADR_O; |
output CYC_O; |
input [31:0] DAT_I; |
output [31:0] DAT_O; |
input ERR_I; |
input RTY_I; |
output [3:0] SEL_O; |
output STB_O; |
output WE_O; |
|
reg [aw-1:0] ADR_O; |
reg [3:0] SEL_O; |
reg CYC_O; |
reg STB_O; |
reg WE_O; |
reg [31:0] DAT_O; |
|
wire [15:0] mem_sizes; // determines the data width of an address range |
reg [31:0] write_burst_buffer[0:7]; |
reg [31:0] read_burst_buffer[0:7]; |
|
reg GO; |
integer cycle_end; |
integer address; |
integer data; |
integer selects; |
integer write_flag; |
|
// |
// mem_sizes determines the data widths of memory space |
// The memory space is divided into eight regions. Each |
// region is controlled by a two bit field. |
// |
// Bits |
// 00 = 8 bit memory space |
// 01 = 16 bit |
// 10 = 32 bit |
// 11 = 64 bit (not supported in this model |
// |
|
assign mem_sizes = 16'b10_01_10_11_00_01_10_11; |
|
function [1:0] data_width; |
input [31:0] adr; |
begin |
casex (adr[31:29]) |
3'b000: data_width = mem_sizes[15:14]; |
3'b001: data_width = mem_sizes[13:12]; |
3'b010: data_width = mem_sizes[11:10]; |
3'b011: data_width = mem_sizes[9:8]; |
3'b100: data_width = mem_sizes[7:6]; |
3'b101: data_width = mem_sizes[5:4]; |
3'b110: data_width = mem_sizes[3:2]; |
3'b111: data_width = mem_sizes[1:0]; |
3'bxxx: data_width = 2'bxx; |
endcase // casex (adr[31:29]) |
end |
endfunction |
|
always @(posedge CLK_I or posedge RST_I) |
begin |
if (RST_I) |
begin |
GO = 1'b0; |
end |
end |
|
// read single |
task rd; |
input [31:0] adr; |
output [31:0] result; |
|
begin |
cycle_end = 1; |
address = adr; |
selects = 255; |
write_flag = 0; |
|
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
// wait for cycle to start |
while (~CYC_O) |
@(posedge CLK_I); |
|
// wait for cycle to end |
while (CYC_O) |
@(posedge CLK_I); |
|
result = data; |
// $display(" Reading %h from address %h", result, address); |
|
end |
endtask // read |
|
task wr; |
input [31:0] adr; |
input [31:0] dat; |
input [3:0] sel; |
begin |
cycle_end = 1; |
address = adr; |
selects = sel; |
write_flag = 1; |
data = dat; |
|
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
// wait for cycle to start |
while (~CYC_O) |
@(posedge CLK_I); |
|
// wait for cycle to end |
while (CYC_O) |
@(posedge CLK_I); |
// $display(" Writing %h to address %h", data, address); |
|
end |
endtask // wr |
|
// block read |
task blkrd; |
input [31:0] adr; |
input end_flag; |
output [31:0] result; |
|
begin |
write_flag = 0; |
cycle_end = end_flag; |
address = adr; |
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
|
result = data; |
end |
endtask // blkrd |
|
// block write |
task blkwr; |
input [31:0] adr; |
input [31:0] dat; |
input [3:0] sel; |
input end_flag; |
begin |
write_flag = 1; |
cycle_end = end_flag; |
address = adr; |
data = dat; |
selects = sel; |
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
|
end |
endtask // blkwr |
|
// RMW |
task rmw; |
input [31:0] adr; |
input [31:0] dat; |
input [3:0] sel; |
output [31:0] result; |
|
begin |
// read phase |
write_flag = 0; |
cycle_end = 0; |
address = adr; |
GO <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
|
result = data; |
|
// write phase |
write_flag = 1; |
address = adr; |
selects = sel; |
GO <= 1; |
data <= dat; |
cycle_end <= 1; |
@(posedge CLK_I); |
// GO <= 0; |
|
while (~(ACK_I & STB_O)) |
@(posedge CLK_I); |
|
end |
endtask // rmw |
|
always @(posedge CLK_I) |
begin |
if (RST_I) |
ADR_O <= 32'h0000_0000; |
else |
ADR_O <= address; |
end |
|
always @(posedge CLK_I) |
begin |
if (RST_I | ERR_I | RTY_I) |
CYC_O <= 1'b0; |
else if ((cycle_end == 1) & ACK_I) |
CYC_O <= 1'b0; |
else if (GO | CYC_O) begin |
CYC_O <= 1'b1; |
GO <= 1'b0; |
end |
end |
|
// stb control |
always @(posedge CLK_I) |
begin |
if (RST_I | ERR_I | RTY_I) |
STB_O <= 1'b0; |
else if (STB_O & ACK_I) |
STB_O <= 1'b0; |
else if (GO | STB_O) |
STB_O <= 1'b1; |
end |
|
// selects & data |
always @(posedge CLK_I) |
begin |
if (write_flag == 0) begin |
SEL_O <= 4'b1111; |
if (STB_O & ACK_I) |
data <= DAT_I; |
end |
else begin |
case (data_width(address)) |
2'b00: begin |
SEL_O <= {3'b000, selects[0]}; |
DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]}; |
end |
2'b01: begin |
SEL_O <= {2'b00, selects[1:0]}; |
DAT_O <= {data[15:0], data[15:0]}; |
end |
2'b10: begin |
SEL_O <= selects; |
DAT_O <= data; |
end |
endcase |
end |
end |
|
always @(posedge CLK_I) |
begin |
if (RST_I) |
WE_O <= 1'b0; |
else if (GO) |
WE_O <= write_flag; |
end |
|
endmodule |
|
|
|
|
|
/gpio_mon.v
0,0 → 1,135
////////////////////////////////////////////////////////////////////// |
//// //// |
//// GPIO Monitor //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Generates and monitors GPIO external signals (+auxiliary) //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:20 lampret |
// Test bench improvements. |
// |
// Revision 1.1 2001/06/05 07:45:22 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
`include "timescale.v" |
`include "gpio_defines.v" |
|
module gpio_mon(gpio_aux, gpio_in, gpio_eclk, gpio_out, gpio_oen); |
|
parameter gw = `GPIO_IOS; |
|
// |
// I/O ports |
// |
output [gw-1:0] gpio_aux; // Auxiliary |
output [gw-1:0] gpio_in; // GPIO inputs |
output gpio_eclk; // GPIO external clock |
input [gw-1:0] gpio_out; // GPIO outputs |
input [gw-1:0] gpio_oen; // GPIO output enables |
|
// |
// Internal regs |
// |
reg [gw-1:0] gpio_aux; |
reg [gw-1:0] gpio_in; |
reg gpio_eclk; |
|
initial gpio_eclk = 0; |
|
// |
// Set gpio_in |
// |
task set_gpioin; |
input [31:0] val; |
begin |
gpio_in = val; |
end |
endtask |
|
// |
// Set gpio_aux |
// |
task set_gpioaux; |
input [31:0] val; |
begin |
gpio_aux = val; |
end |
endtask |
|
// |
// Set gpio_eclk |
// |
task set_gpioeclk; |
input [31:0] val; |
begin |
gpio_eclk = val[0]; |
end |
endtask |
|
|
// |
// Get gpio_out |
// |
task get_gpioout; |
output [31:0] val; |
reg [31:0] val; |
begin |
val = gpio_out; |
end |
endtask |
|
// |
// Get gpio_oen |
// |
task get_gpiooen; |
output [31:0] val; |
begin |
val = gpio_oen; |
end |
endtask |
|
endmodule |
/tb_top.v
0,0 → 1,164
////////////////////////////////////////////////////////////////////// |
//// //// |
//// GPIO Testbench Top //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Top level of testbench. It instantiates all blocks. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/13 20:56:16 lampret |
// Removed zero padding as per Avi Shamli suggestion. |
// |
// Revision 1.2 2001/09/18 15:43:28 lampret |
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v. |
// |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:24 lampret |
// Test bench improvements. |
// |
// Revision 1.1 2001/06/05 07:45:22 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
`include "timescale.v" |
`include "gpio_defines.v" |
|
module tb_top; |
|
parameter aw = `GPIO_ADDRHH+1 ; |
parameter dw = 32; |
parameter gw = `GPIO_IOS; |
|
// |
// Interconnect wires |
// |
wire clk; // Clock |
wire rst; // Reset |
wire cyc; // Cycle valid |
wire [aw-1:0] adr; // Address bus |
wire [dw-1:0] dat_m; // Data bus from PTC to WBM |
wire [3:0] sel; // Data selects |
wire we; // Write enable |
wire stb; // Strobe |
wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC |
wire ack; // Successful cycle termination |
wire err; // Failed cycle termination |
wire [gw-1:0] gpio_aux; // GPIO auxiliary signals |
wire [gw-1:0] gpio_in; // GPIO inputs |
wire gpio_eclk; // GPIO external clock |
wire [gw-1:0] gpio_out; // GPIO outputs |
wire [gw-1:0] gpio_oen; // GPIO output enables |
wire [ 3 : 0 ] tag_o ; |
|
// |
// Instantiation of Clock/Reset Generator |
// |
clkrst clkrst( |
// Clock |
.clk_o(clk), |
// Reset |
.rst_o(rst) |
); |
|
// |
// Instantiation of Master WISHBONE BFM |
// |
wb_master wb_master( |
// WISHBONE Interface |
.CLK_I(clk), |
.RST_I(rst), |
.CYC_O(cyc), |
.ADR_O(adr), |
.DAT_O(dat_ptc), |
.SEL_O(sel), |
.WE_O(we), |
.STB_O(stb), |
.DAT_I(dat_m), |
.ACK_I(ack), |
.ERR_I(err), |
.RTY_I(1'b0), |
.TAG_I(4'b0), |
.TAG_O ( tag_o ) |
); |
|
// |
// Instantiation of PTC core |
// |
gpio_top gpio_top( |
// WISHBONE Interface |
.wb_clk_i(clk), |
.wb_rst_i(rst), |
.wb_cyc_i(cyc), |
.wb_adr_i(adr), |
.wb_dat_i(dat_ptc), |
.wb_sel_i(sel), |
.wb_we_i(we), |
.wb_stb_i(stb), |
.wb_dat_o(dat_m), |
.wb_ack_o(ack), |
.wb_err_o(err), |
.wb_inta_o(), |
|
// Auxiliary inputs interface |
.aux_i(gpio_aux), |
|
// External GPIO Interface |
.ext_pad_i(gpio_in), |
.clk_pad_i(gpio_eclk), |
.ext_pad_o(gpio_out), |
.ext_padoen_o(gpio_oen) |
); |
|
// |
// GPIO Monitor |
// |
gpio_mon gpio_mon( |
.gpio_aux(gpio_aux), |
.gpio_in(gpio_in), |
.gpio_eclk(gpio_eclk), |
.gpio_out(gpio_out), |
.gpio_oen(gpio_oen) |
); |
|
endmodule |
/tb_tasks.v
0,0 → 1,992
////////////////////////////////////////////////////////////////////// |
//// //// |
//// GPIO Testbench Tasks //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Testbench tasks. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2001/12/25 17:21:06 lampret |
// Fixed two typos. |
// |
// Revision 1.5 2001/12/25 17:12:28 lampret |
// Added RGPIO_INTS. |
// |
// Revision 1.4 2001/11/15 02:26:32 lampret |
// Updated timing and fixed some typing errors. |
// |
// Revision 1.3 2001/09/18 16:37:55 lampret |
// Changed VCD output location. |
// |
// Revision 1.2 2001/09/18 15:43:27 lampret |
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v. |
// |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:23 lampret |
// Test bench improvements. |
// |
// Revision 1.1 2001/06/05 07:45:22 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
`include "timescale.v" |
`include "gpio_defines.v" |
`include "tb_defines.v" |
|
module tb_tasks; |
|
integer nr_failed; |
integer ints_disabled; |
integer ints_working; |
integer local_errs; |
|
parameter sh_addr = `GPIO_ADDRLH+1; |
parameter gw = `GPIO_IOS ; |
// |
// Count/report failed tests |
// |
task failed; |
begin |
$display("FAILED !!!"); |
nr_failed = nr_failed + 1; |
end |
endtask |
|
// |
// Set RGPIO_OUT register |
// |
task setout; |
input [31:0] val; |
|
reg [ 31:0 ] addr ; |
begin |
addr = `GPIO_RGPIO_OUT <<sh_addr ; |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111); |
/* $display ( " addr : %h %h", addr, val ) ; |
$display ( " out_pad : %h ", tb_top.gpio_top.out_pad ) ; |
$display ( " rgpio_aux : %h ", tb_top.gpio_top.rgpio_aux) ; |
$display ( " aux_i : %h ", tb_top.gpio_top.aux_i ) ; |
$display ( " rgpio_out : %h ", tb_top.gpio_top.rgpio_out ) ; |
*/ |
end |
|
endtask |
|
// |
// Set RGPIO_OE register |
// |
task setoe; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_INTE register |
// |
task setinte; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_PTRIG register |
// |
task setptrig; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_AUX register |
// |
task setaux; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_CTRL register |
// |
task setctrl; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_INTS register |
// |
task setints; |
input [31:0] val; |
|
begin |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTS<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Display RGPIO_IN register |
// |
task showin; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp); |
$write(" RGPIO_IN: %h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_OUT register |
// |
task showout; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp); |
$write(" RGPIO_OUT: %h", tmp); |
end |
|
endtask |
|
|
// |
// Display RGPIO_OE register |
// |
task showoe; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp); |
$write(" RGPIO_OE:%h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_INTE register |
// |
task showinte; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp); |
$write(" RGPIO_INTE:%h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_PTRIG register |
// |
task showptrig; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp); |
$write(" RGPIO_PTRIG:%h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_AUX register |
// |
task showaux; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp); |
$write(" RGPIO_AUX:%h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_CTRL register |
// |
task showctrl; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp); |
$write(" RGPIO_CTRL: %h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_INTS register |
// |
task showints; |
|
reg [31:0] tmp; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp); |
$write(" RGPIO_INTS:%h", tmp); |
end |
|
endtask |
|
// |
// Compare parameter with RGPIO_IN register |
// |
task comp_in; |
input [31:0] val; |
output ret; |
|
reg [31:0] tmp; |
reg ret; |
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp); |
|
if (tmp == val) |
ret = 1; |
else |
ret = 0; |
end |
|
endtask |
|
// |
// Get RGPIO_IN register |
// |
task getin; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_OUT register |
// |
task getout; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_OE register |
// |
task getoe; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_INTE register |
// |
task getinte; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_PTRIG register |
// |
task getptrig; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_AUX register |
// |
task getaux; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_CTRL register |
// |
task getctrl; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_INTS register |
// |
task getints; |
output [31:0] tmp; |
|
begin |
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Calculate a random and make it narrow to fit on GPIO I/O pins |
// |
task random_gpio; |
output [31:0] tmp; |
|
begin |
tmp = $random & ((1<<`GPIO_IOS)-1); |
end |
|
endtask |
|
// |
// Test operation of control bit RGPIO_CTRL[ECLK] |
// |
task test_eclk; |
reg [gw-1:0 ] l1, l2, l3; |
reg [gw-1:0 ] r1, r2, r3; |
begin |
|
// Set external clock to low state |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// |
// Phase 1 |
// |
// GPIO uses WISHBONE clock to latch gpio_in |
// |
|
// Put something on gpio_in pins |
random_gpio(r1); |
tb_top.gpio_mon.set_gpioin(r1); |
|
// Reset GPIO_CTRL |
setctrl(0); |
|
// Wait for time to advance |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read GPIO_RGPIO_IN |
getin(l1); |
|
// |
// Phase 2 |
// |
// GPIO uses external clock to latch gpio_in |
// |
|
// Set GPIO to use external clock, NEC bit cleared |
setctrl(1 << `GPIO_RGPIO_CTRL_ECLK); |
|
// Put something else on gpio_in pins |
random_gpio(r2); |
tb_top.gpio_mon.set_gpioin(r2); |
|
// Make an external posedge clock pulse |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
tb_top.gpio_mon.set_gpioeclk(1); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read RGPIO_IN |
getin(l2); |
|
// |
// Phase 3 |
// |
// Change GPIO inputs and WB clock but not external clock. |
// RGPIO_IN should not change. |
// |
|
// Put something else on gpio_in pins |
random_gpio(r3); |
tb_top.gpio_mon.set_gpioin(r3); |
|
// Wait for WB clock |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read RGPIO_IN |
getin(l3); |
|
// |
// Phase 4 |
// |
// Compare phases |
// |
if (l1 == r1 && l2 == r2 && l2 == l3) |
$write("."); |
else |
local_errs = local_errs + 1; |
end |
endtask |
|
// |
// Test operation of control bit RGPIO_CTRL[NEC] |
// |
task test_nec; |
integer l1, l2; |
integer r1, r2; |
begin |
// |
// Phase 1 |
// |
// Compare RGPIO_IN before and after negative edge |
// |
|
// Set external clock to low state |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Set GPIO to use external clock and set RGPIO_CTRL[NEC] |
setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC); |
|
// Put random on gpio inputs |
random_gpio(r1); |
tb_top.gpio_mon.set_gpioin(r1); |
|
// Advance time by making an external negedge clock pulse |
tb_top.gpio_mon.set_gpioeclk(1); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Put something on gpio_in pins |
random_gpio(r2); |
tb_top.gpio_mon.set_gpioin(r2); |
|
// Make an external posedge clock pulse |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
tb_top.gpio_mon.set_gpioeclk(1); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read RGPIO_IN (should be the same as r1) |
getin(l1); |
|
// Make an external negedge clock pulse |
tb_top.gpio_mon.set_gpioeclk(1); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
tb_top.gpio_mon.set_gpioeclk(0); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read RGPIO_IN (should be the same as r2) |
getin(l2); |
|
// |
// Phase 2 |
// |
// Compare phases |
// |
// $display("l1 %h l2 %h r1 %h r2 %h", l1, l2, r1, r2); |
if (l1 == r1 && l2 == r2) |
$write("."); |
else |
local_errs = local_errs + 1; |
end |
endtask |
|
// |
// Test input polled mode, output mode and bidirectional |
// |
task test_simple; |
reg [gw-1:0] l1, l2, l3, l4; |
integer i, err; |
begin |
$write(" Testing input mode ..."); |
|
// |
// Phase 1 |
// |
// Compare RGPIO_IN and gpio_in |
// |
|
// Set GPIO to use WB clock |
setctrl(0); |
|
err = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin |
// Put something on gpio_in pins |
random_gpio(l1); |
tb_top.gpio_mon.set_gpioin(l1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read GPIO_RGPIO_IN |
getin(l2); |
|
// Compare gpio_in and RGPIO_IN. Should be equal. |
if (l1 != l2) |
err = err + 1; |
end |
|
// Phase 2 |
// |
// Output result for previous test |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
|
$write(" Testing output mode ..."); |
|
// |
// Phase 3 |
// |
// Compare RGPIO_OUT and gpio_out |
// |
|
err = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin |
// Put something in RGPIO_OUT pins |
l1 = $random; |
setout(l1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read gpio_out |
tb_top.gpio_mon.get_gpioout(l2); |
|
// Compare gpio_out and RGPIO_OUT. Should be equal. |
if (l1 != l2) |
err = err + 1; |
end |
|
// Phase 4 |
// |
// Output result for previous test |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
|
$write(" Testing bidirectional I/O ..."); |
|
// |
// Phase 5 |
// |
// Compare RGPIO_OE and gpio_oen |
// |
|
err = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin |
// Put something in RGPIO_OE pins |
l1 = $random; |
setoe(l1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read gpio_oen |
tb_top.gpio_mon.get_gpiooen(l2); |
|
// Compare gpio_oen and RGPIO_OE. Should be exactly opposite. |
if (l1 != ~l2) |
err = err + 1; |
end |
|
// Phase 6 |
// |
// Output result for previous test |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
|
$write(" Testing auxiliary feature ..."); |
|
// |
// Phase 7 |
// |
// Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux |
// |
|
err = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin |
// Put something on gpio_aux pins |
l1 = $random; |
tb_top.gpio_mon.set_gpioaux(l1); |
|
// Put something in RGPIO_AUX pins |
l2 = $random; |
setaux(l2); |
|
// Put something in RGPIO_OUT pins |
l3 = $random; |
setout(l3); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Read gpio_out |
tb_top.gpio_mon.get_gpioout(l4); |
|
// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux. |
// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT |
// bits are present on gpio_out and where |
if ((l1 & l2 | l3 & ~l2) != l4) |
err = err + 1; |
end |
|
// Phase 8 |
// |
// Output result for previous test |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
|
end |
endtask |
|
// |
// Test interrupts |
// |
task test_ints; |
integer l1, l2, l3, l4; |
integer i, rnd, err; |
integer r1; |
begin |
|
$write(" Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ..."); |
|
// |
// Phase 1 |
// |
// Generate patterns on inputs in interrupt mode |
// |
|
// Disable spurious interrupt monitor |
ints_disabled = 0; |
|
err = 0; |
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin |
|
// Set gpio_in pins |
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff; |
tb_top.gpio_mon.set_gpioin(r1); |
|
// Low level triggering |
setptrig(0); |
|
// Clear RGPIO_INTS |
setints(0); |
|
// Enable interrupts in RGPIO_CTRL |
setctrl(1 << `GPIO_RGPIO_CTRL_INTE); |
|
// Enable interrupts in RGPIO_INTE |
setinte(r1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be zero. |
l1 = tb_top.gpio_top.wb_inta_o; |
|
// Clear gpio_in pins |
tb_top.gpio_mon.set_gpioin(0); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be one. |
l2 = tb_top.gpio_top.wb_inta_o; |
|
// Clear interrupt request |
setctrl(0); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be zero. |
l3 = tb_top.gpio_top.wb_inta_o; |
|
// Get RGPIO_INTS. Should be nonzero. |
getints(l4); |
|
// Check for errors |
if (l1 || !l2 || l3 || (l4 != r1)) begin |
err = err +1; |
end |
end |
|
// Enable spurious interrupt monitor |
ints_disabled = 1; |
|
// Phase 2 |
// |
// Check results |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
end |
endtask |
|
// |
// Test ptrig |
// |
task test_ptrig; |
integer l1, l2, l3; |
integer i, rnd, err; |
integer r1; |
begin |
$write(" Testing ptrig features ..."); |
|
// |
// Phase 1 |
// |
// Generate patterns on inputs in interrupt mode |
// |
|
// Disable spurious interrupt monitor |
ints_disabled = 0; |
|
err = 0; |
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin |
|
// Set bits to one |
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff; |
|
// Set gpio_in pins |
tb_top.gpio_mon.set_gpioin('h00000000); |
|
// Clear old interrupts |
setints(0); |
|
// High level triggering |
setptrig('hffffffff); |
|
// Enable interrupts in RGPIO_CTRL |
setctrl(1 << `GPIO_RGPIO_CTRL_INTE); |
|
// Enable interrupts in RGPIO_INTE |
setinte(r1); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be zero. |
l1 = tb_top.gpio_top.wb_inta_o; |
|
// Clear gpio_in pins |
tb_top.gpio_mon.set_gpioin('hffffffff); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be one. |
l2 = tb_top.gpio_top.wb_inta_o; |
|
// Clear interrupt request |
setctrl(0); |
setints(0); |
|
// Advance time |
@(posedge tb_top.clk); |
@(posedge tb_top.clk); |
|
// Sample interrupt request. Should be zero. |
l3 = tb_top.gpio_top.wb_inta_o; |
|
// Check for errors |
if (l1 || !l2 || l3) |
err = err +1; |
end |
|
// Enable spurious interrupt monitor |
ints_disabled = 1; |
|
// Phase 2 |
// |
// Check results |
// |
if (!err) |
$display(" OK"); |
else |
failed; |
end |
endtask |
|
// |
// Do continues check for interrupts |
// |
always @(posedge tb_top.gpio_top.wb_inta_o) |
if (ints_disabled) begin |
$display("Spurious interrupt detected. "); |
failed; |
ints_working = 9876; |
$display; |
end |
|
// |
// Start of testbench test tasks |
// |
integer i; |
initial begin |
`ifdef GPIO_DUMP_VCD |
$dumpfile("../out/tb_top.vcd"); |
$dumpvars(0); |
`endif |
nr_failed = 0; |
ints_disabled = 1; |
ints_working = 0; |
tb_top.gpio_mon.set_gpioin(0); |
tb_top.gpio_mon.set_gpioaux(0); |
tb_top.gpio_mon.set_gpioeclk(0); |
$display; |
$display("###"); |
$display("### GPIO IP Core Verification ###"); |
$display("###"); |
$display; |
$display("I. Testing correct operation of RGPIO_CTRL control bits"); |
$display; |
|
|
$write(" Testing control bit RGPIO_CTRL[ECLK] ..."); |
local_errs = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) |
test_eclk; |
if (local_errs == 0) |
$display(" OK"); |
else |
failed; |
|
|
$write(" Testing control bit RGPIO_CTRL[NEC] ..."); |
local_errs = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) |
test_nec; |
if (local_errs == 0) |
$display(" OK"); |
else |
failed; |
|
test_ints; |
|
$display; |
$display("II. Testing modes of operation ..."); |
$display; |
|
test_simple; |
test_ptrig; |
|
$display; |
$display("###"); |
$display("### FAILED TESTS: %d ###", nr_failed); |
$display("###"); |
$display; |
$finish; |
end |
|
endmodule |
/tb_defines.v
0,0 → 1,76
////////////////////////////////////////////////////////////////////// |
//// //// |
//// GPIO Testbench Definitions //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Testbench definitions that affect how testbench simulation //// |
//// is performed. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/08/21 22:01:50 lampret |
// More intensive verification. |
// |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:23 lampret |
// Test bench improvements. |
// |
// Revision 1.1 2001/06/05 07:45:22 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
// |
// Define if you want VCD dump |
// |
`define GPIO_DUMP_VCD |
|
// |
// Intensity of verification |
// |
// Higher number means more intensive verification. Higher number |
// means more loops of each subtest (e.g. for some subtests |
// 5 means 50 loops, for others 100 etc). Good numbers are from 1 |
// (very fast and very little verification) to 200 (slow but thorough). |
// Default is 200. |
// |
`define GPIO_VERIF_INTENSITY 200 |
/clkrst.v
0,0 → 1,80
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Clock and Reset Generator //// |
//// //// |
//// This file is part of the GPIO project //// |
//// http://www.opencores.org/cores/gpio/ //// |
//// //// |
//// Description //// |
//// Clock and reset generator. //// |
//// //// |
//// To Do: //// |
//// Nothing //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/06/05 07:45:21 lampret |
// Added initial RTL and test benches. There are still some issues with these files. |
// |
// |
|
`include "timescale.v" |
|
module clkrst(clk_o, rst_o); |
|
// |
// I/O ports |
// |
output clk_o; // Clock |
output rst_o; // Reset |
|
// |
// Internal regs |
// |
reg clk_o; // Clock |
reg rst_o; // Reset |
|
initial begin |
clk_o = 0; |
rst_o = 1; |
#20; |
rst_o = 0; |
end |
|
// |
// Clock |
// |
always #4 clk_o = ~clk_o; |
|
endmodule |
/timescale.v
0,0 → 1,80
`timescale 1ns/10ps |