URL
https://opencores.org/ocsvn/gpio/gpio/trunk
Subversion Repositories gpio
Compare Revisions
- This comparison shows the changes necessary to convert path
/gpio/tags/rel_8/sim
- from Rev 44 to Rev 65
- ↔ Reverse comparison
Rev 44 → Rev 65
/rtl_sim/run/run_sim
0,0 → 1,102
#!/bin/csh -f |
|
if ( $# < 1 ) then |
echo "First argument must be a top level module name!" |
exit |
else |
set SIM_TOP = $1 |
endif |
|
set current_par = 1 |
set output_waveform = 0 |
while ( $current_par < $# ) |
@ current_par = $current_par + 1 |
case wave: |
@ output_waveform = 1 |
breaksw |
default: |
echo 'Unknown option "'$argv[$current_par]'"!' |
exit |
breaksw |
endsw |
end |
|
echo "-CDSLIB ../bin/cds.lib" > ncvlog.args |
echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args |
echo "-MESSAGES" >> ncvlog.args |
echo "-INCDIR ../../../bench/verilog" >> ncvlog.args |
echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args |
echo "-NOCOPYRIGHT" >> ncvlog.args |
echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args |
|
foreach filename ( `cat ../bin/rtl_file_list` ) |
echo "../../../rtl/verilog/"$filename >> ncvlog.args |
end |
|
foreach filename ( `cat ../bin/sim_file_list` ) |
echo "../../../bench/verilog/"$filename >> ncvlog.args |
end |
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ncvlog -f ncvlog.args |
|
echo "-MESSAGES" > ncelab.args |
echo "-NOCOPYRIGHT" >> ncelab.args |
echo "-CDSLIB ../bin/cds.lib" >> ncelab.args |
echo "-HDLVAR ../bin/hdl.var" >> ncelab.args |
echo "-LOGFILE ../log/ncelab.log" >> ncelab.args |
echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args |
echo "-NO_TCHK_MSG" >> ncelab.args |
echo "-ACCESS +RWC" >> ncelab.args |
echo "worklib.tb_tasks" >> ncelab.args |
echo worklib.$SIM_TOP >> ncelab.args |
|
ncelab -f ncelab.args |
|
echo "-MESSAGES" > ncsim.args |
echo "-NOCOPYRIGHT" >> ncsim.args |
echo "-CDSLIB ../bin/cds.lib" >> ncsim.args |
echo "-HDLVAR ../bin/hdl.var" >> ncsim.args |
echo "-INPUT ncsim.tcl" >> ncsim.args |
echo "-LOGFILE ../log/ncsim.log" >> ncsim.args |
echo "worklib.bench:rtl" >> ncsim.args |
|
if ( $output_waveform ) then |
echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl |
echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl |
echo "run" >> ./ncsim.tcl |
else |
echo "run" > ./ncsim.tcl |
endif |
|
echo "quit" >> ncsim.tcl |
|
ncsim -LICQUEUE -f ./ncsim.args |
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set exit_line_nb = `sed -n '/exit/=' < ../log/ncsim.log` |
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#echo "$exit_line_nb" |
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set dead_line_nb = 0 |
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if ( $exit_line_nb ) then |
|
@ dead_line_nb = $exit_line_nb - 1 |
set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ../log/ncsim.log` |
set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ../log/ncsim.log` |
|
echo "$dead_line" |
echo "$exit_line" |
|
echo "TEST: gpio" |
if ( "$dead_line" == "report (deaddead)" ) then |
if ( "$exit_line" == "exit (00000000)" ) then |
echo "STATUS: passed" #|tee -a ../log/run_sim.log 2>&1 |
else |
echo "STATUS: failed" #|tee -a ../log/run_sim.log 2>&1 |
endif |
else |
echo "STATUS: failed" |
endif |
|
endif |
|
rtl_sim/run/run_sim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_sim/bin/sim.sh
===================================================================
--- rtl_sim/bin/sim.sh (nonexistent)
+++ rtl_sim/bin/sim.sh (revision 65)
@@ -0,0 +1,125 @@
+#!/bin/bash
+
+#
+# This script runs RTL and gate-level simulation using different simultion tools.
+# Right now Cadence Verilog-XL and NCSim are supported.
+#
+# Author: Damjan Lampret
+#
+
+#
+# User definitions
+#
+
+# Set simulation tool you are using (xl, ncsim, ncver)
+SIMTOOL=ncsim
+
+# Set test bench top module(s)
+TB_TOP="tb_tasks"
+
+# Set include directories
+INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/"
+
+# Set test bench files
+BENCH_FILES="../../../bench/verilog/*.v"
+
+# Set RTL source files
+RTL_FILES="../../../rtl/verilog/*.v"
+
+# Set gate-level netlist files
+GATE_FILES="../syn/out/final_gpio.v"
+
+# Set libraries (standard cell etc.)
+LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v"
+
+# Set parameters for simulation tool
+if [ $SIMTOOL == xl ]; then
+ PARAM="+turbo+3 -q"
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+elif [ $SIMTOOL == ncver ]; then
+ NCVER_PARAM=""
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+elif [ $SIMTOOL == ncsim ]; then
+ NCPREP_PARAM="-UPDATE +overwrite"
+ NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT"
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+else
+ echo "$SIMTOOL is unsupported simulation tool."
+ exit 0
+fi
+
+#
+# Don't change anything below unless you know what you are doing
+#
+
+# Run simulation in sim directory
+#cd ../sim
+
+# Run actual simulation
+
+# Cadence Verilog-XL
+if [ $SIMTOOL == xl ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Cadence Ncverilog
+elif [ $SIMTOOL == ncver ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES
+ cp ncverilog.log ../log
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+ cp ncverilog.log ../log
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Cadence Ncsim
+elif [ $SIMTOOL == ncsim ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES
+ ./RUN_NC
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+ ./RUN_NC
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Unsupported simulation tool
+else
+ echo "$SIMTOOL is unsupported simulation tool."
+ exit 0;
+fi
rtl_sim/bin/sim.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_sim/bin/sim_file_list
===================================================================
--- rtl_sim/bin/sim_file_list (nonexistent)
+++ rtl_sim/bin/sim_file_list (revision 65)
@@ -0,0 +1,7 @@
+clkrst.v
+gpio_mon.v
+wb_master.v
+tb_tasks.v
+tb_top.v
+
+
rtl_sim/bin/sim_file_list
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak
===================================================================
--- rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak (nonexistent)
+++ rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak (revision 65)
@@ -0,0 +1,3216 @@
+çíïé”ÓµëòìôÌÈÀçéíõûý„æ‚Û€ÙÜÞÕÙ›ÚÞÖÌ•Ž†‘¶²¶Éÿ ê¥ÃjDk X° =J%W