URL
https://opencores.org/ocsvn/gpio/gpio/trunk
Subversion Repositories gpio
Compare Revisions
- This comparison shows the changes necessary to convert path
/gpio/trunk/sim/rtl_sim/bin
- from Rev 53 to Rev 65
- ↔ Reverse comparison
Rev 53 → Rev 65
/INCA_libs/worklib/dir_keeper
--- sim_file_list (nonexistent)
+++ sim_file_list (revision 65)
@@ -0,0 +1,7 @@
+clkrst.v
+gpio_mon.v
+wb_master.v
+tb_tasks.v
+gpio_testbench.v
+
+
sim_file_list
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim.sh
===================================================================
--- sim.sh (nonexistent)
+++ sim.sh (revision 65)
@@ -0,0 +1,125 @@
+#!/bin/bash
+
+#
+# This script runs RTL and gate-level simulation using different simultion tools.
+# Right now Cadence Verilog-XL and NCSim are supported.
+#
+# Author: Damjan Lampret
+#
+
+#
+# User definitions
+#
+
+# Set simulation tool you are using (xl, ncsim, ncver)
+SIMTOOL=ncsim
+
+# Set test bench top module(s)
+TB_TOP="tb_tasks"
+
+# Set include directories
+INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/"
+
+# Set test bench files
+BENCH_FILES="../../../bench/verilog/*.v"
+
+# Set RTL source files
+RTL_FILES="../../../rtl/verilog/*.v"
+
+# Set gate-level netlist files
+GATE_FILES="../syn/out/final_gpio.v"
+
+# Set libraries (standard cell etc.)
+LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v"
+
+# Set parameters for simulation tool
+if [ $SIMTOOL == xl ]; then
+ PARAM="+turbo+3 -q"
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+elif [ $SIMTOOL == ncver ]; then
+ NCVER_PARAM=""
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+elif [ $SIMTOOL == ncsim ]; then
+ NCPREP_PARAM="-UPDATE +overwrite"
+ NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT"
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+else
+ echo "$SIMTOOL is unsupported simulation tool."
+ exit 0
+fi
+
+#
+# Don't change anything below unless you know what you are doing
+#
+
+# Run simulation in sim directory
+#cd ../sim
+
+# Run actual simulation
+
+# Cadence Verilog-XL
+if [ $SIMTOOL == xl ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Cadence Ncverilog
+elif [ $SIMTOOL == ncver ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES
+ cp ncverilog.log ../log
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+ cp ncverilog.log ../log
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Cadence Ncsim
+elif [ $SIMTOOL == ncsim ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES
+ ./RUN_NC
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+ ./RUN_NC
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Unsupported simulation tool
+else
+ echo "$SIMTOOL is unsupported simulation tool."
+ exit 0;
+fi
sim.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_file_list
===================================================================
--- rtl_file_list (nonexistent)
+++ rtl_file_list (revision 65)
@@ -0,0 +1 @@
+gpio_top.v
rtl_file_list
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: cds.lib
===================================================================
--- cds.lib (nonexistent)
+++ cds.lib (revision 65)
@@ -0,0 +1,6 @@
+#
+# cds.lib: Defines the locations of compiled libraries.
+# Created by ncprep on Tue Nov 11 00:24:06 2003
+#
+
+define worklib ./INCA_libs/worklib
Index: hdl.var
===================================================================
--- hdl.var (nonexistent)
+++ hdl.var (revision 65)
@@ -0,0 +1,9 @@
+#
+# hdl.var: Defines variables used by the INCA tools.
+# Created by ncprep on Tue Nov 11 00:24:06 2003
+#
+
+softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
+
+define LIB_MAP ( $LIB_MAP, + => worklib )
+define VIEW_MAP ( $VIEW_MAP, .v => v)