URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588/tags
- from Rev 1 to Rev 28
- ↔ Reverse comparison
Rev 1 → Rev 28
/v1p0/rtl/top/ha1588.v
0,0 → 1,122
`timescale 1ns/1ns |
|
module ha1588 ( |
input rst,clk, |
input wr_in,rd_in, |
input [ 7:0] addr_in, |
input [31:0] data_in, |
output [31:0] data_out, |
|
input rtc_clk, |
|
input rx_gmii_clk, |
input rx_gmii_ctrl, |
input [7:0] rx_gmii_data, |
input tx_gmii_clk, |
input tx_gmii_ctrl, |
input [7:0] tx_gmii_data |
); |
|
wire rtc_rst; |
wire rtc_time_ld, rtc_period_ld, rtc_adj_ld; |
wire [37:0] rtc_time_reg_ns; |
wire [47:0] rtc_time_reg_sec; |
wire [39:0] rtc_period; |
wire [37:0] rtc_time_acc_modulo; |
wire [31:0] rtc_adj_ld_data; |
wire [39:0] rtc_period_adj; |
wire [37:0] rtc_time_reg_ns_val; |
wire [47:0] rtc_time_reg_sec_val; |
wire [35:0] rtc_time_reg_val = {rtc_time_reg_sec_val[5:0],rtc_time_reg_ns_val[37:8]}; // 64.000,000,000 sec |
|
wire rx_q_rst, rx_q_clk; |
wire rx_q_rd_en; |
wire [ 7:0] rx_q_stat; |
wire [63:0] rx_q_data; |
wire tx_q_rst, tx_q_clk; |
wire tx_q_rd_en; |
wire [ 7:0] tx_q_stat; |
wire [63:0] tx_q_data; |
|
rgs u_rgs |
( |
.rst(rst), |
.clk(clk), |
.wr_in(wr_in), |
.rd_in(rd_in), |
.addr_in(addr_in), |
.data_in(data_in), |
.data_out(data_out), |
.rtc_clk_in(rtc_clk), |
.rtc_rst_out(rtc_rst), |
.time_ld_out(rtc_time_ld), |
.time_reg_ns_out(rtc_time_reg_ns), |
.time_reg_sec_out(rtc_time_reg_sec), |
.period_ld_out(rtc_period_ld), |
.period_out(rtc_period), |
.time_acc_modulo_out(rtc_time_acc_modulo), |
.adj_ld_out(rtc_adj_ld), |
.adj_ld_data_out(rtc_adj_ld_data), |
.period_adj_out(rtc_period_adj), |
.time_reg_ns_in(rtc_time_reg_ns_val), |
.time_reg_sec_in(rtc_time_reg_sec_val), |
.rx_q_rst_out(rx_q_rst), |
.rx_q_rd_clk_out(rx_q_clk), |
.rx_q_rd_en_out(rx_q_rd_en), |
.rx_q_stat_in(rx_q_stat), |
.rx_q_data_in(rx_q_data), |
.tx_q_rst_out(tx_q_rst), |
.tx_q_rd_clk_out(tx_q_clk), |
.tx_q_rd_en_out(tx_q_rd_en), |
.tx_q_stat_in(tx_q_stat), |
.tx_q_data_in(tx_q_data) |
); |
|
rtc u_rtc |
( |
.rst(rtc_rst), |
.clk(rtc_clk), |
.time_ld(rtc_time_ld), |
.time_reg_ns_in(rtc_time_reg_ns), |
.time_reg_sec_in(rtc_time_reg_sec), |
.period_ld(rtc_period_ld), |
.period_in(rtc_period), |
.time_acc_modulo(rtc_time_acc_modulo), |
.adj_ld(rtc_adj_ld), |
.adj_ld_data(rtc_adj_ld_data), |
.period_adj(rtc_period_adj), |
.time_reg_ns(rtc_time_reg_ns_val), |
.time_reg_sec(rtc_time_reg_sec_val) |
); |
|
tsu u_rx_tsu |
( |
.rst(rst), |
.gmii_clk(rx_gmii_clk), |
.gmii_ctrl(rx_gmii_ctrl), |
.gmii_data(rx_gmii_data), |
.rtc_timer_clk(rtc_clk), |
.rtc_timer_in(rtc_time_reg_val), |
.q_rst(rx_q_rst), |
.q_rd_clk(rx_q_clk), |
.q_rd_en(rx_q_rd_en), |
.q_rd_stat(rx_q_stat), |
.q_rd_data(rx_q_data) |
); |
|
tsu u_tx_tsu |
( |
.rst(rst), |
.gmii_clk(tx_gmii_clk), |
.gmii_ctrl(tx_gmii_ctrl), |
.gmii_data(tx_gmii_data), |
.rtc_timer_clk(rtc_clk), |
.rtc_timer_in(rtc_time_reg_val), |
.q_rst(tx_q_rst), |
.q_rd_clk(tx_q_clk), |
.q_rd_en(tx_q_rd_en), |
.q_rd_stat(tx_q_stat), |
.q_rd_data(tx_q_data) |
); |
|
endmodule |
/v1p0/rtl/top/ha1588_hw.tcl
0,0 → 1,141
# TCL File Generated by Component Editor 10.1sp1 |
# Sat Mar 31 15:26:56 CST 2012 |
# DO NOT MODIFY |
|
|
# +----------------------------------- |
# | |
# | ha1588 "Hardware Assisted IEEE 1588 IP Core" v1.0 |
# | Walter EDN 2012.03.31.15:26:56 |
# | Hardware Assisted IEEE 1588 IP Core |
# | |
# | ha1588.v |
# | |
# | ../../rtl/top/ha1588.v syn, sim |
# | ../../rtl/reg/reg.v syn, sim |
# | ../../rtl/rtc/rtc.v syn, sim |
# | ../../rtl/tsu/tsu.v syn, sim |
# | ../../rtl/tsu/ptp_parser.v syn, sim |
# | ../../rtl/tsu/ptp_queue.v syn, sim |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | request TCL package from ACDS 10.1 |
# | |
package require -exact sopc 10.1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | module ha1588 |
# | |
set_module_property DESCRIPTION "Hardware Assisted IEEE 1588 IP Core" |
set_module_property NAME ha1588 |
set_module_property VERSION 1.0 |
set_module_property INTERNAL false |
set_module_property OPAQUE_ADDRESS_MAP true |
set_module_property AUTHOR "Walter EDN" |
set_module_property DISPLAY_NAME "Hardware Assisted IEEE 1588 IP Core" |
set_module_property TOP_LEVEL_HDL_FILE ha1588.v |
set_module_property TOP_LEVEL_HDL_MODULE ha1588 |
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true |
set_module_property EDITABLE true |
set_module_property ANALYZE_HDL TRUE |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | files |
# | |
add_file ../../rtl/top/ha1588.v {SYNTHESIS SIMULATION} |
add_file ../../rtl/reg/reg.v {SYNTHESIS SIMULATION} |
add_file ../../rtl/rtc/rtc.v {SYNTHESIS SIMULATION} |
add_file ../../rtl/tsu/tsu.v {SYNTHESIS SIMULATION} |
add_file ../../rtl/tsu/ptp_parser.v {SYNTHESIS SIMULATION} |
add_file ../../rtl/tsu/ptp_queue.v {SYNTHESIS SIMULATION} |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | parameters |
# | |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | display items |
# | |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point clock |
# | |
add_interface clock clock end |
set_interface_property clock clockRate 0 |
|
set_interface_property clock ENABLED true |
|
add_interface_port clock clk clk Input 1 |
add_interface_port clock rst reset Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point avalon_slave |
# | |
add_interface avalon_slave avalon end |
set_interface_property avalon_slave addressAlignment DYNAMIC |
set_interface_property avalon_slave addressUnits WORDS |
set_interface_property avalon_slave associatedClock clock |
set_interface_property avalon_slave burstOnBurstBoundariesOnly false |
set_interface_property avalon_slave explicitAddressSpan 0 |
set_interface_property avalon_slave holdTime 0 |
set_interface_property avalon_slave isMemoryDevice false |
set_interface_property avalon_slave isNonVolatileStorage false |
set_interface_property avalon_slave linewrapBursts false |
set_interface_property avalon_slave maximumPendingReadTransactions 0 |
set_interface_property avalon_slave printableDevice false |
set_interface_property avalon_slave readLatency 0 |
set_interface_property avalon_slave readWaitTime 1 |
set_interface_property avalon_slave setupTime 0 |
set_interface_property avalon_slave timingUnits Cycles |
set_interface_property avalon_slave writeWaitTime 0 |
|
set_interface_property avalon_slave ENABLED true |
|
add_interface_port avalon_slave wr_in write Input 1 |
add_interface_port avalon_slave rd_in read Input 1 |
add_interface_port avalon_slave addr_in address Input 8 |
add_interface_port avalon_slave data_in writedata Input 32 |
add_interface_port avalon_slave data_out readdata Output 32 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point ref_clock |
# | |
add_interface ref_clock conduit end |
|
set_interface_property ref_clock ENABLED true |
|
add_interface_port ref_clock rtc_clk export Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point gmii_monitor |
# | |
add_interface gmii_monitor conduit end |
|
set_interface_property gmii_monitor ENABLED true |
|
add_interface_port gmii_monitor rx_gmii_clk export Input 1 |
add_interface_port gmii_monitor rx_gmii_ctrl export Input 1 |
add_interface_port gmii_monitor rx_gmii_data export Input 8 |
add_interface_port gmii_monitor tx_gmii_clk export Input 1 |
add_interface_port gmii_monitor tx_gmii_ctrl export Input 1 |
add_interface_port gmii_monitor tx_gmii_data export Input 8 |
# | |
# +----------------------------------- |
/v1p0/rtl/tsu/tsu.v
0,0 → 1,201
`timescale 1ns/1ns |
|
module tsu ( |
input rst, |
|
input gmii_clk, |
input gmii_ctrl, |
input [7:0] gmii_data, |
|
input rtc_timer_clk, |
input [35:0] rtc_timer_in, // timeStamp1s_6bit + timeStamp1ns_30bit |
|
input q_rst, |
input q_rd_clk, |
input q_rd_en, |
output [ 7:0] q_rd_stat, |
output [63:0] q_rd_data // seqId_16bit + msgId_4bit + null_8bit + timeStamp1s_6bit + timeStamp1ns_30bit |
); |
|
// buffer gmii input |
reg int_gmii_ctrl; |
reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5; |
reg [7:0] int_gmii_data; |
reg [7:0] int_gmii_data_d1; |
always @(posedge rst or posedge gmii_clk) begin |
if (rst) begin |
int_gmii_ctrl <= 1'b0; |
int_gmii_ctrl_d1 <= 1'b0; |
int_gmii_ctrl_d2 <= 1'b0; |
int_gmii_ctrl_d3 <= 1'b0; |
int_gmii_ctrl_d4 <= 1'b0; |
int_gmii_ctrl_d5 <= 1'b0; |
int_gmii_data <= 8'h00; |
int_gmii_data_d1 <= 8'h00; |
end |
else begin |
int_gmii_ctrl <= gmii_ctrl; |
int_gmii_ctrl_d1 <= int_gmii_ctrl; |
int_gmii_ctrl_d2 <= int_gmii_ctrl_d1; |
int_gmii_ctrl_d3 <= int_gmii_ctrl_d2; |
int_gmii_ctrl_d4 <= int_gmii_ctrl_d3; |
int_gmii_ctrl_d5 <= int_gmii_ctrl_d4; |
int_gmii_data <= gmii_data; |
int_gmii_data_d1 <= int_gmii_data; |
end |
end |
|
// ptp CDC time stamping |
wire ts_req = int_gmii_ctrl; |
reg ts_req_d1, ts_req_d2, ts_req_d3; |
always @(posedge rst or posedge rtc_timer_clk) begin |
if (rst) begin |
ts_req_d1 <= 1'b0; |
ts_req_d2 <= 1'b0; |
ts_req_d3 <= 1'b0; |
end |
else begin |
ts_req_d1 <= ts_req; |
ts_req_d2 <= ts_req_d1; |
ts_req_d3 <= ts_req_d2; |
end |
end |
reg [35:0] rtc_time_stamp; |
always @(posedge rst or posedge rtc_timer_clk) begin |
if (rst) |
rtc_time_stamp <= 36'd0; |
else |
if (ts_req_d2 & !ts_req_d3) |
rtc_time_stamp <= rtc_timer_in; |
end |
reg ts_ack, ts_ack_clr; |
always @(posedge ts_ack_clr or posedge rtc_timer_clk) begin |
if (ts_ack_clr) |
ts_ack <= 1'b0; |
else |
if (ts_req_d2 & !ts_req_d3) |
ts_ack <= 1'b1; |
end |
|
reg ts_ack_d1, ts_ack_d2, ts_ack_d3; |
always @(posedge rst or posedge gmii_clk) begin |
if (rst) begin |
ts_ack_d1 <= 1'b0; |
ts_ack_d2 <= 1'b0; |
ts_ack_d3 <= 1'b0; |
end |
else begin |
ts_ack_d1 <= ts_ack; |
ts_ack_d2 <= ts_ack_d1; |
ts_ack_d3 <= ts_ack_d2; |
end |
end |
reg [35:0] gmii_time_stamp; |
always @(posedge rst or posedge gmii_clk) begin |
if (rst) begin |
gmii_time_stamp <= 36'd0; |
ts_ack_clr <= 1'b0; |
end |
else begin |
if (ts_ack_d2 & !ts_ack_d3) begin |
gmii_time_stamp <= rtc_time_stamp; |
ts_ack_clr <= 1'b1; |
end |
else begin |
gmii_time_stamp <= gmii_time_stamp; |
ts_ack_clr <= 1'b0; |
end |
end |
end |
|
// 8b-32b datapath gearbox |
reg int_valid; |
reg int_sop, int_eop; |
reg [ 1:0] int_bcnt, int_mod; |
reg [31:0] int_data; |
always @(posedge rst or posedge gmii_clk) begin |
if (rst) |
int_bcnt <= 2'd0; |
else |
if (int_gmii_ctrl_d1 | (int_bcnt!=2'd0)) |
int_bcnt <= int_bcnt + 2'd1; |
else |
int_bcnt <= 2'd0; |
end |
always @(posedge rst or posedge gmii_clk) begin |
if (rst) begin |
int_data <= 32'd0; |
int_valid <= 1'b0; |
int_mod <= 2'd0; |
end |
else begin |
if (int_gmii_ctrl_d1) begin |
int_data[ 7: 0] <= (int_bcnt==2'd3)? int_gmii_data_d1:int_data[ 7: 0]; |
int_data[15: 8] <= (int_bcnt==2'd2)? int_gmii_data_d1:int_data[15: 8]; |
int_data[23:16] <= (int_bcnt==2'd1)? int_gmii_data_d1:int_data[23:16]; |
int_data[31:24] <= (int_bcnt==2'd0)? int_gmii_data_d1:int_data[31:24]; |
end |
|
if (int_bcnt==2'd3) |
int_valid <= 1'b1; |
else |
int_valid <= 1'b0; |
|
if (int_gmii_ctrl_d1 & !int_gmii_ctrl_d2) |
int_mod <= 2'd0; |
else if (!int_gmii_ctrl_d1 & int_gmii_ctrl_d2) |
int_mod <= int_bcnt; |
|
if (int_gmii_ctrl & !int_gmii_ctrl_d5 & int_bcnt==2'd3) |
int_sop <= 1'b1; |
else |
int_sop <= 1'b0; |
|
if (!int_gmii_ctrl & int_bcnt==2'd3) |
int_eop <= 1'b1; |
else |
int_eop <= 1'b0; |
|
end |
end |
|
// ptp packet parser here |
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint |
wire ptp_found; |
wire [19:0] ptp_infor; |
ptp_parser parser( |
.clk(gmii_clk), |
.rst(rst), |
.int_data(int_data), |
.int_valid(int_valid), |
.int_sop(int_sop), |
.int_eop(int_eop), |
.int_mod(int_mod), |
.ptp_found(ptp_found), |
.ptp_infor(ptp_infor) |
); |
|
// ptp time stamp dcfifo |
wire q_wr_clk = gmii_clk; |
wire q_wr_en = ptp_found; |
wire [63:0] q_wr_data = {ptp_infor, 8'd0, gmii_time_stamp}; // 20+8+36 bit |
wire [3:0] q_wrusedw; |
wire [3:0] q_rdusedw; |
|
ptp_queue queue( |
.aclr(q_rst), |
|
.wrclk(q_wr_clk), |
.wrreq(q_wr_en && q_wrusedw<=15), // write with overflow protection |
.data(q_wr_data), |
.wrusedw(q_wrusedw), |
|
.rdclk(q_rd_clk), |
.rdreq(q_rd_en && q_rdusedw>= 1), // read with underflow protection |
.q(q_rd_data), |
.rdusedw(q_rdusedw) |
); |
|
assign q_rd_stat = {4'd0, q_rdusedw}; |
|
endmodule |
/v1p0/rtl/tsu/ptp_parser.v
0,0 → 1,208
`timescale 1ns/1ns |
|
module ptp_parser ( |
input clk, rst, |
input [31:0] int_data, |
input int_valid, |
input int_sop, |
input int_eop, |
input [ 1:0] int_mod, |
|
output reg ptp_found, |
output reg [19:0] ptp_infor |
); |
|
reg [31:0] int_data_d1; |
reg int_valid_d1; |
reg int_sop_d1; |
reg int_eop_d1; |
reg [ 1:0] int_mod_d1; |
always @(posedge rst or posedge clk) begin |
if (rst) begin |
int_data_d1 <= 32'h00000000; |
int_valid_d1 <= 1'b0; |
int_sop_d1 <= 1'b0; |
int_eop_d1 <= 1'b0; |
int_mod_d1 <= 2'b00; |
end |
else begin |
if (int_valid) begin |
int_data_d1 <= int_data; |
int_mod_d1 <= int_mod; |
end |
int_valid_d1 <= int_valid; |
int_sop_d1 <= int_sop; |
int_eop_d1 <= int_eop; |
end |
end |
|
reg [ 9:0] int_cnt, bypass_ipv4_cnt, bypass_ipv6_cnt, bypass_udp_cnt, ptp_cnt; |
reg bypass_vlan, ptp_l2, bypass_ipv4, bypass_ipv6, found_udp, bypass_udp, ptp_l4, ptp_event; |
reg [ 3:0] ptp_msgid; |
reg [15:0] ptp_seqid; |
always @(posedge rst or posedge clk) begin |
if (rst) begin |
int_cnt <= 10'd0; |
bypass_ipv4_cnt <= 10'd0; |
bypass_ipv6_cnt <= 10'd0; |
bypass_udp_cnt <= 10'd0; |
end |
else begin |
if (int_valid_d1 && int_sop_d1) |
int_cnt <= 10'd0; |
else if (int_valid_d1) |
int_cnt <= int_cnt + 10'd1 - bypass_vlan - (bypass_ipv4 || bypass_ipv6 || bypass_udp); |
|
if (int_valid_d1 && int_sop_d1) |
bypass_ipv4_cnt <= 10'd0; |
else if (int_valid_d1 && bypass_ipv4) |
bypass_ipv4_cnt <= bypass_ipv4_cnt + 10'd1; |
|
if (int_valid_d1 && int_sop_d1) |
bypass_ipv6_cnt <= 10'd0; |
else if (int_valid_d1 && bypass_ipv6) |
bypass_ipv6_cnt <= bypass_ipv6_cnt + 10'd1; |
|
if (int_valid_d1 && int_sop_d1) |
bypass_udp_cnt <= 10'd0; |
else if (int_valid_d1 && bypass_udp) |
bypass_udp_cnt <= bypass_udp_cnt + 10'd1; |
end |
end |
|
always @(posedge rst or posedge clk) begin |
if (rst) begin |
bypass_vlan <= 1'b0; |
bypass_ipv4 <= 1'b0; |
bypass_ipv6 <= 1'b0; |
found_udp <= 1'b0; |
bypass_udp <= 1'b0; |
ptp_l2 <= 1'b0; |
ptp_l4 <= 1'b0; |
ptp_event <= 1'b0; |
end |
else if (int_valid_d1 && int_sop_d1) begin |
bypass_vlan <= 1'b0; |
bypass_ipv4 <= 1'b0; |
bypass_ipv6 <= 1'b0; |
found_udp <= 1'b0; |
bypass_udp <= 1'b0; |
ptp_l2 <= 1'b0; |
ptp_l4 <= 1'b0; |
ptp_event <= 1'b0; |
end |
else begin |
// bypass vlan |
// ether_type == cvlan |
if (int_valid_d1 && int_cnt==10'd3 && int_data_d1[31:16]==16'h8100) |
bypass_vlan <= 1'b1; |
// ether_type == svlan |
else if (int_valid_d1 && int_cnt==10'd3 && int_data_d1[31:16]==16'h9100) |
bypass_vlan <= 1'b1; |
else if (int_valid_d1 && int_cnt==10'd4 && int_data_d1[31:16]==16'h8100 && bypass_vlan) |
bypass_vlan <= 1'b1; |
else if (int_valid_d1 && bypass_vlan) |
bypass_vlan <= 1'b0; |
|
// bypass ipv4 |
// ether_type == ip, ip_version == 4 |
if (int_valid_d1 && (int_cnt==10'd3 || bypass_vlan && int_cnt==10'd4) && bypass_ipv4_cnt==10'd0 && |
int_data_d1[31:16]==16'h0800 && int_data_d1[15:12]==4'h4) |
bypass_ipv4 <= 1'b1; |
else if (int_valid_d1 && bypass_ipv4_cnt==10'd4) |
bypass_ipv4 <= 1'b0; |
|
// bypass ipv6 |
// ether_type == ip, ip_version == 6 |
if (int_valid_d1 && (int_cnt==10'd3 || bypass_vlan && int_cnt==10'd4) && bypass_ipv6_cnt==10'd0 && |
int_data_d1[31:16]==16'h86dd && int_data_d1[15:12]==4'h6) |
bypass_ipv6 <= 1'b1; |
else if (int_valid_d1 && bypass_ipv6_cnt==10'd9) |
bypass_ipv6 <= 1'b0; |
|
// check if it is UDP |
// ipv4_protocol == udp |
if (int_valid_d1 && bypass_ipv4_cnt==10'd1 && int_data_d1[ 7: 0]== 8'h11) |
found_udp <= 1'b1; |
// ipv6_protocol == udp |
else if (int_valid_d1 && bypass_ipv6_cnt==10'd1 && int_data_d1[31:24]== 8'h11) |
found_udp <= 1'b1; |
|
// bypass udp |
// ipv4_udp |
if (int_valid_d1 && bypass_ipv4_cnt==10'd4 && bypass_udp_cnt==10'd0 && found_udp) |
bypass_udp <= 1'b1; |
else if (int_valid_d1 && bypass_udp_cnt==10'd2) |
bypass_udp <= 1'b0; |
// ipv6_udp |
else if (int_valid_d1 && bypass_ipv6_cnt==10'd9 && bypass_udp_cnt==10'd0 && found_udp) |
bypass_udp <= 1'b1; |
else if (int_valid_d1 && bypass_udp_cnt==10'd2) |
bypass_udp <= 1'b0; |
|
// check if it is L2 PTP |
// ether_type == ptp |
if (int_valid_d1 && (int_cnt==10'd3 || bypass_vlan && int_cnt==10'd4) && int_data_d1[31:16]==16'h88F7) |
ptp_l2 <= 1'b1; |
// check if it is L4 PTP |
// udp_dest_port == ptp_event |
if (int_valid_d1 && bypass_udp_cnt==10'd0 && bypass_udp && |
(int_data_d1[31:16]==16'h013f || int_data_d1[31:16]==16'h0140)) |
ptp_l4 <= 1'b1; |
|
// check if it is PTP Event message |
if (int_valid_d1 && (int_cnt==10'd3 || bypass_vlan && int_cnt==10'd4) && int_data_d1[31:16]==16'h88F7 && |
(int_data_d1[11: 8]== 4'h0 || int_data_d1[11:8]==4'h2)) |
// ptp_message_id == sync || delay_req |
ptp_event <= 1'b1; |
else if (int_valid_d1 && (int_cnt==10'd4 || bypass_vlan && int_cnt==10'd5) && bypass_udp_cnt==10'd1 && ptp_l4 && |
(int_data_d1[11: 8]== 4'h0 || int_data_d1[11:8]==4'h2)) |
// ptp_message_id == sync || delay_req |
ptp_event <= 1'b1; |
end |
end |
|
always @(posedge rst or posedge clk) begin |
if (rst) begin |
ptp_msgid <= 4'd0; |
ptp_seqid <= 16'd0; |
end |
else if (int_valid_d1 && int_sop_d1) begin |
ptp_msgid <= 4'd0; |
ptp_seqid <= 16'd0; |
end |
else begin |
// get PTP identification information as additional information to Timestamp |
// message id |
if (int_valid_d1 && int_cnt==10'd3 && int_data_d1[31:16]==16'h88F7) |
ptp_msgid <= int_data_d1[11: 8]; |
else if (int_valid_d1 && int_cnt==10'd4 && bypass_udp_cnt==10'd1 && ptp_l4) |
ptp_msgid <= int_data_d1[11: 8]; |
// sequence id |
if (int_valid_d1 && int_cnt==10'd11 && ptp_l2) |
ptp_seqid <= int_data_d1[31:16]; |
else if (int_valid_d1 && int_cnt==10'd10 && ptp_l4) |
ptp_seqid <= int_data_d1[31:16]; |
end |
end |
|
always @(posedge rst or posedge clk) begin |
if (rst) begin |
ptp_found <= 1'b0; |
ptp_infor <= 20'd0; |
end |
else if (int_valid_d1 && int_sop_d1) begin |
ptp_found <= 1'b0; |
ptp_infor <= 20'd0; |
end |
else if (int_valid_d1 && int_eop_d1) begin |
ptp_found <= ptp_event; |
ptp_infor <= {ptp_seqid, ptp_msgid}; // 16+4 |
end |
else begin |
ptp_found <= 1'b0; |
ptp_infor <= 20'd0; |
end |
end |
|
endmodule |
/v1p0/rtl/tsu/ptp_queue.v
0,0 → 1,177
// megafunction wizard: %FIFO% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
// MODULE: dcfifo |
|
// ============================================================ |
// File Name: ptp_queue.v |
// Megafunction Name(s): |
// dcfifo |
// |
// Simulation Library Files(s): |
// altera_mf |
// ============================================================ |
// ************************************************************ |
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
// |
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version |
// ************************************************************ |
|
|
//Copyright (C) 1991-2011 Altera Corporation |
//Your use of Altera Corporation's design tools, logic functions |
//and other software and tools, and its AMPP partner logic |
//functions, and any output files from any of the foregoing |
//(including device programming or simulation files), and any |
//associated documentation or information are expressly subject |
//to the terms and conditions of the Altera Program License |
//Subscription Agreement, Altera MegaCore Function License |
//Agreement, or other applicable license agreement, including, |
//without limitation, that your use is for the sole purpose of |
//programming logic devices manufactured by Altera and sold by |
//Altera or its authorized distributors. Please refer to the |
//applicable agreement for further details. |
|
|
// synopsys translate_off |
`timescale 1 ps / 1 ps |
// synopsys translate_on |
module ptp_queue ( |
aclr, |
data, |
rdclk, |
rdreq, |
wrclk, |
wrreq, |
q, |
rdusedw, |
wrusedw); |
|
input aclr; |
input [63:0] data; |
input rdclk; |
input rdreq; |
input wrclk; |
input wrreq; |
output [63:0] q; |
output [3:0] rdusedw; |
output [3:0] wrusedw; |
`ifndef ALTERA_RESERVED_QIS |
// synopsys translate_off |
`endif |
tri0 aclr; |
`ifndef ALTERA_RESERVED_QIS |
// synopsys translate_on |
`endif |
|
wire [63:0] sub_wire0; |
wire [3:0] sub_wire1; |
wire [3:0] sub_wire2; |
wire [63:0] q = sub_wire0[63:0]; |
wire [3:0] wrusedw = sub_wire1[3:0]; |
wire [3:0] rdusedw = sub_wire2[3:0]; |
|
dcfifo dcfifo_component ( |
.rdclk (rdclk), |
.wrclk (wrclk), |
.wrreq (wrreq), |
.aclr (aclr), |
.data (data), |
.rdreq (rdreq), |
.q (sub_wire0), |
.wrusedw (sub_wire1), |
.rdusedw (sub_wire2), |
.rdempty (), |
.rdfull (), |
.wrempty (), |
.wrfull ()); |
defparam |
dcfifo_component.intended_device_family = "Cyclone III", |
dcfifo_component.lpm_numwords = 16, |
dcfifo_component.lpm_showahead = "OFF", |
dcfifo_component.lpm_type = "dcfifo", |
dcfifo_component.lpm_width = 64, |
dcfifo_component.lpm_widthu = 4, |
dcfifo_component.overflow_checking = "ON", |
dcfifo_component.rdsync_delaypipe = 4, |
dcfifo_component.underflow_checking = "ON", |
dcfifo_component.use_eab = "ON", |
dcfifo_component.write_aclr_synch = "OFF", |
dcfifo_component.wrsync_delaypipe = 4; |
|
|
endmodule |
|
// ============================================================ |
// CNX file retrieval info |
// ============================================================ |
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" |
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" |
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" |
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" |
// Retrieval info: PRIVATE: Clock NUMERIC "4" |
// Retrieval info: PRIVATE: Depth NUMERIC "16" |
// Retrieval info: PRIVATE: Empty NUMERIC "1" |
// Retrieval info: PRIVATE: Full NUMERIC "1" |
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" |
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" |
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" |
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" |
// Retrieval info: PRIVATE: Optimize NUMERIC "2" |
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" |
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" |
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" |
// Retrieval info: PRIVATE: UsedW NUMERIC "1" |
// Retrieval info: PRIVATE: Width NUMERIC "64" |
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" |
// Retrieval info: PRIVATE: diff_widths NUMERIC "0" |
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" |
// Retrieval info: PRIVATE: output_width NUMERIC "64" |
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: rsFull NUMERIC "0" |
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" |
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" |
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" |
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: wsFull NUMERIC "0" |
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" |
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" |
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" |
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" |
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64" |
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" |
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" |
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" |
// Retrieval info: CONSTANT: USE_EAB STRING "ON" |
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" |
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" |
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]" |
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]" |
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" |
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" |
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL "rdusedw[3..0]" |
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" |
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" |
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]" |
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 |
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0 |
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 |
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 |
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 |
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 |
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0 |
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0 |
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.v TRUE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.inc FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.cmp FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.bsf FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue_bb.v FALSE |
// Retrieval info: LIB_FILE: altera_mf |
/v1p0/rtl/reg/reg.v
0,0 → 1,309
`timescale 1ns/1ns |
|
module rgs ( |
// generic bus interface |
input rst,clk, |
input wr_in,rd_in, |
input [ 7:0] addr_in, |
input [31:0] data_in, |
output [31:0] data_out, |
// rtc interface |
input rtc_clk_in, |
output rtc_rst_out, |
output time_ld_out, |
output [37:0] time_reg_ns_out, |
output [47:0] time_reg_sec_out, |
output period_ld_out, |
output [39:0] period_out, |
output [37:0] time_acc_modulo_out, |
output adj_ld_out, |
output [31:0] adj_ld_data_out, |
output [39:0] period_adj_out, |
input [37:0] time_reg_ns_in, |
input [47:0] time_reg_sec_in, |
// rx tsu interface |
output rx_q_rst_out, |
output rx_q_rd_clk_out, |
output rx_q_rd_en_out, |
input [ 7:0] rx_q_stat_in, |
input [63:0] rx_q_data_in, |
// tx tsu interface |
output tx_q_rst_out, |
output tx_q_rd_clk_out, |
output tx_q_rd_en_out, |
input [ 7:0] tx_q_stat_in, |
input [63:0] tx_q_data_in |
); |
|
parameter const_00 = 8'h00; |
parameter const_04 = 8'h04; |
parameter const_08 = 8'h08; |
parameter const_0c = 8'h0C; |
parameter const_10 = 8'h10; |
parameter const_14 = 8'h14; |
parameter const_18 = 8'h18; |
parameter const_1c = 8'h1C; |
parameter const_20 = 8'h20; |
parameter const_24 = 8'h24; |
parameter const_28 = 8'h28; |
parameter const_2c = 8'h2C; |
parameter const_30 = 8'h30; |
parameter const_34 = 8'h34; |
parameter const_38 = 8'h38; |
parameter const_3c = 8'h3C; |
parameter const_40 = 8'h40; |
parameter const_44 = 8'h44; |
parameter const_48 = 8'h48; |
parameter const_4c = 8'h4C; |
parameter const_50 = 8'h50; |
parameter const_54 = 8'h54; |
parameter const_58 = 8'h58; |
parameter const_5c = 8'h5C; |
|
wire cs_00 = (addr_in[7:2]==const_00[7:2])? 1'b1: 1'b0; |
wire cs_04 = (addr_in[7:2]==const_04[7:2])? 1'b1: 1'b0; |
wire cs_08 = (addr_in[7:2]==const_08[7:2])? 1'b1: 1'b0; |
wire cs_0c = (addr_in[7:2]==const_0c[7:2])? 1'b1: 1'b0; |
wire cs_10 = (addr_in[7:2]==const_10[7:2])? 1'b1: 1'b0; |
wire cs_14 = (addr_in[7:2]==const_14[7:2])? 1'b1: 1'b0; |
wire cs_18 = (addr_in[7:2]==const_18[7:2])? 1'b1: 1'b0; |
wire cs_1c = (addr_in[7:2]==const_1c[7:2])? 1'b1: 1'b0; |
wire cs_20 = (addr_in[7:2]==const_20[7:2])? 1'b1: 1'b0; |
wire cs_24 = (addr_in[7:2]==const_24[7:2])? 1'b1: 1'b0; |
wire cs_28 = (addr_in[7:2]==const_28[7:2])? 1'b1: 1'b0; |
wire cs_2c = (addr_in[7:2]==const_2c[7:2])? 1'b1: 1'b0; |
wire cs_30 = (addr_in[7:2]==const_30[7:2])? 1'b1: 1'b0; |
wire cs_34 = (addr_in[7:2]==const_34[7:2])? 1'b1: 1'b0; |
wire cs_38 = (addr_in[7:2]==const_38[7:2])? 1'b1: 1'b0; |
wire cs_3c = (addr_in[7:2]==const_3c[7:2])? 1'b1: 1'b0; |
wire cs_40 = (addr_in[7:2]==const_40[7:2])? 1'b1: 1'b0; |
wire cs_44 = (addr_in[7:2]==const_44[7:2])? 1'b1: 1'b0; |
wire cs_48 = (addr_in[7:2]==const_48[7:2])? 1'b1: 1'b0; |
wire cs_4c = (addr_in[7:2]==const_4c[7:2])? 1'b1: 1'b0; |
wire cs_50 = (addr_in[7:2]==const_50[7:2])? 1'b1: 1'b0; |
wire cs_54 = (addr_in[7:2]==const_54[7:2])? 1'b1: 1'b0; |
wire cs_58 = (addr_in[7:2]==const_58[7:2])? 1'b1: 1'b0; |
wire cs_5c = (addr_in[7:2]==const_5c[7:2])? 1'b1: 1'b0; |
|
reg [31:0] reg_00; // ctrl 12 bit |
reg [31:0] reg_04; // qsta 16 bit |
reg [31:0] reg_08; // |
reg [31:0] reg_0c; // |
reg [31:0] reg_10; // tout 16 s |
reg [31:0] reg_14; // tout 32 s |
reg [31:0] reg_18; // tout 30 ns |
reg [31:0] reg_1c; // tout 8 nsf |
reg [31:0] reg_20; // peri 8 ns |
reg [31:0] reg_24; // peri 32 nsf |
reg [31:0] reg_28; // amod 30 ns |
reg [31:0] reg_2c; // amod 8 nsf |
reg [31:0] reg_30; // ajld 32 bit |
reg [31:0] reg_34; // |
reg [31:0] reg_38; // ajpr 8 ns |
reg [31:0] reg_3c; // ajpr 32 nsf |
reg [31:0] reg_40; // tmin 16 s |
reg [31:0] reg_44; // tmin 32 s |
reg [31:0] reg_48; // tmin 30 ns |
reg [31:0] reg_4c; // tmin 8 nsf |
reg [31:0] reg_50; // rxqu 24 bit |
reg [31:0] reg_54; // rxqu 32 bit |
reg [31:0] reg_58; // txqu 24 bit |
reg [31:0] reg_5c; // txqu 32 bit |
|
// write registers |
always @(posedge clk) begin |
if (wr_in && cs_00) reg_00 <= data_in; |
if (wr_in && cs_04) reg_04 <= data_in; |
if (wr_in && cs_08) reg_08 <= data_in; |
if (wr_in && cs_0c) reg_0c <= data_in; |
if (wr_in && cs_10) reg_10 <= data_in; |
if (wr_in && cs_14) reg_14 <= data_in; |
if (wr_in && cs_18) reg_18 <= data_in; |
if (wr_in && cs_1c) reg_1c <= data_in; |
if (wr_in && cs_20) reg_20 <= data_in; |
if (wr_in && cs_24) reg_24 <= data_in; |
if (wr_in && cs_28) reg_28 <= data_in; |
if (wr_in && cs_2c) reg_2c <= data_in; |
if (wr_in && cs_30) reg_30 <= data_in; |
if (wr_in && cs_34) reg_34 <= data_in; |
if (wr_in && cs_38) reg_38 <= data_in; |
if (wr_in && cs_3c) reg_3c <= data_in; |
if (wr_in && cs_40) reg_40 <= data_in; |
if (wr_in && cs_44) reg_44 <= data_in; |
if (wr_in && cs_48) reg_48 <= data_in; |
if (wr_in && cs_4c) reg_4c <= data_in; |
if (wr_in && cs_50) reg_50 <= data_in; |
if (wr_in && cs_54) reg_54 <= data_in; |
if (wr_in && cs_58) reg_58 <= data_in; |
if (wr_in && cs_5c) reg_5c <= data_in; |
end |
|
// read registers |
reg [37:0] time_reg_ns_int; |
reg [47:0] time_reg_sec_int; |
reg [63:0] rx_q_data_int; |
reg [ 7:0] rx_q_stat_int; |
reg [63:0] tx_q_data_int; |
reg [ 7:0] tx_q_stat_int; |
reg time_ok; |
|
reg [31:0] data_out_reg; |
always @(posedge clk) begin |
if (rd_in && cs_00) data_out_reg <= {reg_00[31:1], time_ok}; |
if (rd_in && cs_04) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]}; |
if (rd_in && cs_08) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]}; |
if (rd_in && cs_0c) data_out_reg <= reg_0c; |
if (rd_in && cs_10) data_out_reg <= reg_10; |
if (rd_in && cs_14) data_out_reg <= reg_14; |
if (rd_in && cs_18) data_out_reg <= reg_18; |
if (rd_in && cs_1c) data_out_reg <= reg_1c; |
if (rd_in && cs_20) data_out_reg <= reg_20; |
if (rd_in && cs_24) data_out_reg <= reg_24; |
if (rd_in && cs_28) data_out_reg <= reg_28; |
if (rd_in && cs_2c) data_out_reg <= reg_2c; |
if (rd_in && cs_30) data_out_reg <= reg_30; |
if (rd_in && cs_34) data_out_reg <= reg_34; |
if (rd_in && cs_38) data_out_reg <= reg_38; |
if (rd_in && cs_3c) data_out_reg <= reg_3c; |
if (rd_in && cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]}; |
if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0]; |
if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]}; |
if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]}; |
if (rd_in && cs_50) data_out_reg <= rx_q_data_int[63:32]; |
if (rd_in && cs_54) data_out_reg <= rx_q_data_int[31: 0]; |
if (rd_in && cs_58) data_out_reg <= tx_q_data_int[63:32]; |
if (rd_in && cs_5c) data_out_reg <= tx_q_data_int[31: 0]; |
end |
assign data_out = data_out_reg; |
|
// register mapping |
wire rxq_rst = reg_00[11]; |
wire rxqu_rd = reg_00[10]; |
wire txq_rst = reg_00[ 9]; |
wire txqu_rd = reg_00[ 8]; |
//wire = reg_00[ 7]; |
//wire = reg_00[ 6]; |
//wire = reg_00[ 5]; |
wire rtc_rst = reg_00[ 4]; |
wire time_ld = reg_00[ 3]; |
wire perd_ld = reg_00[ 2]; |
wire adjt_ld = reg_00[ 1]; |
wire time_rd = reg_00[ 0]; |
assign time_reg_sec_out [47:0] = {reg_10[15: 0], reg_14[31: 0]}; |
assign time_reg_ns_out [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]}; |
assign period_out [39:0] = {reg_20[ 7: 0], reg_24[31: 0]}; |
assign time_acc_modulo_out[37:0] = {reg_28[29: 0], reg_2c[ 7: 0]}; |
assign adj_ld_data_out [31:0] = reg_30[31: 0]; |
assign period_adj_out [39:0] = {reg_38[ 7: 0], reg_3c[31: 0]}; |
|
// real time clock |
reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3; |
assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3; |
always @(posedge rtc_clk_in) begin |
rtc_rst_s1 <= rtc_rst; |
rtc_rst_s2 <= rtc_rst_s1; |
rtc_rst_s3 <= rtc_rst_s2; |
end |
|
reg time_ld_s1, time_ld_s2, time_ld_s3; |
assign time_ld_out = time_ld_s2 && !time_ld_s3; |
always @(posedge rtc_clk_in) begin |
time_ld_s1 <= time_ld; |
time_ld_s2 <= time_ld_s1; |
time_ld_s3 <= time_ld_s2; |
end |
|
reg perd_ld_s1, perd_ld_s2, perd_ld_s3; |
assign period_ld_out = perd_ld_s2 && !perd_ld_s3; |
always @(posedge rtc_clk_in) begin |
perd_ld_s1 <= perd_ld; |
perd_ld_s2 <= perd_ld_s1; |
perd_ld_s3 <= perd_ld_s2; |
end |
|
reg adjt_ld_s1, adjt_ld_s2, adjt_ld_s3; |
assign adj_ld_out = adjt_ld_s2 && !adjt_ld_s3; |
always @(posedge rtc_clk_in) begin |
adjt_ld_s1 <= adjt_ld; |
adjt_ld_s2 <= adjt_ld_s1; |
adjt_ld_s3 <= adjt_ld_s2; |
end |
|
// RTC time read CDC hand-shaking |
reg time_rd_s1, time_rd_s2, time_rd_s3; |
wire time_rd_ack = time_rd_s2 && !time_rd_s3; |
always @(posedge rtc_clk_in) begin |
time_rd_s1 <= time_rd; |
time_rd_s2 <= time_rd_s1; |
time_rd_s3 <= time_rd_s2; |
end |
|
always @(posedge rtc_clk_in) begin |
if (time_rd_ack) begin |
time_reg_ns_int <= time_reg_ns_in; |
time_reg_sec_int <= time_reg_sec_in; |
end |
end |
|
reg time_rd_d1; |
wire time_rd_req = time_rd && !time_rd_d1; |
always @(posedge clk) begin |
time_rd_d1 <= time_rd; |
end |
|
always @(posedge clk or posedge time_rd_ack) begin |
if (time_rd_ack) |
time_ok <= 1'b1; |
else if (time_rd_req) |
time_ok <= 1'b0; |
end |
|
// rx time stamp queue |
assign rx_q_rd_clk_out = clk; |
|
reg rxq_rst_d1, rxq_rst_d2, rxq_rst_d3; |
assign rx_q_rst_out = rxq_rst_d2 && !rxq_rst_d3; |
always @(posedge clk) begin |
rxq_rst_d1 <= rxq_rst; |
rxq_rst_d2 <= rxq_rst_d1; |
rxq_rst_d3 <= rxq_rst_d2; |
end |
|
reg rxqu_rd_d1, rxqu_rd_d2, rxqu_rd_d3; |
assign rx_q_rd_en_out = rxqu_rd_d2 && !rxqu_rd_d3; |
always @(posedge clk) begin |
rxqu_rd_d1 <= rxqu_rd; |
rxqu_rd_d2 <= rxqu_rd_d1; |
rxqu_rd_d3 <= rxqu_rd_d2; |
end |
|
always @(posedge clk) begin |
rx_q_data_int <= rx_q_data_in; |
rx_q_stat_int <= rx_q_stat_in; |
end |
|
// tx time stamp queue |
assign tx_q_rd_clk_out = clk; |
|
reg txq_rst_d1, txq_rst_d2, txq_rst_d3; |
assign tx_q_rst_out = txq_rst_d2 && !txq_rst_d3; |
always @(posedge clk) begin |
txq_rst_d1 <= txq_rst; |
txq_rst_d2 <= txq_rst_d1; |
txq_rst_d3 <= txq_rst_d2; |
end |
|
reg txqu_rd_d1, txqu_rd_d2, txqu_rd_d3; |
assign tx_q_rd_en_out = txqu_rd_d2 && !txqu_rd_d3; |
always @(posedge clk) begin |
txqu_rd_d1 <= txqu_rd; |
txqu_rd_d2 <= txqu_rd_d1; |
txqu_rd_d3 <= txqu_rd_d2; |
end |
|
always @(posedge clk) begin |
tx_q_data_int <= tx_q_data_in; |
tx_q_stat_int <= tx_q_stat_in; |
end |
|
endmodule |
/v1p0/rtl/sopc/ha1588_inst.sopc
0,0 → 1,114
<?xml version="1.0" encoding="UTF-8"?> |
<system name="ha1588_inst"> |
<parameter name="bonusData"><![CDATA[bonusData |
{ |
element clk_0 |
{ |
datum _sortIndex |
{ |
value = "0"; |
type = "int"; |
} |
} |
element ha1588_0 |
{ |
datum _sortIndex |
{ |
value = "1"; |
type = "int"; |
} |
} |
element ha1588_inst |
{ |
} |
element mm_master_bfm_0 |
{ |
datum _sortIndex |
{ |
value = "2"; |
type = "int"; |
} |
} |
} |
]]></parameter> |
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> |
<parameter name="deviceFamily" value="CYCLONEIII" /> |
<parameter name="fabricMode" value="SOPC" /> |
<parameter name="generateLegacySim" value="true" /> |
<parameter name="generationId" value="0" /> |
<parameter name="globalResetBus" value="true" /> |
<parameter name="hdlLanguage" value="VERILOG" /> |
<parameter name="maxAdditionalLatency" value="0" /> |
<parameter name="projectName" value="ha1588_inst.qpf" /> |
<parameter name="sopcBorderPoints" value="true" /> |
<parameter name="systemHash" value="4608333994" /> |
<parameter name="timeStamp" value="1333703471124" /> |
<module kind="clock_source" version="10.1" enabled="1" name="clk_0"> |
<parameter name="clockFrequency" value="50000000" /> |
<parameter name="clockFrequencyKnown" value="true" /> |
<parameter name="inputClockFrequency" value="0" /> |
<parameter name="resetSynchronousEdges" value="NONE" /> |
</module> |
<module kind="ha1588" version="1.0" enabled="1" name="ha1588_0"> |
<parameter name="AUTO_CLOCK_CLOCK_RATE" value="50000000" /> |
</module> |
<module |
kind="altera_avalon_mm_master_bfm" |
version="10.1" |
enabled="1" |
name="mm_master_bfm_0"> |
<parameter name="AV_ADDRESS_W" value="32" /> |
<parameter name="AV_SYMBOL_W" value="8" /> |
<parameter name="AV_NUMSYMBOLS" value="4" /> |
<parameter name="AV_BURSTCOUNT_W" value="3" /> |
<parameter name="AV_READRESPONSE_W" value="8" /> |
<parameter name="AV_WRITERESPONSE_W" value="8" /> |
<parameter name="USE_READ" value="1" /> |
<parameter name="USE_WRITE" value="1" /> |
<parameter name="USE_ADDRESS" value="1" /> |
<parameter name="USE_BYTE_ENABLE" value="1" /> |
<parameter name="USE_BURSTCOUNT" value="0" /> |
<parameter name="USE_READ_DATA" value="1" /> |
<parameter name="USE_READ_DATA_VALID" value="1" /> |
<parameter name="USE_WRITE_DATA" value="1" /> |
<parameter name="USE_BEGIN_TRANSFER" value="0" /> |
<parameter name="USE_BEGIN_BURST_TRANSFER" value="0" /> |
<parameter name="USE_ARBITERLOCK" value="0" /> |
<parameter name="USE_DEBUGACCESS" value="0" /> |
<parameter name="USE_WAIT_REQUEST" value="1" /> |
<parameter name="USE_TRANSACTIONID" value="0" /> |
<parameter name="USE_WRITERESPONSE" value="0" /> |
<parameter name="USE_READRESPONSE" value="0" /> |
<parameter name="USE_CLKEN" value="0" /> |
<parameter name="ASSERT_HIGH_RESET" value="1" /> |
<parameter name="ASSERT_HIGH_WAITREQUEST" value="1" /> |
<parameter name="ASSERT_HIGH_READ" value="1" /> |
<parameter name="ASSERT_HIGH_WRITE" value="1" /> |
<parameter name="ASSERT_HIGH_BYTEENABLE" value="1" /> |
<parameter name="ASSERT_HIGH_READDATAVALID" value="1" /> |
<parameter name="ASSERT_HIGH_ARBITERLOCK" value="1" /> |
<parameter name="AV_BURST_LINEWRAP" value="0" /> |
<parameter name="AV_BURST_BNDR_ONLY" value="0" /> |
<parameter name="AV_MAX_PENDING_READS" value="1" /> |
<parameter name="AV_FIX_READ_LATENCY" value="1" /> |
<parameter name="AV_READ_WAIT_TIME" value="1" /> |
<parameter name="AV_WRITE_WAIT_TIME" value="0" /> |
<parameter name="REGISTER_WAITREQUEST" value="0" /> |
<parameter name="AV_REGISTERINCOMINGSIGNALS" value="0" /> |
<parameter name="ADDRESS_UNITS" value="SYMBOLS" /> |
</module> |
<connection kind="clock" version="10.1" start="clk_0.clk" end="ha1588_0.clock" /> |
<connection |
kind="clock" |
version="10.1" |
start="clk_0.clk" |
end="mm_master_bfm_0.clk" /> |
<connection |
kind="avalon" |
version="10.1" |
start="mm_master_bfm_0.m0" |
end="ha1588_0.avalon_slave"> |
<parameter name="arbitrationPriority" value="1" /> |
<parameter name="baseAddress" value="0x0000" /> |
</connection> |
</system> |
/v1p0/rtl/sopc/ha1588_inst.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- # |
# |
# Copyright (C) 1991-2011 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
# |
# -------------------------------------------------------------------------- # |
# |
# Quartus II |
# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version |
# Date created = 15:10:26 March 31, 2012 |
# |
# -------------------------------------------------------------------------- # |
|
QUARTUS_VERSION = "10.1" |
DATE = "15:10:26 March 31, 2012" |
|
# Revisions |
|
PROJECT_REVISION = "ha1588_inst" |
/v1p0/rtl/sopc/ha1588_inst.qsf
0,0 → 1,49
# -------------------------------------------------------------------------- # |
# |
# Copyright (C) 1991-2011 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
# |
# -------------------------------------------------------------------------- # |
# |
# Quartus II |
# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version |
# Date created = 14:25:42 March 31, 2012 |
# |
# -------------------------------------------------------------------------- # |
# |
# Notes: |
# |
# 1) The default values for assignments are stored in the file: |
# ha1588_inst_assignment_defaults.qdf |
# If this file doesn't exist, see file: |
# assignment_defaults.qdf |
# |
# 2) Altera recommends that you do not modify this file. This |
# file is updated automatically by the Quartus II software |
# and any changes you make may be lost or overwritten. |
# |
# -------------------------------------------------------------------------- # |
|
|
set_global_assignment -name FAMILY "Cyclone III" |
set_global_assignment -name DEVICE AUTO |
set_global_assignment -name TOP_LEVEL_ENTITY ha1588_inst |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.1 SP1" |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:25:42 MARCH 31, 2012" |
set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1" |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_global_assignment -name QIP_FILE ha1588_inst.qip |
/v1p0/rtl/sopc/ReadMe.txt
0,0 → 1,2
add the following path in SOPC -> Tools -> Options -> IP Search Path |
../../rtl/top |
/v1p0/rtl/rtc/rtc.v
0,0 → 1,113
`timescale 1ns/1ns |
|
module rtc ( |
input rst, clk, |
// 1. direct time adjustment: ToD set up |
input time_ld, |
input [37:0] time_reg_ns_in, // 37:8 ns, 7:0 ns_fraction |
input [47:0] time_reg_sec_in, // 47:0 sec |
// 2. frequency adjustment: frequency set up for drift compensation |
input period_ld, |
input [39:0] period_in, // 39:32 ns, 31:0 ns_fraction |
input [37:0] time_acc_modulo, // 37: 8 ns, 7:0 ns_fraction |
// 3. precise time adjustment: small time difference adjustment with a time mark |
input adj_ld, |
input [31:0] adj_ld_data, |
input [39:0] period_adj, // 39:32 ns, 31:0 ns_fraction |
|
// time output |
output [37:0] time_reg_ns, // 37:8 ns, 7:0 ns_fraction |
output [47:0] time_reg_sec // 47:0 sec |
); |
|
reg [39:0] period_fix; // 39:32 ns, 31:0 ns_fraction |
reg [31:0] adj_cnt; |
reg [39:0] time_adj; // 39:32 ns, 31:0 ns_fraction |
// frequency and small time difference adjustment registers |
always @(posedge rst or posedge clk) begin |
if (rst) begin |
period_fix <= period_fix; //40'd0; |
adj_cnt <= 32'hffffffff; |
time_adj <= time_adj; //40'd0; |
end |
else begin |
if (period_ld) // load period adjustment |
period_fix <= period_in; |
else |
period_fix <= period_fix; |
|
if (adj_ld) // load precise time adjustment time mark |
adj_cnt <= adj_ld_data; |
else if (adj_cnt==32'hffffffff) |
adj_cnt <= adj_cnt; // no cycling |
else |
adj_cnt <= adj_cnt - 1; // counting down |
|
if (adj_cnt==0) // change period temparorily |
time_adj <= period_fix + period_adj; |
else |
time_adj <= period_fix + 0; |
end |
end |
|
reg [39:0] time_adj_08n_32f; // 39:32 ns, 31:0 ns_fraction |
wire [15:0] time_adj_08n_08f; // 15: 8 ns, 7:0 ns_fraction |
reg [23:0] time_adj_00n_24f; // 23:0 ns_fraction |
// delta-sigma circuit to keep the lower 24bit of time_adj |
always @(posedge rst or posedge clk) begin |
if (rst) begin |
time_adj_08n_32f <= 40'd0; |
time_adj_00n_24f <= 24'd0; |
end |
else begin |
time_adj_08n_32f <= time_adj[39: 0] + {16'd0, time_adj_00n_24f}; // add the delta |
time_adj_00n_24f <= time_adj_08n_32f[23: 0]; // save the delta |
end |
end |
assign time_adj_08n_08f = time_adj_08n_32f[39:24]; // output w/o the delta |
|
reg [37:0] time_acc_30n_08f; // 37:8 ns , 7:0 ns_fraction |
reg [47:0] time_acc_48s; // 47:0 sec |
reg time_acc_48s_inc; |
// time accumulator (48bit_s + 30bit_ns + 8bit_ns_fraction) |
always @(posedge rst or posedge clk) begin |
if (rst) begin |
time_acc_30n_08f <= 38'd0; |
time_acc_48s <= 48'd0; |
time_acc_48s_inc <= 1'b0; |
end |
else begin |
if (time_ld) begin // direct write |
time_acc_30n_08f <= time_reg_ns_in; |
time_acc_48s <= time_reg_sec_in; |
end |
else begin |
|
if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} >= time_acc_modulo) |
time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f} - time_acc_modulo; |
else |
time_acc_30n_08f <= time_acc_30n_08f + {22'd0, time_adj_08n_08f}; |
|
if (time_acc_48s_inc) |
time_acc_48s_inc <= 1'b0; |
else if (time_acc_modulo == 38'd0) |
time_acc_48s_inc <= 1'b0; |
else if (time_acc_30n_08f + {22'd0, time_adj_08n_08f} + {22'd0, time_adj_08n_08f} >= time_acc_modulo) |
time_acc_48s_inc <= 1'b1; |
else |
time_acc_48s_inc <= 1'b0; |
|
if (time_acc_48s_inc) |
time_acc_48s <= time_acc_48s + 1; |
else |
time_acc_48s <= time_acc_48s; |
|
end |
end |
end |
|
// time output (48bit_s + 30bit_ns + 8bit_ns_fraction) |
assign time_reg_ns = time_acc_30n_08f; |
assign time_reg_sec = time_acc_48s; |
|
endmodule |
/v1p0/sim/top/ptp_drv_bfm/ptp_drv_bfm.c
0,0 → 1,183
#include <stdio.h> |
|
#include "svdpi.h" |
#include "../dpiheader.h" |
int ptp_drv_bfm_c(double fw_delay) |
{ |
unsigned int cpu_addr_i; |
unsigned int cpu_data_i; |
unsigned int cpu_data_o; |
|
// LOAD RTC PERIOD AND ACC_MODULO |
cpu_addr_i = 0x00000020; |
cpu_data_i = 0x8; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000024; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000028; |
cpu_data_i = 0x3B9ACA00; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x0000002C; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x4; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// RESET RTC |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0xA10; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// READ RTC SEC AND NS |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x1; |
cpu_wr(cpu_addr_i, cpu_data_i); |
do { |
cpu_addr_i = 0x00000000; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
//printf("%08x\n", (cpu_data_o & 0x1)); |
} while ((cpu_data_o & 0x1) == 0x0); |
cpu_addr_i = 0X00000040; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("\ntime: \n%08x\n", cpu_data_o); |
cpu_addr_i = 0X00000044; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
cpu_addr_i = 0X00000048; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
cpu_addr_i = 0X0000004C; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
// LOAD RTC SEC AND NS |
cpu_addr_i = 0x00000010; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000014; |
cpu_data_i = 0x1; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000018; |
cpu_data_i = 0x3B9AC9F6; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x0000001C; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x8; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// LOAD RTC ADJ |
cpu_addr_i = 0x00000030; |
cpu_data_i = 0x100; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000038; |
cpu_data_i = 0x1; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x0000003C; |
cpu_data_i = 0x20; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x2; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// READ RTC SEC AND NS |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x1; |
cpu_wr(cpu_addr_i, cpu_data_i); |
do { |
cpu_addr_i = 0x00000000; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
//printf("%08x\n", (cpu_data_o & 0x1)); |
} while ((cpu_data_o & 0x1) == 0x0); |
cpu_addr_i = 0X00000040; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("\ntime: \n%08x\n", cpu_data_o); |
cpu_addr_i = 0X00000044; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
cpu_addr_i = 0X00000048; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
cpu_addr_i = 0X0000004C; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
int i; |
// POLL TSU RX STATUS |
int rx_queue_num; |
do { |
cpu_addr_i = 0x00000004; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
rx_queue_num = cpu_data_o; |
//printf("%08x\n", rx_queue_num); |
} while (!(rx_queue_num > 0x2)); |
// READ TSU RX FIFO |
for (i=rx_queue_num; i>0; i--) { |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x400; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000050; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("\nRx stamp: \n%08x\n", cpu_data_o); |
cpu_addr_i = 0x00000054; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
} |
// POLL TSU TX STATUS |
int tx_queue_num; |
do { |
cpu_addr_i = 0x00000008; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
tx_queue_num = cpu_data_o; |
//printf("%08x\n", tx_queue_num); |
} while (!(tx_queue_num > 0x2)); |
// READ TSU TX FIFO |
for (i=tx_queue_num; i>0; i--) { |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x100; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000058; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("\nTx stamp: \n%08x\n", cpu_data_o); |
cpu_addr_i = 0x0000005C; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
} |
|
// READ BACK ALL REGISTERS |
for (;;) |
{ |
int t; |
for (t=0; t<=0x5c; t=t+4) |
{ |
cpu_hd(10); |
|
cpu_addr_i = t; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
} |
} |
|
return(0); /* Return success (required by tasks) */ |
} |
/v1p0/sim/top/ptp_drv_bfm/ptp_drv_bfm.v
0,0 → 1,80
`timescale 1ns/1ns |
|
module ptp_drv_bfm_sv |
( |
input up_clk, |
output up_wr, |
output up_rd, |
output [ 7:0] up_addr, |
output [31:0] up_data_wr, |
input [31:0] up_data_rd |
); |
|
import "DPI-C" context task ptp_drv_bfm_c |
( |
input real fw_delay |
); |
|
reg [ 7:0] up_addr_o; |
reg [31:0] up_data_o; |
wire [31:0] up_data_i; |
reg up_wr_o; |
reg up_rd_o; |
|
export "DPI-C" task cpu_wr; |
task cpu_wr(input int addr, input int data); |
integer i; |
//$display("wr %08x %08x", addr, data); |
for (i=0; i<1; i=i+1) @(posedge up_clk); |
up_addr_o = addr; |
up_data_o = data; |
up_wr_o = 1'b1; |
for (i=0; i<1; i=i+1) @(posedge up_clk); |
up_addr_o = addr; |
up_data_o = data; |
up_wr_o = 1'b0; |
for (i=0; i<1; i=i+1) @(posedge up_clk); |
endtask |
|
export "DPI-C" task cpu_rd; |
task cpu_rd(input int addr, output int data); |
integer i; |
for (i=0; i<2; i=i+1) @(posedge up_clk); |
up_addr_o = addr; |
up_rd_o = 1'b1; |
for (i=0; i<1; i=i+1) @(posedge up_clk); |
up_addr_o = addr; |
up_rd_o = 1'b0; |
for (i=0; i<2; i=i+1) @(posedge up_clk); |
data = up_data_rd; |
//$display("rd %08x %08x", addr, data); |
endtask |
|
export "DPI-C" task cpu_hd; |
task cpu_hd(input int t); |
integer i; |
//$display("#%d",t); |
for (i=0; i<=t; i=i+1) @(posedge up_clk); |
endtask |
|
assign up_wr = up_wr_o; |
assign up_rd = up_rd_o; |
assign up_addr = up_addr_o; |
assign up_data_wr = up_data_o; |
assign up_data_i = up_data_rd; |
|
|
|
// start cpu bfm C model |
reg up_start; |
initial begin |
up_wr_o = 1'b0; |
up_rd_o = 1'b0; |
up_addr_o = 'd0; |
up_data_o = 'd0; |
|
@(posedge up_start); |
#100 ptp_drv_bfm_c(5); |
end |
|
endmodule |
/v1p0/sim/top/sim.sh
0,0 → 1,52
quit -sim |
|
vlib altera |
vdel -lib altera -all |
vlib work |
vdel -lib work -all |
|
vlib altera |
# compile vendor dependent files |
vlog -work altera altera_mf.v |
|
vlib work |
# compile vendor independent files |
vlog -work work ../../rtl/top/ha1588.v +initreg+0 |
vlog -work work ../../rtl/reg/reg.v +initreg+0 |
vlog -work work ../../rtl/rtc/rtc.v +initreg+0 |
vlog -work work ../../rtl/tsu/tsu.v +initreg+0 |
vlog -work work ../../rtl/tsu/ptp_queue.v +initreg+0 |
vlog -work work ../../rtl/tsu/ptp_parser.v +initreg+0 |
|
# compile testbench files |
vlog -work work -sv ha1588_tb.v |
|
# compile nic driver bfm files |
vlog -work work -sv nic_drv_bfm/gmii_rx_bfm.v |
vlog -work work -sv nic_drv_bfm/gmii_tx_bfm.v |
|
# compile ptp driver bfm files |
vlog -work work -sv ptp_drv_bfm/ptp_drv_bfm.v |
|
# compile driver bfm files |
# Sytemverilog DPI steps to combine sv and c |
# step 1: generate dpiheader.h |
vlog -work work -sv -dpiheader dpiheader.h ptp_drv_bfm/ptp_drv_bfm.v |
## step 2: generate ptp_drv_bfm.obj |
#vsim -dpiexportobj ptp_drv_bfm_sv ptp_drv_bfm |
# step 3: generate ptp_drv_bfm_c.so |
gcc -c -I $::env(MODEL_TECH)/../include ptp_drv_bfm/ptp_drv_bfm.c |
# step 4: generate ptp_drv_bfm_c.o |
gcc -shared -Bsymbolic -o ptp_drv_bfm_c.so ptp_drv_bfm.o |
|
vsim -novopt \ |
-L altera \ |
-sv_lib ptp_drv_bfm_c \ |
-t ps \ |
ha1588_tb |
|
log -r */* |
radix -hexadecimal |
do wave.do |
|
run 50000ns |
/v1p0/sim/top/wave.do
0,0 → 1,67
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/up_clk |
add wave -noupdate -format Logic /ha1588_tb/up_wr |
add wave -noupdate -format Logic /ha1588_tb/up_rd |
add wave -noupdate -format Literal /ha1588_tb/up_addr |
add wave -noupdate -format Literal /ha1588_tb/up_data_wr |
add wave -noupdate -format Literal /ha1588_tb/up_data_rd |
add wave -noupdate -format Logic /ha1588_tb/rtc_clk |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/addr_in |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/wr_in |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/rd_in |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/data_in |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/cs_00 |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/reg_00 |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/data_out_reg |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/period_ld_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/rtc_rst_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_ld_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/adj_ld_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_rd_req |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_rd_ack |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_ok |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/time_reg_ns |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rtc/time_acc_48s_inc |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/time_reg_sec |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rtc/rst |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rtc/adj_ld |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/adj_cnt |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/time_adj |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rx_tsu/rst |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rx_tsu/q_rst |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rx_tsu/ptp_found |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rx_tsu/ptp_infor |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rx_tsu/q_rdusedw |
add wave -noupdate -format Literal -radix unsigned /ha1588_tb/NIC_DRV_RX_BFM/num_rx |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_tx_tsu/rst |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_tx_tsu/q_rst |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_tx_tsu/ptp_found |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_tx_tsu/ptp_infor |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_tx_tsu/q_rdusedw |
add wave -noupdate -format Literal -radix unsigned /ha1588_tb/NIC_DRV_TX_BFM/num_tx |
add wave -noupdate -divider {New Divider} |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {3718000 ps} 0} |
configure wave -namecolwidth 333 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {0 ps} {2026775 ps} |
/v1p0/sim/top/ha1588_tb.v
0,0 → 1,78
`timescale 1ns/1ns |
|
module ha1588_tb (); |
|
reg up_clk; |
wire up_wr, up_rd; |
wire [ 7:0] up_addr; |
wire [31:0] up_data_wr, up_data_rd; |
initial begin |
up_clk = 1'b0; |
forever #5 up_clk = !up_clk; |
end |
|
reg rtc_clk; |
initial begin |
rtc_clk = 1'b0; |
forever #4 rtc_clk = !rtc_clk; |
end |
|
reg rst; |
initial begin |
rst = 1'b1; |
#10 rst = 1'b0; |
end |
|
wire rx_gmii_clk; |
wire rx_gmii_ctrl; |
wire [ 7:0] rx_gmii_data; |
wire tx_gmii_clk; |
wire tx_gmii_ctrl; |
wire [ 7:0] tx_gmii_data; |
|
gmii_rx_bfm NIC_DRV_RX_BFM ( |
.gmii_rxclk(rx_gmii_clk), |
.gmii_rxctrl(rx_gmii_ctrl), |
.gmii_rxdata(rx_gmii_data) |
); |
|
gmii_tx_bfm NIC_DRV_TX_BFM ( |
.gmii_txclk(tx_gmii_clk), |
.gmii_txctrl(tx_gmii_ctrl), |
.gmii_txdata(tx_gmii_data) |
); |
|
ptp_drv_bfm_sv PTP_DRV_BFM ( |
.up_clk(up_clk), |
.up_wr(up_wr), |
.up_rd(up_rd), |
.up_addr(up_addr), |
.up_data_wr(up_data_wr), |
.up_data_rd(up_data_rd) |
); |
|
ha1588 PTP_HA_DUT ( |
.rst(rst), |
.clk(up_clk), |
.wr_in(up_wr), |
.rd_in(up_rd), |
.addr_in(up_addr), |
.data_in(up_data_wr), |
.data_out(up_data_rd), |
|
.rtc_clk(rtc_clk), |
|
.rx_gmii_clk(rx_gmii_clk), |
.rx_gmii_ctrl(rx_gmii_ctrl), |
.rx_gmii_data(rx_gmii_data), |
.tx_gmii_clk(tx_gmii_clk), |
.tx_gmii_ctrl(tx_gmii_ctrl), |
.tx_gmii_data(tx_gmii_data) |
); |
|
initial begin |
ha1588_tb.PTP_DRV_BFM.up_start = 1; |
#100000000 $stop; |
end |
|
endmodule |
/v1p0/sim/top/nic_drv_bfm/gmii_rx_bfm.v
0,0 → 1,110
`timescale 1ns/1ns |
|
module gmii_rx_bfm |
( |
output gmii_rxclk, |
output reg gmii_rxctrl, |
output reg [7:0] gmii_rxdata |
); |
|
reg gmii_rxclk_offset; |
initial begin |
gmii_rxclk_offset = 1'b0; |
forever #4 gmii_rxclk_offset = !gmii_rxclk_offset; |
end |
assign #2 gmii_rxclk = gmii_rxclk_offset; |
|
integer feeder_file_rx, r_rx; |
integer start_addr_rx, end_addr_rx; |
integer index_rx, num_rx; |
reg eof_rx; |
reg pcap_endian_rx; |
reg [31:0] pcap_4bytes_rx; |
reg [31:0] packet_leng_rx; |
reg [ 7:0] packet_byte_rx; |
initial |
begin : feeder_rx |
gmii_rxctrl = 1'b0; |
gmii_rxdata = 4'd0; |
#100; |
feeder_file_rx = $fopen("nic_drv_bfm/ptpdv2_rx.pcap","rb"); |
if (feeder_file_rx == 0) |
begin |
$display("Failed to open ptpdv2_rx.pcap!"); |
disable feeder_rx; |
end |
else |
begin |
// test pcap file endian |
r_rx = $fread(pcap_4bytes_rx, feeder_file_rx); |
pcap_endian_rx = (pcap_4bytes_rx == 32'ha1b2c3d4)? 1:0; |
$fseek(feeder_file_rx, -4, 1); |
// skip pcap file header 24*8 |
$fseek(feeder_file_rx, 24, 1); |
// read packet content |
eof_rx = 0; |
num_rx = 0; |
while (!eof_rx & !$feof(feeder_file_rx)) |
begin : fileread_loop |
// skip frame header (8+4)*8 |
start_addr_rx = $ftell(feeder_file_rx); |
$fseek(feeder_file_rx, 8+4, 1); |
// get frame length big endian 4*8 |
r_rx = $fread(packet_leng_rx, feeder_file_rx); |
packet_leng_rx = pcap_endian_rx? |
{packet_leng_rx[31:24], packet_leng_rx[23:16], packet_leng_rx[15: 8], packet_leng_rx[ 7: 0]}: |
{packet_leng_rx[ 7: 0], packet_leng_rx[15: 8], packet_leng_rx[23:16], packet_leng_rx[31:24]}; |
// check whether end of file |
if (r_rx == 0) |
begin |
eof_rx = 1; |
@(posedge gmii_rxclk_offset); |
gmii_rxctrl = 1'b0; |
gmii_rxdata = 8'h00; |
disable fileread_loop; |
end |
// send ifg 96bit=12*8 |
repeat (12) |
begin |
@(posedge gmii_rxclk_offset) |
gmii_rxctrl = 1'b0; |
gmii_rxdata = 8'h00; |
end |
// send frame preamble and sfd 5555555d=4*8 |
repeat (3) |
begin |
@(posedge gmii_rxclk_offset); |
gmii_rxctrl = 1'b1; |
gmii_rxdata = 8'h55; |
end |
@(posedge gmii_rxclk_offset) |
gmii_rxctrl = 1'b1; |
gmii_rxdata = 8'h5d; |
// send frame content |
for (index_rx=0; index_rx<packet_leng_rx; index_rx=index_rx+1) |
begin |
r_rx = $fread(packet_byte_rx, feeder_file_rx); |
@(posedge gmii_rxclk_offset); |
gmii_rxctrl = 1'b1; |
gmii_rxdata = packet_byte_rx; |
// check whether end of file |
if (r_rx == 0) |
begin |
eof_rx = 1; |
@(posedge gmii_rxclk_offset); |
gmii_rxctrl = 1'b0; |
gmii_rxdata = 8'h00; |
disable fileread_loop; |
end |
end |
end_addr_rx = $ftell(feeder_file_rx); |
num_rx = num_rx + 1; |
end |
$fclose(feeder_file_rx); |
gmii_rxctrl = 1'b0; |
gmii_rxdata = 8'h00; |
end |
end |
|
|
endmodule |
/v1p0/sim/top/nic_drv_bfm/gmii_tx_bfm.v
0,0 → 1,110
`timescale 1ns/1ns |
|
module gmii_tx_bfm |
( |
output gmii_txclk, |
output reg gmii_txctrl, |
output reg [7:0] gmii_txdata |
); |
|
reg gmii_txclk_offset; |
initial begin |
gmii_txclk_offset = 1'b0; |
forever #4 gmii_txclk_offset = !gmii_txclk_offset; |
end |
assign #2 gmii_txclk = gmii_txclk_offset; |
|
integer feeder_file_tx, r_tx; |
integer start_addr_tx, end_addr_tx; |
integer index_tx, num_tx; |
reg eof_tx; |
reg pcap_endian_tx; |
reg [31:0] pcap_4bytes_tx; |
reg [31:0] packet_leng_tx; |
reg [ 7:0] packet_byte_tx; |
initial |
begin : feeder_tx |
gmii_txctrl = 1'b0; |
gmii_txdata = 4'd0; |
#100; |
feeder_file_tx = $fopen("nic_drv_bfm/ptpdv2_tx.pcap","rb"); |
if (feeder_file_tx == 0) |
begin |
$display("Failed to open ptpdv2_tx.pcap!"); |
disable feeder_tx; |
end |
else |
begin |
// test pcap file endian |
r_tx = $fread(pcap_4bytes_tx, feeder_file_tx); |
pcap_endian_tx = (pcap_4bytes_tx == 32'ha1b2c3d4)? 1:0; |
$fseek(feeder_file_tx, -4, 1); |
// skip pcap file header 24*8 |
$fseek(feeder_file_tx, 24, 1); |
// read packet content |
eof_tx = 0; |
num_tx = 0; |
while (!eof_tx & !$feof(feeder_file_tx)) |
begin : fileread_loop |
// skip frame header (8+4)*8 |
start_addr_tx = $ftell(feeder_file_tx); |
$fseek(feeder_file_tx, 8+4, 1); |
// get frame length big endian 4*8 |
r_tx = $fread(packet_leng_tx, feeder_file_tx); |
packet_leng_tx = pcap_endian_tx? |
{packet_leng_tx[31:24], packet_leng_tx[23:16], packet_leng_tx[15: 8], packet_leng_tx[ 7: 0]}: |
{packet_leng_tx[ 7: 0], packet_leng_tx[15: 8], packet_leng_tx[23:16], packet_leng_tx[31:24]}; |
// check whether end of file |
if (r_tx == 0) |
begin |
eof_tx = 1; |
@(posedge gmii_txclk_offset); |
gmii_txctrl = 1'b0; |
gmii_txdata = 8'h00; |
disable fileread_loop; |
end |
// send ifg 96bit=12*8 |
repeat (12) |
begin |
@(posedge gmii_txclk_offset) |
gmii_txctrl = 1'b0; |
gmii_txdata = 8'h00; |
end |
// send frame preamble and sfd 5555555d=4*8 |
repeat (3) |
begin |
@(posedge gmii_txclk_offset); |
gmii_txctrl = 1'b1; |
gmii_txdata = 8'h55; |
end |
@(posedge gmii_txclk_offset) |
gmii_txctrl = 1'b1; |
gmii_txdata = 8'h5d; |
// send frame content |
for (index_tx=0; index_tx<packet_leng_tx; index_tx=index_tx+1) |
begin |
r_tx = $fread(packet_byte_tx, feeder_file_tx); |
@(posedge gmii_txclk_offset); |
gmii_txctrl = 1'b1; |
gmii_txdata = packet_byte_tx; |
// check whether end of file |
if (r_tx == 0) |
begin |
eof_tx = 1; |
@(posedge gmii_txclk_offset); |
gmii_txctrl = 1'b0; |
gmii_txdata = 8'h00; |
disable fileread_loop; |
end |
end |
end_addr_tx = $ftell(feeder_file_tx); |
num_tx = num_tx + 1; |
end |
$fclose(feeder_file_tx); |
gmii_txctrl = 1'b0; |
gmii_txdata = 8'h00; |
end |
end |
|
|
endmodule |
/v1p0/sim/top/nic_drv_bfm/ptpdv2_rx.pcap
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
v1p0/sim/top/nic_drv_bfm/ptpdv2_rx.pcap
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: v1p0/sim/top/nic_drv_bfm/ptpdv2_tx.pcap
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: v1p0/sim/top/nic_drv_bfm/ptpdv2_tx.pcap
===================================================================
--- v1p0/sim/top/nic_drv_bfm/ptpdv2_tx.pcap (nonexistent)
+++ v1p0/sim/top/nic_drv_bfm/ptpdv2_tx.pcap (revision 28)
v1p0/sim/top/nic_drv_bfm/ptpdv2_tx.pcap
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: v1p0/sim/top/sim.do
===================================================================
--- v1p0/sim/top/sim.do (nonexistent)
+++ v1p0/sim/top/sim.do (revision 28)
@@ -0,0 +1,53 @@
+quit -sim
+
+vlib altera
+vdel -lib altera -all
+vlib work
+vdel -lib work -all
+
+vlib altera
+# compile vendor dependent files
+vlog -work altera altera_mf.v
+
+vlib work
+# compile vendor independent files
+vlog -work work ../../rtl/top/ha1588.v +initreg+0
+vlog -work work ../../rtl/reg/reg.v +initreg+0
+vlog -work work ../../rtl/rtc/rtc.v +initreg+0
+vlog -work work ../../rtl/tsu/tsu.v +initreg+0
+vlog -work work ../../rtl/tsu/ptp_queue.v +initreg+0
+vlog -work work ../../rtl/tsu/ptp_parser.v +initreg+0
+
+# compile testbench files
+vlog -work work -sv ha1588_tb.v
+
+# compile nic driver bfm files
+vlog -work work -sv nic_drv_bfm/gmii_rx_bfm.v
+vlog -work work -sv nic_drv_bfm/gmii_tx_bfm.v
+
+# compile ptp driver bfm files
+vlog -work work -sv ptp_drv_bfm/ptp_drv_bfm.v
+
+# compile driver bfm files
+# Sytemverilog DPI steps to combine sv and c
+# step 1: generate dpiheader.h
+vlog -work work -sv -dpiheader dpiheader.h ptp_drv_bfm/ptp_drv_bfm.v
+# step 2: generate ptp_drv_bfm.obj
+vsim -dpiexportobj ptp_drv_bfm_sv ptp_drv_bfm_sv
+# step 3: generate ptp_drv_bfm_c.obj
+gcc -c -I $::env(MODEL_TECH)/../include ptp_drv_bfm/ptp_drv_bfm.c
+# step 4: generate ptp_drv_bfm_c.dll
+gcc -shared -Bsymbolic -o ptp_drv_bfm_c.dll ptp_drv_bfm.o \
+ ptp_drv_bfm_sv.obj -L $::env(MODEL_TECH) -lmtipli
+
+vsim -novopt \
+ -L altera \
+ -sv_lib ptp_drv_bfm_c \
+ -t ps \
+ ha1588_tb
+
+log -r */*
+radix -hexadecimal
+do wave.do
+
+run 50000ns
Index: v1p0/sim/top/sim.bat
===================================================================
--- v1p0/sim/top/sim.bat (nonexistent)
+++ v1p0/sim/top/sim.bat (revision 28)
@@ -0,0 +1,7 @@
+title %CD%
+
+SET LM_LICENSE_FILE=C:\lmlicense\licensefile.dat
+SET MODEL_TECH=C:\modeltech_6.5b\win32
+SET PATH=C:\Modeltech_6.5b\win32;C:\modeltech_6.5b\gcc-4.2.1-mingw32\bin
+
+vsim -do sim.do
\ No newline at end of file
Index: v1p0/sim/top/altera_mf.v
===================================================================
--- v1p0/sim/top/altera_mf.v (nonexistent)
+++ v1p0/sim/top/altera_mf.v (revision 28)
@@ -0,0 +1,2844 @@
+// Copyright (C) 1991-2011 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+// Quartus II 10.1 Build 197 11/29/2010
+
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : ALTERA_MF_HINT_EVALUATION
+//
+// Description : Common function to grep the value of altera specific parameters
+// within the lpm_hint parameter.
+//
+// Limitation : No error checking to check whether the content of the lpm_hint
+// is valid or not.
+//
+// Results expected: If the target parameter found, return the value of the parameter.
+// Otherwise, return empty string.
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module ALTERA_MF_HINT_EVALUATION;
+
+// FUNCTON DECLARATION
+
+// This function will search through the string (given string) to look for a match for the
+// a given parameter(compare_param_name). It will return the value for the given parameter.
+function [8*200:1] GET_PARAMETER_VALUE;
+ input [8*200:1] given_string; // string to be searched
+ input [8*50:1] compare_param_name; // parameter name to be looking for in the given_string.
+ integer param_value_char_count; // to indicate current character count in the param_value
+ integer param_name_char_count; // to indicate current character count in the param_name
+ integer white_space_count;
+
+ reg extract_param_value; // if 1 mean extracting parameters value from given string
+ reg extract_param_name; // if 1 mean extracting parameters name from given string
+ reg param_found; // to indicate whether compare_param_name have been found in the given_string
+ reg include_white_space; // if 1, include white space in the parameter value
+
+ reg [8*200:1] reg_string; // to store the value of the given string
+ reg [8*50:1] param_name; // to store parameter name
+ reg [8*20:1] param_value; // to store parameter value
+ reg [8:1] tmp; // to get the value of the current byte
+begin
+ reg_string = given_string;
+ param_value_char_count = 0;
+ param_name_char_count =0;
+ extract_param_value = 1;
+ extract_param_name = 0;
+ param_found = 0;
+ include_white_space = 0;
+ white_space_count = 0;
+
+ tmp = reg_string[8:1];
+
+ // checking every bytes of the reg_string from right to left.
+ while ((tmp != 0 ) && (param_found != 1))
+ begin
+ tmp = reg_string[8:1];
+
+ //if tmp != ' ' or should include white space (trailing white space are ignored)
+ if((tmp != 32) || (include_white_space == 1))
+ begin
+ if(tmp == 32)
+ begin
+ white_space_count = 1;
+ end
+ else if(tmp == 61) // if tmp = '='
+ begin
+ extract_param_value = 0;
+ extract_param_name = 1; // subsequent bytes should be part of param_name
+ include_white_space = 0; // ignore the white space (if any) between param_name and '='
+ white_space_count = 0;
+ param_value = param_value >> (8 * (20 - param_value_char_count));
+ param_value_char_count = 0;
+ end
+ else if (tmp == 44) // if tmp = ','
+ begin
+ extract_param_value = 1; // subsequent bytes should be part of param_value
+ extract_param_name = 0;
+ param_name = param_name >> (8 * (50 - param_name_char_count));
+ param_name_char_count = 0;
+ if(param_name == compare_param_name)
+ param_found = 1; // the compare_param_name have been found in the reg_string
+ end
+ else
+ begin
+ if(extract_param_value == 1)
+ begin
+ param_value_char_count = param_value_char_count + white_space_count + 1;
+ include_white_space = 1;
+ if(white_space_count > 0)
+ begin
+ param_value = {8'b100000, param_value[20*8:9]};
+ white_space_count = 0;
+ end
+ param_value = {tmp, param_value[20*8:9]};
+ end
+ else if(extract_param_name == 1)
+ begin
+ param_name = {tmp, param_name[50*8:9]};
+ param_name_char_count = param_name_char_count + 1;
+ end
+ end
+ end
+ reg_string = reg_string >> 8; // shift 1 byte to the right
+ end
+
+ // for the case whether param_name is the left most part of the reg_string
+ if(extract_param_name == 1)
+ begin
+ param_name = param_name >> (8 * (50 - param_name_char_count));
+
+ if(param_name == compare_param_name)
+ param_found = 1;
+ end
+
+ if (param_found == 1)
+ GET_PARAMETER_VALUE = param_value; // return the value of the parameter been looking for
+ else
+ GET_PARAMETER_VALUE = ""; // return empty string if parameter not found
+
+end
+endfunction
+
+endmodule // ALTERA_MF_HINT_EVALUATION
+
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : ALTERA_DEVICE_FAMILIES
+//
+// Description : Common Altera device families comparison
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module ALTERA_DEVICE_FAMILIES;
+
+function IS_FAMILY_STRATIX;
+ input[8*20:1] device;
+ reg is_stratix;
+begin
+ if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
+ is_stratix = 1;
+ else
+ is_stratix = 0;
+
+ IS_FAMILY_STRATIX = is_stratix;
+end
+endfunction //IS_FAMILY_STRATIX
+
+function IS_FAMILY_STRATIXGX;
+ input[8*20:1] device;
+ reg is_stratixgx;
+begin
+ if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
+ is_stratixgx = 1;
+ else
+ is_stratixgx = 0;
+
+ IS_FAMILY_STRATIXGX = is_stratixgx;
+end
+endfunction //IS_FAMILY_STRATIXGX
+
+function IS_FAMILY_CYCLONE;
+ input[8*20:1] device;
+ reg is_cyclone;
+begin
+ if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
+ is_cyclone = 1;
+ else
+ is_cyclone = 0;
+
+ IS_FAMILY_CYCLONE = is_cyclone;
+end
+endfunction //IS_FAMILY_CYCLONE
+
+function IS_FAMILY_MAXII;
+ input[8*20:1] device;
+ reg is_maxii;
+begin
+ if ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
+ is_maxii = 1;
+ else
+ is_maxii = 0;
+
+ IS_FAMILY_MAXII = is_maxii;
+end
+endfunction //IS_FAMILY_MAXII
+
+function IS_FAMILY_STRATIXII;
+ input[8*20:1] device;
+ reg is_stratixii;
+begin
+ if ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
+ is_stratixii = 1;
+ else
+ is_stratixii = 0;
+
+ IS_FAMILY_STRATIXII = is_stratixii;
+end
+endfunction //IS_FAMILY_STRATIXII
+
+function IS_FAMILY_STRATIXIIGX;
+ input[8*20:1] device;
+ reg is_stratixiigx;
+begin
+ if ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
+ is_stratixiigx = 1;
+ else
+ is_stratixiigx = 0;
+
+ IS_FAMILY_STRATIXIIGX = is_stratixiigx;
+end
+endfunction //IS_FAMILY_STRATIXIIGX
+
+function IS_FAMILY_ARRIAGX;
+ input[8*20:1] device;
+ reg is_arriagx;
+begin
+ if ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
+ is_arriagx = 1;
+ else
+ is_arriagx = 0;
+
+ IS_FAMILY_ARRIAGX = is_arriagx;
+end
+endfunction //IS_FAMILY_ARRIAGX
+
+function IS_FAMILY_CYCLONEII;
+ input[8*20:1] device;
+ reg is_cycloneii;
+begin
+ if ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
+ is_cycloneii = 1;
+ else
+ is_cycloneii = 0;
+
+ IS_FAMILY_CYCLONEII = is_cycloneii;
+end
+endfunction //IS_FAMILY_CYCLONEII
+
+function IS_FAMILY_HARDCOPYII;
+ input[8*20:1] device;
+ reg is_hardcopyii;
+begin
+ if ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
+ is_hardcopyii = 1;
+ else
+ is_hardcopyii = 0;
+
+ IS_FAMILY_HARDCOPYII = is_hardcopyii;
+end
+endfunction //IS_FAMILY_HARDCOPYII
+
+function IS_FAMILY_STRATIXIII;
+ input[8*20:1] device;
+ reg is_stratixiii;
+begin
+ if ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
+ is_stratixiii = 1;
+ else
+ is_stratixiii = 0;
+
+ IS_FAMILY_STRATIXIII = is_stratixiii;
+end
+endfunction //IS_FAMILY_STRATIXIII
+
+function IS_FAMILY_CYCLONEIII;
+ input[8*20:1] device;
+ reg is_cycloneiii;
+begin
+ if ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
+ is_cycloneiii = 1;
+ else
+ is_cycloneiii = 0;
+
+ IS_FAMILY_CYCLONEIII = is_cycloneiii;
+end
+endfunction //IS_FAMILY_CYCLONEIII
+
+function IS_FAMILY_STRATIXIV;
+ input[8*20:1] device;
+ reg is_stratixiv;
+begin
+ if ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
+ is_stratixiv = 1;
+ else
+ is_stratixiv = 0;
+
+ IS_FAMILY_STRATIXIV = is_stratixiv;
+end
+endfunction //IS_FAMILY_STRATIXIV
+
+function IS_FAMILY_ARRIAIIGX;
+ input[8*20:1] device;
+ reg is_arriaiigx;
+begin
+ if ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
+ is_arriaiigx = 1;
+ else
+ is_arriaiigx = 0;
+
+ IS_FAMILY_ARRIAIIGX = is_arriaiigx;
+end
+endfunction //IS_FAMILY_ARRIAIIGX
+
+function IS_FAMILY_HARDCOPYIII;
+ input[8*20:1] device;
+ reg is_hardcopyiii;
+begin
+ if ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
+ is_hardcopyiii = 1;
+ else
+ is_hardcopyiii = 0;
+
+ IS_FAMILY_HARDCOPYIII = is_hardcopyiii;
+end
+endfunction //IS_FAMILY_HARDCOPYIII
+
+function IS_FAMILY_HARDCOPYIV;
+ input[8*20:1] device;
+ reg is_hardcopyiv;
+begin
+ if ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
+ is_hardcopyiv = 1;
+ else
+ is_hardcopyiv = 0;
+
+ IS_FAMILY_HARDCOPYIV = is_hardcopyiv;
+end
+endfunction //IS_FAMILY_HARDCOPYIV
+
+function IS_FAMILY_CYCLONEIIILS;
+ input[8*20:1] device;
+ reg is_cycloneiiils;
+begin
+ if ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
+ is_cycloneiiils = 1;
+ else
+ is_cycloneiiils = 0;
+
+ IS_FAMILY_CYCLONEIIILS = is_cycloneiiils;
+end
+endfunction //IS_FAMILY_CYCLONEIIILS
+
+function IS_FAMILY_CYCLONEIVGX;
+ input[8*20:1] device;
+ reg is_cycloneivgx;
+begin
+ if ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
+ is_cycloneivgx = 1;
+ else
+ is_cycloneivgx = 0;
+
+ IS_FAMILY_CYCLONEIVGX = is_cycloneivgx;
+end
+endfunction //IS_FAMILY_CYCLONEIVGX
+
+function IS_FAMILY_CYCLONEIVE;
+ input[8*20:1] device;
+ reg is_cycloneive;
+begin
+ if ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
+ is_cycloneive = 1;
+ else
+ is_cycloneive = 0;
+
+ IS_FAMILY_CYCLONEIVE = is_cycloneive;
+end
+endfunction //IS_FAMILY_CYCLONEIVE
+
+function IS_FAMILY_STRATIXV;
+ input[8*20:1] device;
+ reg is_stratixv;
+begin
+ if ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)"))
+ is_stratixv = 1;
+ else
+ is_stratixv = 0;
+
+ IS_FAMILY_STRATIXV = is_stratixv;
+end
+endfunction //IS_FAMILY_STRATIXV
+
+function IS_FAMILY_ARRIAIIGZ;
+ input[8*20:1] device;
+ reg is_arriaiigz;
+begin
+ if ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
+ is_arriaiigz = 1;
+ else
+ is_arriaiigz = 0;
+
+ IS_FAMILY_ARRIAIIGZ = is_arriaiigz;
+end
+endfunction //IS_FAMILY_ARRIAIIGZ
+
+function IS_FAMILY_MAXV;
+ input[8*20:1] device;
+ reg is_maxv;
+begin
+ if ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
+ is_maxv = 1;
+ else
+ is_maxv = 0;
+
+ IS_FAMILY_MAXV = is_maxv;
+end
+endfunction //IS_FAMILY_MAXV
+
+function FEATURE_FAMILY_STRATIXGX;
+ input[8*20:1] device;
+ reg var_family_stratixgx;
+begin
+ if (IS_FAMILY_STRATIXGX(device) )
+ var_family_stratixgx = 1;
+ else
+ var_family_stratixgx = 0;
+
+ FEATURE_FAMILY_STRATIXGX = var_family_stratixgx;
+end
+endfunction //FEATURE_FAMILY_STRATIXGX
+
+function FEATURE_FAMILY_CYCLONE;
+ input[8*20:1] device;
+ reg var_family_cyclone;
+begin
+ if (IS_FAMILY_CYCLONE(device) )
+ var_family_cyclone = 1;
+ else
+ var_family_cyclone = 0;
+
+ FEATURE_FAMILY_CYCLONE = var_family_cyclone;
+end
+endfunction //FEATURE_FAMILY_CYCLONE
+
+function FEATURE_FAMILY_STRATIXIIGX;
+ input[8*20:1] device;
+ reg var_family_stratixiigx;
+begin
+ if (IS_FAMILY_STRATIXIIGX(device) || IS_FAMILY_ARRIAGX(device) )
+ var_family_stratixiigx = 1;
+ else
+ var_family_stratixiigx = 0;
+
+ FEATURE_FAMILY_STRATIXIIGX = var_family_stratixiigx;
+end
+endfunction //FEATURE_FAMILY_STRATIXIIGX
+
+function FEATURE_FAMILY_STRATIXIII;
+ input[8*20:1] device;
+ reg var_family_stratixiii;
+begin
+ if (IS_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_STRATIXIV(device) || IS_FAMILY_HARDCOPYIII(device) )
+ var_family_stratixiii = 1;
+ else
+ var_family_stratixiii = 0;
+
+ FEATURE_FAMILY_STRATIXIII = var_family_stratixiii;
+end
+endfunction //FEATURE_FAMILY_STRATIXIII
+
+function FEATURE_FAMILY_STRATIXV;
+ input[8*20:1] device;
+ reg var_family_stratixv;
+begin
+ if (IS_FAMILY_STRATIXV(device) )
+ var_family_stratixv = 1;
+ else
+ var_family_stratixv = 0;
+
+ FEATURE_FAMILY_STRATIXV = var_family_stratixv;
+end
+endfunction //FEATURE_FAMILY_STRATIXV
+
+function FEATURE_FAMILY_STRATIXII;
+ input[8*20:1] device;
+ reg var_family_stratixii;
+begin
+ if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) || FEATURE_FAMILY_STRATIXIII(device) )
+ var_family_stratixii = 1;
+ else
+ var_family_stratixii = 0;
+
+ FEATURE_FAMILY_STRATIXII = var_family_stratixii;
+end
+endfunction //FEATURE_FAMILY_STRATIXII
+
+function FEATURE_FAMILY_CYCLONEIVGX;
+ input[8*20:1] device;
+ reg var_family_cycloneivgx;
+begin
+ if (IS_FAMILY_CYCLONEIVGX(device) || IS_FAMILY_CYCLONEIVGX(device) )
+ var_family_cycloneivgx = 1;
+ else
+ var_family_cycloneivgx = 0;
+
+ FEATURE_FAMILY_CYCLONEIVGX = var_family_cycloneivgx;
+end
+endfunction //FEATURE_FAMILY_CYCLONEIVGX
+
+function FEATURE_FAMILY_CYCLONEIVE;
+ input[8*20:1] device;
+ reg var_family_cycloneive;
+begin
+ if (IS_FAMILY_CYCLONEIVE(device) )
+ var_family_cycloneive = 1;
+ else
+ var_family_cycloneive = 0;
+
+ FEATURE_FAMILY_CYCLONEIVE = var_family_cycloneive;
+end
+endfunction //FEATURE_FAMILY_CYCLONEIVE
+
+function FEATURE_FAMILY_CYCLONEIII;
+ input[8*20:1] device;
+ reg var_family_cycloneiii;
+begin
+ if (IS_FAMILY_CYCLONEIII(device) || IS_FAMILY_CYCLONEIIILS(device) || FEATURE_FAMILY_CYCLONEIVGX(device) || FEATURE_FAMILY_CYCLONEIVE(device) )
+ var_family_cycloneiii = 1;
+ else
+ var_family_cycloneiii = 0;
+
+ FEATURE_FAMILY_CYCLONEIII = var_family_cycloneiii;
+end
+endfunction //FEATURE_FAMILY_CYCLONEIII
+
+function FEATURE_FAMILY_STRATIX_HC;
+ input[8*20:1] device;
+ reg var_family_stratix_hc;
+begin
+ if ((device == "StratixHC") )
+ var_family_stratix_hc = 1;
+ else
+ var_family_stratix_hc = 0;
+
+ FEATURE_FAMILY_STRATIX_HC = var_family_stratix_hc;
+end
+endfunction //FEATURE_FAMILY_STRATIX_HC
+
+function FEATURE_FAMILY_STRATIX;
+ input[8*20:1] device;
+ reg var_family_stratix;
+begin
+ if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_MAXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
+ var_family_stratix = 1;
+ else
+ var_family_stratix = 0;
+
+ FEATURE_FAMILY_STRATIX = var_family_stratix;
+end
+endfunction //FEATURE_FAMILY_STRATIX
+
+function FEATURE_FAMILY_MAXII;
+ input[8*20:1] device;
+ reg var_family_maxii;
+begin
+ if (IS_FAMILY_MAXII(device) || FEATURE_FAMILY_MAXV(device) )
+ var_family_maxii = 1;
+ else
+ var_family_maxii = 0;
+
+ FEATURE_FAMILY_MAXII = var_family_maxii;
+end
+endfunction //FEATURE_FAMILY_MAXII
+
+function FEATURE_FAMILY_MAXV;
+ input[8*20:1] device;
+ reg var_family_maxv;
+begin
+ if (IS_FAMILY_MAXV(device) )
+ var_family_maxv = 1;
+ else
+ var_family_maxv = 0;
+
+ FEATURE_FAMILY_MAXV = var_family_maxv;
+end
+endfunction //FEATURE_FAMILY_MAXV
+
+function FEATURE_FAMILY_CYCLONEII;
+ input[8*20:1] device;
+ reg var_family_cycloneii;
+begin
+ if (IS_FAMILY_CYCLONEII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
+ var_family_cycloneii = 1;
+ else
+ var_family_cycloneii = 0;
+
+ FEATURE_FAMILY_CYCLONEII = var_family_cycloneii;
+end
+endfunction //FEATURE_FAMILY_CYCLONEII
+
+function FEATURE_FAMILY_STRATIXIV;
+ input[8*20:1] device;
+ reg var_family_stratixiv;
+begin
+ if (IS_FAMILY_STRATIXIV(device) || IS_FAMILY_ARRIAIIGX(device) || IS_FAMILY_HARDCOPYIV(device) || FEATURE_FAMILY_STRATIXV(device) || FEATURE_FAMILY_ARRIAIIGZ(device) )
+ var_family_stratixiv = 1;
+ else
+ var_family_stratixiv = 0;
+
+ FEATURE_FAMILY_STRATIXIV = var_family_stratixiv;
+end
+endfunction //FEATURE_FAMILY_STRATIXIV
+
+function FEATURE_FAMILY_ARRIAIIGZ;
+ input[8*20:1] device;
+ reg var_family_arriaiigz;
+begin
+ if (IS_FAMILY_ARRIAIIGZ(device) )
+ var_family_arriaiigz = 1;
+ else
+ var_family_arriaiigz = 0;
+
+ FEATURE_FAMILY_ARRIAIIGZ = var_family_arriaiigz;
+end
+endfunction //FEATURE_FAMILY_ARRIAIIGZ
+
+function FEATURE_FAMILY_ARRIAIIGX;
+ input[8*20:1] device;
+ reg var_family_arriaiigx;
+begin
+ if (IS_FAMILY_ARRIAIIGX(device) )
+ var_family_arriaiigx = 1;
+ else
+ var_family_arriaiigx = 0;
+
+ FEATURE_FAMILY_ARRIAIIGX = var_family_arriaiigx;
+end
+endfunction //FEATURE_FAMILY_ARRIAIIGX
+
+function FEATURE_FAMILY_BASE_STRATIXII;
+ input[8*20:1] device;
+ reg var_family_base_stratixii;
+begin
+ if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) )
+ var_family_base_stratixii = 1;
+ else
+ var_family_base_stratixii = 0;
+
+ FEATURE_FAMILY_BASE_STRATIXII = var_family_base_stratixii;
+end
+endfunction //FEATURE_FAMILY_BASE_STRATIXII
+
+function FEATURE_FAMILY_BASE_STRATIX;
+ input[8*20:1] device;
+ reg var_family_base_stratix;
+begin
+ if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) )
+ var_family_base_stratix = 1;
+ else
+ var_family_base_stratix = 0;
+
+ FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix;
+end
+endfunction //FEATURE_FAMILY_BASE_STRATIX
+
+function FEATURE_FAMILY_BASE_CYCLONEII;
+ input[8*20:1] device;
+ reg var_family_base_cycloneii;
+begin
+ if (IS_FAMILY_CYCLONEII(device) )
+ var_family_base_cycloneii = 1;
+ else
+ var_family_base_cycloneii = 0;
+
+ FEATURE_FAMILY_BASE_CYCLONEII = var_family_base_cycloneii;
+end
+endfunction //FEATURE_FAMILY_BASE_CYCLONEII
+
+function FEATURE_FAMILY_BASE_CYCLONE;
+ input[8*20:1] device;
+ reg var_family_base_cyclone;
+begin
+ if (IS_FAMILY_CYCLONE(device) )
+ var_family_base_cyclone = 1;
+ else
+ var_family_base_cyclone = 0;
+
+ FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone;
+end
+endfunction //FEATURE_FAMILY_BASE_CYCLONE
+
+function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM;
+ input[8*20:1] device;
+ reg var_family_has_stratixii_style_ram;
+begin
+ if (FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
+ var_family_has_stratixii_style_ram = 1;
+ else
+ var_family_has_stratixii_style_ram = 0;
+
+ FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM = var_family_has_stratixii_style_ram;
+end
+endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM
+
+function FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM;
+ input[8*20:1] device;
+ reg var_family_has_stratixiii_style_ram;
+begin
+ if (FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
+ var_family_has_stratixiii_style_ram = 1;
+ else
+ var_family_has_stratixiii_style_ram = 0;
+
+ FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM = var_family_has_stratixiii_style_ram;
+end
+endfunction //FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM
+
+function FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL;
+ input[8*20:1] device;
+ reg var_family_has_stratix_style_pll;
+begin
+ if (FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIXGX(device) )
+ var_family_has_stratix_style_pll = 1;
+ else
+ var_family_has_stratix_style_pll = 0;
+
+ FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL = var_family_has_stratix_style_pll;
+end
+endfunction //FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL
+
+function FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL;
+ input[8*20:1] device;
+ reg var_family_has_stratixii_style_pll;
+begin
+ if (FEATURE_FAMILY_STRATIXII(device) && ! FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEII(device) && ! FEATURE_FAMILY_CYCLONEIII(device) )
+ var_family_has_stratixii_style_pll = 1;
+ else
+ var_family_has_stratixii_style_pll = 0;
+
+ FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL = var_family_has_stratixii_style_pll;
+end
+endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL
+
+function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO;
+ input[8*20:1] device;
+ reg var_family_has_inverted_output_ddio;
+begin
+ if (FEATURE_FAMILY_CYCLONEII(device) )
+ var_family_has_inverted_output_ddio = 1;
+ else
+ var_family_has_inverted_output_ddio = 0;
+
+ FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO = var_family_has_inverted_output_ddio;
+end
+endfunction //FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO
+
+function IS_VALID_FAMILY;
+ input[8*20:1] device;
+ reg is_valid;
+begin
+ if (((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
+ || ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
+ || ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
+ || ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
+ || ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
+ || ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
+ || ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
+ || ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
+ || ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
+ || ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
+ || ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
+ || ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
+ || ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
+ || ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
+ || ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
+ || ((device == "BS") || (device == "bs"))
+ || ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
+ || ((device == "tgx_commercial_v1_1") || (device == "TGX_COMMERCIAL_V1_1"))
+ || ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
+ || ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
+ || ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
+ || ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
+ || ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
+ || ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
+ || ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)"))
+ || ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
+ || ((device == "arriaiigz_commercial_v1_1") || (device == "ARRIAIIGZ_COMMERCIAL_V1_1"))
+ || ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
+ || ((device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V") || (device == "ARRIA V") || (device == "arria v")))
+ is_valid = 1;
+ else
+ is_valid = 0;
+
+ IS_VALID_FAMILY = is_valid;
+end
+endfunction // IS_VALID_FAMILY
+
+
+endmodule // ALTERA_DEVICE_FAMILIES
+
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_dffpipe
+//
+// Description : Dual Clocks FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_dffpipe ( d, clock, aclr,
+ q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_delay = 1;
+ parameter lpm_width = 64;
+
+// LOCAL PARAMETER DECLARATION
+ parameter delay = (lpm_delay < 2) ? 1 : lpm_delay-1;
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] d;
+ input clock;
+ input aclr;
+
+// OUTPUT PORT DECLARATION
+ output [lpm_width-1:0] q;
+
+// INTERNAL REGISTERS DECLARATION
+ reg [(lpm_width*delay)-1:0] dffpipe;
+ reg [lpm_width-1:0] q;
+
+// LOCAL INTEGER DECLARATION
+
+// INITIAL CONSTRUCT BLOCK
+ initial
+ begin
+ dffpipe = {(lpm_width*delay){1'b0}};
+ q <= 0;
+ end
+
+// ALWAYS CONSTRUCT BLOCK
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr)
+ begin
+ dffpipe <= {(lpm_width*delay){1'b0}};
+ q <= 0;
+ end
+ else
+ begin
+ if ((lpm_delay > 0) && ($time > 0))
+ begin
+ if (lpm_delay > 1)
+ begin
+ {q, dffpipe} <= {dffpipe, d};
+ end
+ else
+ q <= d;
+ end
+ end
+ end // @(posedge aclr or posedge clock)
+
+ always @(d)
+ begin
+ if (lpm_delay == 0)
+ q <= d;
+ end // @(d)
+
+endmodule // dcfifo_dffpipe
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_fefifo
+//
+// Description : Dual Clock FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_fefifo ( usedw_in, wreq, rreq, clock, aclr,
+ empty, full);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_widthad = 1;
+ parameter lpm_numwords = 1;
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter lpm_mode = "READ";
+
+// INPUT PORT DECLARATION
+ input [lpm_widthad-1:0] usedw_in;
+ input wreq, rreq;
+ input clock;
+ input aclr;
+
+// OUTPUT PORT DECLARATION
+ output empty, full;
+
+// INTERNAL REGISTERS DECLARATION
+ reg [1:0] sm_empty;
+ reg lrreq;
+ reg i_empty, i_full;
+
+// LOCAL INTEGER DECLARATION
+ integer almostfull;
+
+// INITIAL CONSTRUCT BLOCK
+ initial
+ begin
+ if ((lpm_mode != "READ") && (lpm_mode != "WRITE"))
+ begin
+ $display ("Error! LPM_MODE must be READ or WRITE.");
+ $display ("Time: %0t Instance: %m", $time);
+ end
+ if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
+ begin
+ $display ("Error! UNDERFLOW_CHECKING must be ON or OFF.");
+ $display ("Time: %0t Instance: %m", $time);
+ end
+ if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
+ begin
+ $display ("Error! OVERFLOW_CHECKING must be ON or OFF.");
+ $display ("Time: %0t Instance: %m", $time);
+ end
+
+ sm_empty <= 2'b00;
+ i_empty <= 1'b1;
+ i_full <= 1'b0;
+
+ if (lpm_numwords >= 3)
+ almostfull <= lpm_numwords - 3;
+ else
+ almostfull <= 0;
+ end
+
+// ALWAYS CONSTRUCT BLOCK
+ always @(posedge aclr)
+ begin
+ sm_empty <= 2'b00;
+ i_empty <= 1'b1;
+ i_full <= 1'b0;
+ lrreq <= 1'b0;
+ end // @(posedge aclr)
+
+ always @(posedge clock)
+ begin
+ if (underflow_checking == "OFF")
+ lrreq <= rreq;
+ else
+ lrreq <= rreq && ~i_empty;
+
+ if (~aclr && $time > 0)
+ begin
+ if (lpm_mode == "READ")
+ begin
+ casex (sm_empty)
+ // state_empty
+ 2'b00:
+ if (usedw_in != 0)
+ sm_empty <= 2'b01;
+ // state_non_empty
+ 2'b01:
+ if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq)))
+ sm_empty <= 2'b10;
+ // state_emptywait
+ 2'b10:
+ if (usedw_in > 1)
+ sm_empty <= 2'b01;
+ else
+ sm_empty <= 2'b00;
+ default:
+ $display ("Error! Invalid sm_empty state in read mode.");
+ endcase
+ end // if (lpm_mode == "READ")
+ else if (lpm_mode == "WRITE")
+ begin
+ casex (sm_empty)
+ // state_empty
+ 2'b00:
+ if (wreq)
+ sm_empty <= 2'b01;
+ // state_one
+ 2'b01:
+ if (!wreq)
+ sm_empty <= 2'b11;
+ // state_non_empty
+ 2'b11:
+ if (wreq)
+ sm_empty <= 2'b01;
+ else if (usedw_in == 0)
+ sm_empty <= 2'b00;
+ default:
+ $display ("Error! Invalid sm_empty state in write mode.");
+ endcase
+ end // if (lpm_mode == "WRITE")
+
+ if (~aclr && (usedw_in >= almostfull) && ($time > 0))
+ i_full <= 1'b1;
+ else
+ i_full <= 1'b0;
+ end // if (~aclr && $time > 0)
+ end // @(posedge clock)
+
+ always @(sm_empty)
+ begin
+ i_empty <= !sm_empty[0];
+ end
+ // @(sm_empty)
+
+// CONTINOUS ASSIGNMENT
+ assign empty = i_empty;
+ assign full = i_full;
+endmodule // dcfifo_fefifo
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_async
+//
+// Description : Asynchronous Dual Clocks FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_async (data, rdclk, wrclk, aclr, rdreq, wrreq,
+ rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_width = 1;
+ parameter lpm_widthu = 1;
+ parameter lpm_numwords = 2;
+ parameter delay_rdusedw = 1;
+ parameter delay_wrusedw = 1;
+ parameter rdsync_delaypipe = 0;
+ parameter wrsync_delaypipe = 0;
+ parameter intended_device_family = "Stratix";
+ parameter lpm_showahead = "OFF";
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter use_eab = "ON";
+ parameter add_ram_output_register = "OFF";
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] data;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ input wrreq;
+ input rdreq;
+
+// OUTPUT PORT DECLARATION
+ output rdfull;
+ output wrfull;
+ output rdempty;
+ output wrempty;
+ output [lpm_widthu-1:0] rdusedw;
+ output [lpm_widthu-1:0] wrusedw;
+ output [lpm_width-1:0] q;
+
+// INTERNAL REGISTERS DECLARATION
+ reg [lpm_width-1:0] mem_data [(1< 0))
+ begin
+ i_data_tmp <= data;
+ i_wrptr_tmp <= i_wrptr;
+ i_wren_tmp <= i_wren;
+
+ if (i_wren)
+ begin
+ if (~aclr && ((i_wrptr < (1< 0))
+ begin
+ if (i_wren_tmp)
+ begin
+ mem_data[i_wrptr_tmp] <= i_data_tmp;
+ data_ready[i_wrptr_tmp] <= 1'b0;
+ end
+
+ if ((lpm_showahead == "ON") &&
+ (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1))))
+ i_showahead_flag3 <= 1'b1;
+ end
+ end // @(negedge wrclk)
+
+ always @(posedge rdclk)
+ begin
+
+ if (rdclk && ($time > 0))
+ begin
+ if ((lpm_showahead == "ON") && (add_ram_output_register == "ON") &&
+ ((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)))
+ begin
+ for (k = 0; k < (1< 0))
+ begin
+ if (~aclr && ((i_rdptr < (1< (1 << lpm_widthu))
+ $display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU.");
+ if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF"))
+ $display ("Error! add_ram_output_register must be ON or OFF.");
+ if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
+ $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
+
+ for (i = 0; i < (1 << lpm_widthu); i = i + 1)
+ mem_data[i] <= 0;
+ i_data_tmp <= 0;
+ i_rdptr <= 0;
+ i_wrptr <= 0;
+ i_wrptr_tmp <= 0;
+ i_wren_tmp <= 0;
+
+ i_rdusedw <= 0;
+ i_wrusedw <= 0;
+ i_q_tmp <= 0;
+
+ if (lpm_numwords == (1 << lpm_widthu))
+ cnt_mod <= 1 << (lpm_widthu + 1);
+ else
+ cnt_mod <= 1 << lpm_widthu;
+ end
+
+// COMPONENT INSTANTIATIONS
+ dcfifo_dffpipe RDPTR_D (
+ .d (i_rdptr),
+ .clock (wrclk),
+ .aclr (aclr),
+ .q (w_rdptr_s));
+ dcfifo_dffpipe WRPTR_D (
+ .d (i_wrptr),
+ .clock (wrclk),
+ .aclr (aclr),
+ .q (w_wrptr_r));
+ dcfifo_dffpipe WRPTR_E (
+ .d (w_wrptr_r),
+ .clock (rdclk),
+ .aclr (aclr),
+ .q (w_wrptr_s));
+ defparam
+ RDPTR_D.lpm_delay = 1,
+ RDPTR_D.lpm_width = lpm_widthu + 1,
+ WRPTR_D.lpm_delay = 1,
+ WRPTR_D.lpm_width = lpm_widthu + 1,
+ WRPTR_E.lpm_delay = 1,
+ WRPTR_E.lpm_width = lpm_widthu + 1;
+
+// ALWAYS CONSTRUCT BLOCK
+ always @(posedge aclr)
+ begin
+ i_rdptr <= 0;
+ i_wrptr <= 0;
+ if (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)) ||
+ ((add_ram_output_register == "ON") && (use_eab == "OFF")))
+ if (lpm_showahead == "ON")
+ begin
+ if ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1))
+ i_q_tmp <= {lpm_width{1'bX}};
+ else
+ i_q_tmp <= mem_data[0];
+ end
+ else
+ i_q_tmp <= 0;
+ end // @(posedge aclr)
+
+ always @(posedge wrclk)
+ begin
+ if (aclr && (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)) ||
+ ((add_ram_output_register == "ON") && (use_eab == "OFF"))))
+ begin
+ i_data_tmp <= 0;
+ i_wrptr_tmp <= 0;
+ i_wren_tmp <= 0;
+ end
+ else if (wrclk && ($time > 0))
+ begin
+ i_data_tmp <= data;
+ i_wrptr_tmp <= i_wrptr[lpm_widthu-1:0];
+ i_wren_tmp <= i_wren;
+
+ if (i_wren)
+ begin
+ if (~aclr && (i_wrptr < cnt_mod - 1))
+ i_wrptr <= i_wrptr + 1;
+ else
+ i_wrptr <= 0;
+
+ if (use_eab == "OFF")
+ begin
+ mem_data[i_wrptr[lpm_widthu-1:0]] <= data;
+
+ if (lpm_showahead == "ON")
+ i_showahead_flag2 <= 1'b1;
+ end
+ end
+ end
+ end // @(posedge wrclk)
+
+ always @(negedge wrclk)
+ begin
+ if ((~wrclk && (use_eab == "ON")) && ($time > 0))
+ begin
+ if (i_wren_tmp)
+ begin
+ mem_data[i_wrptr_tmp] <= i_data_tmp;
+ end
+
+ if ((lpm_showahead == "ON") &&
+ (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1))))
+ i_showahead_flag2 <= 1'b1;
+ end
+ end // @(negedge wrclk)
+
+ always @(posedge rdclk)
+ begin
+ if (aclr && (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)) ||
+ ((add_ram_output_register == "ON") && (use_eab == "OFF"))))
+ begin
+ if (lpm_showahead == "ON")
+ begin
+ if ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1))
+ i_q_tmp <= {lpm_width{1'bX}};
+ else
+ i_q_tmp <= mem_data[0];
+ end
+ else
+ i_q_tmp <= 0;
+ end
+ else if (rdclk && i_rden && ($time > 0))
+ begin
+ if (~aclr && (i_rdptr < cnt_mod - 1))
+ i_rdptr <= i_rdptr + 1;
+ else
+ i_rdptr <= 0;
+
+ if ((lpm_showahead == "ON") && (!((use_eab == "ON") &&
+ ((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)))))
+ i_showahead_flag2 <= 1'b1;
+ else
+ i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];
+ end
+ end // @(rdclk)
+
+ always @(posedge i_showahead_flag)
+ begin
+ i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];
+ i_showahead_flag2 <= 1'b0;
+ end // @(posedge i_showahead_flag)
+
+ always @(i_showahead_flag2)
+ begin
+ i_showahead_flag <= i_showahead_flag2;
+ end // @(i_showahead_flag2)
+
+ // Usedw, Empty, Full
+ always @(i_rdptr or w_wrptr_s or cnt_mod)
+ begin
+ if (w_wrptr_s >= i_rdptr)
+ i_rdusedw <= w_wrptr_s - i_rdptr;
+ else
+ i_rdusedw <= w_wrptr_s + cnt_mod - i_rdptr;
+ end // @(i_rdptr or w_wrptr_s)
+
+ always @(i_wrptr or w_rdptr_s or cnt_mod)
+ begin
+ if (i_wrptr >= w_rdptr_s)
+ i_wrusedw <= i_wrptr - w_rdptr_s;
+ else
+ i_wrusedw <= i_wrptr + cnt_mod - w_rdptr_s;
+ end // @(i_wrptr or w_rdptr_s)
+
+
+// CONTINOUS ASSIGNMENT
+ assign i_rden = (underflow_checking == "OFF") ? rdreq : (rdreq && !i_rdempty);
+ assign i_wren = (overflow_checking == "OFF") ? wrreq : (wrreq && !i_wrfull);
+ assign i_rdempty = (i_rdusedw == 0) ? 1'b1 : 1'b0;
+ assign i_wrempty = (i_wrusedw == 0) ? 1'b1 : 1'b0;
+ assign i_rdfull = (((lpm_numwords == (1 << lpm_widthu)) && i_rdusedw[lpm_widthu]) ||
+ ((lpm_numwords < (1 << lpm_widthu)) && (i_rdusedw == lpm_numwords)))
+ ? 1'b1 : 1'b0;
+ assign i_wrfull = (((lpm_numwords == (1 << lpm_widthu)) && i_wrusedw[lpm_widthu]) ||
+ ((lpm_numwords < (1 << lpm_widthu)) && (i_wrusedw == lpm_numwords)))
+ ? 1'b1 : 1'b0;
+ assign rdempty = i_rdempty;
+ assign wrempty = i_wrempty;
+ assign rdfull = i_rdfull;
+ assign wrfull = i_wrfull;
+ assign wrusedw = i_wrusedw[lpm_widthu-1:0];
+ assign rdusedw = i_rdusedw[lpm_widthu-1:0];
+ assign q = i_q_tmp;
+
+endmodule // dcfifo_sync
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_low_latency
+//
+// Description : Dual Clocks FIFO with lowest latency. This fifo implements
+// the fifo behavior for Stratix II, Cyclone II, Stratix III,
+// Cyclone III and Stratix showahead area mode (LPM_SHOWAHEAD=
+// ON, ADD_RAM_OUTPUT_REGISTER=OFF)
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_low_latency (data, rdclk, wrclk, aclr, rdreq, wrreq,
+ rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_width = 1;
+ parameter lpm_widthu = 1;
+ parameter lpm_width_r = lpm_width;
+ parameter lpm_widthu_r = lpm_widthu;
+ parameter lpm_numwords = 2;
+ parameter delay_rdusedw = 2;
+ parameter delay_wrusedw = 2;
+ parameter rdsync_delaypipe = 0;
+ parameter wrsync_delaypipe = 0;
+ parameter intended_device_family = "Stratix";
+ parameter lpm_showahead = "OFF";
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter add_usedw_msb_bit = "OFF";
+ parameter write_aclr_synch = "OFF";
+ parameter use_eab = "ON";
+ parameter clocks_are_synchronized = "FALSE";
+ parameter add_ram_output_register = "OFF";
+ parameter lpm_hint = "USE_EAB=ON";
+
+// LOCAL PARAMETER DECLARATION
+ parameter WIDTH_RATIO = (lpm_width > lpm_width_r) ? lpm_width / lpm_width_r :
+ lpm_width_r / lpm_width;
+ parameter FIFO_DEPTH = (add_usedw_msb_bit == "OFF") ? lpm_widthu_r : lpm_widthu_r -1;
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] data;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ input rdreq;
+ input wrreq;
+
+// OUTPUT PORT DECLARATION
+ output rdfull;
+ output wrfull;
+ output rdempty;
+ output wrempty;
+ output [lpm_widthu_r-1:0] rdusedw;
+ output [lpm_widthu-1:0] wrusedw;
+ output [lpm_width_r-1:0] q;
+
+// INTERNAL REGISTERS DECLARATION
+ reg [lpm_width_r-1:0] mem_data [(1< (1 << lpm_widthu))
+ $display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU.");
+ if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
+ $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
+
+ for (i = 0; i < (1 << lpm_widthu_r) + WIDTH_RATIO; i = i + 1)
+ mem_data[i] <= {lpm_width_r{1'b0}};
+ i_data_tmp <= 0;
+ i_temp_reg <= 0;
+ i_wren_tmp <= 0;
+ i_rdptr_g <= 0;
+ i_rdptr_g1p <= 1;
+ i_wrptr_g <= 0;
+ i_wrptr_g_tmp <= 0;
+ i_wrptr_g1 <= 1;
+ i_delayed_wrptr_g <= 0;
+ i_rdempty <= 1;
+ i_wrempty_area <= 1;
+ i_wrempty_speed <= 1;
+ i_rdempty_rreg <= 1;
+ i_rdfull_speed <= 0;
+ i_rdfull_area <= 0;
+ i_wrfull <= 0;
+ i_wrfull_wreg <= 0;
+ sync_aclr_pre <= 1'b1;
+ sync_aclr <= 1'b1;
+ i_q <= {lpm_width_r{1'b0}};
+ is_underflow <= 0;
+ is_overflow <= 0;
+ no_warn <= 0;
+ i_mem_address <= 0;
+ i_first_bit_position <= 0;
+
+ i_maximize_speed = str_to_int(eva.GET_PARAMETER_VALUE(lpm_hint, "MAXIMIZE_SPEED"));
+
+ if (feature_family_has_stratixiii_style_ram == 1)
+ begin
+ use_wrempty_speed <= 1;
+ use_rdfull_speed <= 1;
+ end
+ else if (feature_family_has_stratixii_style_ram == 1)
+ begin
+ use_wrempty_speed <= ((i_maximize_speed > 5) || (wrsync_delaypipe >= 2)) ? 1 : 0;
+ use_rdfull_speed <= ((i_maximize_speed > 5) || (rdsync_delaypipe >= 2)) ? 1 : 0;
+ end
+ else
+ begin
+ use_wrempty_speed <= 0;
+ use_rdfull_speed <= 0;
+ end
+
+ if (feature_family_has_stratixii_style_ram == 1)
+ begin
+ if (add_usedw_msb_bit == "OFF")
+ begin
+ if (lpm_width_r > lpm_width)
+ begin
+ cnt_mod <= (1 << lpm_widthu) + WIDTH_RATIO;
+ cnt_mod_r <= (1 << lpm_widthu_r) + 1;
+ end
+ else
+ begin
+ cnt_mod <= (1 << lpm_widthu) + 1;
+ cnt_mod_r <= (1 << lpm_widthu_r) + WIDTH_RATIO;
+ end
+ end
+ else
+ begin
+ if (lpm_width_r > lpm_width)
+ begin
+ cnt_mod <= (1 << (lpm_widthu-1)) + WIDTH_RATIO;
+ cnt_mod_r <= (1 << (lpm_widthu_r-1)) + 1;
+ end
+ else
+ begin
+ cnt_mod <= (1 << (lpm_widthu-1)) + 1;
+ cnt_mod_r <= (1 << (lpm_widthu_r-1)) + WIDTH_RATIO;
+ end
+ end
+ end
+ else
+ begin
+ cnt_mod <= 1 << lpm_widthu;
+ cnt_mod_r <= 1 << lpm_widthu_r;
+ end
+
+ if ((lpm_showahead == "OFF") &&
+ ((feature_family_stratixii == 1) ||
+ ((feature_family_cycloneii == 1))))
+ i_q_is_registered = 1'b1;
+ else
+ i_q_is_registered = 1'b0;
+ end
+
+// COMPONENT INSTANTIATIONS
+ dcfifo_dffpipe DP_WS_DGRP (
+ .d (i_rdptr_g),
+ .clock (wrclk),
+ .aclr (aclr),
+ .q (i_ws_dgrp));
+ defparam
+ DP_WS_DGRP.lpm_delay = wrsync_delaypipe,
+ DP_WS_DGRP.lpm_width = lpm_widthu_r + 1;
+
+ dcfifo_dffpipe DP_RS_DGWP (
+ .d (i_delayed_wrptr_g),
+ .clock (rdclk),
+ .aclr (aclr),
+ .q (i_rs_dgwp));
+ defparam
+ DP_RS_DGWP.lpm_delay = rdsync_delaypipe,
+ DP_RS_DGWP.lpm_width = lpm_widthu + 1;
+
+ dcfifo_dffpipe DP_RDUSEDW (
+ .d (i_rdusedw_tmp),
+ .clock (rdclk),
+ .aclr (aclr),
+ .q (i_rdusedw));
+ dcfifo_dffpipe DP_WRUSEDW (
+ .d (i_wrusedw_tmp),
+ .clock (wrclk),
+ .aclr (aclr),
+ .q (i_wrusedw));
+ defparam
+ DP_RDUSEDW.lpm_delay = (delay_rdusedw > 2) ? 2 : delay_rdusedw,
+ DP_RDUSEDW.lpm_width = lpm_widthu_r + 1,
+ DP_WRUSEDW.lpm_delay = (delay_wrusedw > 2) ? 2 : delay_wrusedw,
+ DP_WRUSEDW.lpm_width = lpm_widthu + 1;
+
+// ALWAYS CONSTRUCT BLOCK
+ always @(posedge aclr)
+ begin
+ i_data_tmp <= 0;
+ i_wren_tmp <= 0;
+ i_rdptr_g <= 0;
+ i_rdptr_g1p <= 1;
+ i_wrptr_g <= 0;
+ i_wrptr_g_tmp <= 0;
+ i_wrptr_g1 <= 1;
+ i_delayed_wrptr_g <= 0;
+ i_rdempty <= 1;
+ i_wrempty_area <= 1;
+ i_wrempty_speed <= 1;
+ i_rdempty_rreg <= 1;
+ i_rdfull_speed <= 0;
+ i_rdfull_area <= 0;
+ i_wrfull <= 0;
+ i_wrfull_wreg <= 0;
+ is_underflow <= 0;
+ is_overflow <= 0;
+ no_warn <= 0;
+ i_mem_address <= 0;
+ i_first_bit_position <= 0;
+
+ if(i_q_is_registered)
+ i_q <= 0;
+ else if ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1))
+ i_q <= {lpm_width_r{1'bx}};
+
+ end // @(posedge aclr)
+
+ always @(posedge wrclk or posedge aclr)
+ begin
+ if ($time > 0)
+ begin
+ if (aclr)
+ begin
+ sync_aclr <= 1'b1;
+ sync_aclr_pre <= 1'b1;
+ end
+ else
+ begin
+ sync_aclr <= sync_aclr_pre;
+ sync_aclr_pre <= 1'b0;
+ end
+ end
+ end
+
+ always @(posedge wrclk)
+ begin
+ i_data_tmp <= data;
+ i_wrptr_g_tmp <= i_wrptr_g;
+ i_wren_tmp <= i_wren;
+
+ if (~write_aclr && ($time > 0))
+ begin
+ if (i_wren)
+ begin
+ if (i_wrfull && (overflow_checking == "OFF"))
+ begin
+ if (((feature_family_has_stratixii_style_ram == 1) &&
+ ((use_eab == "ON") || ((use_eab == "OFF") && (lpm_width != lpm_width_r) && (lpm_width_r != 0)) ||
+ ((lpm_numwords < 16) && (clocks_are_synchronized == "FALSE")))) ||
+ ((feature_family_stratix == 1) && (use_eab == "ON") &&
+ (((lpm_showahead == "ON") && (add_ram_output_register == "OFF")) ||
+ (clocks_are_synchronized == "FALSE_LOW_LATENCY"))))
+ begin
+ if (no_warn == 1'b0)
+ begin
+ $display("Warning : Overflow occurred! Fifo output is unknown until the next reset is asserted.");
+ $display("Time: %0t Instance: %m", $time);
+ no_warn <= 1'b1;
+ end
+ is_overflow <= 1'b1;
+ end
+ end
+ else
+ begin
+ if (i_wrptr_g1 < cnt_mod - 1)
+ i_wrptr_g1 <= i_wrptr_g1 + 1;
+ else
+ i_wrptr_g1 <= 0;
+
+ i_wrptr_g <= i_wrptr_g1;
+
+ if (lpm_width > lpm_width_r)
+ begin
+ for (i = 0; i < WIDTH_RATIO; i = i+1)
+ mem_data[i_wrptr_g*WIDTH_RATIO+i] <= data >> (lpm_width_r*i);
+ end
+ else if (lpm_width < lpm_width_r)
+ begin
+ i_mem_address <= i_wrptr_g1 /WIDTH_RATIO;
+ i_first_bit_position <= (i_wrptr_g1 % WIDTH_RATIO) *lpm_width;
+ for(i = 0; i < lpm_width; i = i+1)
+ mem_data[i_mem_address][i_first_bit_position + i] <= data[i];
+ end
+ else
+ mem_data[i_wrptr_g] <= data;
+ end
+ end
+ i_delayed_wrptr_g <= i_wrptr_g;
+ end
+ end // @(wrclk)
+
+ always @(posedge rdclk)
+ begin
+ if(~aclr)
+ begin
+ if (i_rden && ($time > 0))
+ begin
+ if (i_rdempty && (underflow_checking == "OFF"))
+ begin
+ if (((feature_family_has_stratixii_style_ram == 1) &&
+ ((use_eab == "ON") || ((use_eab == "OFF") && (lpm_width != lpm_width_r) && (lpm_width_r != 0)) ||
+ ((lpm_numwords < 16) && (clocks_are_synchronized == "FALSE")))) ||
+ ((feature_family_stratix == 1) && (use_eab == "ON") &&
+ (((lpm_showahead == "ON") && (add_ram_output_register == "OFF")) ||
+ (clocks_are_synchronized == "FALSE_LOW_LATENCY"))))
+ begin
+ if (no_warn == 1'b0)
+ begin
+ $display("Warning : Underflow occurred! Fifo output is unknown until the next reset is asserted.");
+ $display("Time: %0t Instance: %m", $time);
+ no_warn <= 1'b1;
+ end
+ is_underflow <= 1'b1;
+ end
+ end
+ else
+ begin
+ if (i_rdptr_g1p < cnt_mod_r - 1)
+ i_rdptr_g1p <= i_rdptr_g1p + 1;
+ else
+ i_rdptr_g1p <= 0;
+
+ i_rdptr_g <= i_rdptr_g1p;
+ end
+ end
+ end
+ end
+
+ always @(posedge rdclk)
+ begin
+ if (is_underflow || is_overflow)
+ i_q <= {lpm_width_r{1'bx}};
+ else
+ begin
+ if ((! i_q_is_registered) && ($time > 0))
+ begin
+ if (aclr && ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)))
+ i_q <= {lpm_width_r{1'bx}};
+ else
+ begin
+ if (i_rdempty == 1'b1)
+ i_q <= mem_data[i_rdptr_g];
+ else if (i_rden)
+ i_q <= mem_data[i_rdptr_g1p];
+ end
+ end
+ else if (~aclr && i_rden && ($time > 0))
+ i_q <= mem_data[i_rdptr_g];
+ end
+ end
+
+ // Usedw, Empty, Full
+ always @(i_wrptr_g or i_ws_dgrp or cnt_mod)
+ begin
+ if (i_wrptr_g < (i_ws_dgrp*lpm_width_r/lpm_width))
+ i_wrusedw_tmp <= cnt_mod + i_wrptr_g - i_ws_dgrp*lpm_width_r/lpm_width;
+ else
+ i_wrusedw_tmp <= i_wrptr_g - i_ws_dgrp*lpm_width_r/lpm_width;
+
+ if (lpm_width > lpm_width_r)
+ begin
+ if (i_wrptr_g == (i_ws_dgrp/WIDTH_RATIO))
+ i_wrempty_speed <= 1;
+ else
+ i_wrempty_speed <= 0;
+ end
+ else
+ begin
+ if ((i_wrptr_g/WIDTH_RATIO) == i_ws_dgrp)
+ i_wrempty_speed <= 1;
+ else
+ i_wrempty_speed <= 0;
+ end
+ end // @(i_wrptr_g or i_ws_dgrp)
+
+ always @(i_rdptr_g or i_rs_dgwp or cnt_mod)
+ begin
+ if ((i_rs_dgwp*lpm_width/lpm_width_r) < i_rdptr_g)
+ i_rdusedw_tmp <= (cnt_mod + i_rs_dgwp)*lpm_width/lpm_width_r - i_rdptr_g;
+ else
+ i_rdusedw_tmp <= i_rs_dgwp*lpm_width/lpm_width_r - i_rdptr_g;
+
+ if (lpm_width < lpm_width_r)
+ begin
+ if ((i_rdptr_g*lpm_width_r/lpm_width) == (i_rs_dgwp + WIDTH_RATIO) %cnt_mod)
+ i_rdfull_speed <= 1;
+ else
+ i_rdfull_speed <= 0;
+ end
+ else
+ begin
+ if (i_rdptr_g == ((i_rs_dgwp +1) % cnt_mod)*lpm_width/lpm_width_r)
+ i_rdfull_speed <= 1;
+ else
+ i_rdfull_speed <= 0;
+ end
+ end // @(i_wrptr_g or i_rs_dgwp)
+
+ always @(i_wrptr_g1 or i_ws_dgrp or cnt_mod)
+ begin
+ if (lpm_width < lpm_width_r)
+ begin
+ if ((i_wrptr_g1 + WIDTH_RATIO -1) % cnt_mod == (i_ws_dgrp*lpm_width_r/lpm_width))
+ i_wrfull <= 1;
+ else
+ i_wrfull <= 0;
+ end
+ else
+ begin
+ if (i_wrptr_g1 == (i_ws_dgrp*lpm_width_r/lpm_width))
+ i_wrfull <= 1;
+ else
+ i_wrfull <= 0;
+ end
+ end // @(i_wrptr_g1 or i_ws_dgrp)
+
+ always @(i_rdptr_g or i_rs_dgwp)
+ begin
+ if (lpm_width > lpm_width_r)
+ begin
+ if ((i_rdptr_g/WIDTH_RATIO) == i_rs_dgwp)
+ i_rdempty <= 1;
+ else
+ i_rdempty <= 0;
+ end
+ else
+ begin
+ if (i_rdptr_g == i_rs_dgwp/WIDTH_RATIO)
+ i_rdempty <= 1;
+ else
+ i_rdempty <= 0;
+ end
+ end // @(i_rdptr_g or i_rs_dgwp)
+
+ always @(posedge rdclk)
+ begin
+ i_rdfull_area <= i_wrfull_wreg;
+ i_rdempty_rreg <= i_rdempty;
+ end // @(posedge rdclk)
+
+ always @(posedge wrclk)
+ begin
+ i_wrempty_area <= i_rdempty_rreg;
+
+ if ((~aclr) && (write_aclr_synch == "ON") && ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)))
+ i_wrfull_wreg <= (i_wrfull | write_aclr);
+ else
+ i_wrfull_wreg <= i_wrfull;
+ end // @(posedge wrclk)
+
+// CONTINOUS ASSIGNMENT
+ assign i_rden = (underflow_checking == "OFF") ? rdreq : (rdreq && !i_rdempty);
+ assign i_wren = (((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)) &&
+ (write_aclr_synch == "ON")) ?
+ ((overflow_checking == "OFF") ? wrreq && (!sync_aclr)
+ : (wrreq && !(i_wrfull | sync_aclr))) :
+ (overflow_checking == "OFF") ? wrreq : (wrreq && !i_wrfull);
+ assign rdempty = (is_underflow || is_overflow) ? 1'bx : i_rdempty;
+ assign wrempty = (is_underflow || is_overflow) ? 1'bx :
+ (use_wrempty_speed) ? i_wrempty_speed : i_wrempty_area;
+ assign rdfull = (is_underflow || is_overflow) ? 1'bx :
+ (use_rdfull_speed) ? i_rdfull_speed : i_rdfull_area;
+ assign wrfull = (is_underflow || is_overflow) ? 1'bx :
+ (((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)) &&
+ (write_aclr_synch == "ON")) ? (i_wrfull | write_aclr) : i_wrfull;
+ assign wrusedw = (is_underflow || is_overflow) ? {lpm_widthu{1'bx}} :
+ i_wrusedw[lpm_widthu-1:0];
+ assign rdusedw = (is_underflow || is_overflow) ? {lpm_widthu_r{1'bx}} :
+ i_rdusedw[lpm_widthu_r-1:0];
+ assign q = (is_underflow || is_overflow) ? {lpm_width_r{1'bx}} : i_q;
+ assign write_aclr = (((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)) &&
+ (write_aclr_synch == "ON")) ? sync_aclr : aclr;
+
+endmodule // dcfifo_low_latency
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_mixed_widths
+//
+// Description : Mixed widths Dual Clocks FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_mixed_widths ( data, rdclk, wrclk, aclr, rdreq, wrreq,
+ rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_width = 1;
+ parameter lpm_widthu = 1;
+ parameter lpm_width_r = lpm_width;
+ parameter lpm_widthu_r = lpm_widthu;
+ parameter lpm_numwords = 2;
+ parameter delay_rdusedw = 1;
+ parameter delay_wrusedw = 1;
+ parameter rdsync_delaypipe = 0;
+ parameter wrsync_delaypipe = 0;
+ parameter intended_device_family = "Stratix";
+ parameter lpm_showahead = "OFF";
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter clocks_are_synchronized = "FALSE";
+ parameter use_eab = "ON";
+ parameter add_ram_output_register = "OFF";
+ parameter lpm_hint = "USE_EAB=ON";
+ parameter lpm_type = "dcfifo_mixed_widths";
+ parameter add_usedw_msb_bit = "OFF";
+ parameter write_aclr_synch = "OFF";
+
+// LOCAL_PARAMETERS_BEGIN
+
+ parameter add_width = 1;
+ parameter ram_block_type = "AUTO";
+
+ parameter FAMILY_HAS_STRATIXII_STYLE_RAM = (((((intended_device_family == "Stratix II") || (intended_device_family == "STRATIX II") || (intended_device_family == "stratix ii") || (intended_device_family == "StratixII") || (intended_device_family == "STRATIXII") || (intended_device_family == "stratixii") || (intended_device_family == "Armstrong") || (intended_device_family == "ARMSTRONG") || (intended_device_family == "armstrong"))
+ || ((intended_device_family == "HardCopy II") || (intended_device_family == "HARDCOPY II") || (intended_device_family == "hardcopy ii") || (intended_device_family == "HardCopyII") || (intended_device_family == "HARDCOPYII") || (intended_device_family == "hardcopyii") || (intended_device_family == "Fusion") || (intended_device_family == "FUSION") || (intended_device_family == "fusion"))
+ || (((intended_device_family == "Stratix II GX") || (intended_device_family == "STRATIX II GX") || (intended_device_family == "stratix ii gx") || (intended_device_family == "StratixIIGX") || (intended_device_family == "STRATIXIIGX") || (intended_device_family == "stratixiigx"))
+ || ((intended_device_family == "Arria GX") || (intended_device_family == "ARRIA GX") || (intended_device_family == "arria gx") || (intended_device_family == "ArriaGX") || (intended_device_family == "ARRIAGX") || (intended_device_family == "arriagx") || (intended_device_family == "Stratix II GX Lite") || (intended_device_family == "STRATIX II GX LITE") || (intended_device_family == "stratix ii gx lite") || (intended_device_family == "StratixIIGXLite") || (intended_device_family == "STRATIXIIGXLITE") || (intended_device_family == "stratixiigxlite"))
+ ) || (((intended_device_family == "Stratix III") || (intended_device_family == "STRATIX III") || (intended_device_family == "stratix iii") || (intended_device_family == "StratixIII") || (intended_device_family == "STRATIXIII") || (intended_device_family == "stratixiii") || (intended_device_family == "Titan") || (intended_device_family == "TITAN") || (intended_device_family == "titan") || (intended_device_family == "SIII") || (intended_device_family == "siii"))
+ || (((intended_device_family == "Stratix IV") || (intended_device_family == "STRATIX IV") || (intended_device_family == "stratix iv") || (intended_device_family == "TGX") || (intended_device_family == "tgx") || (intended_device_family == "StratixIV") || (intended_device_family == "STRATIXIV") || (intended_device_family == "stratixiv") || (intended_device_family == "Stratix IV (GT)") || (intended_device_family == "STRATIX IV (GT)") || (intended_device_family == "stratix iv (gt)") || (intended_device_family == "Stratix IV (GX)") || (intended_device_family == "STRATIX IV (GX)") || (intended_device_family == "stratix iv (gx)") || (intended_device_family == "Stratix IV (E)") || (intended_device_family == "STRATIX IV (E)") || (intended_device_family == "stratix iv (e)") || (intended_device_family == "StratixIV(GT)") || (intended_device_family == "STRATIXIV(GT)") || (intended_device_family == "stratixiv(gt)") || (intended_device_family == "StratixIV(GX)") || (intended_device_family == "STRATIXIV(GX)") || (intended_device_family == "stratixiv(gx)") || (intended_device_family == "StratixIV(E)") || (intended_device_family == "STRATIXIV(E)") || (intended_device_family == "stratixiv(e)") || (intended_device_family == "StratixIIIGX") || (intended_device_family == "STRATIXIIIGX") || (intended_device_family == "stratixiiigx") || (intended_device_family == "Stratix IV (GT/GX/E)") || (intended_device_family == "STRATIX IV (GT/GX/E)") || (intended_device_family == "stratix iv (gt/gx/e)") || (intended_device_family == "Stratix IV (GT/E/GX)") || (intended_device_family == "STRATIX IV (GT/E/GX)") || (intended_device_family == "stratix iv (gt/e/gx)") || (intended_device_family == "Stratix IV (E/GT/GX)") || (intended_device_family == "STRATIX IV (E/GT/GX)") || (intended_device_family == "stratix iv (e/gt/gx)") || (intended_device_family == "Stratix IV (E/GX/GT)") || (intended_device_family == "STRATIX IV (E/GX/GT)") || (intended_device_family == "stratix iv (e/gx/gt)") || (intended_device_family == "StratixIV(GT/GX/E)") || (intended_device_family == "STRATIXIV(GT/GX/E)") || (intended_device_family == "stratixiv(gt/gx/e)") || (intended_device_family == "StratixIV(GT/E/GX)") || (intended_device_family == "STRATIXIV(GT/E/GX)") || (intended_device_family == "stratixiv(gt/e/gx)") || (intended_device_family == "StratixIV(E/GX/GT)") || (intended_device_family == "STRATIXIV(E/GX/GT)") || (intended_device_family == "stratixiv(e/gx/gt)") || (intended_device_family == "StratixIV(E/GT/GX)") || (intended_device_family == "STRATIXIV(E/GT/GX)") || (intended_device_family == "stratixiv(e/gt/gx)") || (intended_device_family == "Stratix IV (GX/E)") || (intended_device_family == "STRATIX IV (GX/E)") || (intended_device_family == "stratix iv (gx/e)") || (intended_device_family == "StratixIV(GX/E)") || (intended_device_family == "STRATIXIV(GX/E)") || (intended_device_family == "stratixiv(gx/e)"))
+ || ((intended_device_family == "Arria II GX") || (intended_device_family == "ARRIA II GX") || (intended_device_family == "arria ii gx") || (intended_device_family == "ArriaIIGX") || (intended_device_family == "ARRIAIIGX") || (intended_device_family == "arriaiigx") || (intended_device_family == "Arria IIGX") || (intended_device_family == "ARRIA IIGX") || (intended_device_family == "arria iigx") || (intended_device_family == "ArriaII GX") || (intended_device_family == "ARRIAII GX") || (intended_device_family == "arriaii gx") || (intended_device_family == "Arria II") || (intended_device_family == "ARRIA II") || (intended_device_family == "arria ii") || (intended_device_family == "ArriaII") || (intended_device_family == "ARRIAII") || (intended_device_family == "arriaii") || (intended_device_family == "Arria II (GX/E)") || (intended_device_family == "ARRIA II (GX/E)") || (intended_device_family == "arria ii (gx/e)") || (intended_device_family == "ArriaII(GX/E)") || (intended_device_family == "ARRIAII(GX/E)") || (intended_device_family == "arriaii(gx/e)") || (intended_device_family == "PIRANHA") || (intended_device_family == "piranha"))
+ || ((intended_device_family == "HardCopy IV") || (intended_device_family == "HARDCOPY IV") || (intended_device_family == "hardcopy iv") || (intended_device_family == "HardCopyIV") || (intended_device_family == "HARDCOPYIV") || (intended_device_family == "hardcopyiv") || (intended_device_family == "HardCopy IV (GX)") || (intended_device_family == "HARDCOPY IV (GX)") || (intended_device_family == "hardcopy iv (gx)") || (intended_device_family == "HardCopy IV (E)") || (intended_device_family == "HARDCOPY IV (E)") || (intended_device_family == "hardcopy iv (e)") || (intended_device_family == "HardCopyIV(GX)") || (intended_device_family == "HARDCOPYIV(GX)") || (intended_device_family == "hardcopyiv(gx)") || (intended_device_family == "HardCopyIV(E)") || (intended_device_family == "HARDCOPYIV(E)") || (intended_device_family == "hardcopyiv(e)") || (intended_device_family == "HCXIV") || (intended_device_family == "hcxiv") || (intended_device_family == "HardCopy IV (GX/E)") || (intended_device_family == "HARDCOPY IV (GX/E)") || (intended_device_family == "hardcopy iv (gx/e)") || (intended_device_family == "HardCopy IV (E/GX)") || (intended_device_family == "HARDCOPY IV (E/GX)") || (intended_device_family == "hardcopy iv (e/gx)") || (intended_device_family == "HardCopyIV(GX/E)") || (intended_device_family == "HARDCOPYIV(GX/E)") || (intended_device_family == "hardcopyiv(gx/e)") || (intended_device_family == "HardCopyIV(E/GX)") || (intended_device_family == "HARDCOPYIV(E/GX)") || (intended_device_family == "hardcopyiv(e/gx)"))
+ || (((intended_device_family == "Stratix V") || (intended_device_family == "STRATIX V") || (intended_device_family == "stratix v") || (intended_device_family == "StratixV") || (intended_device_family == "STRATIXV") || (intended_device_family == "stratixv") || (intended_device_family == "Stratix V (GS)") || (intended_device_family == "STRATIX V (GS)") || (intended_device_family == "stratix v (gs)") || (intended_device_family == "StratixV(GS)") || (intended_device_family == "STRATIXV(GS)") || (intended_device_family == "stratixv(gs)") || (intended_device_family == "Stratix V (GX)") || (intended_device_family == "STRATIX V (GX)") || (intended_device_family == "stratix v (gx)") || (intended_device_family == "StratixV(GX)") || (intended_device_family == "STRATIXV(GX)") || (intended_device_family == "stratixv(gx)") || (intended_device_family == "Stratix V (GS/GX)") || (intended_device_family == "STRATIX V (GS/GX)") || (intended_device_family == "stratix v (gs/gx)") || (intended_device_family == "StratixV(GS/GX)") || (intended_device_family == "STRATIXV(GS/GX)") || (intended_device_family == "stratixv(gs/gx)") || (intended_device_family == "Stratix V (GX/GS)") || (intended_device_family == "STRATIX V (GX/GS)") || (intended_device_family == "stratix v (gx/gs)") || (intended_device_family == "StratixV(GX/GS)") || (intended_device_family == "STRATIXV(GX/GS)") || (intended_device_family == "stratixv(gx/gs)"))
+ ) || (((intended_device_family == "Arria II GZ") || (intended_device_family == "ARRIA II GZ") || (intended_device_family == "arria ii gz") || (intended_device_family == "ArriaII GZ") || (intended_device_family == "ARRIAII GZ") || (intended_device_family == "arriaii gz") || (intended_device_family == "Arria IIGZ") || (intended_device_family == "ARRIA IIGZ") || (intended_device_family == "arria iigz") || (intended_device_family == "ArriaIIGZ") || (intended_device_family == "ARRIAIIGZ") || (intended_device_family == "arriaiigz"))
+ ) ) || ((intended_device_family == "HardCopy III") || (intended_device_family == "HARDCOPY III") || (intended_device_family == "hardcopy iii") || (intended_device_family == "HardCopyIII") || (intended_device_family == "HARDCOPYIII") || (intended_device_family == "hardcopyiii") || (intended_device_family == "HCX") || (intended_device_family == "hcx"))
+ ) ) || (((intended_device_family == "Cyclone II") || (intended_device_family == "CYCLONE II") || (intended_device_family == "cyclone ii") || (intended_device_family == "Cycloneii") || (intended_device_family == "CYCLONEII") || (intended_device_family == "cycloneii") || (intended_device_family == "Magellan") || (intended_device_family == "MAGELLAN") || (intended_device_family == "magellan"))
+ || (((intended_device_family == "Cyclone III") || (intended_device_family == "CYCLONE III") || (intended_device_family == "cyclone iii") || (intended_device_family == "CycloneIII") || (intended_device_family == "CYCLONEIII") || (intended_device_family == "cycloneiii") || (intended_device_family == "Barracuda") || (intended_device_family == "BARRACUDA") || (intended_device_family == "barracuda") || (intended_device_family == "Cuda") || (intended_device_family == "CUDA") || (intended_device_family == "cuda") || (intended_device_family == "CIII") || (intended_device_family == "ciii"))
+ || ((intended_device_family == "Cyclone III LS") || (intended_device_family == "CYCLONE III LS") || (intended_device_family == "cyclone iii ls") || (intended_device_family == "CycloneIIILS") || (intended_device_family == "CYCLONEIIILS") || (intended_device_family == "cycloneiiils") || (intended_device_family == "Cyclone III LPS") || (intended_device_family == "CYCLONE III LPS") || (intended_device_family == "cyclone iii lps") || (intended_device_family == "Cyclone LPS") || (intended_device_family == "CYCLONE LPS") || (intended_device_family == "cyclone lps") || (intended_device_family == "CycloneLPS") || (intended_device_family == "CYCLONELPS") || (intended_device_family == "cyclonelps") || (intended_device_family == "Tarpon") || (intended_device_family == "TARPON") || (intended_device_family == "tarpon") || (intended_device_family == "Cyclone IIIE") || (intended_device_family == "CYCLONE IIIE") || (intended_device_family == "cyclone iiie"))
+ || (((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
+ || ((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
+ ) || (((intended_device_family == "Cyclone IV E") || (intended_device_family == "CYCLONE IV E") || (intended_device_family == "cyclone iv e") || (intended_device_family == "CycloneIV E") || (intended_device_family == "CYCLONEIV E") || (intended_device_family == "cycloneiv e") || (intended_device_family == "Cyclone IVE") || (intended_device_family == "CYCLONE IVE") || (intended_device_family == "cyclone ive") || (intended_device_family == "CycloneIVE") || (intended_device_family == "CYCLONEIVE") || (intended_device_family == "cycloneive"))
+ ) ) ) ))
+ ? 1 : 0;
+
+ parameter FAMILY_HAS_STRATIXIII_STYLE_RAM = (((((intended_device_family == "Stratix III") || (intended_device_family == "STRATIX III") || (intended_device_family == "stratix iii") || (intended_device_family == "StratixIII") || (intended_device_family == "STRATIXIII") || (intended_device_family == "stratixiii") || (intended_device_family == "Titan") || (intended_device_family == "TITAN") || (intended_device_family == "titan") || (intended_device_family == "SIII") || (intended_device_family == "siii"))
+ || (((intended_device_family == "Stratix IV") || (intended_device_family == "STRATIX IV") || (intended_device_family == "stratix iv") || (intended_device_family == "TGX") || (intended_device_family == "tgx") || (intended_device_family == "StratixIV") || (intended_device_family == "STRATIXIV") || (intended_device_family == "stratixiv") || (intended_device_family == "Stratix IV (GT)") || (intended_device_family == "STRATIX IV (GT)") || (intended_device_family == "stratix iv (gt)") || (intended_device_family == "Stratix IV (GX)") || (intended_device_family == "STRATIX IV (GX)") || (intended_device_family == "stratix iv (gx)") || (intended_device_family == "Stratix IV (E)") || (intended_device_family == "STRATIX IV (E)") || (intended_device_family == "stratix iv (e)") || (intended_device_family == "StratixIV(GT)") || (intended_device_family == "STRATIXIV(GT)") || (intended_device_family == "stratixiv(gt)") || (intended_device_family == "StratixIV(GX)") || (intended_device_family == "STRATIXIV(GX)") || (intended_device_family == "stratixiv(gx)") || (intended_device_family == "StratixIV(E)") || (intended_device_family == "STRATIXIV(E)") || (intended_device_family == "stratixiv(e)") || (intended_device_family == "StratixIIIGX") || (intended_device_family == "STRATIXIIIGX") || (intended_device_family == "stratixiiigx") || (intended_device_family == "Stratix IV (GT/GX/E)") || (intended_device_family == "STRATIX IV (GT/GX/E)") || (intended_device_family == "stratix iv (gt/gx/e)") || (intended_device_family == "Stratix IV (GT/E/GX)") || (intended_device_family == "STRATIX IV (GT/E/GX)") || (intended_device_family == "stratix iv (gt/e/gx)") || (intended_device_family == "Stratix IV (E/GT/GX)") || (intended_device_family == "STRATIX IV (E/GT/GX)") || (intended_device_family == "stratix iv (e/gt/gx)") || (intended_device_family == "Stratix IV (E/GX/GT)") || (intended_device_family == "STRATIX IV (E/GX/GT)") || (intended_device_family == "stratix iv (e/gx/gt)") || (intended_device_family == "StratixIV(GT/GX/E)") || (intended_device_family == "STRATIXIV(GT/GX/E)") || (intended_device_family == "stratixiv(gt/gx/e)") || (intended_device_family == "StratixIV(GT/E/GX)") || (intended_device_family == "STRATIXIV(GT/E/GX)") || (intended_device_family == "stratixiv(gt/e/gx)") || (intended_device_family == "StratixIV(E/GX/GT)") || (intended_device_family == "STRATIXIV(E/GX/GT)") || (intended_device_family == "stratixiv(e/gx/gt)") || (intended_device_family == "StratixIV(E/GT/GX)") || (intended_device_family == "STRATIXIV(E/GT/GX)") || (intended_device_family == "stratixiv(e/gt/gx)") || (intended_device_family == "Stratix IV (GX/E)") || (intended_device_family == "STRATIX IV (GX/E)") || (intended_device_family == "stratix iv (gx/e)") || (intended_device_family == "StratixIV(GX/E)") || (intended_device_family == "STRATIXIV(GX/E)") || (intended_device_family == "stratixiv(gx/e)"))
+ || ((intended_device_family == "Arria II GX") || (intended_device_family == "ARRIA II GX") || (intended_device_family == "arria ii gx") || (intended_device_family == "ArriaIIGX") || (intended_device_family == "ARRIAIIGX") || (intended_device_family == "arriaiigx") || (intended_device_family == "Arria IIGX") || (intended_device_family == "ARRIA IIGX") || (intended_device_family == "arria iigx") || (intended_device_family == "ArriaII GX") || (intended_device_family == "ARRIAII GX") || (intended_device_family == "arriaii gx") || (intended_device_family == "Arria II") || (intended_device_family == "ARRIA II") || (intended_device_family == "arria ii") || (intended_device_family == "ArriaII") || (intended_device_family == "ARRIAII") || (intended_device_family == "arriaii") || (intended_device_family == "Arria II (GX/E)") || (intended_device_family == "ARRIA II (GX/E)") || (intended_device_family == "arria ii (gx/e)") || (intended_device_family == "ArriaII(GX/E)") || (intended_device_family == "ARRIAII(GX/E)") || (intended_device_family == "arriaii(gx/e)") || (intended_device_family == "PIRANHA") || (intended_device_family == "piranha"))
+ || ((intended_device_family == "HardCopy IV") || (intended_device_family == "HARDCOPY IV") || (intended_device_family == "hardcopy iv") || (intended_device_family == "HardCopyIV") || (intended_device_family == "HARDCOPYIV") || (intended_device_family == "hardcopyiv") || (intended_device_family == "HardCopy IV (GX)") || (intended_device_family == "HARDCOPY IV (GX)") || (intended_device_family == "hardcopy iv (gx)") || (intended_device_family == "HardCopy IV (E)") || (intended_device_family == "HARDCOPY IV (E)") || (intended_device_family == "hardcopy iv (e)") || (intended_device_family == "HardCopyIV(GX)") || (intended_device_family == "HARDCOPYIV(GX)") || (intended_device_family == "hardcopyiv(gx)") || (intended_device_family == "HardCopyIV(E)") || (intended_device_family == "HARDCOPYIV(E)") || (intended_device_family == "hardcopyiv(e)") || (intended_device_family == "HCXIV") || (intended_device_family == "hcxiv") || (intended_device_family == "HardCopy IV (GX/E)") || (intended_device_family == "HARDCOPY IV (GX/E)") || (intended_device_family == "hardcopy iv (gx/e)") || (intended_device_family == "HardCopy IV (E/GX)") || (intended_device_family == "HARDCOPY IV (E/GX)") || (intended_device_family == "hardcopy iv (e/gx)") || (intended_device_family == "HardCopyIV(GX/E)") || (intended_device_family == "HARDCOPYIV(GX/E)") || (intended_device_family == "hardcopyiv(gx/e)") || (intended_device_family == "HardCopyIV(E/GX)") || (intended_device_family == "HARDCOPYIV(E/GX)") || (intended_device_family == "hardcopyiv(e/gx)"))
+ || (((intended_device_family == "Stratix V") || (intended_device_family == "STRATIX V") || (intended_device_family == "stratix v") || (intended_device_family == "StratixV") || (intended_device_family == "STRATIXV") || (intended_device_family == "stratixv") || (intended_device_family == "Stratix V (GS)") || (intended_device_family == "STRATIX V (GS)") || (intended_device_family == "stratix v (gs)") || (intended_device_family == "StratixV(GS)") || (intended_device_family == "STRATIXV(GS)") || (intended_device_family == "stratixv(gs)") || (intended_device_family == "Stratix V (GX)") || (intended_device_family == "STRATIX V (GX)") || (intended_device_family == "stratix v (gx)") || (intended_device_family == "StratixV(GX)") || (intended_device_family == "STRATIXV(GX)") || (intended_device_family == "stratixv(gx)") || (intended_device_family == "Stratix V (GS/GX)") || (intended_device_family == "STRATIX V (GS/GX)") || (intended_device_family == "stratix v (gs/gx)") || (intended_device_family == "StratixV(GS/GX)") || (intended_device_family == "STRATIXV(GS/GX)") || (intended_device_family == "stratixv(gs/gx)") || (intended_device_family == "Stratix V (GX/GS)") || (intended_device_family == "STRATIX V (GX/GS)") || (intended_device_family == "stratix v (gx/gs)") || (intended_device_family == "StratixV(GX/GS)") || (intended_device_family == "STRATIXV(GX/GS)") || (intended_device_family == "stratixv(gx/gs)"))
+ ) || (((intended_device_family == "Arria II GZ") || (intended_device_family == "ARRIA II GZ") || (intended_device_family == "arria ii gz") || (intended_device_family == "ArriaII GZ") || (intended_device_family == "ARRIAII GZ") || (intended_device_family == "arriaii gz") || (intended_device_family == "Arria IIGZ") || (intended_device_family == "ARRIA IIGZ") || (intended_device_family == "arria iigz") || (intended_device_family == "ArriaIIGZ") || (intended_device_family == "ARRIAIIGZ") || (intended_device_family == "arriaiigz"))
+ ) ) || ((intended_device_family == "HardCopy III") || (intended_device_family == "HARDCOPY III") || (intended_device_family == "hardcopy iii") || (intended_device_family == "HardCopyIII") || (intended_device_family == "HARDCOPYIII") || (intended_device_family == "hardcopyiii") || (intended_device_family == "HCX") || (intended_device_family == "hcx"))
+ ) || (((intended_device_family == "Cyclone III") || (intended_device_family == "CYCLONE III") || (intended_device_family == "cyclone iii") || (intended_device_family == "CycloneIII") || (intended_device_family == "CYCLONEIII") || (intended_device_family == "cycloneiii") || (intended_device_family == "Barracuda") || (intended_device_family == "BARRACUDA") || (intended_device_family == "barracuda") || (intended_device_family == "Cuda") || (intended_device_family == "CUDA") || (intended_device_family == "cuda") || (intended_device_family == "CIII") || (intended_device_family == "ciii"))
+ || ((intended_device_family == "Cyclone III LS") || (intended_device_family == "CYCLONE III LS") || (intended_device_family == "cyclone iii ls") || (intended_device_family == "CycloneIIILS") || (intended_device_family == "CYCLONEIIILS") || (intended_device_family == "cycloneiiils") || (intended_device_family == "Cyclone III LPS") || (intended_device_family == "CYCLONE III LPS") || (intended_device_family == "cyclone iii lps") || (intended_device_family == "Cyclone LPS") || (intended_device_family == "CYCLONE LPS") || (intended_device_family == "cyclone lps") || (intended_device_family == "CycloneLPS") || (intended_device_family == "CYCLONELPS") || (intended_device_family == "cyclonelps") || (intended_device_family == "Tarpon") || (intended_device_family == "TARPON") || (intended_device_family == "tarpon") || (intended_device_family == "Cyclone IIIE") || (intended_device_family == "CYCLONE IIIE") || (intended_device_family == "cyclone iiie"))
+ || (((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
+ || ((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
+ ) || (((intended_device_family == "Cyclone IV E") || (intended_device_family == "CYCLONE IV E") || (intended_device_family == "cyclone iv e") || (intended_device_family == "CycloneIV E") || (intended_device_family == "CYCLONEIV E") || (intended_device_family == "cycloneiv e") || (intended_device_family == "Cyclone IVE") || (intended_device_family == "CYCLONE IVE") || (intended_device_family == "cyclone ive") || (intended_device_family == "CycloneIVE") || (intended_device_family == "CYCLONEIVE") || (intended_device_family == "cycloneive"))
+ ) ) ))
+ ? 1 : 0;
+
+ parameter WRITE_SIDE_SYNCHRONIZERS = (wrsync_delaypipe != 0) ? wrsync_delaypipe :
+ (((FAMILY_HAS_STRATIXII_STYLE_RAM == 1) || (FAMILY_HAS_STRATIXIII_STYLE_RAM == 1))
+ && (clocks_are_synchronized == "FALSE"))
+ ? 4 : 3;
+
+ parameter READ_SIDE_SYNCHRONIZERS = (rdsync_delaypipe != 0) ? rdsync_delaypipe :
+ (((FAMILY_HAS_STRATIXII_STYLE_RAM == 1) || (FAMILY_HAS_STRATIXIII_STYLE_RAM == 1))
+ && (clocks_are_synchronized == "FALSE"))
+ ? 4 : 3;
+
+// LOCAL_PARAMETERS_END
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] data;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ input rdreq;
+ input wrreq;
+
+// OUTPUT PORT DECLARATION
+ output rdfull;
+ output wrfull;
+ output rdempty;
+ output wrempty;
+ output [lpm_widthu_r-1:0] rdusedw;
+ output [lpm_widthu-1:0] wrusedw;
+ output [lpm_width_r-1:0] q;
+
+// INTERNAL WIRE DECLARATION
+ wire w_rdfull_s;
+ wire w_wrfull_s;
+ wire w_rdempty_s;
+ wire w_wrempty_s;
+ wire w_rdfull_a;
+ wire w_wrfull_a;
+ wire w_rdempty_a;
+ wire w_wrempty_a;
+ wire w_rdfull_l;
+ wire w_wrfull_l;
+ wire w_rdempty_l;
+ wire w_wrempty_l;
+ wire [lpm_widthu-1:0] w_rdusedw_s;
+ wire [lpm_widthu-1:0] w_wrusedw_s;
+ wire [lpm_widthu-1:0] w_rdusedw_a;
+ wire [lpm_widthu-1:0] w_wrusedw_a;
+ wire [lpm_widthu_r-1:0] w_rdusedw_l;
+ wire [lpm_widthu-1:0] w_wrusedw_l;
+ wire [lpm_width-1:0] w_q_s;
+ wire [lpm_width-1:0] w_q_a;
+ wire [lpm_width_r-1:0] w_q_l;
+
+// INTERNAL REGISTER DECLARATION
+ reg feature_family_has_stratixii_style_ram;
+ reg feature_family_stratix;
+ reg use_low_latency_fifo;
+
+// INTERNAL TRI DECLARATION
+ tri0 aclr;
+
+// COMPONENT INSTANTIATIONS
+ ALTERA_DEVICE_FAMILIES dev ();
+
+ initial
+ begin
+ feature_family_has_stratixii_style_ram = dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family);
+ feature_family_stratix = dev.FEATURE_FAMILY_STRATIX(intended_device_family);
+
+ use_low_latency_fifo = (((feature_family_has_stratixii_style_ram == 1) &&
+ ((use_eab == "ON") || ((use_eab == "OFF") && (lpm_width != lpm_width_r) && (lpm_width_r != 0)) ||
+ ((lpm_numwords < 16) && (clocks_are_synchronized == "FALSE")))) ||
+ ((feature_family_stratix == 1) && (use_eab == "ON") &&
+ (((lpm_showahead == "ON") && (add_ram_output_register == "OFF")) ||
+ (clocks_are_synchronized == "FALSE_LOW_LATENCY"))));
+ end
+
+ generate
+ if (clocks_are_synchronized == "TRUE")
+ begin : dcfifo_sync
+ dcfifo_sync #(
+ .lpm_width (lpm_width),
+ .lpm_widthu (lpm_widthu),
+ .lpm_numwords (lpm_numwords),
+ .intended_device_family (intended_device_family),
+ .lpm_showahead (lpm_showahead),
+ .underflow_checking (underflow_checking),
+ .overflow_checking (overflow_checking),
+ .use_eab (use_eab),
+ .add_ram_output_register (add_ram_output_register))
+ SYNC (
+ .data (data),
+ .rdclk (rdclk),
+ .wrclk (wrclk),
+ .aclr (aclr),
+ .rdreq (rdreq),
+ .wrreq (wrreq),
+ .rdfull (w_rdfull_s),
+ .wrfull (w_wrfull_s),
+ .rdempty (w_rdempty_s),
+ .wrempty (w_wrempty_s),
+ .rdusedw (w_rdusedw_s),
+ .wrusedw (w_wrusedw_s),
+ .q (w_q_s));
+ end
+ endgenerate
+
+ generate
+ if (clocks_are_synchronized != "TRUE")
+ begin : dcfifo_async
+ dcfifo_async #(
+ .lpm_width (lpm_width),
+ .lpm_widthu (lpm_widthu),
+ .lpm_numwords (lpm_numwords),
+ .delay_rdusedw (delay_rdusedw),
+ .delay_wrusedw (delay_wrusedw),
+ .rdsync_delaypipe (READ_SIDE_SYNCHRONIZERS),
+ .wrsync_delaypipe (WRITE_SIDE_SYNCHRONIZERS),
+ .intended_device_family (intended_device_family),
+ .lpm_showahead (lpm_showahead),
+ .underflow_checking (underflow_checking),
+ .overflow_checking (overflow_checking),
+ .use_eab (use_eab),
+ .add_ram_output_register (add_ram_output_register))
+ ASYNC (
+ .data (data),
+ .rdclk (rdclk),
+ .wrclk (wrclk),
+ .aclr (aclr),
+ .rdreq (rdreq),
+ .wrreq (wrreq),
+ .rdfull (w_rdfull_a),
+ .wrfull (w_wrfull_a),
+ .rdempty (w_rdempty_a),
+ .wrempty (w_wrempty_a),
+ .rdusedw (w_rdusedw_a),
+ .wrusedw (w_wrusedw_a),
+ .q (w_q_a) );
+ end
+ endgenerate
+
+ dcfifo_low_latency LOWLATENCY (
+ .data (data),
+ .rdclk (rdclk),
+ .wrclk (wrclk),
+ .aclr (aclr),
+ .rdreq (rdreq),
+ .wrreq (wrreq),
+ .rdfull (w_rdfull_l),
+ .wrfull (w_wrfull_l),
+ .rdempty (w_rdempty_l),
+ .wrempty (w_wrempty_l),
+ .rdusedw (w_rdusedw_l),
+ .wrusedw (w_wrusedw_l),
+ .q (w_q_l) );
+ defparam
+ LOWLATENCY.lpm_width = lpm_width,
+ LOWLATENCY.lpm_widthu = lpm_widthu,
+ LOWLATENCY.lpm_width_r = lpm_width_r,
+ LOWLATENCY.lpm_widthu_r = lpm_widthu_r,
+ LOWLATENCY.lpm_numwords = lpm_numwords,
+ LOWLATENCY.delay_rdusedw = delay_rdusedw,
+ LOWLATENCY.delay_wrusedw = delay_wrusedw,
+ LOWLATENCY.rdsync_delaypipe = (READ_SIDE_SYNCHRONIZERS > 3 ? READ_SIDE_SYNCHRONIZERS - 2 : 1),
+ LOWLATENCY.wrsync_delaypipe = (WRITE_SIDE_SYNCHRONIZERS > 3 ? WRITE_SIDE_SYNCHRONIZERS - 2 : 1),
+ LOWLATENCY.intended_device_family = intended_device_family,
+ LOWLATENCY.lpm_showahead = lpm_showahead,
+ LOWLATENCY.underflow_checking = underflow_checking,
+ LOWLATENCY.overflow_checking = overflow_checking,
+ LOWLATENCY.add_usedw_msb_bit = add_usedw_msb_bit,
+ LOWLATENCY.write_aclr_synch = write_aclr_synch,
+ LOWLATENCY.use_eab = use_eab,
+ LOWLATENCY.clocks_are_synchronized = clocks_are_synchronized,
+ LOWLATENCY.add_ram_output_register = add_ram_output_register,
+ LOWLATENCY.lpm_hint = lpm_hint;
+
+// INITIAL CONSTRUCT BLOCK
+ initial
+ begin
+ if(((wrsync_delaypipe == 0) || (rdsync_delaypipe == 0)) && (clocks_are_synchronized == "FALSE"))
+ begin
+ if ((FAMILY_HAS_STRATIXII_STYLE_RAM == 1) || (FAMILY_HAS_STRATIXIII_STYLE_RAM == 1))
+ begin
+ $display ("Warning! Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2.");
+ $display("Time: %0t Instance: %m", $time);
+ end
+ end
+ end
+
+// CONTINOUS ASSIGNMENT
+ assign rdfull = (use_low_latency_fifo == 1) ? w_rdfull_l :
+ (clocks_are_synchronized == "TRUE") ? w_rdfull_s : w_rdfull_a;
+
+ assign wrfull = (use_low_latency_fifo == 1) ? w_wrfull_l :
+ (clocks_are_synchronized == "TRUE") ? w_wrfull_s : w_wrfull_a;
+
+ assign rdempty = (use_low_latency_fifo == 1) ? w_rdempty_l :
+ (clocks_are_synchronized == "TRUE") ? w_rdempty_s : w_rdempty_a;
+
+ assign wrempty = (use_low_latency_fifo == 1) ? w_wrempty_l :
+ (clocks_are_synchronized == "TRUE") ? w_wrempty_s : w_wrempty_a;
+
+ assign rdusedw = (use_low_latency_fifo == 1) ? w_rdusedw_l :
+ (clocks_are_synchronized == "TRUE") ? w_rdusedw_s : w_rdusedw_a;
+
+ assign wrusedw = (use_low_latency_fifo == 1) ? w_wrusedw_l :
+ (clocks_are_synchronized == "TRUE") ? w_wrusedw_s : w_wrusedw_a;
+
+ assign q = (use_low_latency_fifo == 1) ? w_q_l :
+ (clocks_are_synchronized == "TRUE") ? w_q_s : w_q_a;
+
+endmodule // dcfifo_mixed_widths
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo
+//
+// Description : Dual Clocks FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo ( data, rdclk, wrclk, aclr, rdreq, wrreq,
+ rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_width = 1;
+ parameter lpm_widthu = 1;
+ parameter lpm_numwords = 2;
+ parameter delay_rdusedw = 1;
+ parameter delay_wrusedw = 1;
+ parameter rdsync_delaypipe = 0;
+ parameter wrsync_delaypipe = 0;
+ parameter intended_device_family = "Stratix";
+ parameter lpm_showahead = "OFF";
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter clocks_are_synchronized = "FALSE";
+ parameter use_eab = "ON";
+ parameter add_ram_output_register = "OFF";
+ parameter lpm_hint = "USE_EAB=ON";
+ parameter lpm_type = "dcfifo";
+ parameter add_usedw_msb_bit = "OFF";
+ parameter write_aclr_synch = "OFF";
+
+// LOCAL_PARAMETERS_BEGIN
+
+ parameter add_width = 1;
+ parameter ram_block_type = "AUTO";
+
+// LOCAL_PARAMETERS_END
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] data;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ input rdreq;
+ input wrreq;
+
+// OUTPUT PORT DECLARATION
+ output rdfull;
+ output wrfull;
+ output rdempty;
+ output wrempty;
+ output [lpm_widthu-1:0] rdusedw;
+ output [lpm_widthu-1:0] wrusedw;
+ output [lpm_width-1:0] q;
+
+// INTERNAL WIRE DECLARATION
+ wire w_rdfull;
+ wire w_wrfull;
+ wire w_rdempty;
+ wire w_wrempty;
+ wire [lpm_widthu-1:0] w_rdusedw;
+ wire [lpm_widthu-1:0] w_wrusedw;
+ wire [lpm_width-1:0] w_q;
+
+// INTERNAL TRI DECLARATION
+ tri0 aclr;
+
+ dcfifo_mixed_widths DCFIFO_MW (
+ .data (data),
+ .rdclk (rdclk),
+ .wrclk (wrclk),
+ .aclr (aclr),
+ .rdreq (rdreq),
+ .wrreq (wrreq),
+ .rdfull (w_rdfull),
+ .wrfull (w_wrfull),
+ .rdempty (w_rdempty),
+ .wrempty (w_wrempty),
+ .rdusedw (w_rdusedw),
+ .wrusedw (w_wrusedw),
+ .q (w_q) );
+ defparam
+ DCFIFO_MW.lpm_width = lpm_width,
+ DCFIFO_MW.lpm_widthu = lpm_widthu,
+ DCFIFO_MW.lpm_width_r = lpm_width,
+ DCFIFO_MW.lpm_widthu_r = lpm_widthu,
+ DCFIFO_MW.lpm_numwords = lpm_numwords,
+ DCFIFO_MW.delay_rdusedw = delay_rdusedw,
+ DCFIFO_MW.delay_wrusedw = delay_wrusedw,
+ DCFIFO_MW.rdsync_delaypipe = rdsync_delaypipe,
+ DCFIFO_MW.wrsync_delaypipe = wrsync_delaypipe,
+ DCFIFO_MW.intended_device_family = intended_device_family,
+ DCFIFO_MW.lpm_showahead = lpm_showahead,
+ DCFIFO_MW.underflow_checking = underflow_checking,
+ DCFIFO_MW.overflow_checking = overflow_checking,
+ DCFIFO_MW.clocks_are_synchronized = clocks_are_synchronized,
+ DCFIFO_MW.use_eab = use_eab,
+ DCFIFO_MW.add_ram_output_register = add_ram_output_register,
+ DCFIFO_MW.add_width = add_width,
+ DCFIFO_MW.ram_block_type = ram_block_type,
+ DCFIFO_MW.add_usedw_msb_bit = add_usedw_msb_bit,
+ DCFIFO_MW.write_aclr_synch = write_aclr_synch,
+ DCFIFO_MW.lpm_hint = lpm_hint;
+
+// CONTINOUS ASSIGNMENT
+ assign rdfull = w_rdfull;
+ assign wrfull = w_wrfull;
+ assign rdempty = w_rdempty;
+ assign wrempty = w_wrempty;
+ assign rdusedw = w_rdusedw;
+ assign wrusedw = w_wrusedw;
+ assign q = w_q;
+
+endmodule // dcfifo
+// END OF MODULE
+
Index: v1p0/sim/rtc/rtc_timer_tb.v
===================================================================
--- v1p0/sim/rtc/rtc_timer_tb.v (nonexistent)
+++ v1p0/sim/rtc/rtc_timer_tb.v (revision 28)
@@ -0,0 +1,154 @@
+`timescale 1ns/1ns
+
+module rtc_timer_tb ;
+
+ reg rst;
+ reg clk;
+ wire [37:0] time_reg_ns;
+ wire [47:0] time_reg_sec;
+ reg period_ld;
+ reg [39:0] period_in;
+ reg [37:0] time_acc_modulo;
+ reg adj_ld;
+ reg [31:0] adj_ld_data;
+ reg [39:0] period_adj;
+ reg time_ld;
+ reg [37:0] time_reg_ns_in;
+ reg [47:0] time_reg_sec_in;
+ rtc
+ DUT (
+ .rst (rst ) ,
+ .clk (clk ) ,
+ .time_ld (time_ld ) ,
+ .time_reg_ns_in (time_reg_ns_in ) ,
+ .time_reg_sec_in (time_reg_sec_in ) ,
+ .time_reg_ns (time_reg_ns ) ,
+ .time_reg_sec (time_reg_sec ) ,
+ .period_ld (period_ld ) ,
+ .period_in (period_in ) ,
+ .time_acc_modulo (time_acc_modulo ) ,
+ .adj_ld (adj_ld ) ,
+ .period_adj (period_adj ) ,
+ .adj_ld_data (adj_ld_data ) );
+
+
+initial begin
+ clk = 1'b0;
+ forever #4 clk = !clk;
+end
+initial begin
+ rst = 1'b0;
+ @(posedge clk);
+ rst = 1'b1;
+ @(posedge clk);
+ rst = 1'b0;
+end
+initial begin
+ #2000 $stop;
+end
+
+// main process
+integer i;
+initial begin
+
+ /////////////////////////
+ // reset default values
+ /////////////////////////
+
+ @(posedge rst);
+ // frequency load
+ period_ld = 1'b0;
+ period_in[39:32] = 8'h00; // ns
+ period_in[31: 0] = 32'h00000000; // ns fraction
+ time_acc_modulo = 38'd256_000000000;
+ // time load
+ time_ld = 1'b0;
+ time_reg_ns_in[37:8] = 30'd0; // ns
+ time_reg_ns_in[ 7:0] = 8'h00; // ns fraction
+ time_reg_sec_in = 48'd0;
+ // time fine tune load
+ adj_ld = 1'b0;
+ adj_ld_data = 32'd10;
+ period_adj = 40'h00_00000000;
+ @(negedge rst);
+
+ ////////////////////
+ // time adjustment
+ ////////////////////
+
+ for (i=0; i<20; i=i+1) @(posedge clk);
+ // load default period
+ period_ld = 1'b1;
+ period_in[39:32] = 8'h08; // ns
+ period_in[31: 0] = 32'h00000000; // ns fraction
+ @(posedge clk);
+ period_ld = 1'b0;
+
+ for (i=0; i<20; i=i+1) @(posedge clk);
+ // fine tune time difference by 0
+ adj_ld = 1'b1;
+ adj_ld_data = 32'd10;
+ period_adj[39:32] = 8'h00; // ns // can be negative?
+ period_adj[31: 0] = 32'h00000000; // ns fraction
+ @(posedge clk);
+ adj_ld = 1'b0;
+
+ for (i=0; i<20; i=i+1) @(posedge clk);
+ // load time ToD values
+ time_ld = 1'b1;
+ time_reg_ns_in[37:8] = 30'd999999990; // ns
+ time_reg_ns_in[ 7:0] = 8'h00; // ns fraction
+ time_reg_sec_in = 48'd10;
+ @(posedge clk);
+ time_ld = 1'b0;
+
+ for (i=0; i<20; i=i+1) @(posedge clk);
+ // fine tune frequency difference
+ period_ld = 1'b1;
+ period_in[39:32] = 8'h08; // ns
+ period_in[31: 0] = 32'h10200000; // ns fraction
+ @(posedge clk);
+ period_ld = 1'b0;
+
+ for (i=0; i<20; i=i+1) @(posedge clk);
+ // fine tune time difference
+ adj_ld = 1'b1;
+ adj_ld_data = 32'd10;
+ period_adj[39:32] = 8'h02; // ns // can be negative?
+ period_adj[31: 0] = 32'h20800000; // ns fraction
+ @(posedge clk);
+ adj_ld = 1'b0;
+end
+
+// sec+ns watchpoint
+wire [29:0] time_acc_modulo_ns_ = time_acc_modulo[37:8];
+wire [47:0] time_reg_sec_in_ = time_reg_sec_in[47:0];
+wire [29:0] time_reg_ns_in_ = time_reg_ns_in[37:8];
+wire [47:0] time_reg_sec_ = time_reg_sec[47:0];
+wire [29:0] time_reg_ns_ = time_reg_ns[37:8];
+wire [ 7:0] period_ns_ = period_in[39:32];
+wire [ 7:0] period_adj_ns_ = period_adj[39:32];
+wire time_reg_sec_inc_ = DUT.time_acc_48s_inc;
+// ns fraction watchpoint
+wire [ 7:0] time_acc_modulo_ns_f = time_acc_modulo[7:0];
+wire [ 7:0] time_reg_ns_in_f = time_reg_ns_in[7:0];
+wire [ 7:0] time_reg_ns_f = time_reg_ns[7:0];
+wire [31:0] period_ns_f = period_in[31:0];
+wire [31:0] period_adj_ns_f = period_adj[31:0];
+
+// ns time incremental watchpoint
+reg [47:0] time_reg_sec__d1;
+reg [29:0] time_reg_ns__d1;
+always @(posedge clk) begin
+ time_reg_sec__d1 <= time_reg_sec_;
+ time_reg_ns__d1 <= time_reg_ns_;
+end
+wire [29:0] time_reg_ns__delta = (time_reg_sec__d1!=time_reg_sec_)?
+ (time_acc_modulo_ns_-(time_reg_ns__d1-time_reg_ns_)):
+ (time_reg_ns_-time_reg_ns__d1);
+
+// Delta-Sigma circuit watchpoint
+wire [23:0] time_adj_08n_32f_24f = rtc_timer_tb.DUT.time_adj_08n_32f[23:0];
+
+endmodule
+
Index: v1p0/sim/rtc/wave.do
===================================================================
--- v1p0/sim/rtc/wave.do (nonexistent)
+++ v1p0/sim/rtc/wave.do (revision 28)
@@ -0,0 +1,67 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider input
+add wave -noupdate -format Logic /rtc_timer_tb/rst
+add wave -noupdate -format Logic /rtc_timer_tb/clk
+add wave -noupdate -divider {direct write}
+add wave -noupdate -format Logic /rtc_timer_tb/time_ld
+add wave -noupdate -format Literal /rtc_timer_tb/DUT/time_reg_ns_in
+add wave -noupdate -format Literal /rtc_timer_tb/DUT/time_reg_sec_in
+add wave -noupdate -divider {freq adjustment}
+add wave -noupdate -format Logic /rtc_timer_tb/period_ld
+add wave -noupdate -format Literal /rtc_timer_tb/period_in
+add wave -noupdate -divider {1s modulo}
+add wave -noupdate -format Literal /rtc_timer_tb/time_acc_modulo
+add wave -noupdate -divider {time adjustment}
+add wave -noupdate -format Logic /rtc_timer_tb/adj_ld
+add wave -noupdate -format Literal /rtc_timer_tb/adj_ld_data
+add wave -noupdate -format Literal /rtc_timer_tb/DUT/period_adj
+add wave -noupdate -divider output
+add wave -noupdate -format Literal /rtc_timer_tb/time_reg_sec
+add wave -noupdate -format Literal /rtc_timer_tb/time_reg_ns
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -divider {INTERNAL Signals}
+add wave -noupdate -divider {precise time control}
+add wave -noupdate -format Literal -radix hexadecimal /rtc_timer_tb/DUT/adj_cnt
+add wave -noupdate -format Literal -radix hexadecimal /rtc_timer_tb/DUT/time_adj
+add wave -noupdate -divider Delta-Sigma
+add wave -noupdate -format Literal /rtc_timer_tb/DUT/time_adj_08n_32f
+add wave -noupdate -format Literal /rtc_timer_tb/DUT/time_adj_08n_08f
+add wave -noupdate -format Literal /rtc_timer_tb/DUT/time_adj_00n_24f
+add wave -noupdate -divider {WATCHPOINT Signals}
+add wave -noupdate -divider {ns and sec}
+add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_acc_modulo_ns_
+add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_reg_ns__delta
+add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_reg_sec_in_
+add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_reg_ns_in_
+add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_reg_sec_
+add wave -noupdate -format Logic /rtc_timer_tb/time_reg_sec_inc_
+add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_reg_ns_
+add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/period_ns_
+add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/period_adj_ns_
+add wave -noupdate -divider {ns fraction}
+add wave -noupdate -format Literal /rtc_timer_tb/time_acc_modulo_ns_f
+add wave -noupdate -format Literal /rtc_timer_tb/time_reg_ns_in_f
+add wave -noupdate -format Literal /rtc_timer_tb/time_reg_ns_f
+add wave -noupdate -format Literal /rtc_timer_tb/period_ns_f
+add wave -noupdate -format Literal /rtc_timer_tb/period_adj_ns_f
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -divider {New Divider}
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {533 ns} 0}
+configure wave -namecolwidth 222
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {476 ns} {632 ns}
Index: v1p0/sim/rtc/sim.do
===================================================================
--- v1p0/sim/rtc/sim.do (nonexistent)
+++ v1p0/sim/rtc/sim.do (revision 28)
@@ -0,0 +1,10 @@
+vlib work
+vlog -work work ../../rtl/rtc/rtc.v
+vlog -work work rtc_timer_tb.v
+vsim -novopt work.rtc_timer_tb
+
+log -r */*
+radix -hexadecimal
+do wave.do
+
+run -all
Index: v1p0/sim/tsu/tsu_queue_tb.v
===================================================================
--- v1p0/sim/tsu/tsu_queue_tb.v (nonexistent)
+++ v1p0/sim/tsu/tsu_queue_tb.v (revision 28)
@@ -0,0 +1,103 @@
+`timescale 1ns/1ns
+
+module tsu_queue_tb;
+
+reg rst;
+wire gmii_rxclk;
+wire gmii_rxctrl;
+wire [ 7:0] gmii_rxdata;
+wire gmii_txclk;
+wire gmii_txctrl;
+wire [ 7:0] gmii_txdata;
+reg rtc_timer_clk;
+reg [79:0] rtc_timer_in;
+reg q_rd_clk;
+reg q_rd_en;
+wire [ 7:0] q_rd_stat;
+wire [55:0] q_rd_data;
+
+initial begin
+ // emulate the hardware behavior when power-up
+ DUT_RX.ts_ack = 1'b0;
+ DUT_TX.ts_ack = 1'b0;
+
+ rst = 1'b0;
+ #10 rst = 1'b1;
+ #20 rst = 1'b0;
+
+ fork
+ @(posedge BFM_RX.eof_rx);
+ @(posedge BFM_TX.eof_tx);
+ join
+ #100 $stop;
+end
+
+initial begin
+ q_rd_clk = 1'b0;
+ forever #5 q_rd_clk = !q_rd_clk;
+end
+
+initial begin
+ rtc_timer_clk = 1'b0;
+ forever #4 rtc_timer_clk = !rtc_timer_clk;
+end
+
+initial begin
+ rtc_timer_in = 80'd0;
+ forever @(posedge rtc_timer_clk) rtc_timer_in = rtc_timer_in +1;
+end
+
+tsu DUT_RX
+ (
+ .rst(rst),
+
+ .gmii_clk(gmii_rxclk),
+ .gmii_ctrl(gmii_rxctrl),
+ .gmii_data(gmii_rxdata),
+
+ .rtc_timer_clk(rtc_timer_clk),
+ .rtc_timer_in(rtc_timer_in[31:0]),
+
+ .q_rst(rst),
+ .q_rd_clk(q_rd_clk),
+ .q_rd_en(q_rd_en),
+ .q_rd_stat(q_rd_stat),
+ .q_rd_data(q_rd_data)
+ );
+
+gmii_rx_bfm BFM_RX
+ (
+ .gmii_rxclk(gmii_rxclk),
+ .gmii_rxctrl(gmii_rxctrl),
+ .gmii_rxdata(gmii_rxdata)
+ );
+
+
+tsu DUT_TX
+ (
+ .rst(rst),
+
+ .gmii_clk(gmii_txclk),
+ .gmii_ctrl(gmii_txctrl),
+ .gmii_data(gmii_txdata),
+
+ .rtc_timer_clk(rtc_timer_clk),
+ .rtc_timer_in(rtc_timer_in[31:0]),
+
+ .q_rst(rst),
+ .q_rd_clk(q_rd_clk),
+ .q_rd_en(),
+ .q_rd_stat(),
+ .q_rd_data()
+ );
+
+gmii_tx_bfm BFM_TX
+ (
+ .gmii_txclk(gmii_txclk),
+ .gmii_txctrl(gmii_txctrl),
+ .gmii_txdata(gmii_txdata)
+ );
+
+
+endmodule
+
Index: v1p0/sim/tsu/sim.do
===================================================================
--- v1p0/sim/tsu/sim.do (nonexistent)
+++ v1p0/sim/tsu/sim.do (revision 28)
@@ -0,0 +1,24 @@
+quit -sim
+
+vlib altera
+vdel -lib altera -all
+vlib work
+vdel -lib work -all
+
+vlib altera
+vlog -work altera altera_mf.v
+
+vlib work
+vlog -work work ../../rtl/tsu/tsu.v
+vlog -work work ../../rtl/tsu/ptp_parser.v
+vlog -work work ../../rtl/tsu/ptp_queue.v
+vlog -work work gmii_rx_bfm.v
+vlog -work work gmii_tx_bfm.v
+vlog -work work tsu_queue_tb.v
+vsim -novopt -L altera work.tsu_queue_tb
+
+log -r */*
+radix -hexadecimal
+do wave.do
+
+run -all
Index: v1p0/sim/tsu/ptpdv2_rx.pcap
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: v1p0/sim/tsu/ptpdv2_rx.pcap
===================================================================
--- v1p0/sim/tsu/ptpdv2_rx.pcap (nonexistent)
+++ v1p0/sim/tsu/ptpdv2_rx.pcap (revision 28)
v1p0/sim/tsu/ptpdv2_rx.pcap
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: v1p0/sim/tsu/wave.do
===================================================================
--- v1p0/sim/tsu/wave.do (nonexistent)
+++ v1p0/sim/tsu/wave.do (revision 28)
@@ -0,0 +1,65 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/gmii_clk
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/gmii_ctrl
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/gmii_data
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_req
+add wave -noupdate -format Literal -radix hexadecimal /tsu_queue_tb/DUT_RX/rtc_time_stamp
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_ack
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_ack_clr
+add wave -noupdate -format Literal -radix hexadecimal /tsu_queue_tb/DUT_RX/gmii_time_stamp
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_gmii_ctrl
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_gmii_data
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_bcnt
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_valid
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_sop
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_eop
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_data
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_mod
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/int_cnt
+add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/bypass_ipv4_cnt
+add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/bypass_ipv6_cnt
+add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/bypass_udp_cnt
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/int_valid_d1
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/int_sop_d1
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/int_eop_d1
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/int_mod_d1
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/int_data_d1
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_vlan
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_ipv4
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_ipv6
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_udp
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_l2
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_l4
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_event
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_msgid
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_seqid
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_found
+add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_infor
+add wave -noupdate -divider {New Divider}
+add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/BFM_RX/num_rx
+add wave -noupdate -divider {New Divider}
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {341698 ps} 0}
+configure wave -namecolwidth 188
+configure wave -valuecolwidth 165
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {247010400 ps}
Index: v1p0/sim/tsu/gmii_rx_bfm.v
===================================================================
--- v1p0/sim/tsu/gmii_rx_bfm.v (nonexistent)
+++ v1p0/sim/tsu/gmii_rx_bfm.v (revision 28)
@@ -0,0 +1,110 @@
+`timescale 1ns/1ns
+
+module gmii_rx_bfm
+ (
+ output gmii_rxclk,
+ output reg gmii_rxctrl,
+ output reg [7:0] gmii_rxdata
+ );
+
+reg gmii_rxclk_offset;
+initial begin
+ gmii_rxclk_offset = 1'b0;
+ forever #4 gmii_rxclk_offset = !gmii_rxclk_offset;
+end
+assign #2 gmii_rxclk = gmii_rxclk_offset;
+
+integer feeder_file_rx, r_rx;
+integer start_addr_rx, end_addr_rx;
+integer index_rx, num_rx;
+reg eof_rx;
+reg pcap_endian_rx;
+reg [31:0] pcap_4bytes_rx;
+reg [31:0] packet_leng_rx;
+reg [ 7:0] packet_byte_rx;
+initial
+begin : feeder_rx
+ gmii_rxctrl = 1'b0;
+ gmii_rxdata = 4'd0;
+ #100;
+ feeder_file_rx = $fopen("ptpdv2_rx.pcap","rb");
+ if (feeder_file_rx == 0)
+ begin
+ $display("Failed to open ptpdv2_rx.pcap!");
+ disable feeder_rx;
+ end
+ else
+ begin
+ // test pcap file endian
+ r_rx = $fread(pcap_4bytes_rx, feeder_file_rx);
+ pcap_endian_rx = (pcap_4bytes_rx == 32'ha1b2c3d4)? 1:0;
+ $fseek(feeder_file_rx, -4, 1);
+ // skip pcap file header 24*8
+ $fseek(feeder_file_rx, 24, 1);
+ // read packet content
+ eof_rx = 0;
+ num_rx = 0;
+ while (!eof_rx & !$feof(feeder_file_rx))
+ begin : fileread_loop
+ // skip frame header (8+4)*8
+ start_addr_rx = $ftell(feeder_file_rx);
+ $fseek(feeder_file_rx, 8+4, 1);
+ // get frame length big endian 4*8
+ r_rx = $fread(packet_leng_rx, feeder_file_rx);
+ packet_leng_rx = pcap_endian_rx?
+ {packet_leng_rx[31:24], packet_leng_rx[23:16], packet_leng_rx[15: 8], packet_leng_rx[ 7: 0]}:
+ {packet_leng_rx[ 7: 0], packet_leng_rx[15: 8], packet_leng_rx[23:16], packet_leng_rx[31:24]};
+ // check whether end of file
+ if (r_rx == 0)
+ begin
+ eof_rx = 1;
+ @(posedge gmii_rxclk_offset);
+ gmii_rxctrl = 1'b0;
+ gmii_rxdata = 8'h00;
+ disable fileread_loop;
+ end
+ // send ifg 96bit=12*8
+ repeat (12)
+ begin
+ @(posedge gmii_rxclk_offset)
+ gmii_rxctrl = 1'b0;
+ gmii_rxdata = 8'h00;
+ end
+ // send frame preamble and sfd 5555555d=4*8
+ repeat (3)
+ begin
+ @(posedge gmii_rxclk_offset);
+ gmii_rxctrl = 1'b1;
+ gmii_rxdata = 8'h55;
+ end
+ @(posedge gmii_rxclk_offset)
+ gmii_rxctrl = 1'b1;
+ gmii_rxdata = 8'h5d;
+ // send frame content
+ for (index_rx=0; index_rx> (8 * (20 - param_value_char_count));
+ param_value_char_count = 0;
+ end
+ else if (tmp == 44) // if tmp = ','
+ begin
+ extract_param_value = 1; // subsequent bytes should be part of param_value
+ extract_param_name = 0;
+ param_name = param_name >> (8 * (50 - param_name_char_count));
+ param_name_char_count = 0;
+ if(param_name == compare_param_name)
+ param_found = 1; // the compare_param_name have been found in the reg_string
+ end
+ else
+ begin
+ if(extract_param_value == 1)
+ begin
+ param_value_char_count = param_value_char_count + white_space_count + 1;
+ include_white_space = 1;
+ if(white_space_count > 0)
+ begin
+ param_value = {8'b100000, param_value[20*8:9]};
+ white_space_count = 0;
+ end
+ param_value = {tmp, param_value[20*8:9]};
+ end
+ else if(extract_param_name == 1)
+ begin
+ param_name = {tmp, param_name[50*8:9]};
+ param_name_char_count = param_name_char_count + 1;
+ end
+ end
+ end
+ reg_string = reg_string >> 8; // shift 1 byte to the right
+ end
+
+ // for the case whether param_name is the left most part of the reg_string
+ if(extract_param_name == 1)
+ begin
+ param_name = param_name >> (8 * (50 - param_name_char_count));
+
+ if(param_name == compare_param_name)
+ param_found = 1;
+ end
+
+ if (param_found == 1)
+ GET_PARAMETER_VALUE = param_value; // return the value of the parameter been looking for
+ else
+ GET_PARAMETER_VALUE = ""; // return empty string if parameter not found
+
+end
+endfunction
+
+endmodule // ALTERA_MF_HINT_EVALUATION
+
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : ALTERA_DEVICE_FAMILIES
+//
+// Description : Common Altera device families comparison
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module ALTERA_DEVICE_FAMILIES;
+
+function IS_FAMILY_STRATIX;
+ input[8*20:1] device;
+ reg is_stratix;
+begin
+ if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
+ is_stratix = 1;
+ else
+ is_stratix = 0;
+
+ IS_FAMILY_STRATIX = is_stratix;
+end
+endfunction //IS_FAMILY_STRATIX
+
+function IS_FAMILY_STRATIXGX;
+ input[8*20:1] device;
+ reg is_stratixgx;
+begin
+ if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
+ is_stratixgx = 1;
+ else
+ is_stratixgx = 0;
+
+ IS_FAMILY_STRATIXGX = is_stratixgx;
+end
+endfunction //IS_FAMILY_STRATIXGX
+
+function IS_FAMILY_CYCLONE;
+ input[8*20:1] device;
+ reg is_cyclone;
+begin
+ if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
+ is_cyclone = 1;
+ else
+ is_cyclone = 0;
+
+ IS_FAMILY_CYCLONE = is_cyclone;
+end
+endfunction //IS_FAMILY_CYCLONE
+
+function IS_FAMILY_MAXII;
+ input[8*20:1] device;
+ reg is_maxii;
+begin
+ if ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
+ is_maxii = 1;
+ else
+ is_maxii = 0;
+
+ IS_FAMILY_MAXII = is_maxii;
+end
+endfunction //IS_FAMILY_MAXII
+
+function IS_FAMILY_STRATIXII;
+ input[8*20:1] device;
+ reg is_stratixii;
+begin
+ if ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
+ is_stratixii = 1;
+ else
+ is_stratixii = 0;
+
+ IS_FAMILY_STRATIXII = is_stratixii;
+end
+endfunction //IS_FAMILY_STRATIXII
+
+function IS_FAMILY_STRATIXIIGX;
+ input[8*20:1] device;
+ reg is_stratixiigx;
+begin
+ if ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
+ is_stratixiigx = 1;
+ else
+ is_stratixiigx = 0;
+
+ IS_FAMILY_STRATIXIIGX = is_stratixiigx;
+end
+endfunction //IS_FAMILY_STRATIXIIGX
+
+function IS_FAMILY_ARRIAGX;
+ input[8*20:1] device;
+ reg is_arriagx;
+begin
+ if ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
+ is_arriagx = 1;
+ else
+ is_arriagx = 0;
+
+ IS_FAMILY_ARRIAGX = is_arriagx;
+end
+endfunction //IS_FAMILY_ARRIAGX
+
+function IS_FAMILY_CYCLONEII;
+ input[8*20:1] device;
+ reg is_cycloneii;
+begin
+ if ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
+ is_cycloneii = 1;
+ else
+ is_cycloneii = 0;
+
+ IS_FAMILY_CYCLONEII = is_cycloneii;
+end
+endfunction //IS_FAMILY_CYCLONEII
+
+function IS_FAMILY_HARDCOPYII;
+ input[8*20:1] device;
+ reg is_hardcopyii;
+begin
+ if ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
+ is_hardcopyii = 1;
+ else
+ is_hardcopyii = 0;
+
+ IS_FAMILY_HARDCOPYII = is_hardcopyii;
+end
+endfunction //IS_FAMILY_HARDCOPYII
+
+function IS_FAMILY_STRATIXIII;
+ input[8*20:1] device;
+ reg is_stratixiii;
+begin
+ if ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
+ is_stratixiii = 1;
+ else
+ is_stratixiii = 0;
+
+ IS_FAMILY_STRATIXIII = is_stratixiii;
+end
+endfunction //IS_FAMILY_STRATIXIII
+
+function IS_FAMILY_CYCLONEIII;
+ input[8*20:1] device;
+ reg is_cycloneiii;
+begin
+ if ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
+ is_cycloneiii = 1;
+ else
+ is_cycloneiii = 0;
+
+ IS_FAMILY_CYCLONEIII = is_cycloneiii;
+end
+endfunction //IS_FAMILY_CYCLONEIII
+
+function IS_FAMILY_STRATIXIV;
+ input[8*20:1] device;
+ reg is_stratixiv;
+begin
+ if ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
+ is_stratixiv = 1;
+ else
+ is_stratixiv = 0;
+
+ IS_FAMILY_STRATIXIV = is_stratixiv;
+end
+endfunction //IS_FAMILY_STRATIXIV
+
+function IS_FAMILY_ARRIAIIGX;
+ input[8*20:1] device;
+ reg is_arriaiigx;
+begin
+ if ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
+ is_arriaiigx = 1;
+ else
+ is_arriaiigx = 0;
+
+ IS_FAMILY_ARRIAIIGX = is_arriaiigx;
+end
+endfunction //IS_FAMILY_ARRIAIIGX
+
+function IS_FAMILY_HARDCOPYIII;
+ input[8*20:1] device;
+ reg is_hardcopyiii;
+begin
+ if ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
+ is_hardcopyiii = 1;
+ else
+ is_hardcopyiii = 0;
+
+ IS_FAMILY_HARDCOPYIII = is_hardcopyiii;
+end
+endfunction //IS_FAMILY_HARDCOPYIII
+
+function IS_FAMILY_HARDCOPYIV;
+ input[8*20:1] device;
+ reg is_hardcopyiv;
+begin
+ if ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
+ is_hardcopyiv = 1;
+ else
+ is_hardcopyiv = 0;
+
+ IS_FAMILY_HARDCOPYIV = is_hardcopyiv;
+end
+endfunction //IS_FAMILY_HARDCOPYIV
+
+function IS_FAMILY_CYCLONEIIILS;
+ input[8*20:1] device;
+ reg is_cycloneiiils;
+begin
+ if ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
+ is_cycloneiiils = 1;
+ else
+ is_cycloneiiils = 0;
+
+ IS_FAMILY_CYCLONEIIILS = is_cycloneiiils;
+end
+endfunction //IS_FAMILY_CYCLONEIIILS
+
+function IS_FAMILY_CYCLONEIVGX;
+ input[8*20:1] device;
+ reg is_cycloneivgx;
+begin
+ if ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
+ is_cycloneivgx = 1;
+ else
+ is_cycloneivgx = 0;
+
+ IS_FAMILY_CYCLONEIVGX = is_cycloneivgx;
+end
+endfunction //IS_FAMILY_CYCLONEIVGX
+
+function IS_FAMILY_CYCLONEIVE;
+ input[8*20:1] device;
+ reg is_cycloneive;
+begin
+ if ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
+ is_cycloneive = 1;
+ else
+ is_cycloneive = 0;
+
+ IS_FAMILY_CYCLONEIVE = is_cycloneive;
+end
+endfunction //IS_FAMILY_CYCLONEIVE
+
+function IS_FAMILY_STRATIXV;
+ input[8*20:1] device;
+ reg is_stratixv;
+begin
+ if ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)"))
+ is_stratixv = 1;
+ else
+ is_stratixv = 0;
+
+ IS_FAMILY_STRATIXV = is_stratixv;
+end
+endfunction //IS_FAMILY_STRATIXV
+
+function IS_FAMILY_ARRIAIIGZ;
+ input[8*20:1] device;
+ reg is_arriaiigz;
+begin
+ if ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
+ is_arriaiigz = 1;
+ else
+ is_arriaiigz = 0;
+
+ IS_FAMILY_ARRIAIIGZ = is_arriaiigz;
+end
+endfunction //IS_FAMILY_ARRIAIIGZ
+
+function IS_FAMILY_MAXV;
+ input[8*20:1] device;
+ reg is_maxv;
+begin
+ if ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
+ is_maxv = 1;
+ else
+ is_maxv = 0;
+
+ IS_FAMILY_MAXV = is_maxv;
+end
+endfunction //IS_FAMILY_MAXV
+
+function FEATURE_FAMILY_STRATIXGX;
+ input[8*20:1] device;
+ reg var_family_stratixgx;
+begin
+ if (IS_FAMILY_STRATIXGX(device) )
+ var_family_stratixgx = 1;
+ else
+ var_family_stratixgx = 0;
+
+ FEATURE_FAMILY_STRATIXGX = var_family_stratixgx;
+end
+endfunction //FEATURE_FAMILY_STRATIXGX
+
+function FEATURE_FAMILY_CYCLONE;
+ input[8*20:1] device;
+ reg var_family_cyclone;
+begin
+ if (IS_FAMILY_CYCLONE(device) )
+ var_family_cyclone = 1;
+ else
+ var_family_cyclone = 0;
+
+ FEATURE_FAMILY_CYCLONE = var_family_cyclone;
+end
+endfunction //FEATURE_FAMILY_CYCLONE
+
+function FEATURE_FAMILY_STRATIXIIGX;
+ input[8*20:1] device;
+ reg var_family_stratixiigx;
+begin
+ if (IS_FAMILY_STRATIXIIGX(device) || IS_FAMILY_ARRIAGX(device) )
+ var_family_stratixiigx = 1;
+ else
+ var_family_stratixiigx = 0;
+
+ FEATURE_FAMILY_STRATIXIIGX = var_family_stratixiigx;
+end
+endfunction //FEATURE_FAMILY_STRATIXIIGX
+
+function FEATURE_FAMILY_STRATIXIII;
+ input[8*20:1] device;
+ reg var_family_stratixiii;
+begin
+ if (IS_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_STRATIXIV(device) || IS_FAMILY_HARDCOPYIII(device) )
+ var_family_stratixiii = 1;
+ else
+ var_family_stratixiii = 0;
+
+ FEATURE_FAMILY_STRATIXIII = var_family_stratixiii;
+end
+endfunction //FEATURE_FAMILY_STRATIXIII
+
+function FEATURE_FAMILY_STRATIXV;
+ input[8*20:1] device;
+ reg var_family_stratixv;
+begin
+ if (IS_FAMILY_STRATIXV(device) )
+ var_family_stratixv = 1;
+ else
+ var_family_stratixv = 0;
+
+ FEATURE_FAMILY_STRATIXV = var_family_stratixv;
+end
+endfunction //FEATURE_FAMILY_STRATIXV
+
+function FEATURE_FAMILY_STRATIXII;
+ input[8*20:1] device;
+ reg var_family_stratixii;
+begin
+ if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) || FEATURE_FAMILY_STRATIXIII(device) )
+ var_family_stratixii = 1;
+ else
+ var_family_stratixii = 0;
+
+ FEATURE_FAMILY_STRATIXII = var_family_stratixii;
+end
+endfunction //FEATURE_FAMILY_STRATIXII
+
+function FEATURE_FAMILY_CYCLONEIVGX;
+ input[8*20:1] device;
+ reg var_family_cycloneivgx;
+begin
+ if (IS_FAMILY_CYCLONEIVGX(device) || IS_FAMILY_CYCLONEIVGX(device) )
+ var_family_cycloneivgx = 1;
+ else
+ var_family_cycloneivgx = 0;
+
+ FEATURE_FAMILY_CYCLONEIVGX = var_family_cycloneivgx;
+end
+endfunction //FEATURE_FAMILY_CYCLONEIVGX
+
+function FEATURE_FAMILY_CYCLONEIVE;
+ input[8*20:1] device;
+ reg var_family_cycloneive;
+begin
+ if (IS_FAMILY_CYCLONEIVE(device) )
+ var_family_cycloneive = 1;
+ else
+ var_family_cycloneive = 0;
+
+ FEATURE_FAMILY_CYCLONEIVE = var_family_cycloneive;
+end
+endfunction //FEATURE_FAMILY_CYCLONEIVE
+
+function FEATURE_FAMILY_CYCLONEIII;
+ input[8*20:1] device;
+ reg var_family_cycloneiii;
+begin
+ if (IS_FAMILY_CYCLONEIII(device) || IS_FAMILY_CYCLONEIIILS(device) || FEATURE_FAMILY_CYCLONEIVGX(device) || FEATURE_FAMILY_CYCLONEIVE(device) )
+ var_family_cycloneiii = 1;
+ else
+ var_family_cycloneiii = 0;
+
+ FEATURE_FAMILY_CYCLONEIII = var_family_cycloneiii;
+end
+endfunction //FEATURE_FAMILY_CYCLONEIII
+
+function FEATURE_FAMILY_STRATIX_HC;
+ input[8*20:1] device;
+ reg var_family_stratix_hc;
+begin
+ if ((device == "StratixHC") )
+ var_family_stratix_hc = 1;
+ else
+ var_family_stratix_hc = 0;
+
+ FEATURE_FAMILY_STRATIX_HC = var_family_stratix_hc;
+end
+endfunction //FEATURE_FAMILY_STRATIX_HC
+
+function FEATURE_FAMILY_STRATIX;
+ input[8*20:1] device;
+ reg var_family_stratix;
+begin
+ if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_MAXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
+ var_family_stratix = 1;
+ else
+ var_family_stratix = 0;
+
+ FEATURE_FAMILY_STRATIX = var_family_stratix;
+end
+endfunction //FEATURE_FAMILY_STRATIX
+
+function FEATURE_FAMILY_MAXII;
+ input[8*20:1] device;
+ reg var_family_maxii;
+begin
+ if (IS_FAMILY_MAXII(device) || FEATURE_FAMILY_MAXV(device) )
+ var_family_maxii = 1;
+ else
+ var_family_maxii = 0;
+
+ FEATURE_FAMILY_MAXII = var_family_maxii;
+end
+endfunction //FEATURE_FAMILY_MAXII
+
+function FEATURE_FAMILY_MAXV;
+ input[8*20:1] device;
+ reg var_family_maxv;
+begin
+ if (IS_FAMILY_MAXV(device) )
+ var_family_maxv = 1;
+ else
+ var_family_maxv = 0;
+
+ FEATURE_FAMILY_MAXV = var_family_maxv;
+end
+endfunction //FEATURE_FAMILY_MAXV
+
+function FEATURE_FAMILY_CYCLONEII;
+ input[8*20:1] device;
+ reg var_family_cycloneii;
+begin
+ if (IS_FAMILY_CYCLONEII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
+ var_family_cycloneii = 1;
+ else
+ var_family_cycloneii = 0;
+
+ FEATURE_FAMILY_CYCLONEII = var_family_cycloneii;
+end
+endfunction //FEATURE_FAMILY_CYCLONEII
+
+function FEATURE_FAMILY_STRATIXIV;
+ input[8*20:1] device;
+ reg var_family_stratixiv;
+begin
+ if (IS_FAMILY_STRATIXIV(device) || IS_FAMILY_ARRIAIIGX(device) || IS_FAMILY_HARDCOPYIV(device) || FEATURE_FAMILY_STRATIXV(device) || FEATURE_FAMILY_ARRIAIIGZ(device) )
+ var_family_stratixiv = 1;
+ else
+ var_family_stratixiv = 0;
+
+ FEATURE_FAMILY_STRATIXIV = var_family_stratixiv;
+end
+endfunction //FEATURE_FAMILY_STRATIXIV
+
+function FEATURE_FAMILY_ARRIAIIGZ;
+ input[8*20:1] device;
+ reg var_family_arriaiigz;
+begin
+ if (IS_FAMILY_ARRIAIIGZ(device) )
+ var_family_arriaiigz = 1;
+ else
+ var_family_arriaiigz = 0;
+
+ FEATURE_FAMILY_ARRIAIIGZ = var_family_arriaiigz;
+end
+endfunction //FEATURE_FAMILY_ARRIAIIGZ
+
+function FEATURE_FAMILY_ARRIAIIGX;
+ input[8*20:1] device;
+ reg var_family_arriaiigx;
+begin
+ if (IS_FAMILY_ARRIAIIGX(device) )
+ var_family_arriaiigx = 1;
+ else
+ var_family_arriaiigx = 0;
+
+ FEATURE_FAMILY_ARRIAIIGX = var_family_arriaiigx;
+end
+endfunction //FEATURE_FAMILY_ARRIAIIGX
+
+function FEATURE_FAMILY_BASE_STRATIXII;
+ input[8*20:1] device;
+ reg var_family_base_stratixii;
+begin
+ if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) )
+ var_family_base_stratixii = 1;
+ else
+ var_family_base_stratixii = 0;
+
+ FEATURE_FAMILY_BASE_STRATIXII = var_family_base_stratixii;
+end
+endfunction //FEATURE_FAMILY_BASE_STRATIXII
+
+function FEATURE_FAMILY_BASE_STRATIX;
+ input[8*20:1] device;
+ reg var_family_base_stratix;
+begin
+ if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) )
+ var_family_base_stratix = 1;
+ else
+ var_family_base_stratix = 0;
+
+ FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix;
+end
+endfunction //FEATURE_FAMILY_BASE_STRATIX
+
+function FEATURE_FAMILY_BASE_CYCLONEII;
+ input[8*20:1] device;
+ reg var_family_base_cycloneii;
+begin
+ if (IS_FAMILY_CYCLONEII(device) )
+ var_family_base_cycloneii = 1;
+ else
+ var_family_base_cycloneii = 0;
+
+ FEATURE_FAMILY_BASE_CYCLONEII = var_family_base_cycloneii;
+end
+endfunction //FEATURE_FAMILY_BASE_CYCLONEII
+
+function FEATURE_FAMILY_BASE_CYCLONE;
+ input[8*20:1] device;
+ reg var_family_base_cyclone;
+begin
+ if (IS_FAMILY_CYCLONE(device) )
+ var_family_base_cyclone = 1;
+ else
+ var_family_base_cyclone = 0;
+
+ FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone;
+end
+endfunction //FEATURE_FAMILY_BASE_CYCLONE
+
+function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM;
+ input[8*20:1] device;
+ reg var_family_has_stratixii_style_ram;
+begin
+ if (FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_CYCLONEII(device) )
+ var_family_has_stratixii_style_ram = 1;
+ else
+ var_family_has_stratixii_style_ram = 0;
+
+ FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM = var_family_has_stratixii_style_ram;
+end
+endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM
+
+function FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM;
+ input[8*20:1] device;
+ reg var_family_has_stratixiii_style_ram;
+begin
+ if (FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEIII(device) )
+ var_family_has_stratixiii_style_ram = 1;
+ else
+ var_family_has_stratixiii_style_ram = 0;
+
+ FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM = var_family_has_stratixiii_style_ram;
+end
+endfunction //FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM
+
+function FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL;
+ input[8*20:1] device;
+ reg var_family_has_stratix_style_pll;
+begin
+ if (FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIXGX(device) )
+ var_family_has_stratix_style_pll = 1;
+ else
+ var_family_has_stratix_style_pll = 0;
+
+ FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL = var_family_has_stratix_style_pll;
+end
+endfunction //FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL
+
+function FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL;
+ input[8*20:1] device;
+ reg var_family_has_stratixii_style_pll;
+begin
+ if (FEATURE_FAMILY_STRATIXII(device) && ! FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEII(device) && ! FEATURE_FAMILY_CYCLONEIII(device) )
+ var_family_has_stratixii_style_pll = 1;
+ else
+ var_family_has_stratixii_style_pll = 0;
+
+ FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL = var_family_has_stratixii_style_pll;
+end
+endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL
+
+function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO;
+ input[8*20:1] device;
+ reg var_family_has_inverted_output_ddio;
+begin
+ if (FEATURE_FAMILY_CYCLONEII(device) )
+ var_family_has_inverted_output_ddio = 1;
+ else
+ var_family_has_inverted_output_ddio = 0;
+
+ FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO = var_family_has_inverted_output_ddio;
+end
+endfunction //FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO
+
+function IS_VALID_FAMILY;
+ input[8*20:1] device;
+ reg is_valid;
+begin
+ if (((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
+ || ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
+ || ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
+ || ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
+ || ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
+ || ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
+ || ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
+ || ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
+ || ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
+ || ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
+ || ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
+ || ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan"))
+ || ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
+ || ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
+ || ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
+ || ((device == "BS") || (device == "bs"))
+ || ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
+ || ((device == "tgx_commercial_v1_1") || (device == "TGX_COMMERCIAL_V1_1"))
+ || ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
+ || ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
+ || ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
+ || ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
+ || ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
+ || ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
+ || ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)"))
+ || ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
+ || ((device == "arriaiigz_commercial_v1_1") || (device == "ARRIAIIGZ_COMMERCIAL_V1_1"))
+ || ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
+ || ((device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V") || (device == "ARRIA V") || (device == "arria v")))
+ is_valid = 1;
+ else
+ is_valid = 0;
+
+ IS_VALID_FAMILY = is_valid;
+end
+endfunction // IS_VALID_FAMILY
+
+
+endmodule // ALTERA_DEVICE_FAMILIES
+
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_dffpipe
+//
+// Description : Dual Clocks FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_dffpipe ( d, clock, aclr,
+ q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_delay = 1;
+ parameter lpm_width = 64;
+
+// LOCAL PARAMETER DECLARATION
+ parameter delay = (lpm_delay < 2) ? 1 : lpm_delay-1;
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] d;
+ input clock;
+ input aclr;
+
+// OUTPUT PORT DECLARATION
+ output [lpm_width-1:0] q;
+
+// INTERNAL REGISTERS DECLARATION
+ reg [(lpm_width*delay)-1:0] dffpipe;
+ reg [lpm_width-1:0] q;
+
+// LOCAL INTEGER DECLARATION
+
+// INITIAL CONSTRUCT BLOCK
+ initial
+ begin
+ dffpipe = {(lpm_width*delay){1'b0}};
+ q <= 0;
+ end
+
+// ALWAYS CONSTRUCT BLOCK
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr)
+ begin
+ dffpipe <= {(lpm_width*delay){1'b0}};
+ q <= 0;
+ end
+ else
+ begin
+ if ((lpm_delay > 0) && ($time > 0))
+ begin
+ if (lpm_delay > 1)
+ begin
+ {q, dffpipe} <= {dffpipe, d};
+ end
+ else
+ q <= d;
+ end
+ end
+ end // @(posedge aclr or posedge clock)
+
+ always @(d)
+ begin
+ if (lpm_delay == 0)
+ q <= d;
+ end // @(d)
+
+endmodule // dcfifo_dffpipe
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_fefifo
+//
+// Description : Dual Clock FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_fefifo ( usedw_in, wreq, rreq, clock, aclr,
+ empty, full);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_widthad = 1;
+ parameter lpm_numwords = 1;
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter lpm_mode = "READ";
+
+// INPUT PORT DECLARATION
+ input [lpm_widthad-1:0] usedw_in;
+ input wreq, rreq;
+ input clock;
+ input aclr;
+
+// OUTPUT PORT DECLARATION
+ output empty, full;
+
+// INTERNAL REGISTERS DECLARATION
+ reg [1:0] sm_empty;
+ reg lrreq;
+ reg i_empty, i_full;
+
+// LOCAL INTEGER DECLARATION
+ integer almostfull;
+
+// INITIAL CONSTRUCT BLOCK
+ initial
+ begin
+ if ((lpm_mode != "READ") && (lpm_mode != "WRITE"))
+ begin
+ $display ("Error! LPM_MODE must be READ or WRITE.");
+ $display ("Time: %0t Instance: %m", $time);
+ end
+ if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
+ begin
+ $display ("Error! UNDERFLOW_CHECKING must be ON or OFF.");
+ $display ("Time: %0t Instance: %m", $time);
+ end
+ if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
+ begin
+ $display ("Error! OVERFLOW_CHECKING must be ON or OFF.");
+ $display ("Time: %0t Instance: %m", $time);
+ end
+
+ sm_empty <= 2'b00;
+ i_empty <= 1'b1;
+ i_full <= 1'b0;
+
+ if (lpm_numwords >= 3)
+ almostfull <= lpm_numwords - 3;
+ else
+ almostfull <= 0;
+ end
+
+// ALWAYS CONSTRUCT BLOCK
+ always @(posedge aclr)
+ begin
+ sm_empty <= 2'b00;
+ i_empty <= 1'b1;
+ i_full <= 1'b0;
+ lrreq <= 1'b0;
+ end // @(posedge aclr)
+
+ always @(posedge clock)
+ begin
+ if (underflow_checking == "OFF")
+ lrreq <= rreq;
+ else
+ lrreq <= rreq && ~i_empty;
+
+ if (~aclr && $time > 0)
+ begin
+ if (lpm_mode == "READ")
+ begin
+ casex (sm_empty)
+ // state_empty
+ 2'b00:
+ if (usedw_in != 0)
+ sm_empty <= 2'b01;
+ // state_non_empty
+ 2'b01:
+ if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq)))
+ sm_empty <= 2'b10;
+ // state_emptywait
+ 2'b10:
+ if (usedw_in > 1)
+ sm_empty <= 2'b01;
+ else
+ sm_empty <= 2'b00;
+ default:
+ $display ("Error! Invalid sm_empty state in read mode.");
+ endcase
+ end // if (lpm_mode == "READ")
+ else if (lpm_mode == "WRITE")
+ begin
+ casex (sm_empty)
+ // state_empty
+ 2'b00:
+ if (wreq)
+ sm_empty <= 2'b01;
+ // state_one
+ 2'b01:
+ if (!wreq)
+ sm_empty <= 2'b11;
+ // state_non_empty
+ 2'b11:
+ if (wreq)
+ sm_empty <= 2'b01;
+ else if (usedw_in == 0)
+ sm_empty <= 2'b00;
+ default:
+ $display ("Error! Invalid sm_empty state in write mode.");
+ endcase
+ end // if (lpm_mode == "WRITE")
+
+ if (~aclr && (usedw_in >= almostfull) && ($time > 0))
+ i_full <= 1'b1;
+ else
+ i_full <= 1'b0;
+ end // if (~aclr && $time > 0)
+ end // @(posedge clock)
+
+ always @(sm_empty)
+ begin
+ i_empty <= !sm_empty[0];
+ end
+ // @(sm_empty)
+
+// CONTINOUS ASSIGNMENT
+ assign empty = i_empty;
+ assign full = i_full;
+endmodule // dcfifo_fefifo
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_async
+//
+// Description : Asynchronous Dual Clocks FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_async (data, rdclk, wrclk, aclr, rdreq, wrreq,
+ rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_width = 1;
+ parameter lpm_widthu = 1;
+ parameter lpm_numwords = 2;
+ parameter delay_rdusedw = 1;
+ parameter delay_wrusedw = 1;
+ parameter rdsync_delaypipe = 0;
+ parameter wrsync_delaypipe = 0;
+ parameter intended_device_family = "Stratix";
+ parameter lpm_showahead = "OFF";
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter use_eab = "ON";
+ parameter add_ram_output_register = "OFF";
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] data;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ input wrreq;
+ input rdreq;
+
+// OUTPUT PORT DECLARATION
+ output rdfull;
+ output wrfull;
+ output rdempty;
+ output wrempty;
+ output [lpm_widthu-1:0] rdusedw;
+ output [lpm_widthu-1:0] wrusedw;
+ output [lpm_width-1:0] q;
+
+// INTERNAL REGISTERS DECLARATION
+ reg [lpm_width-1:0] mem_data [(1< 0))
+ begin
+ i_data_tmp <= data;
+ i_wrptr_tmp <= i_wrptr;
+ i_wren_tmp <= i_wren;
+
+ if (i_wren)
+ begin
+ if (~aclr && ((i_wrptr < (1< 0))
+ begin
+ if (i_wren_tmp)
+ begin
+ mem_data[i_wrptr_tmp] <= i_data_tmp;
+ data_ready[i_wrptr_tmp] <= 1'b0;
+ end
+
+ if ((lpm_showahead == "ON") &&
+ (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1))))
+ i_showahead_flag3 <= 1'b1;
+ end
+ end // @(negedge wrclk)
+
+ always @(posedge rdclk)
+ begin
+
+ if (rdclk && ($time > 0))
+ begin
+ if ((lpm_showahead == "ON") && (add_ram_output_register == "ON") &&
+ ((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)))
+ begin
+ for (k = 0; k < (1< 0))
+ begin
+ if (~aclr && ((i_rdptr < (1< (1 << lpm_widthu))
+ $display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU.");
+ if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF"))
+ $display ("Error! add_ram_output_register must be ON or OFF.");
+ if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
+ $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
+
+ for (i = 0; i < (1 << lpm_widthu); i = i + 1)
+ mem_data[i] <= 0;
+ i_data_tmp <= 0;
+ i_rdptr <= 0;
+ i_wrptr <= 0;
+ i_wrptr_tmp <= 0;
+ i_wren_tmp <= 0;
+
+ i_rdusedw <= 0;
+ i_wrusedw <= 0;
+ i_q_tmp <= 0;
+
+ if (lpm_numwords == (1 << lpm_widthu))
+ cnt_mod <= 1 << (lpm_widthu + 1);
+ else
+ cnt_mod <= 1 << lpm_widthu;
+ end
+
+// COMPONENT INSTANTIATIONS
+ dcfifo_dffpipe RDPTR_D (
+ .d (i_rdptr),
+ .clock (wrclk),
+ .aclr (aclr),
+ .q (w_rdptr_s));
+ dcfifo_dffpipe WRPTR_D (
+ .d (i_wrptr),
+ .clock (wrclk),
+ .aclr (aclr),
+ .q (w_wrptr_r));
+ dcfifo_dffpipe WRPTR_E (
+ .d (w_wrptr_r),
+ .clock (rdclk),
+ .aclr (aclr),
+ .q (w_wrptr_s));
+ defparam
+ RDPTR_D.lpm_delay = 1,
+ RDPTR_D.lpm_width = lpm_widthu + 1,
+ WRPTR_D.lpm_delay = 1,
+ WRPTR_D.lpm_width = lpm_widthu + 1,
+ WRPTR_E.lpm_delay = 1,
+ WRPTR_E.lpm_width = lpm_widthu + 1;
+
+// ALWAYS CONSTRUCT BLOCK
+ always @(posedge aclr)
+ begin
+ i_rdptr <= 0;
+ i_wrptr <= 0;
+ if (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)) ||
+ ((add_ram_output_register == "ON") && (use_eab == "OFF")))
+ if (lpm_showahead == "ON")
+ begin
+ if ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1))
+ i_q_tmp <= {lpm_width{1'bX}};
+ else
+ i_q_tmp <= mem_data[0];
+ end
+ else
+ i_q_tmp <= 0;
+ end // @(posedge aclr)
+
+ always @(posedge wrclk)
+ begin
+ if (aclr && (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)) ||
+ ((add_ram_output_register == "ON") && (use_eab == "OFF"))))
+ begin
+ i_data_tmp <= 0;
+ i_wrptr_tmp <= 0;
+ i_wren_tmp <= 0;
+ end
+ else if (wrclk && ($time > 0))
+ begin
+ i_data_tmp <= data;
+ i_wrptr_tmp <= i_wrptr[lpm_widthu-1:0];
+ i_wren_tmp <= i_wren;
+
+ if (i_wren)
+ begin
+ if (~aclr && (i_wrptr < cnt_mod - 1))
+ i_wrptr <= i_wrptr + 1;
+ else
+ i_wrptr <= 0;
+
+ if (use_eab == "OFF")
+ begin
+ mem_data[i_wrptr[lpm_widthu-1:0]] <= data;
+
+ if (lpm_showahead == "ON")
+ i_showahead_flag2 <= 1'b1;
+ end
+ end
+ end
+ end // @(posedge wrclk)
+
+ always @(negedge wrclk)
+ begin
+ if ((~wrclk && (use_eab == "ON")) && ($time > 0))
+ begin
+ if (i_wren_tmp)
+ begin
+ mem_data[i_wrptr_tmp] <= i_data_tmp;
+ end
+
+ if ((lpm_showahead == "ON") &&
+ (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1))))
+ i_showahead_flag2 <= 1'b1;
+ end
+ end // @(negedge wrclk)
+
+ always @(posedge rdclk)
+ begin
+ if (aclr && (!((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)) ||
+ ((add_ram_output_register == "ON") && (use_eab == "OFF"))))
+ begin
+ if (lpm_showahead == "ON")
+ begin
+ if ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1))
+ i_q_tmp <= {lpm_width{1'bX}};
+ else
+ i_q_tmp <= mem_data[0];
+ end
+ else
+ i_q_tmp <= 0;
+ end
+ else if (rdclk && i_rden && ($time > 0))
+ begin
+ if (~aclr && (i_rdptr < cnt_mod - 1))
+ i_rdptr <= i_rdptr + 1;
+ else
+ i_rdptr <= 0;
+
+ if ((lpm_showahead == "ON") && (!((use_eab == "ON") &&
+ ((feature_family_base_stratix == 1) ||
+ (feature_family_base_cyclone == 1)))))
+ i_showahead_flag2 <= 1'b1;
+ else
+ i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];
+ end
+ end // @(rdclk)
+
+ always @(posedge i_showahead_flag)
+ begin
+ i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]];
+ i_showahead_flag2 <= 1'b0;
+ end // @(posedge i_showahead_flag)
+
+ always @(i_showahead_flag2)
+ begin
+ i_showahead_flag <= i_showahead_flag2;
+ end // @(i_showahead_flag2)
+
+ // Usedw, Empty, Full
+ always @(i_rdptr or w_wrptr_s or cnt_mod)
+ begin
+ if (w_wrptr_s >= i_rdptr)
+ i_rdusedw <= w_wrptr_s - i_rdptr;
+ else
+ i_rdusedw <= w_wrptr_s + cnt_mod - i_rdptr;
+ end // @(i_rdptr or w_wrptr_s)
+
+ always @(i_wrptr or w_rdptr_s or cnt_mod)
+ begin
+ if (i_wrptr >= w_rdptr_s)
+ i_wrusedw <= i_wrptr - w_rdptr_s;
+ else
+ i_wrusedw <= i_wrptr + cnt_mod - w_rdptr_s;
+ end // @(i_wrptr or w_rdptr_s)
+
+
+// CONTINOUS ASSIGNMENT
+ assign i_rden = (underflow_checking == "OFF") ? rdreq : (rdreq && !i_rdempty);
+ assign i_wren = (overflow_checking == "OFF") ? wrreq : (wrreq && !i_wrfull);
+ assign i_rdempty = (i_rdusedw == 0) ? 1'b1 : 1'b0;
+ assign i_wrempty = (i_wrusedw == 0) ? 1'b1 : 1'b0;
+ assign i_rdfull = (((lpm_numwords == (1 << lpm_widthu)) && i_rdusedw[lpm_widthu]) ||
+ ((lpm_numwords < (1 << lpm_widthu)) && (i_rdusedw == lpm_numwords)))
+ ? 1'b1 : 1'b0;
+ assign i_wrfull = (((lpm_numwords == (1 << lpm_widthu)) && i_wrusedw[lpm_widthu]) ||
+ ((lpm_numwords < (1 << lpm_widthu)) && (i_wrusedw == lpm_numwords)))
+ ? 1'b1 : 1'b0;
+ assign rdempty = i_rdempty;
+ assign wrempty = i_wrempty;
+ assign rdfull = i_rdfull;
+ assign wrfull = i_wrfull;
+ assign wrusedw = i_wrusedw[lpm_widthu-1:0];
+ assign rdusedw = i_rdusedw[lpm_widthu-1:0];
+ assign q = i_q_tmp;
+
+endmodule // dcfifo_sync
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_low_latency
+//
+// Description : Dual Clocks FIFO with lowest latency. This fifo implements
+// the fifo behavior for Stratix II, Cyclone II, Stratix III,
+// Cyclone III and Stratix showahead area mode (LPM_SHOWAHEAD=
+// ON, ADD_RAM_OUTPUT_REGISTER=OFF)
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_low_latency (data, rdclk, wrclk, aclr, rdreq, wrreq,
+ rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_width = 1;
+ parameter lpm_widthu = 1;
+ parameter lpm_width_r = lpm_width;
+ parameter lpm_widthu_r = lpm_widthu;
+ parameter lpm_numwords = 2;
+ parameter delay_rdusedw = 2;
+ parameter delay_wrusedw = 2;
+ parameter rdsync_delaypipe = 0;
+ parameter wrsync_delaypipe = 0;
+ parameter intended_device_family = "Stratix";
+ parameter lpm_showahead = "OFF";
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter add_usedw_msb_bit = "OFF";
+ parameter write_aclr_synch = "OFF";
+ parameter use_eab = "ON";
+ parameter clocks_are_synchronized = "FALSE";
+ parameter add_ram_output_register = "OFF";
+ parameter lpm_hint = "USE_EAB=ON";
+
+// LOCAL PARAMETER DECLARATION
+ parameter WIDTH_RATIO = (lpm_width > lpm_width_r) ? lpm_width / lpm_width_r :
+ lpm_width_r / lpm_width;
+ parameter FIFO_DEPTH = (add_usedw_msb_bit == "OFF") ? lpm_widthu_r : lpm_widthu_r -1;
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] data;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ input rdreq;
+ input wrreq;
+
+// OUTPUT PORT DECLARATION
+ output rdfull;
+ output wrfull;
+ output rdempty;
+ output wrempty;
+ output [lpm_widthu_r-1:0] rdusedw;
+ output [lpm_widthu-1:0] wrusedw;
+ output [lpm_width_r-1:0] q;
+
+// INTERNAL REGISTERS DECLARATION
+ reg [lpm_width_r-1:0] mem_data [(1< (1 << lpm_widthu))
+ $display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU.");
+ if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
+ $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
+
+ for (i = 0; i < (1 << lpm_widthu_r) + WIDTH_RATIO; i = i + 1)
+ mem_data[i] <= {lpm_width_r{1'b0}};
+ i_data_tmp <= 0;
+ i_temp_reg <= 0;
+ i_wren_tmp <= 0;
+ i_rdptr_g <= 0;
+ i_rdptr_g1p <= 1;
+ i_wrptr_g <= 0;
+ i_wrptr_g_tmp <= 0;
+ i_wrptr_g1 <= 1;
+ i_delayed_wrptr_g <= 0;
+ i_rdempty <= 1;
+ i_wrempty_area <= 1;
+ i_wrempty_speed <= 1;
+ i_rdempty_rreg <= 1;
+ i_rdfull_speed <= 0;
+ i_rdfull_area <= 0;
+ i_wrfull <= 0;
+ i_wrfull_wreg <= 0;
+ sync_aclr_pre <= 1'b1;
+ sync_aclr <= 1'b1;
+ i_q <= {lpm_width_r{1'b0}};
+ is_underflow <= 0;
+ is_overflow <= 0;
+ no_warn <= 0;
+ i_mem_address <= 0;
+ i_first_bit_position <= 0;
+
+ i_maximize_speed = str_to_int(eva.GET_PARAMETER_VALUE(lpm_hint, "MAXIMIZE_SPEED"));
+
+ if (feature_family_has_stratixiii_style_ram == 1)
+ begin
+ use_wrempty_speed <= 1;
+ use_rdfull_speed <= 1;
+ end
+ else if (feature_family_has_stratixii_style_ram == 1)
+ begin
+ use_wrempty_speed <= ((i_maximize_speed > 5) || (wrsync_delaypipe >= 2)) ? 1 : 0;
+ use_rdfull_speed <= ((i_maximize_speed > 5) || (rdsync_delaypipe >= 2)) ? 1 : 0;
+ end
+ else
+ begin
+ use_wrempty_speed <= 0;
+ use_rdfull_speed <= 0;
+ end
+
+ if (feature_family_has_stratixii_style_ram == 1)
+ begin
+ if (add_usedw_msb_bit == "OFF")
+ begin
+ if (lpm_width_r > lpm_width)
+ begin
+ cnt_mod <= (1 << lpm_widthu) + WIDTH_RATIO;
+ cnt_mod_r <= (1 << lpm_widthu_r) + 1;
+ end
+ else
+ begin
+ cnt_mod <= (1 << lpm_widthu) + 1;
+ cnt_mod_r <= (1 << lpm_widthu_r) + WIDTH_RATIO;
+ end
+ end
+ else
+ begin
+ if (lpm_width_r > lpm_width)
+ begin
+ cnt_mod <= (1 << (lpm_widthu-1)) + WIDTH_RATIO;
+ cnt_mod_r <= (1 << (lpm_widthu_r-1)) + 1;
+ end
+ else
+ begin
+ cnt_mod <= (1 << (lpm_widthu-1)) + 1;
+ cnt_mod_r <= (1 << (lpm_widthu_r-1)) + WIDTH_RATIO;
+ end
+ end
+ end
+ else
+ begin
+ cnt_mod <= 1 << lpm_widthu;
+ cnt_mod_r <= 1 << lpm_widthu_r;
+ end
+
+ if ((lpm_showahead == "OFF") &&
+ ((feature_family_stratixii == 1) ||
+ ((feature_family_cycloneii == 1))))
+ i_q_is_registered = 1'b1;
+ else
+ i_q_is_registered = 1'b0;
+ end
+
+// COMPONENT INSTANTIATIONS
+ dcfifo_dffpipe DP_WS_DGRP (
+ .d (i_rdptr_g),
+ .clock (wrclk),
+ .aclr (aclr),
+ .q (i_ws_dgrp));
+ defparam
+ DP_WS_DGRP.lpm_delay = wrsync_delaypipe,
+ DP_WS_DGRP.lpm_width = lpm_widthu_r + 1;
+
+ dcfifo_dffpipe DP_RS_DGWP (
+ .d (i_delayed_wrptr_g),
+ .clock (rdclk),
+ .aclr (aclr),
+ .q (i_rs_dgwp));
+ defparam
+ DP_RS_DGWP.lpm_delay = rdsync_delaypipe,
+ DP_RS_DGWP.lpm_width = lpm_widthu + 1;
+
+ dcfifo_dffpipe DP_RDUSEDW (
+ .d (i_rdusedw_tmp),
+ .clock (rdclk),
+ .aclr (aclr),
+ .q (i_rdusedw));
+ dcfifo_dffpipe DP_WRUSEDW (
+ .d (i_wrusedw_tmp),
+ .clock (wrclk),
+ .aclr (aclr),
+ .q (i_wrusedw));
+ defparam
+ DP_RDUSEDW.lpm_delay = (delay_rdusedw > 2) ? 2 : delay_rdusedw,
+ DP_RDUSEDW.lpm_width = lpm_widthu_r + 1,
+ DP_WRUSEDW.lpm_delay = (delay_wrusedw > 2) ? 2 : delay_wrusedw,
+ DP_WRUSEDW.lpm_width = lpm_widthu + 1;
+
+// ALWAYS CONSTRUCT BLOCK
+ always @(posedge aclr)
+ begin
+ i_data_tmp <= 0;
+ i_wren_tmp <= 0;
+ i_rdptr_g <= 0;
+ i_rdptr_g1p <= 1;
+ i_wrptr_g <= 0;
+ i_wrptr_g_tmp <= 0;
+ i_wrptr_g1 <= 1;
+ i_delayed_wrptr_g <= 0;
+ i_rdempty <= 1;
+ i_wrempty_area <= 1;
+ i_wrempty_speed <= 1;
+ i_rdempty_rreg <= 1;
+ i_rdfull_speed <= 0;
+ i_rdfull_area <= 0;
+ i_wrfull <= 0;
+ i_wrfull_wreg <= 0;
+ is_underflow <= 0;
+ is_overflow <= 0;
+ no_warn <= 0;
+ i_mem_address <= 0;
+ i_first_bit_position <= 0;
+
+ if(i_q_is_registered)
+ i_q <= 0;
+ else if ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1))
+ i_q <= {lpm_width_r{1'bx}};
+
+ end // @(posedge aclr)
+
+ always @(posedge wrclk or posedge aclr)
+ begin
+ if ($time > 0)
+ begin
+ if (aclr)
+ begin
+ sync_aclr <= 1'b1;
+ sync_aclr_pre <= 1'b1;
+ end
+ else
+ begin
+ sync_aclr <= sync_aclr_pre;
+ sync_aclr_pre <= 1'b0;
+ end
+ end
+ end
+
+ always @(posedge wrclk)
+ begin
+ i_data_tmp <= data;
+ i_wrptr_g_tmp <= i_wrptr_g;
+ i_wren_tmp <= i_wren;
+
+ if (~write_aclr && ($time > 0))
+ begin
+ if (i_wren)
+ begin
+ if (i_wrfull && (overflow_checking == "OFF"))
+ begin
+ if (((feature_family_has_stratixii_style_ram == 1) &&
+ ((use_eab == "ON") || ((use_eab == "OFF") && (lpm_width != lpm_width_r) && (lpm_width_r != 0)) ||
+ ((lpm_numwords < 16) && (clocks_are_synchronized == "FALSE")))) ||
+ ((feature_family_stratix == 1) && (use_eab == "ON") &&
+ (((lpm_showahead == "ON") && (add_ram_output_register == "OFF")) ||
+ (clocks_are_synchronized == "FALSE_LOW_LATENCY"))))
+ begin
+ if (no_warn == 1'b0)
+ begin
+ $display("Warning : Overflow occurred! Fifo output is unknown until the next reset is asserted.");
+ $display("Time: %0t Instance: %m", $time);
+ no_warn <= 1'b1;
+ end
+ is_overflow <= 1'b1;
+ end
+ end
+ else
+ begin
+ if (i_wrptr_g1 < cnt_mod - 1)
+ i_wrptr_g1 <= i_wrptr_g1 + 1;
+ else
+ i_wrptr_g1 <= 0;
+
+ i_wrptr_g <= i_wrptr_g1;
+
+ if (lpm_width > lpm_width_r)
+ begin
+ for (i = 0; i < WIDTH_RATIO; i = i+1)
+ mem_data[i_wrptr_g*WIDTH_RATIO+i] <= data >> (lpm_width_r*i);
+ end
+ else if (lpm_width < lpm_width_r)
+ begin
+ i_mem_address <= i_wrptr_g1 /WIDTH_RATIO;
+ i_first_bit_position <= (i_wrptr_g1 % WIDTH_RATIO) *lpm_width;
+ for(i = 0; i < lpm_width; i = i+1)
+ mem_data[i_mem_address][i_first_bit_position + i] <= data[i];
+ end
+ else
+ mem_data[i_wrptr_g] <= data;
+ end
+ end
+ i_delayed_wrptr_g <= i_wrptr_g;
+ end
+ end // @(wrclk)
+
+ always @(posedge rdclk)
+ begin
+ if(~aclr)
+ begin
+ if (i_rden && ($time > 0))
+ begin
+ if (i_rdempty && (underflow_checking == "OFF"))
+ begin
+ if (((feature_family_has_stratixii_style_ram == 1) &&
+ ((use_eab == "ON") || ((use_eab == "OFF") && (lpm_width != lpm_width_r) && (lpm_width_r != 0)) ||
+ ((lpm_numwords < 16) && (clocks_are_synchronized == "FALSE")))) ||
+ ((feature_family_stratix == 1) && (use_eab == "ON") &&
+ (((lpm_showahead == "ON") && (add_ram_output_register == "OFF")) ||
+ (clocks_are_synchronized == "FALSE_LOW_LATENCY"))))
+ begin
+ if (no_warn == 1'b0)
+ begin
+ $display("Warning : Underflow occurred! Fifo output is unknown until the next reset is asserted.");
+ $display("Time: %0t Instance: %m", $time);
+ no_warn <= 1'b1;
+ end
+ is_underflow <= 1'b1;
+ end
+ end
+ else
+ begin
+ if (i_rdptr_g1p < cnt_mod_r - 1)
+ i_rdptr_g1p <= i_rdptr_g1p + 1;
+ else
+ i_rdptr_g1p <= 0;
+
+ i_rdptr_g <= i_rdptr_g1p;
+ end
+ end
+ end
+ end
+
+ always @(posedge rdclk)
+ begin
+ if (is_underflow || is_overflow)
+ i_q <= {lpm_width_r{1'bx}};
+ else
+ begin
+ if ((! i_q_is_registered) && ($time > 0))
+ begin
+ if (aclr && ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)))
+ i_q <= {lpm_width_r{1'bx}};
+ else
+ begin
+ if (i_rdempty == 1'b1)
+ i_q <= mem_data[i_rdptr_g];
+ else if (i_rden)
+ i_q <= mem_data[i_rdptr_g1p];
+ end
+ end
+ else if (~aclr && i_rden && ($time > 0))
+ i_q <= mem_data[i_rdptr_g];
+ end
+ end
+
+ // Usedw, Empty, Full
+ always @(i_wrptr_g or i_ws_dgrp or cnt_mod)
+ begin
+ if (i_wrptr_g < (i_ws_dgrp*lpm_width_r/lpm_width))
+ i_wrusedw_tmp <= cnt_mod + i_wrptr_g - i_ws_dgrp*lpm_width_r/lpm_width;
+ else
+ i_wrusedw_tmp <= i_wrptr_g - i_ws_dgrp*lpm_width_r/lpm_width;
+
+ if (lpm_width > lpm_width_r)
+ begin
+ if (i_wrptr_g == (i_ws_dgrp/WIDTH_RATIO))
+ i_wrempty_speed <= 1;
+ else
+ i_wrempty_speed <= 0;
+ end
+ else
+ begin
+ if ((i_wrptr_g/WIDTH_RATIO) == i_ws_dgrp)
+ i_wrempty_speed <= 1;
+ else
+ i_wrempty_speed <= 0;
+ end
+ end // @(i_wrptr_g or i_ws_dgrp)
+
+ always @(i_rdptr_g or i_rs_dgwp or cnt_mod)
+ begin
+ if ((i_rs_dgwp*lpm_width/lpm_width_r) < i_rdptr_g)
+ i_rdusedw_tmp <= (cnt_mod + i_rs_dgwp)*lpm_width/lpm_width_r - i_rdptr_g;
+ else
+ i_rdusedw_tmp <= i_rs_dgwp*lpm_width/lpm_width_r - i_rdptr_g;
+
+ if (lpm_width < lpm_width_r)
+ begin
+ if ((i_rdptr_g*lpm_width_r/lpm_width) == (i_rs_dgwp + WIDTH_RATIO) %cnt_mod)
+ i_rdfull_speed <= 1;
+ else
+ i_rdfull_speed <= 0;
+ end
+ else
+ begin
+ if (i_rdptr_g == ((i_rs_dgwp +1) % cnt_mod)*lpm_width/lpm_width_r)
+ i_rdfull_speed <= 1;
+ else
+ i_rdfull_speed <= 0;
+ end
+ end // @(i_wrptr_g or i_rs_dgwp)
+
+ always @(i_wrptr_g1 or i_ws_dgrp or cnt_mod)
+ begin
+ if (lpm_width < lpm_width_r)
+ begin
+ if ((i_wrptr_g1 + WIDTH_RATIO -1) % cnt_mod == (i_ws_dgrp*lpm_width_r/lpm_width))
+ i_wrfull <= 1;
+ else
+ i_wrfull <= 0;
+ end
+ else
+ begin
+ if (i_wrptr_g1 == (i_ws_dgrp*lpm_width_r/lpm_width))
+ i_wrfull <= 1;
+ else
+ i_wrfull <= 0;
+ end
+ end // @(i_wrptr_g1 or i_ws_dgrp)
+
+ always @(i_rdptr_g or i_rs_dgwp)
+ begin
+ if (lpm_width > lpm_width_r)
+ begin
+ if ((i_rdptr_g/WIDTH_RATIO) == i_rs_dgwp)
+ i_rdempty <= 1;
+ else
+ i_rdempty <= 0;
+ end
+ else
+ begin
+ if (i_rdptr_g == i_rs_dgwp/WIDTH_RATIO)
+ i_rdempty <= 1;
+ else
+ i_rdempty <= 0;
+ end
+ end // @(i_rdptr_g or i_rs_dgwp)
+
+ always @(posedge rdclk)
+ begin
+ i_rdfull_area <= i_wrfull_wreg;
+ i_rdempty_rreg <= i_rdempty;
+ end // @(posedge rdclk)
+
+ always @(posedge wrclk)
+ begin
+ i_wrempty_area <= i_rdempty_rreg;
+
+ if ((~aclr) && (write_aclr_synch == "ON") && ((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)))
+ i_wrfull_wreg <= (i_wrfull | write_aclr);
+ else
+ i_wrfull_wreg <= i_wrfull;
+ end // @(posedge wrclk)
+
+// CONTINOUS ASSIGNMENT
+ assign i_rden = (underflow_checking == "OFF") ? rdreq : (rdreq && !i_rdempty);
+ assign i_wren = (((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)) &&
+ (write_aclr_synch == "ON")) ?
+ ((overflow_checking == "OFF") ? wrreq && (!sync_aclr)
+ : (wrreq && !(i_wrfull | sync_aclr))) :
+ (overflow_checking == "OFF") ? wrreq : (wrreq && !i_wrfull);
+ assign rdempty = (is_underflow || is_overflow) ? 1'bx : i_rdempty;
+ assign wrempty = (is_underflow || is_overflow) ? 1'bx :
+ (use_wrempty_speed) ? i_wrempty_speed : i_wrempty_area;
+ assign rdfull = (is_underflow || is_overflow) ? 1'bx :
+ (use_rdfull_speed) ? i_rdfull_speed : i_rdfull_area;
+ assign wrfull = (is_underflow || is_overflow) ? 1'bx :
+ (((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)) &&
+ (write_aclr_synch == "ON")) ? (i_wrfull | write_aclr) : i_wrfull;
+ assign wrusedw = (is_underflow || is_overflow) ? {lpm_widthu{1'bx}} :
+ i_wrusedw[lpm_widthu-1:0];
+ assign rdusedw = (is_underflow || is_overflow) ? {lpm_widthu_r{1'bx}} :
+ i_rdusedw[lpm_widthu_r-1:0];
+ assign q = (is_underflow || is_overflow) ? {lpm_width_r{1'bx}} : i_q;
+ assign write_aclr = (((feature_family_stratixii == 1) ||
+ (feature_family_cycloneii == 1)) &&
+ (write_aclr_synch == "ON")) ? sync_aclr : aclr;
+
+endmodule // dcfifo_low_latency
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo_mixed_widths
+//
+// Description : Mixed widths Dual Clocks FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo_mixed_widths ( data, rdclk, wrclk, aclr, rdreq, wrreq,
+ rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_width = 1;
+ parameter lpm_widthu = 1;
+ parameter lpm_width_r = lpm_width;
+ parameter lpm_widthu_r = lpm_widthu;
+ parameter lpm_numwords = 2;
+ parameter delay_rdusedw = 1;
+ parameter delay_wrusedw = 1;
+ parameter rdsync_delaypipe = 0;
+ parameter wrsync_delaypipe = 0;
+ parameter intended_device_family = "Stratix";
+ parameter lpm_showahead = "OFF";
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter clocks_are_synchronized = "FALSE";
+ parameter use_eab = "ON";
+ parameter add_ram_output_register = "OFF";
+ parameter lpm_hint = "USE_EAB=ON";
+ parameter lpm_type = "dcfifo_mixed_widths";
+ parameter add_usedw_msb_bit = "OFF";
+ parameter write_aclr_synch = "OFF";
+
+// LOCAL_PARAMETERS_BEGIN
+
+ parameter add_width = 1;
+ parameter ram_block_type = "AUTO";
+
+ parameter FAMILY_HAS_STRATIXII_STYLE_RAM = (((((intended_device_family == "Stratix II") || (intended_device_family == "STRATIX II") || (intended_device_family == "stratix ii") || (intended_device_family == "StratixII") || (intended_device_family == "STRATIXII") || (intended_device_family == "stratixii") || (intended_device_family == "Armstrong") || (intended_device_family == "ARMSTRONG") || (intended_device_family == "armstrong"))
+ || ((intended_device_family == "HardCopy II") || (intended_device_family == "HARDCOPY II") || (intended_device_family == "hardcopy ii") || (intended_device_family == "HardCopyII") || (intended_device_family == "HARDCOPYII") || (intended_device_family == "hardcopyii") || (intended_device_family == "Fusion") || (intended_device_family == "FUSION") || (intended_device_family == "fusion"))
+ || (((intended_device_family == "Stratix II GX") || (intended_device_family == "STRATIX II GX") || (intended_device_family == "stratix ii gx") || (intended_device_family == "StratixIIGX") || (intended_device_family == "STRATIXIIGX") || (intended_device_family == "stratixiigx"))
+ || ((intended_device_family == "Arria GX") || (intended_device_family == "ARRIA GX") || (intended_device_family == "arria gx") || (intended_device_family == "ArriaGX") || (intended_device_family == "ARRIAGX") || (intended_device_family == "arriagx") || (intended_device_family == "Stratix II GX Lite") || (intended_device_family == "STRATIX II GX LITE") || (intended_device_family == "stratix ii gx lite") || (intended_device_family == "StratixIIGXLite") || (intended_device_family == "STRATIXIIGXLITE") || (intended_device_family == "stratixiigxlite"))
+ ) || (((intended_device_family == "Stratix III") || (intended_device_family == "STRATIX III") || (intended_device_family == "stratix iii") || (intended_device_family == "StratixIII") || (intended_device_family == "STRATIXIII") || (intended_device_family == "stratixiii") || (intended_device_family == "Titan") || (intended_device_family == "TITAN") || (intended_device_family == "titan") || (intended_device_family == "SIII") || (intended_device_family == "siii"))
+ || (((intended_device_family == "Stratix IV") || (intended_device_family == "STRATIX IV") || (intended_device_family == "stratix iv") || (intended_device_family == "TGX") || (intended_device_family == "tgx") || (intended_device_family == "StratixIV") || (intended_device_family == "STRATIXIV") || (intended_device_family == "stratixiv") || (intended_device_family == "Stratix IV (GT)") || (intended_device_family == "STRATIX IV (GT)") || (intended_device_family == "stratix iv (gt)") || (intended_device_family == "Stratix IV (GX)") || (intended_device_family == "STRATIX IV (GX)") || (intended_device_family == "stratix iv (gx)") || (intended_device_family == "Stratix IV (E)") || (intended_device_family == "STRATIX IV (E)") || (intended_device_family == "stratix iv (e)") || (intended_device_family == "StratixIV(GT)") || (intended_device_family == "STRATIXIV(GT)") || (intended_device_family == "stratixiv(gt)") || (intended_device_family == "StratixIV(GX)") || (intended_device_family == "STRATIXIV(GX)") || (intended_device_family == "stratixiv(gx)") || (intended_device_family == "StratixIV(E)") || (intended_device_family == "STRATIXIV(E)") || (intended_device_family == "stratixiv(e)") || (intended_device_family == "StratixIIIGX") || (intended_device_family == "STRATIXIIIGX") || (intended_device_family == "stratixiiigx") || (intended_device_family == "Stratix IV (GT/GX/E)") || (intended_device_family == "STRATIX IV (GT/GX/E)") || (intended_device_family == "stratix iv (gt/gx/e)") || (intended_device_family == "Stratix IV (GT/E/GX)") || (intended_device_family == "STRATIX IV (GT/E/GX)") || (intended_device_family == "stratix iv (gt/e/gx)") || (intended_device_family == "Stratix IV (E/GT/GX)") || (intended_device_family == "STRATIX IV (E/GT/GX)") || (intended_device_family == "stratix iv (e/gt/gx)") || (intended_device_family == "Stratix IV (E/GX/GT)") || (intended_device_family == "STRATIX IV (E/GX/GT)") || (intended_device_family == "stratix iv (e/gx/gt)") || (intended_device_family == "StratixIV(GT/GX/E)") || (intended_device_family == "STRATIXIV(GT/GX/E)") || (intended_device_family == "stratixiv(gt/gx/e)") || (intended_device_family == "StratixIV(GT/E/GX)") || (intended_device_family == "STRATIXIV(GT/E/GX)") || (intended_device_family == "stratixiv(gt/e/gx)") || (intended_device_family == "StratixIV(E/GX/GT)") || (intended_device_family == "STRATIXIV(E/GX/GT)") || (intended_device_family == "stratixiv(e/gx/gt)") || (intended_device_family == "StratixIV(E/GT/GX)") || (intended_device_family == "STRATIXIV(E/GT/GX)") || (intended_device_family == "stratixiv(e/gt/gx)") || (intended_device_family == "Stratix IV (GX/E)") || (intended_device_family == "STRATIX IV (GX/E)") || (intended_device_family == "stratix iv (gx/e)") || (intended_device_family == "StratixIV(GX/E)") || (intended_device_family == "STRATIXIV(GX/E)") || (intended_device_family == "stratixiv(gx/e)"))
+ || ((intended_device_family == "Arria II GX") || (intended_device_family == "ARRIA II GX") || (intended_device_family == "arria ii gx") || (intended_device_family == "ArriaIIGX") || (intended_device_family == "ARRIAIIGX") || (intended_device_family == "arriaiigx") || (intended_device_family == "Arria IIGX") || (intended_device_family == "ARRIA IIGX") || (intended_device_family == "arria iigx") || (intended_device_family == "ArriaII GX") || (intended_device_family == "ARRIAII GX") || (intended_device_family == "arriaii gx") || (intended_device_family == "Arria II") || (intended_device_family == "ARRIA II") || (intended_device_family == "arria ii") || (intended_device_family == "ArriaII") || (intended_device_family == "ARRIAII") || (intended_device_family == "arriaii") || (intended_device_family == "Arria II (GX/E)") || (intended_device_family == "ARRIA II (GX/E)") || (intended_device_family == "arria ii (gx/e)") || (intended_device_family == "ArriaII(GX/E)") || (intended_device_family == "ARRIAII(GX/E)") || (intended_device_family == "arriaii(gx/e)") || (intended_device_family == "PIRANHA") || (intended_device_family == "piranha"))
+ || ((intended_device_family == "HardCopy IV") || (intended_device_family == "HARDCOPY IV") || (intended_device_family == "hardcopy iv") || (intended_device_family == "HardCopyIV") || (intended_device_family == "HARDCOPYIV") || (intended_device_family == "hardcopyiv") || (intended_device_family == "HardCopy IV (GX)") || (intended_device_family == "HARDCOPY IV (GX)") || (intended_device_family == "hardcopy iv (gx)") || (intended_device_family == "HardCopy IV (E)") || (intended_device_family == "HARDCOPY IV (E)") || (intended_device_family == "hardcopy iv (e)") || (intended_device_family == "HardCopyIV(GX)") || (intended_device_family == "HARDCOPYIV(GX)") || (intended_device_family == "hardcopyiv(gx)") || (intended_device_family == "HardCopyIV(E)") || (intended_device_family == "HARDCOPYIV(E)") || (intended_device_family == "hardcopyiv(e)") || (intended_device_family == "HCXIV") || (intended_device_family == "hcxiv") || (intended_device_family == "HardCopy IV (GX/E)") || (intended_device_family == "HARDCOPY IV (GX/E)") || (intended_device_family == "hardcopy iv (gx/e)") || (intended_device_family == "HardCopy IV (E/GX)") || (intended_device_family == "HARDCOPY IV (E/GX)") || (intended_device_family == "hardcopy iv (e/gx)") || (intended_device_family == "HardCopyIV(GX/E)") || (intended_device_family == "HARDCOPYIV(GX/E)") || (intended_device_family == "hardcopyiv(gx/e)") || (intended_device_family == "HardCopyIV(E/GX)") || (intended_device_family == "HARDCOPYIV(E/GX)") || (intended_device_family == "hardcopyiv(e/gx)"))
+ || (((intended_device_family == "Stratix V") || (intended_device_family == "STRATIX V") || (intended_device_family == "stratix v") || (intended_device_family == "StratixV") || (intended_device_family == "STRATIXV") || (intended_device_family == "stratixv") || (intended_device_family == "Stratix V (GS)") || (intended_device_family == "STRATIX V (GS)") || (intended_device_family == "stratix v (gs)") || (intended_device_family == "StratixV(GS)") || (intended_device_family == "STRATIXV(GS)") || (intended_device_family == "stratixv(gs)") || (intended_device_family == "Stratix V (GX)") || (intended_device_family == "STRATIX V (GX)") || (intended_device_family == "stratix v (gx)") || (intended_device_family == "StratixV(GX)") || (intended_device_family == "STRATIXV(GX)") || (intended_device_family == "stratixv(gx)") || (intended_device_family == "Stratix V (GS/GX)") || (intended_device_family == "STRATIX V (GS/GX)") || (intended_device_family == "stratix v (gs/gx)") || (intended_device_family == "StratixV(GS/GX)") || (intended_device_family == "STRATIXV(GS/GX)") || (intended_device_family == "stratixv(gs/gx)") || (intended_device_family == "Stratix V (GX/GS)") || (intended_device_family == "STRATIX V (GX/GS)") || (intended_device_family == "stratix v (gx/gs)") || (intended_device_family == "StratixV(GX/GS)") || (intended_device_family == "STRATIXV(GX/GS)") || (intended_device_family == "stratixv(gx/gs)"))
+ ) || (((intended_device_family == "Arria II GZ") || (intended_device_family == "ARRIA II GZ") || (intended_device_family == "arria ii gz") || (intended_device_family == "ArriaII GZ") || (intended_device_family == "ARRIAII GZ") || (intended_device_family == "arriaii gz") || (intended_device_family == "Arria IIGZ") || (intended_device_family == "ARRIA IIGZ") || (intended_device_family == "arria iigz") || (intended_device_family == "ArriaIIGZ") || (intended_device_family == "ARRIAIIGZ") || (intended_device_family == "arriaiigz"))
+ ) ) || ((intended_device_family == "HardCopy III") || (intended_device_family == "HARDCOPY III") || (intended_device_family == "hardcopy iii") || (intended_device_family == "HardCopyIII") || (intended_device_family == "HARDCOPYIII") || (intended_device_family == "hardcopyiii") || (intended_device_family == "HCX") || (intended_device_family == "hcx"))
+ ) ) || (((intended_device_family == "Cyclone II") || (intended_device_family == "CYCLONE II") || (intended_device_family == "cyclone ii") || (intended_device_family == "Cycloneii") || (intended_device_family == "CYCLONEII") || (intended_device_family == "cycloneii") || (intended_device_family == "Magellan") || (intended_device_family == "MAGELLAN") || (intended_device_family == "magellan"))
+ || (((intended_device_family == "Cyclone III") || (intended_device_family == "CYCLONE III") || (intended_device_family == "cyclone iii") || (intended_device_family == "CycloneIII") || (intended_device_family == "CYCLONEIII") || (intended_device_family == "cycloneiii") || (intended_device_family == "Barracuda") || (intended_device_family == "BARRACUDA") || (intended_device_family == "barracuda") || (intended_device_family == "Cuda") || (intended_device_family == "CUDA") || (intended_device_family == "cuda") || (intended_device_family == "CIII") || (intended_device_family == "ciii"))
+ || ((intended_device_family == "Cyclone III LS") || (intended_device_family == "CYCLONE III LS") || (intended_device_family == "cyclone iii ls") || (intended_device_family == "CycloneIIILS") || (intended_device_family == "CYCLONEIIILS") || (intended_device_family == "cycloneiiils") || (intended_device_family == "Cyclone III LPS") || (intended_device_family == "CYCLONE III LPS") || (intended_device_family == "cyclone iii lps") || (intended_device_family == "Cyclone LPS") || (intended_device_family == "CYCLONE LPS") || (intended_device_family == "cyclone lps") || (intended_device_family == "CycloneLPS") || (intended_device_family == "CYCLONELPS") || (intended_device_family == "cyclonelps") || (intended_device_family == "Tarpon") || (intended_device_family == "TARPON") || (intended_device_family == "tarpon") || (intended_device_family == "Cyclone IIIE") || (intended_device_family == "CYCLONE IIIE") || (intended_device_family == "cyclone iiie"))
+ || (((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
+ || ((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
+ ) || (((intended_device_family == "Cyclone IV E") || (intended_device_family == "CYCLONE IV E") || (intended_device_family == "cyclone iv e") || (intended_device_family == "CycloneIV E") || (intended_device_family == "CYCLONEIV E") || (intended_device_family == "cycloneiv e") || (intended_device_family == "Cyclone IVE") || (intended_device_family == "CYCLONE IVE") || (intended_device_family == "cyclone ive") || (intended_device_family == "CycloneIVE") || (intended_device_family == "CYCLONEIVE") || (intended_device_family == "cycloneive"))
+ ) ) ) ))
+ ? 1 : 0;
+
+ parameter FAMILY_HAS_STRATIXIII_STYLE_RAM = (((((intended_device_family == "Stratix III") || (intended_device_family == "STRATIX III") || (intended_device_family == "stratix iii") || (intended_device_family == "StratixIII") || (intended_device_family == "STRATIXIII") || (intended_device_family == "stratixiii") || (intended_device_family == "Titan") || (intended_device_family == "TITAN") || (intended_device_family == "titan") || (intended_device_family == "SIII") || (intended_device_family == "siii"))
+ || (((intended_device_family == "Stratix IV") || (intended_device_family == "STRATIX IV") || (intended_device_family == "stratix iv") || (intended_device_family == "TGX") || (intended_device_family == "tgx") || (intended_device_family == "StratixIV") || (intended_device_family == "STRATIXIV") || (intended_device_family == "stratixiv") || (intended_device_family == "Stratix IV (GT)") || (intended_device_family == "STRATIX IV (GT)") || (intended_device_family == "stratix iv (gt)") || (intended_device_family == "Stratix IV (GX)") || (intended_device_family == "STRATIX IV (GX)") || (intended_device_family == "stratix iv (gx)") || (intended_device_family == "Stratix IV (E)") || (intended_device_family == "STRATIX IV (E)") || (intended_device_family == "stratix iv (e)") || (intended_device_family == "StratixIV(GT)") || (intended_device_family == "STRATIXIV(GT)") || (intended_device_family == "stratixiv(gt)") || (intended_device_family == "StratixIV(GX)") || (intended_device_family == "STRATIXIV(GX)") || (intended_device_family == "stratixiv(gx)") || (intended_device_family == "StratixIV(E)") || (intended_device_family == "STRATIXIV(E)") || (intended_device_family == "stratixiv(e)") || (intended_device_family == "StratixIIIGX") || (intended_device_family == "STRATIXIIIGX") || (intended_device_family == "stratixiiigx") || (intended_device_family == "Stratix IV (GT/GX/E)") || (intended_device_family == "STRATIX IV (GT/GX/E)") || (intended_device_family == "stratix iv (gt/gx/e)") || (intended_device_family == "Stratix IV (GT/E/GX)") || (intended_device_family == "STRATIX IV (GT/E/GX)") || (intended_device_family == "stratix iv (gt/e/gx)") || (intended_device_family == "Stratix IV (E/GT/GX)") || (intended_device_family == "STRATIX IV (E/GT/GX)") || (intended_device_family == "stratix iv (e/gt/gx)") || (intended_device_family == "Stratix IV (E/GX/GT)") || (intended_device_family == "STRATIX IV (E/GX/GT)") || (intended_device_family == "stratix iv (e/gx/gt)") || (intended_device_family == "StratixIV(GT/GX/E)") || (intended_device_family == "STRATIXIV(GT/GX/E)") || (intended_device_family == "stratixiv(gt/gx/e)") || (intended_device_family == "StratixIV(GT/E/GX)") || (intended_device_family == "STRATIXIV(GT/E/GX)") || (intended_device_family == "stratixiv(gt/e/gx)") || (intended_device_family == "StratixIV(E/GX/GT)") || (intended_device_family == "STRATIXIV(E/GX/GT)") || (intended_device_family == "stratixiv(e/gx/gt)") || (intended_device_family == "StratixIV(E/GT/GX)") || (intended_device_family == "STRATIXIV(E/GT/GX)") || (intended_device_family == "stratixiv(e/gt/gx)") || (intended_device_family == "Stratix IV (GX/E)") || (intended_device_family == "STRATIX IV (GX/E)") || (intended_device_family == "stratix iv (gx/e)") || (intended_device_family == "StratixIV(GX/E)") || (intended_device_family == "STRATIXIV(GX/E)") || (intended_device_family == "stratixiv(gx/e)"))
+ || ((intended_device_family == "Arria II GX") || (intended_device_family == "ARRIA II GX") || (intended_device_family == "arria ii gx") || (intended_device_family == "ArriaIIGX") || (intended_device_family == "ARRIAIIGX") || (intended_device_family == "arriaiigx") || (intended_device_family == "Arria IIGX") || (intended_device_family == "ARRIA IIGX") || (intended_device_family == "arria iigx") || (intended_device_family == "ArriaII GX") || (intended_device_family == "ARRIAII GX") || (intended_device_family == "arriaii gx") || (intended_device_family == "Arria II") || (intended_device_family == "ARRIA II") || (intended_device_family == "arria ii") || (intended_device_family == "ArriaII") || (intended_device_family == "ARRIAII") || (intended_device_family == "arriaii") || (intended_device_family == "Arria II (GX/E)") || (intended_device_family == "ARRIA II (GX/E)") || (intended_device_family == "arria ii (gx/e)") || (intended_device_family == "ArriaII(GX/E)") || (intended_device_family == "ARRIAII(GX/E)") || (intended_device_family == "arriaii(gx/e)") || (intended_device_family == "PIRANHA") || (intended_device_family == "piranha"))
+ || ((intended_device_family == "HardCopy IV") || (intended_device_family == "HARDCOPY IV") || (intended_device_family == "hardcopy iv") || (intended_device_family == "HardCopyIV") || (intended_device_family == "HARDCOPYIV") || (intended_device_family == "hardcopyiv") || (intended_device_family == "HardCopy IV (GX)") || (intended_device_family == "HARDCOPY IV (GX)") || (intended_device_family == "hardcopy iv (gx)") || (intended_device_family == "HardCopy IV (E)") || (intended_device_family == "HARDCOPY IV (E)") || (intended_device_family == "hardcopy iv (e)") || (intended_device_family == "HardCopyIV(GX)") || (intended_device_family == "HARDCOPYIV(GX)") || (intended_device_family == "hardcopyiv(gx)") || (intended_device_family == "HardCopyIV(E)") || (intended_device_family == "HARDCOPYIV(E)") || (intended_device_family == "hardcopyiv(e)") || (intended_device_family == "HCXIV") || (intended_device_family == "hcxiv") || (intended_device_family == "HardCopy IV (GX/E)") || (intended_device_family == "HARDCOPY IV (GX/E)") || (intended_device_family == "hardcopy iv (gx/e)") || (intended_device_family == "HardCopy IV (E/GX)") || (intended_device_family == "HARDCOPY IV (E/GX)") || (intended_device_family == "hardcopy iv (e/gx)") || (intended_device_family == "HardCopyIV(GX/E)") || (intended_device_family == "HARDCOPYIV(GX/E)") || (intended_device_family == "hardcopyiv(gx/e)") || (intended_device_family == "HardCopyIV(E/GX)") || (intended_device_family == "HARDCOPYIV(E/GX)") || (intended_device_family == "hardcopyiv(e/gx)"))
+ || (((intended_device_family == "Stratix V") || (intended_device_family == "STRATIX V") || (intended_device_family == "stratix v") || (intended_device_family == "StratixV") || (intended_device_family == "STRATIXV") || (intended_device_family == "stratixv") || (intended_device_family == "Stratix V (GS)") || (intended_device_family == "STRATIX V (GS)") || (intended_device_family == "stratix v (gs)") || (intended_device_family == "StratixV(GS)") || (intended_device_family == "STRATIXV(GS)") || (intended_device_family == "stratixv(gs)") || (intended_device_family == "Stratix V (GX)") || (intended_device_family == "STRATIX V (GX)") || (intended_device_family == "stratix v (gx)") || (intended_device_family == "StratixV(GX)") || (intended_device_family == "STRATIXV(GX)") || (intended_device_family == "stratixv(gx)") || (intended_device_family == "Stratix V (GS/GX)") || (intended_device_family == "STRATIX V (GS/GX)") || (intended_device_family == "stratix v (gs/gx)") || (intended_device_family == "StratixV(GS/GX)") || (intended_device_family == "STRATIXV(GS/GX)") || (intended_device_family == "stratixv(gs/gx)") || (intended_device_family == "Stratix V (GX/GS)") || (intended_device_family == "STRATIX V (GX/GS)") || (intended_device_family == "stratix v (gx/gs)") || (intended_device_family == "StratixV(GX/GS)") || (intended_device_family == "STRATIXV(GX/GS)") || (intended_device_family == "stratixv(gx/gs)"))
+ ) || (((intended_device_family == "Arria II GZ") || (intended_device_family == "ARRIA II GZ") || (intended_device_family == "arria ii gz") || (intended_device_family == "ArriaII GZ") || (intended_device_family == "ARRIAII GZ") || (intended_device_family == "arriaii gz") || (intended_device_family == "Arria IIGZ") || (intended_device_family == "ARRIA IIGZ") || (intended_device_family == "arria iigz") || (intended_device_family == "ArriaIIGZ") || (intended_device_family == "ARRIAIIGZ") || (intended_device_family == "arriaiigz"))
+ ) ) || ((intended_device_family == "HardCopy III") || (intended_device_family == "HARDCOPY III") || (intended_device_family == "hardcopy iii") || (intended_device_family == "HardCopyIII") || (intended_device_family == "HARDCOPYIII") || (intended_device_family == "hardcopyiii") || (intended_device_family == "HCX") || (intended_device_family == "hcx"))
+ ) || (((intended_device_family == "Cyclone III") || (intended_device_family == "CYCLONE III") || (intended_device_family == "cyclone iii") || (intended_device_family == "CycloneIII") || (intended_device_family == "CYCLONEIII") || (intended_device_family == "cycloneiii") || (intended_device_family == "Barracuda") || (intended_device_family == "BARRACUDA") || (intended_device_family == "barracuda") || (intended_device_family == "Cuda") || (intended_device_family == "CUDA") || (intended_device_family == "cuda") || (intended_device_family == "CIII") || (intended_device_family == "ciii"))
+ || ((intended_device_family == "Cyclone III LS") || (intended_device_family == "CYCLONE III LS") || (intended_device_family == "cyclone iii ls") || (intended_device_family == "CycloneIIILS") || (intended_device_family == "CYCLONEIIILS") || (intended_device_family == "cycloneiiils") || (intended_device_family == "Cyclone III LPS") || (intended_device_family == "CYCLONE III LPS") || (intended_device_family == "cyclone iii lps") || (intended_device_family == "Cyclone LPS") || (intended_device_family == "CYCLONE LPS") || (intended_device_family == "cyclone lps") || (intended_device_family == "CycloneLPS") || (intended_device_family == "CYCLONELPS") || (intended_device_family == "cyclonelps") || (intended_device_family == "Tarpon") || (intended_device_family == "TARPON") || (intended_device_family == "tarpon") || (intended_device_family == "Cyclone IIIE") || (intended_device_family == "CYCLONE IIIE") || (intended_device_family == "cyclone iiie"))
+ || (((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
+ || ((intended_device_family == "Cyclone IV GX") || (intended_device_family == "CYCLONE IV GX") || (intended_device_family == "cyclone iv gx") || (intended_device_family == "Cyclone IVGX") || (intended_device_family == "CYCLONE IVGX") || (intended_device_family == "cyclone ivgx") || (intended_device_family == "CycloneIV GX") || (intended_device_family == "CYCLONEIV GX") || (intended_device_family == "cycloneiv gx") || (intended_device_family == "CycloneIVGX") || (intended_device_family == "CYCLONEIVGX") || (intended_device_family == "cycloneivgx") || (intended_device_family == "Cyclone IV") || (intended_device_family == "CYCLONE IV") || (intended_device_family == "cyclone iv") || (intended_device_family == "CycloneIV") || (intended_device_family == "CYCLONEIV") || (intended_device_family == "cycloneiv") || (intended_device_family == "Cyclone IV (GX)") || (intended_device_family == "CYCLONE IV (GX)") || (intended_device_family == "cyclone iv (gx)") || (intended_device_family == "CycloneIV(GX)") || (intended_device_family == "CYCLONEIV(GX)") || (intended_device_family == "cycloneiv(gx)") || (intended_device_family == "Cyclone III GX") || (intended_device_family == "CYCLONE III GX") || (intended_device_family == "cyclone iii gx") || (intended_device_family == "CycloneIII GX") || (intended_device_family == "CYCLONEIII GX") || (intended_device_family == "cycloneiii gx") || (intended_device_family == "Cyclone IIIGX") || (intended_device_family == "CYCLONE IIIGX") || (intended_device_family == "cyclone iiigx") || (intended_device_family == "CycloneIIIGX") || (intended_device_family == "CYCLONEIIIGX") || (intended_device_family == "cycloneiiigx") || (intended_device_family == "Cyclone III GL") || (intended_device_family == "CYCLONE III GL") || (intended_device_family == "cyclone iii gl") || (intended_device_family == "CycloneIII GL") || (intended_device_family == "CYCLONEIII GL") || (intended_device_family == "cycloneiii gl") || (intended_device_family == "Cyclone IIIGL") || (intended_device_family == "CYCLONE IIIGL") || (intended_device_family == "cyclone iiigl") || (intended_device_family == "CycloneIIIGL") || (intended_device_family == "CYCLONEIIIGL") || (intended_device_family == "cycloneiiigl") || (intended_device_family == "Stingray") || (intended_device_family == "STINGRAY") || (intended_device_family == "stingray"))
+ ) || (((intended_device_family == "Cyclone IV E") || (intended_device_family == "CYCLONE IV E") || (intended_device_family == "cyclone iv e") || (intended_device_family == "CycloneIV E") || (intended_device_family == "CYCLONEIV E") || (intended_device_family == "cycloneiv e") || (intended_device_family == "Cyclone IVE") || (intended_device_family == "CYCLONE IVE") || (intended_device_family == "cyclone ive") || (intended_device_family == "CycloneIVE") || (intended_device_family == "CYCLONEIVE") || (intended_device_family == "cycloneive"))
+ ) ) ))
+ ? 1 : 0;
+
+ parameter WRITE_SIDE_SYNCHRONIZERS = (wrsync_delaypipe != 0) ? wrsync_delaypipe :
+ (((FAMILY_HAS_STRATIXII_STYLE_RAM == 1) || (FAMILY_HAS_STRATIXIII_STYLE_RAM == 1))
+ && (clocks_are_synchronized == "FALSE"))
+ ? 4 : 3;
+
+ parameter READ_SIDE_SYNCHRONIZERS = (rdsync_delaypipe != 0) ? rdsync_delaypipe :
+ (((FAMILY_HAS_STRATIXII_STYLE_RAM == 1) || (FAMILY_HAS_STRATIXIII_STYLE_RAM == 1))
+ && (clocks_are_synchronized == "FALSE"))
+ ? 4 : 3;
+
+// LOCAL_PARAMETERS_END
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] data;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ input rdreq;
+ input wrreq;
+
+// OUTPUT PORT DECLARATION
+ output rdfull;
+ output wrfull;
+ output rdempty;
+ output wrempty;
+ output [lpm_widthu_r-1:0] rdusedw;
+ output [lpm_widthu-1:0] wrusedw;
+ output [lpm_width_r-1:0] q;
+
+// INTERNAL WIRE DECLARATION
+ wire w_rdfull_s;
+ wire w_wrfull_s;
+ wire w_rdempty_s;
+ wire w_wrempty_s;
+ wire w_rdfull_a;
+ wire w_wrfull_a;
+ wire w_rdempty_a;
+ wire w_wrempty_a;
+ wire w_rdfull_l;
+ wire w_wrfull_l;
+ wire w_rdempty_l;
+ wire w_wrempty_l;
+ wire [lpm_widthu-1:0] w_rdusedw_s;
+ wire [lpm_widthu-1:0] w_wrusedw_s;
+ wire [lpm_widthu-1:0] w_rdusedw_a;
+ wire [lpm_widthu-1:0] w_wrusedw_a;
+ wire [lpm_widthu_r-1:0] w_rdusedw_l;
+ wire [lpm_widthu-1:0] w_wrusedw_l;
+ wire [lpm_width-1:0] w_q_s;
+ wire [lpm_width-1:0] w_q_a;
+ wire [lpm_width_r-1:0] w_q_l;
+
+// INTERNAL REGISTER DECLARATION
+ reg feature_family_has_stratixii_style_ram;
+ reg feature_family_stratix;
+ reg use_low_latency_fifo;
+
+// INTERNAL TRI DECLARATION
+ tri0 aclr;
+
+// COMPONENT INSTANTIATIONS
+ ALTERA_DEVICE_FAMILIES dev ();
+
+ initial
+ begin
+ feature_family_has_stratixii_style_ram = dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family);
+ feature_family_stratix = dev.FEATURE_FAMILY_STRATIX(intended_device_family);
+
+ use_low_latency_fifo = (((feature_family_has_stratixii_style_ram == 1) &&
+ ((use_eab == "ON") || ((use_eab == "OFF") && (lpm_width != lpm_width_r) && (lpm_width_r != 0)) ||
+ ((lpm_numwords < 16) && (clocks_are_synchronized == "FALSE")))) ||
+ ((feature_family_stratix == 1) && (use_eab == "ON") &&
+ (((lpm_showahead == "ON") && (add_ram_output_register == "OFF")) ||
+ (clocks_are_synchronized == "FALSE_LOW_LATENCY"))));
+ end
+
+ generate
+ if (clocks_are_synchronized == "TRUE")
+ begin : dcfifo_sync
+ dcfifo_sync #(
+ .lpm_width (lpm_width),
+ .lpm_widthu (lpm_widthu),
+ .lpm_numwords (lpm_numwords),
+ .intended_device_family (intended_device_family),
+ .lpm_showahead (lpm_showahead),
+ .underflow_checking (underflow_checking),
+ .overflow_checking (overflow_checking),
+ .use_eab (use_eab),
+ .add_ram_output_register (add_ram_output_register))
+ SYNC (
+ .data (data),
+ .rdclk (rdclk),
+ .wrclk (wrclk),
+ .aclr (aclr),
+ .rdreq (rdreq),
+ .wrreq (wrreq),
+ .rdfull (w_rdfull_s),
+ .wrfull (w_wrfull_s),
+ .rdempty (w_rdempty_s),
+ .wrempty (w_wrempty_s),
+ .rdusedw (w_rdusedw_s),
+ .wrusedw (w_wrusedw_s),
+ .q (w_q_s));
+ end
+ endgenerate
+
+ generate
+ if (clocks_are_synchronized != "TRUE")
+ begin : dcfifo_async
+ dcfifo_async #(
+ .lpm_width (lpm_width),
+ .lpm_widthu (lpm_widthu),
+ .lpm_numwords (lpm_numwords),
+ .delay_rdusedw (delay_rdusedw),
+ .delay_wrusedw (delay_wrusedw),
+ .rdsync_delaypipe (READ_SIDE_SYNCHRONIZERS),
+ .wrsync_delaypipe (WRITE_SIDE_SYNCHRONIZERS),
+ .intended_device_family (intended_device_family),
+ .lpm_showahead (lpm_showahead),
+ .underflow_checking (underflow_checking),
+ .overflow_checking (overflow_checking),
+ .use_eab (use_eab),
+ .add_ram_output_register (add_ram_output_register))
+ ASYNC (
+ .data (data),
+ .rdclk (rdclk),
+ .wrclk (wrclk),
+ .aclr (aclr),
+ .rdreq (rdreq),
+ .wrreq (wrreq),
+ .rdfull (w_rdfull_a),
+ .wrfull (w_wrfull_a),
+ .rdempty (w_rdempty_a),
+ .wrempty (w_wrempty_a),
+ .rdusedw (w_rdusedw_a),
+ .wrusedw (w_wrusedw_a),
+ .q (w_q_a) );
+ end
+ endgenerate
+
+ dcfifo_low_latency LOWLATENCY (
+ .data (data),
+ .rdclk (rdclk),
+ .wrclk (wrclk),
+ .aclr (aclr),
+ .rdreq (rdreq),
+ .wrreq (wrreq),
+ .rdfull (w_rdfull_l),
+ .wrfull (w_wrfull_l),
+ .rdempty (w_rdempty_l),
+ .wrempty (w_wrempty_l),
+ .rdusedw (w_rdusedw_l),
+ .wrusedw (w_wrusedw_l),
+ .q (w_q_l) );
+ defparam
+ LOWLATENCY.lpm_width = lpm_width,
+ LOWLATENCY.lpm_widthu = lpm_widthu,
+ LOWLATENCY.lpm_width_r = lpm_width_r,
+ LOWLATENCY.lpm_widthu_r = lpm_widthu_r,
+ LOWLATENCY.lpm_numwords = lpm_numwords,
+ LOWLATENCY.delay_rdusedw = delay_rdusedw,
+ LOWLATENCY.delay_wrusedw = delay_wrusedw,
+ LOWLATENCY.rdsync_delaypipe = (READ_SIDE_SYNCHRONIZERS > 3 ? READ_SIDE_SYNCHRONIZERS - 2 : 1),
+ LOWLATENCY.wrsync_delaypipe = (WRITE_SIDE_SYNCHRONIZERS > 3 ? WRITE_SIDE_SYNCHRONIZERS - 2 : 1),
+ LOWLATENCY.intended_device_family = intended_device_family,
+ LOWLATENCY.lpm_showahead = lpm_showahead,
+ LOWLATENCY.underflow_checking = underflow_checking,
+ LOWLATENCY.overflow_checking = overflow_checking,
+ LOWLATENCY.add_usedw_msb_bit = add_usedw_msb_bit,
+ LOWLATENCY.write_aclr_synch = write_aclr_synch,
+ LOWLATENCY.use_eab = use_eab,
+ LOWLATENCY.clocks_are_synchronized = clocks_are_synchronized,
+ LOWLATENCY.add_ram_output_register = add_ram_output_register,
+ LOWLATENCY.lpm_hint = lpm_hint;
+
+// INITIAL CONSTRUCT BLOCK
+ initial
+ begin
+ if(((wrsync_delaypipe == 0) || (rdsync_delaypipe == 0)) && (clocks_are_synchronized == "FALSE"))
+ begin
+ if ((FAMILY_HAS_STRATIXII_STYLE_RAM == 1) || (FAMILY_HAS_STRATIXIII_STYLE_RAM == 1))
+ begin
+ $display ("Warning! Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2.");
+ $display("Time: %0t Instance: %m", $time);
+ end
+ end
+ end
+
+// CONTINOUS ASSIGNMENT
+ assign rdfull = (use_low_latency_fifo == 1) ? w_rdfull_l :
+ (clocks_are_synchronized == "TRUE") ? w_rdfull_s : w_rdfull_a;
+
+ assign wrfull = (use_low_latency_fifo == 1) ? w_wrfull_l :
+ (clocks_are_synchronized == "TRUE") ? w_wrfull_s : w_wrfull_a;
+
+ assign rdempty = (use_low_latency_fifo == 1) ? w_rdempty_l :
+ (clocks_are_synchronized == "TRUE") ? w_rdempty_s : w_rdempty_a;
+
+ assign wrempty = (use_low_latency_fifo == 1) ? w_wrempty_l :
+ (clocks_are_synchronized == "TRUE") ? w_wrempty_s : w_wrempty_a;
+
+ assign rdusedw = (use_low_latency_fifo == 1) ? w_rdusedw_l :
+ (clocks_are_synchronized == "TRUE") ? w_rdusedw_s : w_rdusedw_a;
+
+ assign wrusedw = (use_low_latency_fifo == 1) ? w_wrusedw_l :
+ (clocks_are_synchronized == "TRUE") ? w_wrusedw_s : w_wrusedw_a;
+
+ assign q = (use_low_latency_fifo == 1) ? w_q_l :
+ (clocks_are_synchronized == "TRUE") ? w_q_s : w_q_a;
+
+endmodule // dcfifo_mixed_widths
+// END OF MODULE
+
+//START_MODULE_NAME------------------------------------------------------------
+//
+// Module Name : dcfifo
+//
+// Description : Dual Clocks FIFO
+//
+// Limitation :
+//
+// Results expected:
+//
+//END_MODULE_NAME--------------------------------------------------------------
+
+// BEGINNING OF MODULE
+`timescale 1 ps / 1 ps
+
+// MODULE DECLARATION
+module dcfifo ( data, rdclk, wrclk, aclr, rdreq, wrreq,
+ rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q);
+
+// GLOBAL PARAMETER DECLARATION
+ parameter lpm_width = 1;
+ parameter lpm_widthu = 1;
+ parameter lpm_numwords = 2;
+ parameter delay_rdusedw = 1;
+ parameter delay_wrusedw = 1;
+ parameter rdsync_delaypipe = 0;
+ parameter wrsync_delaypipe = 0;
+ parameter intended_device_family = "Stratix";
+ parameter lpm_showahead = "OFF";
+ parameter underflow_checking = "ON";
+ parameter overflow_checking = "ON";
+ parameter clocks_are_synchronized = "FALSE";
+ parameter use_eab = "ON";
+ parameter add_ram_output_register = "OFF";
+ parameter lpm_hint = "USE_EAB=ON";
+ parameter lpm_type = "dcfifo";
+ parameter add_usedw_msb_bit = "OFF";
+ parameter write_aclr_synch = "OFF";
+
+// LOCAL_PARAMETERS_BEGIN
+
+ parameter add_width = 1;
+ parameter ram_block_type = "AUTO";
+
+// LOCAL_PARAMETERS_END
+
+// INPUT PORT DECLARATION
+ input [lpm_width-1:0] data;
+ input rdclk;
+ input wrclk;
+ input aclr;
+ input rdreq;
+ input wrreq;
+
+// OUTPUT PORT DECLARATION
+ output rdfull;
+ output wrfull;
+ output rdempty;
+ output wrempty;
+ output [lpm_widthu-1:0] rdusedw;
+ output [lpm_widthu-1:0] wrusedw;
+ output [lpm_width-1:0] q;
+
+// INTERNAL WIRE DECLARATION
+ wire w_rdfull;
+ wire w_wrfull;
+ wire w_rdempty;
+ wire w_wrempty;
+ wire [lpm_widthu-1:0] w_rdusedw;
+ wire [lpm_widthu-1:0] w_wrusedw;
+ wire [lpm_width-1:0] w_q;
+
+// INTERNAL TRI DECLARATION
+ tri0 aclr;
+
+ dcfifo_mixed_widths DCFIFO_MW (
+ .data (data),
+ .rdclk (rdclk),
+ .wrclk (wrclk),
+ .aclr (aclr),
+ .rdreq (rdreq),
+ .wrreq (wrreq),
+ .rdfull (w_rdfull),
+ .wrfull (w_wrfull),
+ .rdempty (w_rdempty),
+ .wrempty (w_wrempty),
+ .rdusedw (w_rdusedw),
+ .wrusedw (w_wrusedw),
+ .q (w_q) );
+ defparam
+ DCFIFO_MW.lpm_width = lpm_width,
+ DCFIFO_MW.lpm_widthu = lpm_widthu,
+ DCFIFO_MW.lpm_width_r = lpm_width,
+ DCFIFO_MW.lpm_widthu_r = lpm_widthu,
+ DCFIFO_MW.lpm_numwords = lpm_numwords,
+ DCFIFO_MW.delay_rdusedw = delay_rdusedw,
+ DCFIFO_MW.delay_wrusedw = delay_wrusedw,
+ DCFIFO_MW.rdsync_delaypipe = rdsync_delaypipe,
+ DCFIFO_MW.wrsync_delaypipe = wrsync_delaypipe,
+ DCFIFO_MW.intended_device_family = intended_device_family,
+ DCFIFO_MW.lpm_showahead = lpm_showahead,
+ DCFIFO_MW.underflow_checking = underflow_checking,
+ DCFIFO_MW.overflow_checking = overflow_checking,
+ DCFIFO_MW.clocks_are_synchronized = clocks_are_synchronized,
+ DCFIFO_MW.use_eab = use_eab,
+ DCFIFO_MW.add_ram_output_register = add_ram_output_register,
+ DCFIFO_MW.add_width = add_width,
+ DCFIFO_MW.ram_block_type = ram_block_type,
+ DCFIFO_MW.add_usedw_msb_bit = add_usedw_msb_bit,
+ DCFIFO_MW.write_aclr_synch = write_aclr_synch,
+ DCFIFO_MW.lpm_hint = lpm_hint;
+
+// CONTINOUS ASSIGNMENT
+ assign rdfull = w_rdfull;
+ assign wrfull = w_wrfull;
+ assign rdempty = w_rdempty;
+ assign wrempty = w_wrempty;
+ assign rdusedw = w_rdusedw;
+ assign wrusedw = w_wrusedw;
+ assign q = w_q;
+
+endmodule // dcfifo
+// END OF MODULE
+
Index: v1p0/sim/tsu/ptpdv2_tx.pcap
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: v1p0/sim/tsu/ptpdv2_tx.pcap
===================================================================
--- v1p0/sim/tsu/ptpdv2_tx.pcap (nonexistent)
+++ v1p0/sim/tsu/ptpdv2_tx.pcap (revision 28)
v1p0/sim/tsu/ptpdv2_tx.pcap
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: v1p0/par/altera/ha1588.qpf
===================================================================
--- v1p0/par/altera/ha1588.qpf (nonexistent)
+++ v1p0/par/altera/ha1588.qpf (revision 28)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
+# Date created = 14:35:47 March 31, 2012
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "10.1"
+DATE = "14:35:47 March 31, 2012"
+
+# Revisions
+
+PROJECT_REVISION = "ha1588"
Index: v1p0/par/altera/ha1588.qsf
===================================================================
--- v1p0/par/altera/ha1588.qsf (nonexistent)
+++ v1p0/par/altera/ha1588.qsf (revision 28)
@@ -0,0 +1,63 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
+# Date created = 14:35:47 March 31, 2012
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ha1588_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name TOP_LEVEL_ENTITY ha1588
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:35:47 MARCH 31, 2012"
+set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name SDC_FILE ha1588.sdc
+set_global_assignment -name VERILOG_FILE ../../rtl/top/ha1588.v
+set_global_assignment -name VERILOG_FILE ../../rtl/rtc/rtc.v
+set_global_assignment -name VERILOG_FILE ../../rtl/reg/reg.v
+set_global_assignment -name VERILOG_FILE ../../rtl/tsu/tsu.v
+set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_queue.v
+set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_parser.v
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: v1p0/par/altera/ha1588.sdc
===================================================================
--- v1p0/par/altera/ha1588.sdc (nonexistent)
+++ v1p0/par/altera/ha1588.sdc (revision 28)
@@ -0,0 +1,171 @@
+## Generated SDC file "ha1588.sdc"
+
+## Copyright (C) 1991-2011 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions
+## and other software and tools, and its AMPP partner logic
+## functions, and any output files from any of the foregoing
+## (including device programming or simulation files), and any
+## associated documentation or information are expressly subject
+## to the terms and conditions of the Altera Program License
+## Subscription Agreement, Altera MegaCore Function License
+## Agreement, or other applicable license agreement, including,
+## without limitation, that your use is for the sole purpose of
+## programming logic devices manufactured by Altera and sold by
+## Altera or its authorized distributors. Please refer to the
+## applicable agreement for further details.
+
+
+## VENDOR "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version"
+
+## DATE "Sat Mar 31 15:03:15 2012"
+
+##
+## DEVICE "EP3C5F256C6"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}]
+create_clock -name {rtc_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {rtc_clk}]
+create_clock -name {tx_gmii_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {tx_gmii_clk}]
+create_clock -name {rx_gmii_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {rx_gmii_clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] 0.020
+set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] 0.020
+set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] 0.020
+set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] 0.020
+set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] 0.020
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] 0.020
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] 0.020
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] 0.020
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.020
+set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.020
+set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.020
+set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.020
+set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.020
+set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.020
+set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {rtc_clk}] 0.040
+set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.020
+set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.020
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -exclusive -group [get_clocks {clk}] \
+ -group [get_clocks {rtc_clk}] \
+ -group [get_clocks {rx_gmii_clk}] \
+ -group [get_clocks {tx_gmii_clk}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_gd9:dffpipe18|dffe19a*}]
+set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_fd9:dffpipe15|dffe16a*}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
Index: v1p0/doc/ptpv1.pcap
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: v1p0/doc/ptpv1.pcap
===================================================================
--- v1p0/doc/ptpv1.pcap (nonexistent)
+++ v1p0/doc/ptpv1.pcap (revision 28)
v1p0/doc/ptpv1.pcap
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: v1p0/doc/ptpv2.pcap
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: v1p0/doc/ptpv2.pcap
===================================================================
--- v1p0/doc/ptpv2.pcap (nonexistent)
+++ v1p0/doc/ptpv2.pcap (revision 28)
v1p0/doc/ptpv2.pcap
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property