URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
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/ha1588/trunk/doc
- from Rev 10 to Rev 39
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Rev 10 → Rev 39
/DESCRIPTION.txt
0,0 → 1,36
General Description |
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Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packet transmitting and receiving is implemented with any existing MAC inside or outside the FPAG; The IP Core will implement the tunable Real-Time Clock and Time Stamping of PTP event packets (L2, UDP/IPv4/MPLS/VLAN and UDP/IPv6/MPLS/VLAN) in two-step-mode. |
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Feature Description |
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RTC: Real Time Clock. |
* Standard PTP clock output with 2^48s and 2^32ns time resolution. |
* Tunable accumulator based clock with 2^-8ns time resolution and 2^-32ns period resolution. |
** Direct ToD write, with 2^-8ns resolution. |
** Direct frequency write, with 2^-32ns resolution. |
** Timed temporary time adjustment, with 2^-8ns resolution and 2^32bit timer. |
* Clock Domain Crossing hand-shaking, for SW read and write accesses. |
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TSU: Time Stamping Unit. |
* Two-Step PTP operation. |
* 15-entry timestamp queue. |
* 128bit timestamp format. |
** 16bit extra information. |
** 80bit timestamp. |
** 32bit packet identity data. |
* GMII interface tap with line-speed PTP event packet parsing. |
** Sync |
** Delay_Req |
** Pdelay_Req |
** Pdelay_Resp |
* Variety of PTP packet formats support. |
** L2 PTP packet with stacked VLAN tags. |
** IPv4 and IPv6 UDP PTP packet with stacked VLAN tags and stacked MPLS labels. |
* 32bit internal datapath for easier timing closure. |
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SystemVerilog DPI based simulation environment is included for SW driver development. |
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The IP Core can be used as an IP Component in Altera SOPC Builder. |
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The only FPGA vendor dependent module is the timestamp queue. This Altera DCFIFO can be replaced by other FPGA vendor specific dual clock FIFO. |
/RTC MEMORY MAP.csv
0,0 → 1,48
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REG NAME, REG ADDR, BIT, NAME, R/W, DESCRIPTION, DEFAULT, |
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RTC_CTRL, 0x00000000, 31: 5, NULL, R/W, , 0, |
, , 4, RTC_SET_RESET, R/W, , 0, |
, , 3, RTC_SET_TIME, R/W, , 0, |
, , 2, RTC_SET_PERIOD, R/W, , 0, |
, , 1, RTC_SET_ADJ, R/W, , 0, |
, , 0, RTC_GET_TIME, R/W, , 0, |
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RTC_NULL_0x04, 0x00000004, 31: 0, NULL, R/W, , 0, |
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RTC_NULL_0x08, 0x00000008, 31: 0, NULL, R/W, , 0, |
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RTC_NULL_0x0C, 0x0000000C, 31: 0, NULL, R/W, , 0, |
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RTC_TIME_SEC_H, 0x00000010, 31:16, NULL, R/W, , 0, |
, , 15: 0, RTC_TIME_SEC_47_32, R/W, , 0, |
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RTC_TIME_SEC_L, 0x00000014, 31: 0, RTC_TIME_SEC_31_00, R/W, , 0, |
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RTC_TIME_NSC_H, 0x00000018, 31:30, NULL, R/W, , 0, |
, , 29: 0, RTC_TIME_NSC_29_00, R/W, , 0, |
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RTC_TIME_NSC_L, 0x0000001C, 31: 8, NULL, R/W, , 0, |
, , 7: 0, RTC_TIME_SUB_NSC_07_00, R/W, , 0, |
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RTC_PERIOD_H, 0x00000020, 31: 8, NULL, R/W, , 0, |
, , 7: 0, RTC_PERIOD_NSC_07_00, R/W, , 0, |
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RTC_PERIOD_L, 0x00000024, 31: 0, RTC_PERIOD_SUB_NSC_31_00, R/W, , 0, |
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RTC_ADJPER_H, 0x00000028, 31: 8, NULL, R/W, , 0, |
, , 7: 0, RTC_ADJPER_NSC_07_00, R/W, , 0, |
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RTC_ADJPER_L, 0x0000002C, 31: 0, RTC_ADJPER_SUB_NSC_31_00, R/W, , 0, |
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RTC_ADJNUM, 0x00000030, 31: 0, RTC_ADJNUM_CNT_31_00, R/W, , 0, |
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RTC_NULL_0x34, 0x00000034, 31: 0, NULL, R/W, , 0, |
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RTC_NULL_0x38, 0x00000038, 31: 0, NULL, R/W, , 0, |
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RTC_NULL_0x3C, 0x0000003C, 31: 0, NULL, R/W, , 0, |
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/TSU MEMORY MAP.csv
0,0 → 1,52
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REG NAME, REG ADDR, BIT, NAME, R/W, DESCRIPTION, DEFAULT, |
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TSU_RXCTRL, 0x00000040, 31: 2, NULL, R/W, , 0, |
, , 1, TSU_SET_RXRST, R/W, , 0, |
, , 0, TSU_GET_RXQUE, R/W, , 0, |
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TSU_RXQUE_STATUS, 0x00000044, 31: 8, NULL, R/W, , 0, |
, , 7: 0, TSU_RXQUE_NUMBER, R/W, , 0, |
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TSU_NULL_0x48, 0x00000048, 31: 0, NULL, R/W, , 0, |
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TSU_NULL_0x4C, 0x0000004C, 31: 0, NULL, R/W, , 0, |
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TSU_RXQUE_DATA_HH, 0x00000050, 31:16, NULL, R/W, , 0, |
, , 15: 0, TSU_RXQUE_SEC_47_32, R/W, , 0, |
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TSU_RXQUE_DATA_HL, 0x00000054, 31: 0, TSU_RXQUE_SEC_31_00, R/W, , 0, |
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TSU_RXQUE_DATA_LH, 0x00000058, 31:30, NULL, R/W, , 0, |
, , 29: 0, TSU_RXQUE_NSC_29_00, R/W, , 0, |
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TSU_RXQUE_DATA_LL, 0x0000005C, 31:28, TSU_RXQUE_PTP_MSG_ID, R/W, , 0, |
, , 27:16, TSU_RXQUE_PTP_CK_SUM, R/W, , 0, |
, , 15: 0, TSU_RXQUE_PTP_SEQ_ID, R/W, , 0, |
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TSU_TXCTRL, 0x00000060, 31: 2, NULL, R/W, , 0, |
, , 1, TSU_SET_TXRST, R/W, , 0, |
, , 0, TSU_GET_TXQUE, R/W, , 0, |
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TSU_TXQUE_STATUS, 0x00000064, 31: 8, NULL, R/W, , 0, |
, , 7: 0, TSU_TXQUE_NUMBER, R/W, , 0, |
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TSU_NULL_0x68, 0x00000068, 31: 0, NULL, R/W, , 0, |
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TSU_NULL_0x6C, 0x0000006C, 31: 0, NULL, R/W, , 0, |
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TSU_TXQUE_DATA_HH, 0x00000070, 31:16, NULL, R/W, , 0, |
, , 15: 0, TSU_TXQUE_SEC_47_32, R/W, , 0, |
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TSU_TXQUE_DATA_HL, 0x00000074, 31: 0, TSU_TXQUE_SEC_31_00, R/W, , 0, |
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TSU_TXQUE_DATA_LH, 0x00000078, 31:30, NULL, R/W, , 0, |
, , 29: 0, TSU_TXQUE_NSC_29_00, R/W, , 0, |
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TSU_TXQUE_DATA_LL, 0x0000007C, 31:28, TSU_TXQUE_PTP_MSG_ID, R/W, , 0, |
, , 27:16, TSU_TXQUE_PTP_CK_SUM, R/W, , 0, |
, , 15: 0, TSU_TXQUE_PTP_SEQ_ID, R/W, , 0, |
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