URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588/trunk/par
- from Rev 29 to Rev 68
- ↔ Reverse comparison
Rev 29 → Rev 68
/altera/cleanup.sh
0,0 → 1,2
rm -rf db incremental_db output |
rm -f *.qdf |
/altera/ha1588.qsf
41,7 → 41,7
set_global_assignment -name TOP_LEVEL_ENTITY ha1588 |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.1 SP1" |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:35:47 MARCH 31, 2012" |
set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1" |
set_global_assignment -name LAST_QUARTUS_VERSION 12.1 |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
51,6 → 51,8
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON |
set_global_assignment -name FITTER_EFFORT "STANDARD FIT" |
set_global_assignment -name SDC_FILE ha1588.sdc |
set_global_assignment -name SEARCH_PATH .\\ip |
set_global_assignment -name VERILOG_FILE ./ip/dcfifo_128b_16.v |
set_global_assignment -name VERILOG_FILE ../../rtl/top/ha1588.v |
set_global_assignment -name VERILOG_FILE ../../rtl/rtc/rtc.v |
set_global_assignment -name VERILOG_FILE ../../rtl/reg/reg.v |
62,4 → 64,6
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON |
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED |
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
|
/altera/ip/dcfifo_128b_16.v
0,0 → 1,189
// megafunction wizard: %FIFO% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
// MODULE: dcfifo |
|
// ============================================================ |
// File Name: dcfifo_128b_16.v |
// Megafunction Name(s): |
// dcfifo |
// |
// Simulation Library Files(s): |
// altera_mf |
// ============================================================ |
// ************************************************************ |
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
// |
// 12.1 Build 177 11/07/2012 SJ Web Edition |
// ************************************************************ |
|
|
//Copyright (C) 1991-2012 Altera Corporation |
//Your use of Altera Corporation's design tools, logic functions |
//and other software and tools, and its AMPP partner logic |
//functions, and any output files from any of the foregoing |
//(including device programming or simulation files), and any |
//associated documentation or information are expressly subject |
//to the terms and conditions of the Altera Program License |
//Subscription Agreement, Altera MegaCore Function License |
//Agreement, or other applicable license agreement, including, |
//without limitation, that your use is for the sole purpose of |
//programming logic devices manufactured by Altera and sold by |
//Altera or its authorized distributors. Please refer to the |
//applicable agreement for further details. |
|
|
// synopsys translate_off |
`timescale 1 ps / 1 ps |
// synopsys translate_on |
module dcfifo_128b_16 ( |
aclr, |
data, |
rdclk, |
rdreq, |
wrclk, |
wrreq, |
q, |
rdempty, |
rdusedw, |
wrfull, |
wrusedw); |
|
input aclr; |
input [127:0] data; |
input rdclk; |
input rdreq; |
input wrclk; |
input wrreq; |
output [127:0] q; |
output rdempty; |
output [3:0] rdusedw; |
output wrfull; |
output [3:0] wrusedw; |
`ifndef ALTERA_RESERVED_QIS |
// synopsys translate_off |
`endif |
tri0 aclr; |
`ifndef ALTERA_RESERVED_QIS |
// synopsys translate_on |
`endif |
|
wire sub_wire0; |
wire [127:0] sub_wire1; |
wire sub_wire2; |
wire [3:0] sub_wire3; |
wire [3:0] sub_wire4; |
wire wrfull = sub_wire0; |
wire [127:0] q = sub_wire1[127:0]; |
wire rdempty = sub_wire2; |
wire [3:0] wrusedw = sub_wire3[3:0]; |
wire [3:0] rdusedw = sub_wire4[3:0]; |
|
dcfifo dcfifo_component ( |
.rdclk (rdclk), |
.wrclk (wrclk), |
.wrreq (wrreq), |
.aclr (aclr), |
.data (data), |
.rdreq (rdreq), |
.wrfull (sub_wire0), |
.q (sub_wire1), |
.rdempty (sub_wire2), |
.wrusedw (sub_wire3), |
.rdusedw (sub_wire4), |
.rdfull (), |
.wrempty ()); |
defparam |
dcfifo_component.intended_device_family = "Cyclone III", |
dcfifo_component.lpm_numwords = 16, |
dcfifo_component.lpm_showahead = "OFF", |
dcfifo_component.lpm_type = "dcfifo", |
dcfifo_component.lpm_width = 128, |
dcfifo_component.lpm_widthu = 4, |
dcfifo_component.overflow_checking = "ON", |
dcfifo_component.rdsync_delaypipe = 4, |
dcfifo_component.underflow_checking = "ON", |
dcfifo_component.use_eab = "ON", |
dcfifo_component.write_aclr_synch = "OFF", |
dcfifo_component.wrsync_delaypipe = 4; |
|
|
endmodule |
|
// ============================================================ |
// CNX file retrieval info |
// ============================================================ |
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" |
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" |
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" |
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" |
// Retrieval info: PRIVATE: Clock NUMERIC "4" |
// Retrieval info: PRIVATE: Depth NUMERIC "16" |
// Retrieval info: PRIVATE: Empty NUMERIC "1" |
// Retrieval info: PRIVATE: Full NUMERIC "1" |
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" |
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" |
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" |
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" |
// Retrieval info: PRIVATE: Optimize NUMERIC "0" |
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" |
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" |
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" |
// Retrieval info: PRIVATE: UsedW NUMERIC "1" |
// Retrieval info: PRIVATE: Width NUMERIC "128" |
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" |
// Retrieval info: PRIVATE: diff_widths NUMERIC "0" |
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" |
// Retrieval info: PRIVATE: output_width NUMERIC "128" |
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" |
// Retrieval info: PRIVATE: rsFull NUMERIC "0" |
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" |
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" |
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" |
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: wsFull NUMERIC "1" |
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" |
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" |
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" |
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" |
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" |
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" |
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" |
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" |
// Retrieval info: CONSTANT: USE_EAB STRING "ON" |
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" |
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" |
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]" |
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]" |
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" |
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" |
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" |
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL "rdusedw[3..0]" |
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" |
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" |
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" |
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]" |
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 |
// Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 |
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 |
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 |
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 |
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 |
// Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 |
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 |
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0 |
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 |
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 |
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_128b_16.v TRUE |
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_128b_16.inc FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_128b_16.cmp FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_128b_16.bsf FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_128b_16_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo_128b_16_bb.v FALSE |
// Retrieval info: LIB_FILE: altera_mf |
/altera/ip/define.h
0,0 → 1,189
`define USE_ALTERA_IP |
/altera/cleanup.bat
0,0 → 1,2
rmdir /S /Q db incremental_db output |
del *.qws *.qdf |
/xilinx/ha1588.tcl
0,0 → 1,24
create_project -force ha1588 . -part xc7z020clg484-1 |
set_property board zc702 [current_project] |
|
add_files -norecurse ha1588.ucf |
add_files -norecurse ./ip/define.h |
set_property is_global_include true [get_files ./ip/define.h] |
add_files -norecurse ./ip/dcfifo_128b_16.ngc |
add_files -norecurse ./ip/dcfifo_128b_16.v |
add_files -norecurse ../../rtl/top/ha1588.v |
add_files -norecurse ../../rtl/reg/reg.v |
add_files -norecurse ../../rtl/rtc/rtc.v |
add_files -norecurse ../../rtl/tsu/tsu.v |
add_files -norecurse ../../rtl/tsu/ptp_parser.v |
add_files -norecurse ../../rtl/tsu/ptp_queue.v |
|
reset_run synth_1 |
reset_run impl_1 |
|
#launch_runs synth_1 -jobs 1 |
#wait_on_run synth_1 |
|
#launch_runs impl_1 -jobs 1 |
#wait_on_run impl_1 |
|
/xilinx/cleanup.sh
0,0 → 1,2
rm -r -f .Xil *.srcs *.data *.runs *.cache |
rm -f *.log *.jou |
/xilinx/ip/dcfifo_128b_16.v
0,0 → 1,491
/******************************************************************************* |
* This file is owned and controlled by Xilinx and must be used solely * |
* for design, simulation, implementation and creation of design files * |
* limited to Xilinx devices or technologies. Use with non-Xilinx * |
* devices or technologies is expressly prohibited and immediately * |
* terminates your license. * |
* * |
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * |
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * |
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * |
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * |
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * |
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * |
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * |
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * |
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * |
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * |
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * |
* PARTICULAR PURPOSE. * |
* * |
* Xilinx products are not intended for use in life support appliances, * |
* devices, or systems. Use in such applications are expressly * |
* prohibited. * |
* * |
* (c) Copyright 1995-2013 Xilinx, Inc. * |
* All rights reserved. * |
*******************************************************************************/ |
// You must compile the wrapper file dcfifo_128b_16.v when simulating |
// the core, dcfifo_128b_16. When compiling the wrapper file, be sure to |
// reference the XilinxCoreLib Verilog simulation library. For detailed |
// instructions, please refer to the "CORE Generator Help". |
|
// The synthesis directives "translate_off/translate_on" specified below are |
// supported by Xilinx, Mentor Graphics and Synplicity synthesis |
// tools. Ensure they are correct for your synthesis tool(s). |
|
`timescale 1ns/1ps |
|
module dcfifo_128b_16( |
rst, |
wr_clk, |
rd_clk, |
din, |
wr_en, |
rd_en, |
dout, |
full, |
empty, |
rd_data_count, |
wr_data_count |
); |
|
input rst; |
input wr_clk; |
input rd_clk; |
input [127 : 0] din; |
input wr_en; |
input rd_en; |
output [127 : 0] dout; |
output full; |
output empty; |
output [3 : 0] rd_data_count; |
output [3 : 0] wr_data_count; |
|
// synthesis translate_off |
|
FIFO_GENERATOR_V9_3 #( |
.C_ADD_NGC_CONSTRAINT(0), |
.C_APPLICATION_TYPE_AXIS(0), |
.C_APPLICATION_TYPE_RACH(0), |
.C_APPLICATION_TYPE_RDCH(0), |
.C_APPLICATION_TYPE_WACH(0), |
.C_APPLICATION_TYPE_WDCH(0), |
.C_APPLICATION_TYPE_WRCH(0), |
.C_AXI_ADDR_WIDTH(32), |
.C_AXI_ARUSER_WIDTH(1), |
.C_AXI_AWUSER_WIDTH(1), |
.C_AXI_BUSER_WIDTH(1), |
.C_AXI_DATA_WIDTH(64), |
.C_AXI_ID_WIDTH(4), |
.C_AXI_RUSER_WIDTH(1), |
.C_AXI_TYPE(0), |
.C_AXI_WUSER_WIDTH(1), |
.C_AXIS_TDATA_WIDTH(64), |
.C_AXIS_TDEST_WIDTH(4), |
.C_AXIS_TID_WIDTH(8), |
.C_AXIS_TKEEP_WIDTH(4), |
.C_AXIS_TSTRB_WIDTH(4), |
.C_AXIS_TUSER_WIDTH(4), |
.C_AXIS_TYPE(0), |
.C_COMMON_CLOCK(0), |
.C_COUNT_TYPE(0), |
.C_DATA_COUNT_WIDTH(4), |
.C_DEFAULT_VALUE("BlankString"), |
.C_DIN_WIDTH(128), |
.C_DIN_WIDTH_AXIS(1), |
.C_DIN_WIDTH_RACH(32), |
.C_DIN_WIDTH_RDCH(64), |
.C_DIN_WIDTH_WACH(32), |
.C_DIN_WIDTH_WDCH(64), |
.C_DIN_WIDTH_WRCH(2), |
.C_DOUT_RST_VAL("0"), |
.C_DOUT_WIDTH(128), |
.C_ENABLE_RLOCS(0), |
.C_ENABLE_RST_SYNC(1), |
.C_ERROR_INJECTION_TYPE(0), |
.C_ERROR_INJECTION_TYPE_AXIS(0), |
.C_ERROR_INJECTION_TYPE_RACH(0), |
.C_ERROR_INJECTION_TYPE_RDCH(0), |
.C_ERROR_INJECTION_TYPE_WACH(0), |
.C_ERROR_INJECTION_TYPE_WDCH(0), |
.C_ERROR_INJECTION_TYPE_WRCH(0), |
.C_FAMILY("virtex7"), |
.C_FULL_FLAGS_RST_VAL(0), |
.C_HAS_ALMOST_EMPTY(0), |
.C_HAS_ALMOST_FULL(0), |
.C_HAS_AXI_ARUSER(0), |
.C_HAS_AXI_AWUSER(0), |
.C_HAS_AXI_BUSER(0), |
.C_HAS_AXI_RD_CHANNEL(0), |
.C_HAS_AXI_RUSER(0), |
.C_HAS_AXI_WR_CHANNEL(0), |
.C_HAS_AXI_WUSER(0), |
.C_HAS_AXIS_TDATA(0), |
.C_HAS_AXIS_TDEST(0), |
.C_HAS_AXIS_TID(0), |
.C_HAS_AXIS_TKEEP(0), |
.C_HAS_AXIS_TLAST(0), |
.C_HAS_AXIS_TREADY(1), |
.C_HAS_AXIS_TSTRB(0), |
.C_HAS_AXIS_TUSER(0), |
.C_HAS_BACKUP(0), |
.C_HAS_DATA_COUNT(0), |
.C_HAS_DATA_COUNTS_AXIS(0), |
.C_HAS_DATA_COUNTS_RACH(0), |
.C_HAS_DATA_COUNTS_RDCH(0), |
.C_HAS_DATA_COUNTS_WACH(0), |
.C_HAS_DATA_COUNTS_WDCH(0), |
.C_HAS_DATA_COUNTS_WRCH(0), |
.C_HAS_INT_CLK(0), |
.C_HAS_MASTER_CE(0), |
.C_HAS_MEMINIT_FILE(0), |
.C_HAS_OVERFLOW(0), |
.C_HAS_PROG_FLAGS_AXIS(0), |
.C_HAS_PROG_FLAGS_RACH(0), |
.C_HAS_PROG_FLAGS_RDCH(0), |
.C_HAS_PROG_FLAGS_WACH(0), |
.C_HAS_PROG_FLAGS_WDCH(0), |
.C_HAS_PROG_FLAGS_WRCH(0), |
.C_HAS_RD_DATA_COUNT(1), |
.C_HAS_RD_RST(0), |
.C_HAS_RST(1), |
.C_HAS_SLAVE_CE(0), |
.C_HAS_SRST(0), |
.C_HAS_UNDERFLOW(0), |
.C_HAS_VALID(0), |
.C_HAS_WR_ACK(0), |
.C_HAS_WR_DATA_COUNT(1), |
.C_HAS_WR_RST(0), |
.C_IMPLEMENTATION_TYPE(2), |
.C_IMPLEMENTATION_TYPE_AXIS(1), |
.C_IMPLEMENTATION_TYPE_RACH(1), |
.C_IMPLEMENTATION_TYPE_RDCH(1), |
.C_IMPLEMENTATION_TYPE_WACH(1), |
.C_IMPLEMENTATION_TYPE_WDCH(1), |
.C_IMPLEMENTATION_TYPE_WRCH(1), |
.C_INIT_WR_PNTR_VAL(0), |
.C_INTERFACE_TYPE(0), |
.C_MEMORY_TYPE(1), |
.C_MIF_FILE_NAME("BlankString"), |
.C_MSGON_VAL(1), |
.C_OPTIMIZATION_MODE(0), |
.C_OVERFLOW_LOW(0), |
.C_PRELOAD_LATENCY(2), |
.C_PRELOAD_REGS(1), |
.C_PRIM_FIFO_TYPE("512x72"), |
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2), |
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), |
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), |
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), |
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), |
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), |
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), |
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3), |
.C_PROG_EMPTY_TYPE(0), |
.C_PROG_EMPTY_TYPE_AXIS(0), |
.C_PROG_EMPTY_TYPE_RACH(0), |
.C_PROG_EMPTY_TYPE_RDCH(0), |
.C_PROG_EMPTY_TYPE_WACH(0), |
.C_PROG_EMPTY_TYPE_WDCH(0), |
.C_PROG_EMPTY_TYPE_WRCH(0), |
.C_PROG_FULL_THRESH_ASSERT_VAL(13), |
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), |
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), |
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), |
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), |
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), |
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), |
.C_PROG_FULL_THRESH_NEGATE_VAL(12), |
.C_PROG_FULL_TYPE(0), |
.C_PROG_FULL_TYPE_AXIS(0), |
.C_PROG_FULL_TYPE_RACH(0), |
.C_PROG_FULL_TYPE_RDCH(0), |
.C_PROG_FULL_TYPE_WACH(0), |
.C_PROG_FULL_TYPE_WDCH(0), |
.C_PROG_FULL_TYPE_WRCH(0), |
.C_RACH_TYPE(0), |
.C_RD_DATA_COUNT_WIDTH(4), |
.C_RD_DEPTH(16), |
.C_RD_FREQ(1), |
.C_RD_PNTR_WIDTH(4), |
.C_RDCH_TYPE(0), |
.C_REG_SLICE_MODE_AXIS(0), |
.C_REG_SLICE_MODE_RACH(0), |
.C_REG_SLICE_MODE_RDCH(0), |
.C_REG_SLICE_MODE_WACH(0), |
.C_REG_SLICE_MODE_WDCH(0), |
.C_REG_SLICE_MODE_WRCH(0), |
.C_SYNCHRONIZER_STAGE(2), |
.C_UNDERFLOW_LOW(0), |
.C_USE_COMMON_OVERFLOW(0), |
.C_USE_COMMON_UNDERFLOW(0), |
.C_USE_DEFAULT_SETTINGS(0), |
.C_USE_DOUT_RST(1), |
.C_USE_ECC(0), |
.C_USE_ECC_AXIS(0), |
.C_USE_ECC_RACH(0), |
.C_USE_ECC_RDCH(0), |
.C_USE_ECC_WACH(0), |
.C_USE_ECC_WDCH(0), |
.C_USE_ECC_WRCH(0), |
.C_USE_EMBEDDED_REG(1), |
.C_USE_FIFO16_FLAGS(0), |
.C_USE_FWFT_DATA_COUNT(0), |
.C_VALID_LOW(0), |
.C_WACH_TYPE(0), |
.C_WDCH_TYPE(0), |
.C_WR_ACK_LOW(0), |
.C_WR_DATA_COUNT_WIDTH(4), |
.C_WR_DEPTH(16), |
.C_WR_DEPTH_AXIS(1024), |
.C_WR_DEPTH_RACH(16), |
.C_WR_DEPTH_RDCH(1024), |
.C_WR_DEPTH_WACH(16), |
.C_WR_DEPTH_WDCH(1024), |
.C_WR_DEPTH_WRCH(16), |
.C_WR_FREQ(1), |
.C_WR_PNTR_WIDTH(4), |
.C_WR_PNTR_WIDTH_AXIS(10), |
.C_WR_PNTR_WIDTH_RACH(4), |
.C_WR_PNTR_WIDTH_RDCH(10), |
.C_WR_PNTR_WIDTH_WACH(4), |
.C_WR_PNTR_WIDTH_WDCH(10), |
.C_WR_PNTR_WIDTH_WRCH(4), |
.C_WR_RESPONSE_LATENCY(1), |
.C_WRCH_TYPE(0) |
) |
inst ( |
.RST(rst), |
.WR_CLK(wr_clk), |
.RD_CLK(rd_clk), |
.DIN(din), |
.WR_EN(wr_en), |
.RD_EN(rd_en), |
.DOUT(dout), |
.FULL(full), |
.EMPTY(empty), |
.RD_DATA_COUNT(rd_data_count), |
.WR_DATA_COUNT(wr_data_count), |
.BACKUP(), |
.BACKUP_MARKER(), |
.CLK(), |
.SRST(), |
.WR_RST(), |
.RD_RST(), |
.PROG_EMPTY_THRESH(), |
.PROG_EMPTY_THRESH_ASSERT(), |
.PROG_EMPTY_THRESH_NEGATE(), |
.PROG_FULL_THRESH(), |
.PROG_FULL_THRESH_ASSERT(), |
.PROG_FULL_THRESH_NEGATE(), |
.INT_CLK(), |
.INJECTDBITERR(), |
.INJECTSBITERR(), |
.ALMOST_FULL(), |
.WR_ACK(), |
.OVERFLOW(), |
.ALMOST_EMPTY(), |
.VALID(), |
.UNDERFLOW(), |
.DATA_COUNT(), |
.PROG_FULL(), |
.PROG_EMPTY(), |
.SBITERR(), |
.DBITERR(), |
.M_ACLK(), |
.S_ACLK(), |
.S_ARESETN(), |
.M_ACLK_EN(), |
.S_ACLK_EN(), |
.S_AXI_AWID(), |
.S_AXI_AWADDR(), |
.S_AXI_AWLEN(), |
.S_AXI_AWSIZE(), |
.S_AXI_AWBURST(), |
.S_AXI_AWLOCK(), |
.S_AXI_AWCACHE(), |
.S_AXI_AWPROT(), |
.S_AXI_AWQOS(), |
.S_AXI_AWREGION(), |
.S_AXI_AWUSER(), |
.S_AXI_AWVALID(), |
.S_AXI_AWREADY(), |
.S_AXI_WID(), |
.S_AXI_WDATA(), |
.S_AXI_WSTRB(), |
.S_AXI_WLAST(), |
.S_AXI_WUSER(), |
.S_AXI_WVALID(), |
.S_AXI_WREADY(), |
.S_AXI_BID(), |
.S_AXI_BRESP(), |
.S_AXI_BUSER(), |
.S_AXI_BVALID(), |
.S_AXI_BREADY(), |
.M_AXI_AWID(), |
.M_AXI_AWADDR(), |
.M_AXI_AWLEN(), |
.M_AXI_AWSIZE(), |
.M_AXI_AWBURST(), |
.M_AXI_AWLOCK(), |
.M_AXI_AWCACHE(), |
.M_AXI_AWPROT(), |
.M_AXI_AWQOS(), |
.M_AXI_AWREGION(), |
.M_AXI_AWUSER(), |
.M_AXI_AWVALID(), |
.M_AXI_AWREADY(), |
.M_AXI_WID(), |
.M_AXI_WDATA(), |
.M_AXI_WSTRB(), |
.M_AXI_WLAST(), |
.M_AXI_WUSER(), |
.M_AXI_WVALID(), |
.M_AXI_WREADY(), |
.M_AXI_BID(), |
.M_AXI_BRESP(), |
.M_AXI_BUSER(), |
.M_AXI_BVALID(), |
.M_AXI_BREADY(), |
.S_AXI_ARID(), |
.S_AXI_ARADDR(), |
.S_AXI_ARLEN(), |
.S_AXI_ARSIZE(), |
.S_AXI_ARBURST(), |
.S_AXI_ARLOCK(), |
.S_AXI_ARCACHE(), |
.S_AXI_ARPROT(), |
.S_AXI_ARQOS(), |
.S_AXI_ARREGION(), |
.S_AXI_ARUSER(), |
.S_AXI_ARVALID(), |
.S_AXI_ARREADY(), |
.S_AXI_RID(), |
.S_AXI_RDATA(), |
.S_AXI_RRESP(), |
.S_AXI_RLAST(), |
.S_AXI_RUSER(), |
.S_AXI_RVALID(), |
.S_AXI_RREADY(), |
.M_AXI_ARID(), |
.M_AXI_ARADDR(), |
.M_AXI_ARLEN(), |
.M_AXI_ARSIZE(), |
.M_AXI_ARBURST(), |
.M_AXI_ARLOCK(), |
.M_AXI_ARCACHE(), |
.M_AXI_ARPROT(), |
.M_AXI_ARQOS(), |
.M_AXI_ARREGION(), |
.M_AXI_ARUSER(), |
.M_AXI_ARVALID(), |
.M_AXI_ARREADY(), |
.M_AXI_RID(), |
.M_AXI_RDATA(), |
.M_AXI_RRESP(), |
.M_AXI_RLAST(), |
.M_AXI_RUSER(), |
.M_AXI_RVALID(), |
.M_AXI_RREADY(), |
.S_AXIS_TVALID(), |
.S_AXIS_TREADY(), |
.S_AXIS_TDATA(), |
.S_AXIS_TSTRB(), |
.S_AXIS_TKEEP(), |
.S_AXIS_TLAST(), |
.S_AXIS_TID(), |
.S_AXIS_TDEST(), |
.S_AXIS_TUSER(), |
.M_AXIS_TVALID(), |
.M_AXIS_TREADY(), |
.M_AXIS_TDATA(), |
.M_AXIS_TSTRB(), |
.M_AXIS_TKEEP(), |
.M_AXIS_TLAST(), |
.M_AXIS_TID(), |
.M_AXIS_TDEST(), |
.M_AXIS_TUSER(), |
.AXI_AW_INJECTSBITERR(), |
.AXI_AW_INJECTDBITERR(), |
.AXI_AW_PROG_FULL_THRESH(), |
.AXI_AW_PROG_EMPTY_THRESH(), |
.AXI_AW_DATA_COUNT(), |
.AXI_AW_WR_DATA_COUNT(), |
.AXI_AW_RD_DATA_COUNT(), |
.AXI_AW_SBITERR(), |
.AXI_AW_DBITERR(), |
.AXI_AW_OVERFLOW(), |
.AXI_AW_UNDERFLOW(), |
.AXI_AW_PROG_FULL(), |
.AXI_AW_PROG_EMPTY(), |
.AXI_W_INJECTSBITERR(), |
.AXI_W_INJECTDBITERR(), |
.AXI_W_PROG_FULL_THRESH(), |
.AXI_W_PROG_EMPTY_THRESH(), |
.AXI_W_DATA_COUNT(), |
.AXI_W_WR_DATA_COUNT(), |
.AXI_W_RD_DATA_COUNT(), |
.AXI_W_SBITERR(), |
.AXI_W_DBITERR(), |
.AXI_W_OVERFLOW(), |
.AXI_W_UNDERFLOW(), |
.AXI_B_INJECTSBITERR(), |
.AXI_W_PROG_FULL(), |
.AXI_W_PROG_EMPTY(), |
.AXI_B_INJECTDBITERR(), |
.AXI_B_PROG_FULL_THRESH(), |
.AXI_B_PROG_EMPTY_THRESH(), |
.AXI_B_DATA_COUNT(), |
.AXI_B_WR_DATA_COUNT(), |
.AXI_B_RD_DATA_COUNT(), |
.AXI_B_SBITERR(), |
.AXI_B_DBITERR(), |
.AXI_B_OVERFLOW(), |
.AXI_B_UNDERFLOW(), |
.AXI_AR_INJECTSBITERR(), |
.AXI_B_PROG_FULL(), |
.AXI_B_PROG_EMPTY(), |
.AXI_AR_INJECTDBITERR(), |
.AXI_AR_PROG_FULL_THRESH(), |
.AXI_AR_PROG_EMPTY_THRESH(), |
.AXI_AR_DATA_COUNT(), |
.AXI_AR_WR_DATA_COUNT(), |
.AXI_AR_RD_DATA_COUNT(), |
.AXI_AR_SBITERR(), |
.AXI_AR_DBITERR(), |
.AXI_AR_OVERFLOW(), |
.AXI_AR_UNDERFLOW(), |
.AXI_AR_PROG_FULL(), |
.AXI_AR_PROG_EMPTY(), |
.AXI_R_INJECTSBITERR(), |
.AXI_R_INJECTDBITERR(), |
.AXI_R_PROG_FULL_THRESH(), |
.AXI_R_PROG_EMPTY_THRESH(), |
.AXI_R_DATA_COUNT(), |
.AXI_R_WR_DATA_COUNT(), |
.AXI_R_RD_DATA_COUNT(), |
.AXI_R_SBITERR(), |
.AXI_R_DBITERR(), |
.AXI_R_OVERFLOW(), |
.AXI_R_UNDERFLOW(), |
.AXIS_INJECTSBITERR(), |
.AXI_R_PROG_FULL(), |
.AXI_R_PROG_EMPTY(), |
.AXIS_INJECTDBITERR(), |
.AXIS_PROG_FULL_THRESH(), |
.AXIS_PROG_EMPTY_THRESH(), |
.AXIS_DATA_COUNT(), |
.AXIS_WR_DATA_COUNT(), |
.AXIS_RD_DATA_COUNT(), |
.AXIS_SBITERR(), |
.AXIS_DBITERR(), |
.AXIS_OVERFLOW(), |
.AXIS_UNDERFLOW(), |
.AXIS_PROG_FULL(), |
.AXIS_PROG_EMPTY() |
); |
|
// synthesis translate_on |
|
endmodule |
/xilinx/ip/cleanup.sh
0,0 → 1,491
rm -f *.txt *.gise *.cdc *.veo *.xdc *.xise *.tcl *.ucf *.ncf *.asy |
/xilinx/ip/define.h
0,0 → 1,491
`define USE_XILINX_IP |
/xilinx/ip/dcfifo_128b_16.ngc
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.6e |
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|
/xilinx/ip/dcfifo_128b_16.xco
0,0 → 1,213
############################################################## |
# |
# Xilinx Core Generator version 14.3 |
# Date: Mon Feb 04 13:33:11 2013 |
# |
############################################################## |
# |
# This file contains the customisation parameters for a |
# Xilinx CORE Generator IP GUI. It is strongly recommended |
# that you do not manually alter this file as it may cause |
# unexpected and unsupported behavior. |
# |
############################################################## |
# |
# Generated from component: xilinx.com:ip:fifo_generator:9.3 |
# |
############################################################## |
# |
# BEGIN Project Options |
SET addpads = false |
SET asysymbol = false |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = Verilog |
SET device = xc7vx330t |
SET devicefamily = virtex7 |
SET flowvendor = Other |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = ffg1157 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -3 |
SET verilogsim = true |
SET vhdlsim = false |
# END Project Options |
# BEGIN Select |
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 |
# END Select |
# BEGIN Parameters |
CSET add_ngc_constraint_axi=false |
CSET almost_empty_flag=false |
CSET almost_full_flag=false |
CSET aruser_width=1 |
CSET awuser_width=1 |
CSET axi_address_width=32 |
CSET axi_data_width=64 |
CSET axi_type=AXI4_Stream |
CSET axis_type=FIFO |
CSET buser_width=1 |
CSET clock_enable_type=Slave_Interface_Clock_Enable |
CSET clock_type_axi=Common_Clock |
CSET component_name=dcfifo_128b_16 |
CSET data_count=false |
CSET data_count_width=4 |
CSET disable_timing_violations=false |
CSET disable_timing_violations_axi=false |
CSET dout_reset_value=0 |
CSET empty_threshold_assert_value=2 |
CSET empty_threshold_assert_value_axis=1022 |
CSET empty_threshold_assert_value_rach=1022 |
CSET empty_threshold_assert_value_rdch=1022 |
CSET empty_threshold_assert_value_wach=1022 |
CSET empty_threshold_assert_value_wdch=1022 |
CSET empty_threshold_assert_value_wrch=1022 |
CSET empty_threshold_negate_value=3 |
CSET enable_aruser=false |
CSET enable_awuser=false |
CSET enable_buser=false |
CSET enable_common_overflow=false |
CSET enable_common_underflow=false |
CSET enable_data_counts_axis=false |
CSET enable_data_counts_rach=false |
CSET enable_data_counts_rdch=false |
CSET enable_data_counts_wach=false |
CSET enable_data_counts_wdch=false |
CSET enable_data_counts_wrch=false |
CSET enable_ecc=false |
CSET enable_ecc_axis=false |
CSET enable_ecc_rach=false |
CSET enable_ecc_rdch=false |
CSET enable_ecc_wach=false |
CSET enable_ecc_wdch=false |
CSET enable_ecc_wrch=false |
CSET enable_read_channel=false |
CSET enable_read_pointer_increment_by2=false |
CSET enable_reset_synchronization=true |
CSET enable_ruser=false |
CSET enable_tdata=false |
CSET enable_tdest=false |
CSET enable_tid=false |
CSET enable_tkeep=false |
CSET enable_tlast=false |
CSET enable_tready=true |
CSET enable_tstrobe=false |
CSET enable_tuser=false |
CSET enable_write_channel=false |
CSET enable_wuser=false |
CSET fifo_application_type_axis=Data_FIFO |
CSET fifo_application_type_rach=Data_FIFO |
CSET fifo_application_type_rdch=Data_FIFO |
CSET fifo_application_type_wach=Data_FIFO |
CSET fifo_application_type_wdch=Data_FIFO |
CSET fifo_application_type_wrch=Data_FIFO |
CSET fifo_implementation=Independent_Clocks_Block_RAM |
CSET fifo_implementation_axis=Common_Clock_Block_RAM |
CSET fifo_implementation_rach=Common_Clock_Block_RAM |
CSET fifo_implementation_rdch=Common_Clock_Block_RAM |
CSET fifo_implementation_wach=Common_Clock_Block_RAM |
CSET fifo_implementation_wdch=Common_Clock_Block_RAM |
CSET fifo_implementation_wrch=Common_Clock_Block_RAM |
CSET full_flags_reset_value=0 |
CSET full_threshold_assert_value=13 |
CSET full_threshold_assert_value_axis=1023 |
CSET full_threshold_assert_value_rach=1023 |
CSET full_threshold_assert_value_rdch=1023 |
CSET full_threshold_assert_value_wach=1023 |
CSET full_threshold_assert_value_wdch=1023 |
CSET full_threshold_assert_value_wrch=1023 |
CSET full_threshold_negate_value=12 |
CSET id_width=4 |
CSET inject_dbit_error=false |
CSET inject_dbit_error_axis=false |
CSET inject_dbit_error_rach=false |
CSET inject_dbit_error_rdch=false |
CSET inject_dbit_error_wach=false |
CSET inject_dbit_error_wdch=false |
CSET inject_dbit_error_wrch=false |
CSET inject_sbit_error=false |
CSET inject_sbit_error_axis=false |
CSET inject_sbit_error_rach=false |
CSET inject_sbit_error_rdch=false |
CSET inject_sbit_error_wach=false |
CSET inject_sbit_error_wdch=false |
CSET inject_sbit_error_wrch=false |
CSET input_data_width=128 |
CSET input_depth=16 |
CSET input_depth_axis=1024 |
CSET input_depth_rach=16 |
CSET input_depth_rdch=1024 |
CSET input_depth_wach=16 |
CSET input_depth_wdch=1024 |
CSET input_depth_wrch=16 |
CSET interface_type=Native |
CSET output_data_width=128 |
CSET output_depth=16 |
CSET overflow_flag=false |
CSET overflow_flag_axi=false |
CSET overflow_sense=Active_High |
CSET overflow_sense_axi=Active_High |
CSET performance_options=Standard_FIFO |
CSET programmable_empty_type=No_Programmable_Empty_Threshold |
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold |
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold |
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold |
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold |
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold |
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold |
CSET programmable_full_type=No_Programmable_Full_Threshold |
CSET programmable_full_type_axis=No_Programmable_Full_Threshold |
CSET programmable_full_type_rach=No_Programmable_Full_Threshold |
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold |
CSET programmable_full_type_wach=No_Programmable_Full_Threshold |
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold |
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold |
CSET rach_type=FIFO |
CSET rdch_type=FIFO |
CSET read_clock_frequency=1 |
CSET read_data_count=true |
CSET read_data_count_width=4 |
CSET register_slice_mode_axis=Fully_Registered |
CSET register_slice_mode_rach=Fully_Registered |
CSET register_slice_mode_rdch=Fully_Registered |
CSET register_slice_mode_wach=Fully_Registered |
CSET register_slice_mode_wdch=Fully_Registered |
CSET register_slice_mode_wrch=Fully_Registered |
CSET reset_pin=true |
CSET reset_type=Asynchronous_Reset |
CSET ruser_width=1 |
CSET synchronization_stages=2 |
CSET synchronization_stages_axi=2 |
CSET tdata_width=64 |
CSET tdest_width=4 |
CSET tid_width=8 |
CSET tkeep_width=4 |
CSET tstrb_width=4 |
CSET tuser_width=4 |
CSET underflow_flag=false |
CSET underflow_flag_axi=false |
CSET underflow_sense=Active_High |
CSET underflow_sense_axi=Active_High |
CSET use_clock_enable=false |
CSET use_dout_reset=true |
CSET use_embedded_registers=true |
CSET use_extra_logic=false |
CSET valid_flag=false |
CSET valid_sense=Active_High |
CSET wach_type=FIFO |
CSET wdch_type=FIFO |
CSET wrch_type=FIFO |
CSET write_acknowledge_flag=false |
CSET write_acknowledge_sense=Active_High |
CSET write_clock_frequency=1 |
CSET write_data_count=true |
CSET write_data_count_width=4 |
CSET wuser_width=1 |
# END Parameters |
# BEGIN Extra information |
MISC pkg_timestamp=2012-07-25T18:11:59Z |
# END Extra information |
GENERATE |
# CRC: e52bce2e |
/xilinx/ip/coregen.cgp
0,0 → 1,22
# Date: Sat Feb 02 08:52:06 2013 |
|
SET addpads = false |
SET asysymbol = false |
SET busformat = BusFormatAngleBracketNotRipped |
SET createndf = false |
SET designentry = Verilog |
SET device = xc7vx330t |
SET devicefamily = virtex7 |
SET flowvendor = Other |
SET formalverification = false |
SET foundationsym = false |
SET implementationfiletype = Ngc |
SET package = ffg1157 |
SET removerpms = false |
SET simulationfiles = Behavioral |
SET speedgrade = -3 |
SET verilogsim = true |
SET vhdlsim = false |
SET workingdirectory = .\tmp\ |
|
# CRC: 2066751 |
/xilinx/ip/cleanup.bat
0,0 → 1,22
del *.txt *.gise *.cdc *.veo *.xdc *.xise *.tcl *.ucf *.ncf *.asy |
/xilinx/ip/coregen.cgc
0,0 → 1,939
<?xml version="1.0" encoding="UTF-8"?> |
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" > |
<spirit:vendor>xilinx.com</spirit:vendor> |
<spirit:library>project</spirit:library> |
<spirit:name>coregen</spirit:name> |
<spirit:version>1.0</spirit:version> |
<spirit:componentInstances> |
<spirit:componentInstance> |
<spirit:instanceName>dcfifo_128b_16</spirit:instanceName> |
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="9.3" /> |
<spirit:configurableElementValues> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">dcfifo_128b_16</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION">Independent_Clocks_Block_RAM</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">2</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES_AXI">2</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PERFORMANCE_OPTIONS">Standard_FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DATA_WIDTH">128</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH">16</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DATA_WIDTH">128</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DEPTH">16</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PIN">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET_SYNCHRONIZATION">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">Asynchronous_Reset</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_FLAGS_RESET_VALUE">0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DOUT_RESET">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_RESET_VALUE">0</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_FULL_FLAG">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_EMPTY_FLAG">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_FLAG">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_SENSE">Active_High</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE">Active_High</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_FLAG">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_SENSE">Active_High</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE">Active_High</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXTRA_LOGIC">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT_WIDTH">4</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT_WIDTH">4</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT_WIDTH">4</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_CLOCK_FREQUENCY">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_CLOCK_FREQUENCY">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE">No_Programmable_Full_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE">13</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_NEGATE_VALUE">12</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE">No_Programmable_Empty_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE">2</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_NEGATE_VALUE">3</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Stream</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_TYPE_AXI">Common_Clock</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_ENABLE">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_ENABLE_TYPE">Slave_Interface_Clock_Enable</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WRITE_CHANNEL">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_CHANNEL">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDRESS_WIDTH">32</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DATA_WIDTH">64</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_AWUSER">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WUSER">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BUSER">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ARUSER">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RUSER">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">1</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDATA">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_WIDTH">64</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TID">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">8</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDEST">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">4</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TUSER">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TREADY">true</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TLAST">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TSTROBE">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">4</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TKEEP">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">4</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WACH_TYPE">FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WACH">Common_Clock_Block_RAM</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WACH">Data_FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WACH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WACH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WACH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WACH">16</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WACH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WACH">No_Programmable_Full_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WACH">1023</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WACH">1022</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WDCH_TYPE">FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WDCH">Common_Clock_Block_RAM</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WDCH">Data_FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WDCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WDCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WDCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WDCH">1024</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WDCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WDCH">1023</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WDCH">1022</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRCH_TYPE">FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WRCH">Common_Clock_Block_RAM</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WRCH">Data_FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WRCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WRCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WRCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WRCH">16</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WRCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WRCH">No_Programmable_Full_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WRCH">1023</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WRCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WRCH">1022</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RACH_TYPE">FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RACH">Common_Clock_Block_RAM</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RACH">Data_FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RACH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RACH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RACH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RACH">16</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RACH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RACH">No_Programmable_Full_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RACH">1023</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RACH">No_Programmable_Empty_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RACH">1022</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDCH_TYPE">FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RDCH">Common_Clock_Block_RAM</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RDCH">Data_FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RDCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RDCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RDCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RDCH">1024</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RDCH">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RDCH">No_Programmable_Full_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RDCH">1023</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RDCH">No_Programmable_Empty_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RDCH">1022</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXIS_TYPE">FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_AXIS">Common_Clock_Block_RAM</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_AXIS">Data_FIFO</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_AXIS">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_AXIS">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_AXIS">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_AXIS">1024</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_AXIS">false</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_AXIS">No_Programmable_Full_Threshold</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_AXIS">1023</spirit:configurableElementValue> |
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_AXIS">No_Programmable_Empty_Threshold</spirit:configurableElementValue> |
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<xilinx:checkSum>0x88F84BC0</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16/simulation/timing/wave_isim.tcl</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>tcl</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:33:14 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0xFDE9214A</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16/simulation/timing/wave_mti.do</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>unknown</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:33:14 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x82BB2BF0</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16/simulation/timing/wave_ncsim.sv</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>unknown</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:33:14 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x0E95A497</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>ngc_netlist_generator</xilinx:name> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16.ngc</xilinx:name> |
<xilinx:userFileType>ngc</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:34:56 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x1BAFB488</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>obfuscate_netlist_generator</xilinx:name> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>padded_implementation_netlist_generator</xilinx:name> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>instantiation_template_generator</xilinx:name> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16.veo</xilinx:name> |
<xilinx:userFileType>veo</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:34:57 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0xCFCA16A7</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>structural_simulation_model_generator</xilinx:name> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16.v</xilinx:name> |
<xilinx:userFileType>verilog</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:34:57 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0xED78854A</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>all_documents_generator</xilinx:name> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16/doc/fifo_generator_v9_3_readme.txt</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>txt</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:34:58 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0xD700FB89</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16/doc/fifo_generator_v9_3_vinfo.html</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>unknown</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:34:58 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x5A766369</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16/doc/pg057-fifo-generator.pdf</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>pdf</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:34:58 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x1E7EB5CF</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>readme_documents_generator</xilinx:name> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>asy_generator</xilinx:name> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>xmdf_generator</xilinx:name> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16_xmdf.tcl</xilinx:name> |
<xilinx:userFileType>tclXmdf</xilinx:userFileType> |
<xilinx:userFileType>tcl</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:34:58 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x5C093755</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>synthesis_ise_generator</xilinx:name> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16.gise</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>gise</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:35:06 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x7F79B55A</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16.xise</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>xise</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:35:06 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x5720AD26</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>ise_generator</xilinx:name> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16.gise</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>gise</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:35:10 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x22FA6F25</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16.xise</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>xise</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:35:10 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x766DEC71</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>deliver_readme_generator</xilinx:name> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>flist_generator</xilinx:name> |
<xilinx:file> |
<xilinx:name>./dcfifo_128b_16_flist.txt</xilinx:name> |
<xilinx:userFileType>ignore</xilinx:userFileType> |
<xilinx:userFileType>txtFlist</xilinx:userFileType> |
<xilinx:userFileType>txt</xilinx:userFileType> |
<xilinx:timeStamp>Mon Feb 04 13:35:10 GMT 2013</xilinx:timeStamp> |
<xilinx:checkSum>0x65B154FB</xilinx:checkSum> |
<xilinx:generationId>generationID_1879581046</xilinx:generationId> |
</xilinx:file> |
</xilinx:fileSet> |
<xilinx:fileSet> |
<xilinx:name>view_readme_generator</xilinx:name> |
</xilinx:fileSet> |
</xilinx:generationHistory> |
</spirit:vendorExtensions> |
</spirit:componentInstance> |
</spirit:componentInstances> |
<spirit:vendorExtensions> |
<xilinx:instanceProperties> |
<xilinx:projectOptions> |
<xilinx:projectName>coregen</xilinx:projectName> |
<xilinx:outputDirectory>./</xilinx:outputDirectory> |
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory> |
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory> |
</xilinx:projectOptions> |
<xilinx:part> |
<xilinx:device>xc7vx330t</xilinx:device> |
<xilinx:deviceFamily>virtex7</xilinx:deviceFamily> |
<xilinx:package>ffg1157</xilinx:package> |
<xilinx:speedGrade>-3</xilinx:speedGrade> |
</xilinx:part> |
<xilinx:flowOptions> |
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat> |
<xilinx:designEntry>Verilog</xilinx:designEntry> |
<xilinx:asySymbol>false</xilinx:asySymbol> |
<xilinx:flowVendor>Other</xilinx:flowVendor> |
<xilinx:addPads>false</xilinx:addPads> |
<xilinx:removeRPMs>false</xilinx:removeRPMs> |
<xilinx:createNDF>false</xilinx:createNDF> |
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType> |
<xilinx:formalVerification>false</xilinx:formalVerification> |
</xilinx:flowOptions> |
<xilinx:simulationOptions> |
<xilinx:simulationModel>Behavioral</xilinx:simulationModel> |
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage> |
<xilinx:foundationSym>false</xilinx:foundationSym> |
</xilinx:simulationOptions> |
</xilinx:instanceProperties> |
</spirit:vendorExtensions> |
</spirit:design> |
|
/xilinx/ha1588.ucf
0,0 → 1,17
|
NET "clk" TNM_NET = "TS_CPU_GRP"; |
TIMESPEC "TS_CPU" = PERIOD "TS_CPU_GRP" 10 ns HIGH 50%; |
|
NET "rtc_clk" TNM_NET = "TS_RTC_GRP"; |
TIMESPEC "TS_RTC" = PERIOD "TS_RTC_GRP" 8 ns HIGH 50%; |
|
NET "rx_gmii_clk" TNM_NET = "TS_RX_GRP"; |
TIMESPEC "TS_RX" = PERIOD "TS_RX_GRP" 8 ns HIGH 50%; |
|
NET "tx_gmii_clk" TNM_NET = "TS_TX_GRP"; |
TIMESPEC "TS_TX" = PERIOD "TS_TX_GRP" 8 ns HIGH 50%; |
|
TIMESPEC TS_FALSE_PATH0 = FROM TS_CPU_GRP TO TS_RTC_GRP 10 ns DATAPATHONLY; |
TIMESPEC TS_FALSE_PATH1 = FROM TS_RTC_GRP TO TS_CPU_GRP 8 ns DATAPATHONLY; |
|
|
/xilinx/cleanup.bat
0,0 → 1,2
rmdir /S /Q .Xil ha1588.srcs ha1588.data ha1588.runs ha1588.cache |
del *.log *.jou |
/xilinx/ha1588.ppr
0,0 → 1,28
<?xml version="1.0"?> |
<!--Product Version: PlanAhead v14.3--> |
<Project Version="4" Minor="36"> |
<FileSet Dir="sources_1" File="fileset.xml"/> |
<FileSet Dir="constrs_1" File="fileset.xml"/> |
<FileSet Dir="sim_1" File="fileset.xml"/> |
<RunSet Dir="runs" File="runs.xml"/> |
<DefaultLaunch Dir="$PRUNDIR"/> |
<DefaultPromote Dir="$PROMOTEDIR"/> |
<Config> |
<Option Name="Id" Val="1fb7eaafab3c4053a159b0b999c44d10"/> |
<Option Name="Part" Val="xc7z020clg484-1"/> |
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> |
<Option Name="TargetLanguage" Val="Verilog"/> |
<Option Name="TargetSimulator" Val="ISim"/> |
<Option Name="Board" Val="zc702"/> |
<Option Name="SourceMgmtMode" Val="All"/> |
<Option Name="ActiveSimSet" Val="sim_1"/> |
<Option Name="CxlOverwriteLibs" Val="1"/> |
<Option Name="CxlFuncsim" Val="1"/> |
<Option Name="CxlTimesim" Val="1"/> |
<Option Name="CxlCore" Val="1"/> |
<Option Name="CxlEdk" Val="0"/> |
<Option Name="CxlExcludeCores" Val="1"/> |
<Option Name="CxlExcludeSubLibs" Val="0"/> |
</Config> |
</Project> |
|