URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588/trunk/rtl/top
- from Rev 30 to Rev 32
- ↔ Reverse comparison
Rev 30 → Rev 32
/ha1588.v
7,7 → 7,9
input [31:0] data_in, |
output [31:0] data_out, |
|
input rtc_clk, |
input rtc_clk, |
output [31:0] rtc_time_ptp_ns, |
output [47:0] rtc_time_ptp_sec, |
|
input rx_gmii_clk, |
input rx_gmii_ctrl, |
27,7 → 29,7
wire [39:0] rtc_period_adj; |
wire [37:0] rtc_time_reg_ns_val; |
wire [47:0] rtc_time_reg_sec_val; |
wire [35:0] rtc_time_reg_val = {rtc_time_reg_sec_val[3:0], 2'b00, rtc_time_reg_ns_val[37:8]}; // 16.000,000,000 sec |
wire [79:0] rtc_time_ptp_val = {rtc_time_ptp_sec[47:0], rtc_time_ptp_ns[31:0]}; |
|
wire rx_q_rst, rx_q_clk; |
wire rx_q_rd_en; |
86,7 → 88,9
.adj_ld_data(rtc_adj_ld_data), |
.period_adj(rtc_period_adj), |
.time_reg_ns(rtc_time_reg_ns_val), |
.time_reg_sec(rtc_time_reg_sec_val) |
.time_reg_sec(rtc_time_reg_sec_val), |
.time_ptp_ns(rtc_time_ptp_ns), |
.time_ptp_sec(rtc_time_ptp_sec) |
); |
|
tsu u_rx_tsu |
96,7 → 100,7
.gmii_ctrl(rx_gmii_ctrl), |
.gmii_data(rx_gmii_data), |
.rtc_timer_clk(rtc_clk), |
.rtc_timer_in(rtc_time_reg_val), |
.rtc_timer_in(rtc_time_ptp_val), |
.q_rst(rx_q_rst), |
.q_rd_clk(rx_q_clk), |
.q_rd_en(rx_q_rd_en), |
111,7 → 115,7
.gmii_ctrl(tx_gmii_ctrl), |
.gmii_data(tx_gmii_data), |
.rtc_timer_clk(rtc_clk), |
.rtc_timer_in(rtc_time_reg_val), |
.rtc_timer_in(rtc_time_ptp_val), |
.q_rst(tx_q_rst), |
.q_rd_clk(tx_q_clk), |
.q_rd_en(tx_q_rd_en), |
/ha1588_hw.tcl
1,5 → 1,5
# TCL File Generated by Component Editor 10.1sp1 |
# Sat Mar 31 15:26:56 CST 2012 |
# Sat Mar 31 21:26:56 CST 2012 |
# DO NOT MODIFY |
|
|
6,7 → 6,7
# +----------------------------------- |
# | |
# | ha1588 "Hardware Assisted IEEE 1588 IP Core" v1.0 |
# | Walter EDN 2012.03.31.15:26:56 |
# | B.B.Y.&H.W. 2012.03.31.21:26:56 |
# | Hardware Assisted IEEE 1588 IP Core |
# | |
# | ha1588.v |
35,7 → 35,7
set_module_property VERSION 1.0 |
set_module_property INTERNAL false |
set_module_property OPAQUE_ADDRESS_MAP true |
set_module_property AUTHOR "Walter EDN" |
set_module_property AUTHOR "B.B.Y.&H.W." |
set_module_property DISPLAY_NAME "Hardware Assisted IEEE 1588 IP Core" |
set_module_property TOP_LEVEL_HDL_FILE ha1588.v |
set_module_property TOP_LEVEL_HDL_MODULE ha1588 |
121,6 → 121,8
set_interface_property ref_clock ENABLED true |
|
add_interface_port ref_clock rtc_clk export Input 1 |
add_interface_port ref_clock rtc_time_ptp_ns export Output 32 |
add_interface_port ref_clock rtc_time_ptp_sec export Output 48 |
# | |
# +----------------------------------- |
|