URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588/trunk/rtl
- from Rev 25 to Rev 27
- ↔ Reverse comparison
Rev 25 → Rev 27
/top/ha1588.v
27,16 → 27,16
wire [39:0] rtc_period_adj; |
wire [37:0] rtc_time_reg_ns_val; |
wire [47:0] rtc_time_reg_sec_val; |
wire [31:0] rtc_time_reg_val = {rtc_time_reg_sec_val[1:0],rtc_time_reg_ns_val[37:8]}; // 4.000000000 sec |
wire [35:0] rtc_time_reg_val = {rtc_time_reg_sec_val[5:0],rtc_time_reg_ns_val[37:8]}; // 64.000,000,000 sec |
|
wire rx_q_rst, rx_q_clk; |
wire rx_q_rd_en; |
wire [ 7:0] rx_q_stat; |
wire [55:0] rx_q_data; |
wire [63:0] rx_q_data; |
wire tx_q_rst, tx_q_clk; |
wire tx_q_rd_en; |
wire [ 7:0] tx_q_stat; |
wire [55:0] tx_q_data; |
wire [63:0] tx_q_data; |
|
rgs u_rgs |
( |
/tsu/tsu.v
8,13 → 8,13
input [7:0] gmii_data, |
|
input rtc_timer_clk, |
input [31:0] rtc_timer_in, // timeStamp1s_2bit + timeStamp1ns_30bit |
input [35:0] rtc_timer_in, // timeStamp1s_6bit + timeStamp1ns_30bit |
|
input q_rst, |
input q_rd_clk, |
input q_rd_en, |
output [ 7:0] q_rd_stat, |
output [55:0] q_rd_data // null_4bit + seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit |
output [63:0] q_rd_data // seqId_16bit + msgId_4bit + null_8bit + timeStamp1s_6bit + timeStamp1ns_30bit |
); |
|
// buffer gmii input |
60,10 → 60,10
ts_req_d3 <= ts_req_d2; |
end |
end |
reg [31:0] rtc_time_stamp; |
reg [35:0] rtc_time_stamp; |
always @(posedge rst or posedge rtc_timer_clk) begin |
if (rst) |
rtc_time_stamp <= 32'd0; |
rtc_time_stamp <= 36'd0; |
else |
if (ts_req_d2 & !ts_req_d3) |
rtc_time_stamp <= rtc_timer_in; |
90,10 → 90,10
ts_ack_d3 <= ts_ack_d2; |
end |
end |
reg [31:0] gmii_time_stamp; |
reg [35:0] gmii_time_stamp; |
always @(posedge rst or posedge gmii_clk) begin |
if (rst) begin |
gmii_time_stamp <= 32'd0; |
gmii_time_stamp <= 36'd0; |
ts_ack_clr <= 1'b0; |
end |
else begin |
162,7 → 162,7
// ptp packet parser here |
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint |
wire ptp_found; |
wire [51:0] ptp_infor; |
wire [19:0] ptp_infor; |
ptp_parser parser( |
.clk(gmii_clk), |
.rst(rst), |
171,7 → 171,6
.int_sop(int_sop), |
.int_eop(int_eop), |
.int_mod(int_mod), |
.sop_time(gmii_time_stamp), |
.ptp_found(ptp_found), |
.ptp_infor(ptp_infor) |
); |
179,7 → 178,7
// ptp time stamp dcfifo |
wire q_wr_clk = gmii_clk; |
wire q_wr_en = ptp_found; |
wire [55:0] q_wr_data = {4'd0, ptp_infor}; |
wire [63:0] q_wr_data = {ptp_infor, 8'd0, gmii_time_stamp}; // 20+8+36 bit |
wire [3:0] q_wrusedw; |
wire [3:0] q_rdusedw; |
|
187,12 → 186,12
.aclr(q_rst), |
|
.wrclk(q_wr_clk), |
.wrreq(q_wr_en && q_wrusedw<=15), |
.wrreq(q_wr_en && q_wrusedw<=15), // write with overflow protection |
.data(q_wr_data), |
.wrusedw(q_wrusedw), |
|
.rdclk(q_rd_clk), |
.rdreq(q_rd_en && q_rdusedw>=1), |
.rdreq(q_rd_en && q_rdusedw>= 1), // read with underflow protection |
.q(q_rd_data), |
.rdusedw(q_rdusedw) |
); |
/tsu/ptp_parser.v
7,10 → 7,9
input int_sop, |
input int_eop, |
input [ 1:0] int_mod, |
input [31:0] sop_time, |
|
output reg ptp_found, |
output reg [51:0] ptp_infor |
output reg [19:0] ptp_infor |
); |
|
reg [31:0] int_data_d1; |
190,19 → 189,19
always @(posedge rst or posedge clk) begin |
if (rst) begin |
ptp_found <= 1'b0; |
ptp_infor <= 52'd0; |
ptp_infor <= 20'd0; |
end |
else if (int_valid_d1 && int_sop_d1) begin |
ptp_found <= 1'b0; |
ptp_infor <= 52'd0; |
ptp_infor <= 20'd0; |
end |
else if (int_valid_d1 && int_eop_d1) begin |
ptp_found <= ptp_event; |
ptp_infor <= {ptp_seqid, ptp_msgid, sop_time}; // 16+4+32 |
ptp_infor <= {ptp_seqid, ptp_msgid}; // 16+4 |
end |
else begin |
ptp_found <= 1'b0; |
ptp_infor <= 52'd0; |
ptp_infor <= 20'd0; |
end |
end |
|
/tsu/ptp_queue.v
1,177 → 1,177
// megafunction wizard: %FIFO% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
// MODULE: dcfifo |
|
// ============================================================ |
// File Name: ptp_queue.v |
// Megafunction Name(s): |
// dcfifo |
// |
// Simulation Library Files(s): |
// altera_mf |
// ============================================================ |
// ************************************************************ |
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
// |
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition |
// ************************************************************ |
|
|
//Copyright (C) 1991-2011 Altera Corporation |
//Your use of Altera Corporation's design tools, logic functions |
//and other software and tools, and its AMPP partner logic |
//functions, and any output files from any of the foregoing |
//(including device programming or simulation files), and any |
//associated documentation or information are expressly subject |
//to the terms and conditions of the Altera Program License |
//Subscription Agreement, Altera MegaCore Function License |
//Agreement, or other applicable license agreement, including, |
//without limitation, that your use is for the sole purpose of |
//programming logic devices manufactured by Altera and sold by |
//Altera or its authorized distributors. Please refer to the |
//applicable agreement for further details. |
|
|
// synopsys translate_off |
`timescale 1 ps / 1 ps |
// synopsys translate_on |
module ptp_queue ( |
aclr, |
data, |
rdclk, |
rdreq, |
wrclk, |
wrreq, |
q, |
rdusedw, |
wrusedw); |
|
input aclr; |
input [55:0] data; |
input rdclk; |
input rdreq; |
input wrclk; |
input wrreq; |
output [55:0] q; |
output [3:0] rdusedw; |
output [3:0] wrusedw; |
`ifndef ALTERA_RESERVED_QIS |
// synopsys translate_off |
`endif |
tri0 aclr; |
`ifndef ALTERA_RESERVED_QIS |
// synopsys translate_on |
`endif |
|
wire [55:0] sub_wire0; |
wire [3:0] sub_wire1; |
wire [3:0] sub_wire2; |
wire [55:0] q = sub_wire0[55:0]; |
wire [3:0] wrusedw = sub_wire1[3:0]; |
wire [3:0] rdusedw = sub_wire2[3:0]; |
|
dcfifo dcfifo_component ( |
.rdclk (rdclk), |
.wrclk (wrclk), |
.wrreq (wrreq), |
.aclr (aclr), |
.data (data), |
.rdreq (rdreq), |
.q (sub_wire0), |
.wrusedw (sub_wire1), |
.rdusedw (sub_wire2), |
.rdempty (), |
.rdfull (), |
.wrempty (), |
.wrfull ()); |
defparam |
dcfifo_component.intended_device_family = "Cyclone III", |
dcfifo_component.lpm_numwords = 16, |
dcfifo_component.lpm_showahead = "OFF", |
dcfifo_component.lpm_type = "dcfifo", |
dcfifo_component.lpm_width = 56, |
dcfifo_component.lpm_widthu = 4, |
dcfifo_component.overflow_checking = "ON", |
dcfifo_component.rdsync_delaypipe = 4, |
dcfifo_component.underflow_checking = "ON", |
dcfifo_component.use_eab = "ON", |
dcfifo_component.write_aclr_synch = "OFF", |
dcfifo_component.wrsync_delaypipe = 4; |
|
|
endmodule |
|
// ============================================================ |
// CNX file retrieval info |
// ============================================================ |
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" |
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" |
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" |
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" |
// Retrieval info: PRIVATE: Clock NUMERIC "4" |
// Retrieval info: PRIVATE: Depth NUMERIC "16" |
// Retrieval info: PRIVATE: Empty NUMERIC "1" |
// Retrieval info: PRIVATE: Full NUMERIC "1" |
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" |
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" |
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" |
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" |
// Retrieval info: PRIVATE: Optimize NUMERIC "2" |
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" |
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" |
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" |
// Retrieval info: PRIVATE: UsedW NUMERIC "1" |
// Retrieval info: PRIVATE: Width NUMERIC "56" |
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" |
// Retrieval info: PRIVATE: diff_widths NUMERIC "0" |
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" |
// Retrieval info: PRIVATE: output_width NUMERIC "56" |
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: rsFull NUMERIC "0" |
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" |
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" |
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" |
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: wsFull NUMERIC "0" |
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" |
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" |
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" |
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" |
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "56" |
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" |
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" |
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" |
// Retrieval info: CONSTANT: USE_EAB STRING "ON" |
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" |
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" |
// Retrieval info: USED_PORT: data 0 0 56 0 INPUT NODEFVAL "data[55..0]" |
// Retrieval info: USED_PORT: q 0 0 56 0 OUTPUT NODEFVAL "q[55..0]" |
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" |
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" |
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL "rdusedw[3..0]" |
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" |
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" |
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]" |
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 |
// Retrieval info: CONNECT: @data 0 0 56 0 data 0 0 56 0 |
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 |
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 |
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 |
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 |
// Retrieval info: CONNECT: q 0 0 56 0 @q 0 0 56 0 |
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0 |
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.v TRUE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.inc FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.cmp FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.bsf FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue_bb.v FALSE |
// Retrieval info: LIB_FILE: altera_mf |
// megafunction wizard: %FIFO% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
// MODULE: dcfifo |
|
// ============================================================ |
// File Name: ptp_queue.v |
// Megafunction Name(s): |
// dcfifo |
// |
// Simulation Library Files(s): |
// altera_mf |
// ============================================================ |
// ************************************************************ |
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
// |
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version |
// ************************************************************ |
|
|
//Copyright (C) 1991-2011 Altera Corporation |
//Your use of Altera Corporation's design tools, logic functions |
//and other software and tools, and its AMPP partner logic |
//functions, and any output files from any of the foregoing |
//(including device programming or simulation files), and any |
//associated documentation or information are expressly subject |
//to the terms and conditions of the Altera Program License |
//Subscription Agreement, Altera MegaCore Function License |
//Agreement, or other applicable license agreement, including, |
//without limitation, that your use is for the sole purpose of |
//programming logic devices manufactured by Altera and sold by |
//Altera or its authorized distributors. Please refer to the |
//applicable agreement for further details. |
|
|
// synopsys translate_off |
`timescale 1 ps / 1 ps |
// synopsys translate_on |
module ptp_queue ( |
aclr, |
data, |
rdclk, |
rdreq, |
wrclk, |
wrreq, |
q, |
rdusedw, |
wrusedw); |
|
input aclr; |
input [63:0] data; |
input rdclk; |
input rdreq; |
input wrclk; |
input wrreq; |
output [63:0] q; |
output [3:0] rdusedw; |
output [3:0] wrusedw; |
`ifndef ALTERA_RESERVED_QIS |
// synopsys translate_off |
`endif |
tri0 aclr; |
`ifndef ALTERA_RESERVED_QIS |
// synopsys translate_on |
`endif |
|
wire [63:0] sub_wire0; |
wire [3:0] sub_wire1; |
wire [3:0] sub_wire2; |
wire [63:0] q = sub_wire0[63:0]; |
wire [3:0] wrusedw = sub_wire1[3:0]; |
wire [3:0] rdusedw = sub_wire2[3:0]; |
|
dcfifo dcfifo_component ( |
.rdclk (rdclk), |
.wrclk (wrclk), |
.wrreq (wrreq), |
.aclr (aclr), |
.data (data), |
.rdreq (rdreq), |
.q (sub_wire0), |
.wrusedw (sub_wire1), |
.rdusedw (sub_wire2), |
.rdempty (), |
.rdfull (), |
.wrempty (), |
.wrfull ()); |
defparam |
dcfifo_component.intended_device_family = "Cyclone III", |
dcfifo_component.lpm_numwords = 16, |
dcfifo_component.lpm_showahead = "OFF", |
dcfifo_component.lpm_type = "dcfifo", |
dcfifo_component.lpm_width = 64, |
dcfifo_component.lpm_widthu = 4, |
dcfifo_component.overflow_checking = "ON", |
dcfifo_component.rdsync_delaypipe = 4, |
dcfifo_component.underflow_checking = "ON", |
dcfifo_component.use_eab = "ON", |
dcfifo_component.write_aclr_synch = "OFF", |
dcfifo_component.wrsync_delaypipe = 4; |
|
|
endmodule |
|
// ============================================================ |
// CNX file retrieval info |
// ============================================================ |
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" |
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" |
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" |
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" |
// Retrieval info: PRIVATE: Clock NUMERIC "4" |
// Retrieval info: PRIVATE: Depth NUMERIC "16" |
// Retrieval info: PRIVATE: Empty NUMERIC "1" |
// Retrieval info: PRIVATE: Full NUMERIC "1" |
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" |
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" |
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" |
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" |
// Retrieval info: PRIVATE: Optimize NUMERIC "2" |
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" |
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" |
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" |
// Retrieval info: PRIVATE: UsedW NUMERIC "1" |
// Retrieval info: PRIVATE: Width NUMERIC "64" |
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" |
// Retrieval info: PRIVATE: diff_widths NUMERIC "0" |
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" |
// Retrieval info: PRIVATE: output_width NUMERIC "64" |
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: rsFull NUMERIC "0" |
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" |
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" |
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" |
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: wsFull NUMERIC "0" |
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" |
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" |
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" |
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" |
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64" |
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" |
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" |
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" |
// Retrieval info: CONSTANT: USE_EAB STRING "ON" |
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" |
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" |
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]" |
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]" |
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" |
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" |
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL "rdusedw[3..0]" |
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" |
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" |
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]" |
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 |
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0 |
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 |
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 |
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 |
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 |
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0 |
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0 |
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.v TRUE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.inc FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.cmp FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.bsf FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue_bb.v FALSE |
// Retrieval info: LIB_FILE: altera_mf |
/reg/reg.v
26,13 → 26,13
output rx_q_rd_clk_out, |
output rx_q_rd_en_out, |
input [ 7:0] rx_q_stat_in, |
input [55:0] rx_q_data_in, |
input [63:0] rx_q_data_in, |
// tx tsu interface |
output tx_q_rst_out, |
output tx_q_rd_clk_out, |
output tx_q_rd_en_out, |
input [ 7:0] tx_q_stat_in, |
input [55:0] tx_q_data_in |
input [63:0] tx_q_data_in |
); |
|
parameter const_00 = 8'h00; |
141,9 → 141,9
// read registers |
reg [37:0] time_reg_ns_int; |
reg [47:0] time_reg_sec_int; |
reg [55:0] rx_q_data_int; |
reg [63:0] rx_q_data_int; |
reg [ 7:0] rx_q_stat_int; |
reg [55:0] tx_q_data_int; |
reg [63:0] tx_q_data_int; |
reg [ 7:0] tx_q_stat_int; |
reg time_ok; |
|
169,10 → 169,10
if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0]; |
if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]}; |
if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]}; |
if (rd_in && cs_50) data_out_reg <= { 8'd0, rx_q_data_int[55:32]}; |
if (rd_in && cs_54) data_out_reg <= rx_q_data_int[31: 0]; |
if (rd_in && cs_58) data_out_reg <= { 8'd0, tx_q_data_int[55:32]}; |
if (rd_in && cs_5c) data_out_reg <= tx_q_data_int[31: 0]; |
if (rd_in && cs_50) data_out_reg <= rx_q_data_int[63:32]; |
if (rd_in && cs_54) data_out_reg <= rx_q_data_int[31: 0]; |
if (rd_in && cs_58) data_out_reg <= tx_q_data_int[63:32]; |
if (rd_in && cs_5c) data_out_reg <= tx_q_data_int[31: 0]; |
end |
assign data_out = data_out_reg; |
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