URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588/trunk/rtl
- from Rev 44 to Rev 45
- ↔ Reverse comparison
Rev 44 → Rev 45
/rtc/rtc.v
104,8 → 104,8
// time accumulator pre adder (48bit_s + 30bit_ns + 8bit_ns_fraction) |
always @(posedge rst or posedge clk) begin |
if (rst) begin |
time_acc_30n_08f_pre_pos <= {22'd0, time_adj_08n_08f}; |
time_acc_30n_08f_pre_neg <= {22'd0, time_adj_08n_08f}; |
time_acc_30n_08f_pre_pos <= 38'd0; |
time_acc_30n_08f_pre_neg <= 38'd0; |
end |
else begin |
if (time_ld) begin // direct write |
/reg/reg.v
207,36 → 207,36
reg [31:0] data_out_reg; |
always @(posedge clk) begin |
// register mapping: RTC |
if (rd_in && cs_00) data_out_reg <= {reg_00[31: 2], adj_ld_done_in, time_ok}; |
if (rd_in && cs_04) data_out_reg <= reg_04; |
if (rd_in && cs_08) data_out_reg <= reg_08; |
if (rd_in && cs_0c) data_out_reg <= reg_0c; |
if (rd_in && cs_00) data_out_reg <= {27'd0, reg_00[ 4: 2], adj_ld_done_in, time_ok}; |
if (rd_in && cs_04) data_out_reg <= 32'd0; |
if (rd_in && cs_08) data_out_reg <= 32'd0; |
if (rd_in && cs_0c) data_out_reg <= 32'd0; |
if (rd_in && cs_10) data_out_reg <= {16'd0, time_reg_sec_int[47:32]}; |
if (rd_in && cs_14) data_out_reg <= time_reg_sec_int[31: 0] ; |
if (rd_in && cs_18) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]}; |
if (rd_in && cs_1c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]}; |
if (rd_in && cs_20) data_out_reg <= reg_20; |
if (rd_in && cs_20) data_out_reg <= {24'd0, reg_20[ 7: 0]}; |
if (rd_in && cs_24) data_out_reg <= reg_24; |
if (rd_in && cs_28) data_out_reg <= reg_28; |
if (rd_in && cs_28) data_out_reg <= {24'd0, reg_28[ 7: 0]}; |
if (rd_in && cs_2c) data_out_reg <= reg_2c; |
if (rd_in && cs_30) data_out_reg <= reg_30; |
if (rd_in && cs_34) data_out_reg <= reg_34; |
if (rd_in && cs_38) data_out_reg <= reg_38; |
if (rd_in && cs_3c) data_out_reg <= reg_3c; |
if (rd_in && cs_34) data_out_reg <= 32'd0; |
if (rd_in && cs_38) data_out_reg <= 32'd0; |
if (rd_in && cs_3c) data_out_reg <= 32'd0; |
// register mapping: TSU RX |
if (rd_in && cs_40) data_out_reg <= {reg_40[31: 2], reg_40[ 1], rxqu_ok}; |
if (rd_in && cs_44) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]}; |
if (rd_in && cs_48) data_out_reg <= reg_48; |
if (rd_in && cs_4c) data_out_reg <= reg_4c; |
if (rd_in && cs_40) data_out_reg <= {30'd0, reg_40[ 1], rxqu_ok}; |
if (rd_in && cs_44) data_out_reg <= {reg_44[31:24], 16'd0, rx_q_stat_int[ 7: 0]}; |
if (rd_in && cs_48) data_out_reg <= 32'd0; |
if (rd_in && cs_4c) data_out_reg <= 32'd0; |
if (rd_in && cs_50) data_out_reg <= rx_q_data_int[127: 96]; |
if (rd_in && cs_54) data_out_reg <= rx_q_data_int[ 95: 64]; |
if (rd_in && cs_58) data_out_reg <= rx_q_data_int[ 63: 32]; |
if (rd_in && cs_5c) data_out_reg <= rx_q_data_int[ 31: 0]; |
// register mapping: TSU TX |
if (rd_in && cs_60) data_out_reg <= {reg_60[31: 2], reg_60[ 1], txqu_ok}; |
if (rd_in && cs_64) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]}; |
if (rd_in && cs_68) data_out_reg <= reg_68; |
if (rd_in && cs_6c) data_out_reg <= reg_6c; |
if (rd_in && cs_60) data_out_reg <= {30'd0, reg_60[ 1], txqu_ok}; |
if (rd_in && cs_64) data_out_reg <= {reg_64[31:24], 16'd0, tx_q_stat_int[ 7: 0]}; |
if (rd_in && cs_68) data_out_reg <= 32'd0; |
if (rd_in && cs_6c) data_out_reg <= 32'd0; |
if (rd_in && cs_70) data_out_reg <= tx_q_data_int[127: 96]; |
if (rd_in && cs_74) data_out_reg <= tx_q_data_int[ 95: 64]; |
if (rd_in && cs_78) data_out_reg <= tx_q_data_int[ 63: 32]; |