URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588/trunk/rtl
- from Rev 69 to Rev 70
- ↔ Reverse comparison
Rev 69 → Rev 70
/bus/qsys/ha1588_avl.v
0,0 → 1,77
/* |
* ha1588_avl.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
* This library is free software; you can redistribute it and/or |
* modify it under the terms of the GNU Lesser General Public |
* License as published by the Free Software Foundation; either |
* version 2.1 of the License, or (at your option) any later version. |
* |
* This library is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
* Lesser General Public License for more details. |
* |
* You should have received a copy of the GNU Lesser General Public |
* License along with this library; if not, write to the Free Software |
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
* MA 02110-1301 USA |
*/ |
|
`timescale 1ns/1ns |
|
module ha1588_avl ( |
input rst,clk, |
input wr_in,rd_in, |
input [ 7:0] addr_in, |
input [31:0] data_in, |
output [31:0] data_out, |
|
input rtc_clk, |
output [31:0] rtc_time_ptp_ns, |
output [47:0] rtc_time_ptp_sec, |
output rtc_time_one_pps, |
|
input rx_gmii_clk, |
input rx_gmii_ctrl, |
input [7:0] rx_gmii_data, |
input rx_giga_mode, |
|
input tx_gmii_clk, |
input tx_gmii_ctrl, |
input [7:0] tx_gmii_data, |
input tx_giga_mode |
); |
|
parameter addr_is_in_word = 1; |
|
ha1588 |
#( |
.addr_is_in_word(addr_is_in_word) |
) |
ha1588_inst ( |
.rst(rst), |
.clk(clk), |
.wr_in(wr_in), |
.rd_in(rd_in), |
.addr_in(addr_in), |
.data_in(data_in), |
.data_out(data_out), |
|
.rtc_clk(rtc_clk), |
.rtc_time_ptp_ns(rtc_time_ptp_ns), |
.rtc_time_ptp_sec(rtc_time_ptp_sec), |
.rtc_time_one_pps(rtc_time_one_pps), |
|
.rx_gmii_clk(rx_gmii_clk), |
.rx_gmii_ctrl(rx_gmii_ctrl), |
.rx_gmii_data(rx_gmii_data), |
.rx_giga_mode(rx_giga_mode), |
.tx_gmii_clk(tx_gmii_clk), |
.tx_gmii_ctrl(tx_gmii_ctrl), |
.tx_gmii_data(tx_gmii_data), |
.tx_giga_mode(tx_giga_mode) |
); |
|
endmodule |
/bus/qsys/ha1588_hw.tcl
9,8 → 9,10
# | BABY&HW 2012.03.31.21:26:56 |
# | Hardware Assisted IEEE 1588 IP Core |
# | |
# | ha1588.v |
# | ha1588_avl.v |
# | |
# | ../../../par/altera/ip/define.h syn, sim |
# | ../../../par/altera/ip/dcfifo_128b_16.v syn, sim |
# | ../../../rtl/top/ha1588.v syn, sim |
# | ../../../rtl/reg/reg.v syn, sim |
# | ../../../rtl/rtc/rtc.v syn, sim |
28,17 → 30,17
# +----------------------------------- |
|
# +----------------------------------- |
# | module ha1588 |
# | module ha1588_avl |
# | |
set_module_property DESCRIPTION "Hardware Assisted IEEE 1588 IP Core" |
set_module_property NAME ha1588 |
set_module_property NAME ha1588_avl |
set_module_property VERSION 1.0 |
set_module_property INTERNAL false |
set_module_property OPAQUE_ADDRESS_MAP true |
set_module_property AUTHOR "BABY&HW" |
set_module_property DISPLAY_NAME "Hardware Assisted IEEE 1588 IP Core" |
set_module_property TOP_LEVEL_HDL_FILE ha1588.v |
set_module_property TOP_LEVEL_HDL_MODULE ha1588 |
set_module_property TOP_LEVEL_HDL_FILE ha1588_avl.v |
set_module_property TOP_LEVEL_HDL_MODULE ha1588_avl |
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true |
set_module_property EDITABLE true |
set_module_property ANALYZE_HDL TRUE |
48,8 → 50,9
# +----------------------------------- |
# | files |
# | |
add_file ha1588_avl.v {SYNTHESIS SIMULATION} |
add_file ../../../par/altera/ip/define.h {SYNTHESIS SIMULATION} |
add_file ../../../par/altera/ip/dcfifo_128_16.v {SYNTHESIS SIMULATION} |
add_file ../../../par/altera/ip/dcfifo_128b_16.v {SYNTHESIS SIMULATION} |
add_file ../../../rtl/top/ha1588.v {SYNTHESIS SIMULATION} |
add_file ../../../rtl/reg/reg.v {SYNTHESIS SIMULATION} |
add_file ../../../rtl/rtc/rtc.v {SYNTHESIS SIMULATION} |