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URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

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  • This comparison shows the changes necessary to convert path 
    /ha1588/trunk/sim/top
    from Rev 34 to Rev 37
    ↔ Reverse comparison
  •

Rev 34 → Rev 37

/ptp_drv_bfm/ptp_drv_bfm.c
1,7 → 1,7
/*
* $ptp_drv_bfm.c
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
54,23 → 54,28
#define RTC_SET_RESET 0x10
#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit
#define RTC_ACCMOD_L 0x0 // 256 for 8bit
#define RTC_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk
#define RTC_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk
#define RTC_PERIOD_L 0x0
 
// define TSU address values
#define TSU_CTRL 0x00000050
#define TSU_RXQUE_STATUS 0x00000054
#define TSU_TXQUE_STATUS 0x00000058
#define TSU_NULL_0x5C 0x0000005C
#define TSU_RXQUE_DATA_H 0x00000060
#define TSU_RXQUE_DATA_L 0x00000064
#define TSU_TXQUE_DATA_H 0x00000068
#define TSU_TXQUE_DATA_L 0x0000006C
#define TSU_CTRL 0x00000050
#define TSU_RXQUE_STATUS 0x00000054
#define TSU_TXQUE_STATUS 0x00000058
#define TSU_NULL_0x5C 0x0000005C
#define TSU_RXQUE_DATA_HH 0x00000060
#define TSU_RXQUE_DATA_HL 0x00000064
#define TSU_RXQUE_DATA_LH 0x00000068
#define TSU_RXQUE_DATA_LL 0x0000006C
#define TSU_TXQUE_DATA_HH 0x00000070
#define TSU_TXQUE_DATA_HL 0x00000074
#define TSU_TXQUE_DATA_LH 0x00000078
#define TSU_TXQUE_DATA_LL 0x0000007C
// define TSU data values
#define TSU_SET_CTRL_0 0x0
#define TSU_GET_TXQUE 0x1
#define TSU_GET_RXQUE 0x4
#define TSU_SET_RESET 0xA
#define TSU_SET_RXRST 0x8
#define TSU_SET_TXRST 0x2
 
int ptp_drv_bfm_c(double fw_delay)
{
82,114 → 87,140
cpu_addr_i = RTC_PERIOD_H_LOAD;
cpu_data_i = RTC_PERIOD_H;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_PERIOD_L_LOAD;
cpu_data_i = RTC_PERIOD_L;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_ACCMOD_H_LOAD;
cpu_data_i = RTC_ACCMOD_H;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_ACCMOD_L_LOAD;
cpu_data_i = RTC_ACCMOD_L;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_PERIOD;
cpu_wr(cpu_addr_i, cpu_data_i);
// RESET RTC AND TSU
 
// RESET RTC
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_RESET;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_RESET;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// READ RTC SEC AND NS
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
// LOAD RTC SEC AND NS
cpu_addr_i = RTC_TIME_SEC_H_LOAD;
cpu_data_i = 0x0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_TIME_SEC_L_LOAD;
cpu_data_i = 0x1;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_TIME_NSC_H_LOAD;
cpu_data_i = RTC_ACCMOD_H - 0xA;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_TIME_NSC_L_LOAD;
cpu_data_i = 0x0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// LOAD RTC ADJ
cpu_addr_i = RTC_ADJNUM_LOAD;
cpu_data_i = 0x100;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_ADJPER_H_LOAD;
cpu_data_i = 0x1;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_ADJPER_L_LOAD;
cpu_data_i = 0x20;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_ADJ;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// READ RTC SEC AND NS
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
197,68 → 228,171
int i;
int rx_queue_num;
int tx_queue_num;
 
// RESET TSU
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_RXRST + TSU_SET_TXRST;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// READ TSU
while (1) {
// POLL TSU RX STATUS
cpu_addr_i = TSU_RXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
rx_queue_num = cpu_data_o;
//printf("%08x\n", rx_queue_num);
if (rx_queue_num > 0x0) {
// READ TSU RX FIFO
for (i=rx_queue_num; i>0; i--) {
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_RXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
do {
 
// POLL TSU RX STATUS
cpu_addr_i = TSU_RXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
rx_queue_num = cpu_data_o;
//printf("%08x\n", rx_queue_num);
 
if (rx_queue_num > 0x0) {
for (i=rx_queue_num; i>0; i--) {
 
// READ TSU RX FIFO
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_RXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = TSU_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
 
cpu_addr_i = TSU_RXQUE_DATA_HH;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
cpu_addr_i = TSU_RXQUE_DATA_H;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\nRx stamp: \n%08x\n", cpu_data_o);
cpu_addr_i = TSU_RXQUE_DATA_L;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
printf("\nRx stamp: \n%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_RXQUE_DATA_HL;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_RXQUE_DATA_LH;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_RXQUE_DATA_LL;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
// READ RTC SEC AND NS
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
}
}
}
// POLL TSU TX STATUS
cpu_addr_i = TSU_TXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
tx_queue_num = cpu_data_o;
//printf("%08x\n", tx_queue_num);
if (tx_queue_num > 0x0) {
// READ TSU TX FIFO
for (i=tx_queue_num; i>0; i--) {
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_TXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
do {
 
// POLL TSU TX STATUS
cpu_addr_i = TSU_TXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
tx_queue_num = cpu_data_o;
//printf("%08x\n", tx_queue_num);
 
if (tx_queue_num > 0x0) {
for (i=tx_queue_num; i>0; i--) {
 
// READ TSU TX FIFO
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_TXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = TSU_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
 
cpu_addr_i = TSU_TXQUE_DATA_HH;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
cpu_addr_i = TSU_TXQUE_DATA_H;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\nTx stamp: \n%08x\n", cpu_data_o);
cpu_addr_i = TSU_TXQUE_DATA_L;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
printf("\nTx stamp: \n%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_TXQUE_DATA_HL;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_TXQUE_DATA_LH;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_TXQUE_DATA_LL;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
// READ RTC SEC AND NS
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
}
}
}
}
 
// READ BACK ALL REGISTERS
for (;;)
{
int t;
for (t=0; t<=0x5c; t=t+4)
for (t=0; t<=0xff; t=t+4)
{
cpu_hd(10);
 
/ptp_drv_bfm/ptp_drv_bfm.v
1,7 → 1,7
/*
* $ptp_drv_bfm.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/wave.do
76,4 → 76,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {18099011 ps} {18680581 ps}
WaveRestoreZoom {0 ps} {52500 ns}
/ha1588_tb.v
1,7 → 1,7
/*
* $ha1588_tb.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/nic_drv_bfm/gmii_rx_bfm.v
1,7 → 1,7
/*
* $gmii_rx_bfm.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
35,7 → 35,7
end
assign #2 gmii_rxclk = gmii_rxclk_offset;
 
integer feeder_file_rx, r_rx;
integer feeder_file_rx, r_rx, s_rx;
integer start_addr_rx, end_addr_rx;
integer index_rx, num_rx;
reg eof_rx;
59,9 → 59,9
// test pcap file endian
r_rx = $fread(pcap_4bytes_rx, feeder_file_rx);
pcap_endian_rx = (pcap_4bytes_rx == 32'ha1b2c3d4)? 1:0;
$fseek(feeder_file_rx, -4, 1);
s_rx = $fseek(feeder_file_rx, -4, 1);
// skip pcap file header 24*8
$fseek(feeder_file_rx, 24, 1);
s_rx = $fseek(feeder_file_rx, 24, 1);
// read packet content
eof_rx = 0;
num_rx = 0;
69,7 → 69,7
begin : fileread_loop
// skip frame header (8+4)*8
start_addr_rx = $ftell(feeder_file_rx);
$fseek(feeder_file_rx, 8+4, 1);
s_rx = $fseek(feeder_file_rx, 8+4, 1);
// get frame length big endian 4*8
r_rx = $fread(packet_leng_rx, feeder_file_rx);
packet_leng_rx = pcap_endian_rx?
/nic_drv_bfm/gmii_tx_bfm.v
1,7 → 1,7
/*
* $gmii_tx_bfm.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
35,7 → 35,7
end
assign #2 gmii_txclk = gmii_txclk_offset;
 
integer feeder_file_tx, r_tx;
integer feeder_file_tx, r_tx, s_tx;
integer start_addr_tx, end_addr_tx;
integer index_tx, num_tx;
reg eof_tx;
59,9 → 59,9
// test pcap file endian
r_tx = $fread(pcap_4bytes_tx, feeder_file_tx);
pcap_endian_tx = (pcap_4bytes_tx == 32'ha1b2c3d4)? 1:0;
$fseek(feeder_file_tx, -4, 1);
s_tx = $fseek(feeder_file_tx, -4, 1);
// skip pcap file header 24*8
$fseek(feeder_file_tx, 24, 1);
s_tx = $fseek(feeder_file_tx, 24, 1);
// read packet content
eof_tx = 0;
num_tx = 0;
69,7 → 69,7
begin : fileread_loop
// skip frame header (8+4)*8
start_addr_tx = $ftell(feeder_file_tx);
$fseek(feeder_file_tx, 8+4, 1);
s_tx = $fseek(feeder_file_tx, 8+4, 1);
// get frame length big endian 4*8
r_tx = $fread(packet_leng_tx, feeder_file_tx);
packet_leng_tx = pcap_endian_tx?

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