URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588/trunk/sim
- from Rev 37 to Rev 38
- ↔ Reverse comparison
Rev 37 → Rev 38
/top/ptp_drv_bfm/ptp_drv_bfm.c
1,5 → 1,5
/* |
* $ptp_drv_bfm.c |
* ptp_drv_bfm.c |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
25,42 → 25,44
#include "../dpiheader.h" |
|
// define RTC address values |
#define RTC_CTRL 0x00000000 |
#define RTC_NULL_0x4 0x00000004 |
#define RTC_NULL_0x8 0x00000008 |
#define RTC_NULL_0xC 0x0000000C |
#define RTC_TIME_SEC_H_LOAD 0x00000010 |
#define RTC_TIME_SEC_L_LOAD 0x00000014 |
#define RTC_TIME_NSC_H_LOAD 0x00000018 |
#define RTC_TIME_NSC_L_LOAD 0x0000001C |
#define RTC_PERIOD_H_LOAD 0x00000020 |
#define RTC_PERIOD_L_LOAD 0x00000024 |
#define RTC_ACCMOD_H_LOAD 0x00000028 |
#define RTC_ACCMOD_L_LOAD 0x0000002C |
#define RTC_ADJNUM_LOAD 0x00000030 |
#define RTC_NULL_0x34 0x00000034 |
#define RTC_ADJPER_H_LOAD 0x00000038 |
#define RTC_ADJPER_L_LOAD 0x0000003C |
#define RTC_TIME_SEC_H_READ 0x00000040 |
#define RTC_TIME_SEC_L_READ 0x00000044 |
#define RTC_TIME_NSC_H_READ 0x00000048 |
#define RTC_TIME_NSC_L_READ 0x0000004C |
#define RTC_CTRL 0x00000000 |
#define RTC_NULL_0x4 0x00000004 |
#define RTC_NULL_0x8 0x00000008 |
#define RTC_NULL_0xC 0x0000000C |
#define RTC_TIME_SEC_H 0x00000010 |
#define RTC_TIME_SEC_L 0x00000014 |
#define RTC_TIME_NSC_H 0x00000018 |
#define RTC_TIME_NSC_L 0x0000001C |
#define RTC_PERIOD_H 0x00000020 |
#define RTC_PERIOD_L 0x00000024 |
#define RTC_ADJPER_H 0x00000028 |
#define RTC_ADJPER_L 0x0000002C |
#define RTC_ADJNUM 0x00000030 |
#define RTC_NULL_0x34 0x00000034 |
#define RTC_NULL_0x38 0x00000038 |
#define RTC_NULL_0x3C 0x0000003C |
// define RTC control values |
#define RTC_SET_CTRL_0 0x00 |
#define RTC_GET_TIME 0x01 |
#define RTC_SET_ADJ 0x02 |
#define RTC_SET_PERIOD 0x04 |
#define RTC_SET_TIME 0x08 |
#define RTC_SET_RESET 0x10 |
// define RTC data values |
#define RTC_SET_CTRL_0 0x0 |
#define RTC_GET_TIME 0x1 |
#define RTC_SET_ADJ 0x2 |
#define RTC_SET_PERIOD 0x4 |
#define RTC_SET_TIME 0x8 |
#define RTC_SET_RESET 0x10 |
#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit |
#define RTC_ACCMOD_L 0x0 // 256 for 8bit |
#define RTC_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk |
#define RTC_PERIOD_L 0x0 |
#define RTC_SET_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk |
#define RTC_SET_PERIOD_L 0x0 |
// define RTC constant |
#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit |
#define RTC_ACCMOD_L 0x0 // 256 for 8bit |
|
// define TSU address values |
#define TSU_CTRL 0x00000050 |
#define TSU_RXQUE_STATUS 0x00000054 |
#define TSU_TXQUE_STATUS 0x00000058 |
#define TSU_CTRL 0x00000040 |
#define TSU_RXQUE_STATUS 0x00000044 |
#define TSU_TXQUE_STATUS 0x00000048 |
#define TSU_NULL_0x4C 0x0000004C |
#define TSU_NULL_0x50 0x00000050 |
#define TSU_NULL_0x54 0x00000054 |
#define TSU_NULL_0x58 0x00000058 |
#define TSU_NULL_0x5C 0x0000005C |
#define TSU_RXQUE_DATA_HH 0x00000060 |
#define TSU_RXQUE_DATA_HL 0x00000064 |
70,12 → 72,12
#define TSU_TXQUE_DATA_HL 0x00000074 |
#define TSU_TXQUE_DATA_LH 0x00000078 |
#define TSU_TXQUE_DATA_LL 0x0000007C |
// define TSU data values |
#define TSU_SET_CTRL_0 0x0 |
#define TSU_GET_TXQUE 0x1 |
#define TSU_GET_RXQUE 0x4 |
#define TSU_SET_RXRST 0x8 |
#define TSU_SET_TXRST 0x2 |
// define TSU control values |
#define TSU_SET_CTRL_0 0x00 |
#define TSU_GET_TXQUE 0x01 |
#define TSU_SET_TXRST 0x02 |
#define TSU_GET_RXQUE 0x04 |
#define TSU_SET_RXRST 0x08 |
|
int ptp_drv_bfm_c(double fw_delay) |
{ |
83,23 → 85,15
unsigned int cpu_data_i; |
unsigned int cpu_data_o; |
|
// LOAD RTC PERIOD AND ACC_MODULO |
cpu_addr_i = RTC_PERIOD_H_LOAD; |
cpu_data_i = RTC_PERIOD_H; |
// LOAD RTC PERIOD |
cpu_addr_i = RTC_PERIOD_H; |
cpu_data_i = RTC_SET_PERIOD_H; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = RTC_PERIOD_L_LOAD; |
cpu_data_i = RTC_PERIOD_L; |
cpu_addr_i = RTC_PERIOD_L; |
cpu_data_i = RTC_SET_PERIOD_L; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = RTC_ACCMOD_H_LOAD; |
cpu_data_i = RTC_ACCMOD_H; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = RTC_ACCMOD_L_LOAD; |
cpu_data_i = RTC_ACCMOD_L; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = RTC_CTRL; |
cpu_data_i = RTC_SET_CTRL_0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
129,39 → 123,39
do { |
cpu_addr_i = RTC_CTRL; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
//printf("%08x\n", (cpu_data_o & 0x1)); |
//printf("%08x\n", cpu_data_o); |
} while ((cpu_data_o & RTC_GET_TIME) == 0x0); |
|
cpu_addr_i = RTC_TIME_SEC_H_READ; |
cpu_addr_i = RTC_TIME_SEC_H; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("\ntime: \n%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_SEC_L_READ; |
cpu_addr_i = RTC_TIME_SEC_L; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_NSC_H_READ; |
cpu_addr_i = RTC_TIME_NSC_H; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_NSC_L_READ; |
cpu_addr_i = RTC_TIME_NSC_L; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
// LOAD RTC SEC AND NS |
cpu_addr_i = RTC_TIME_SEC_H_LOAD; |
cpu_addr_i = RTC_TIME_SEC_H; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = RTC_TIME_SEC_L_LOAD; |
cpu_addr_i = RTC_TIME_SEC_L; |
cpu_data_i = 0x1; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = RTC_TIME_NSC_H_LOAD; |
cpu_addr_i = RTC_TIME_NSC_H; |
cpu_data_i = RTC_ACCMOD_H - 0xA; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = RTC_TIME_NSC_L_LOAD; |
cpu_addr_i = RTC_TIME_NSC_L; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
174,15 → 168,15
cpu_wr(cpu_addr_i, cpu_data_i); |
|
// LOAD RTC ADJ |
cpu_addr_i = RTC_ADJNUM_LOAD; |
cpu_addr_i = RTC_ADJNUM; |
cpu_data_i = 0x100; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = RTC_ADJPER_H_LOAD; |
cpu_addr_i = RTC_ADJPER_H; |
cpu_data_i = 0x1; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = RTC_ADJPER_L_LOAD; |
cpu_addr_i = RTC_ADJPER_L; |
cpu_data_i = 0x20; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
194,6 → 188,12
cpu_data_i = RTC_SET_ADJ; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
do { |
cpu_addr_i = RTC_CTRL; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
//printf("%08x\n", cpu_data_o); |
} while ((cpu_data_o & RTC_SET_ADJ) == 0x0); |
|
// READ RTC SEC AND NS |
cpu_addr_i = RTC_CTRL; |
cpu_data_i = RTC_SET_CTRL_0; |
206,22 → 206,22
do { |
cpu_addr_i = RTC_CTRL; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
//printf("%08x\n", (cpu_data_o & 0x1)); |
//printf("%08x\n", cpu_data_o); |
} while ((cpu_data_o & RTC_GET_TIME) == 0x0); |
|
cpu_addr_i = RTC_TIME_SEC_H_READ; |
cpu_addr_i = RTC_TIME_SEC_H; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("\ntime: \n%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_SEC_L_READ; |
cpu_addr_i = RTC_TIME_SEC_L; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_NSC_H_READ; |
cpu_addr_i = RTC_TIME_NSC_H; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_NSC_L_READ; |
cpu_addr_i = RTC_TIME_NSC_L; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
262,7 → 262,7
do { |
cpu_addr_i = TSU_CTRL; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
//printf("%08x\n", (cpu_data_o & 0x1)); |
//printf("%08x\n", cpu_data_o); |
} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0); |
|
cpu_addr_i = TSU_RXQUE_DATA_HH; |
293,22 → 293,22
do { |
cpu_addr_i = RTC_CTRL; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
//printf("%08x\n", (cpu_data_o & 0x1)); |
//printf("%08x\n", cpu_data_o); |
} while ((cpu_data_o & RTC_GET_TIME) == 0x0); |
|
cpu_addr_i = RTC_TIME_SEC_H_READ; |
cpu_addr_i = RTC_TIME_SEC_H; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("\ntime: \n%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_SEC_L_READ; |
cpu_addr_i = RTC_TIME_SEC_L; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_NSC_H_READ; |
cpu_addr_i = RTC_TIME_NSC_H; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_NSC_L_READ; |
cpu_addr_i = RTC_TIME_NSC_L; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
} |
335,7 → 335,7
do { |
cpu_addr_i = TSU_CTRL; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
//printf("%08x\n", (cpu_data_o & 0x1)); |
//printf("%08x\n", cpu_data_o); |
} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0); |
|
cpu_addr_i = TSU_TXQUE_DATA_HH; |
366,22 → 366,22
do { |
cpu_addr_i = RTC_CTRL; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
//printf("%08x\n", (cpu_data_o & 0x1)); |
//printf("%08x\n", cpu_data_o); |
} while ((cpu_data_o & RTC_GET_TIME) == 0x0); |
|
cpu_addr_i = RTC_TIME_SEC_H_READ; |
cpu_addr_i = RTC_TIME_SEC_H; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("\ntime: \n%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_SEC_L_READ; |
cpu_addr_i = RTC_TIME_SEC_L; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_NSC_H_READ; |
cpu_addr_i = RTC_TIME_NSC_H; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
|
cpu_addr_i = RTC_TIME_NSC_L_READ; |
cpu_addr_i = RTC_TIME_NSC_L; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
printf("%08x\n", cpu_data_o); |
} |
/top/ptp_drv_bfm/ptp_drv_bfm.v
1,5 → 1,5
/* |
* $ptp_drv_bfm.v |
* ptp_drv_bfm.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
/top/ha1588_tb.v
1,5 → 1,5
/* |
* $ha1588_tb.v |
* ha1588_tb.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
/top/nic_drv_bfm/gmii_rx_bfm.v
1,5 → 1,5
/* |
* $gmii_rx_bfm.v |
* gmii_rx_bfm.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
/top/nic_drv_bfm/gmii_tx_bfm.v
1,5 → 1,5
/* |
* $gmii_tx_bfm.v |
* gmii_tx_bfm.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
/rtc/rtc_timer_tb.v
1,5 → 1,5
/* |
* $rtc_timer_tb.v |
* rtc_timer_tb.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
25,11 → 25,11
|
reg rst; |
reg clk; |
wire adj_ld_done; |
wire [37:0] time_reg_ns; |
wire [47:0] time_reg_sec; |
reg period_ld; |
reg [39:0] period_in; |
reg [37:0] time_acc_modulo; |
reg adj_ld; |
reg [31:0] adj_ld_data; |
reg [39:0] period_adj; |
45,12 → 45,14
.time_reg_sec_in (time_reg_sec_in ) , |
.time_reg_ns (time_reg_ns ) , |
.time_reg_sec (time_reg_sec ) , |
.time_ptp_ns ( ) , |
.time_ptp_sec ( ) , |
.period_ld (period_ld ) , |
.period_in (period_in ) , |
.time_acc_modulo (time_acc_modulo ) , |
.adj_ld (adj_ld ) , |
.period_adj (period_adj ) , |
.adj_ld_data (adj_ld_data ) ); |
.adj_ld_data (adj_ld_data ) , |
.adj_ld_done ( ) ); |
|
|
initial begin |
81,7 → 83,6
period_ld = 1'b0; |
period_in[39:32] = 8'h00; // ns |
period_in[31: 0] = 32'h00000000; // ns fraction |
time_acc_modulo = 38'd256_000000000; |
// time load |
time_ld = 1'b0; |
time_reg_ns_in[37:8] = 30'd0; // ns |
142,7 → 143,6
end |
|
// sec+ns watchpoint |
wire [29:0] time_acc_modulo_ns_ = time_acc_modulo[37:8]; |
wire [47:0] time_reg_sec_in_ = time_reg_sec_in[47:0]; |
wire [29:0] time_reg_ns_in_ = time_reg_ns_in[37:8]; |
wire [47:0] time_reg_sec_ = time_reg_sec[47:0]; |
151,7 → 151,6
wire [ 7:0] period_adj_ns_ = period_adj[39:32]; |
wire time_reg_sec_inc_ = DUT.time_acc_48s_inc; |
// ns fraction watchpoint |
wire [ 7:0] time_acc_modulo_ns_f = time_acc_modulo[7:0]; |
wire [ 7:0] time_reg_ns_in_f = time_reg_ns_in[7:0]; |
wire [ 7:0] time_reg_ns_f = time_reg_ns[7:0]; |
wire [31:0] period_ns_f = period_in[31:0]; |
165,7 → 164,7
time_reg_ns__d1 <= time_reg_ns_; |
end |
wire [29:0] time_reg_ns__delta = (time_reg_sec__d1!=time_reg_sec_)? |
(time_acc_modulo_ns_-(time_reg_ns__d1-time_reg_ns_)): |
(DUT.time_acc_modulo/256-(time_reg_ns__d1-time_reg_ns_)): |
(time_reg_ns_-time_reg_ns__d1); |
|
// Delta-Sigma circuit watchpoint |
/rtc/wave.do
11,7 → 11,6
add wave -noupdate -format Logic /rtc_timer_tb/period_ld |
add wave -noupdate -format Literal /rtc_timer_tb/period_in |
add wave -noupdate -divider {1s modulo} |
add wave -noupdate -format Literal /rtc_timer_tb/time_acc_modulo |
add wave -noupdate -divider {time adjustment} |
add wave -noupdate -format Logic /rtc_timer_tb/adj_ld |
add wave -noupdate -format Literal /rtc_timer_tb/adj_ld_data |
23,6 → 22,7
add wave -noupdate -divider {INTERNAL Signals} |
add wave -noupdate -divider {precise time control} |
add wave -noupdate -format Literal -radix hexadecimal /rtc_timer_tb/DUT/adj_cnt |
add wave -noupdate -format Logic /rtc_timer_tb/DUT/adj_ld_done |
add wave -noupdate -format Literal -radix hexadecimal /rtc_timer_tb/DUT/time_adj |
add wave -noupdate -divider Delta-Sigma |
add wave -noupdate -format Literal /rtc_timer_tb/DUT/time_adj_08n_32f |
30,7 → 30,6
add wave -noupdate -format Literal /rtc_timer_tb/DUT/time_adj_00n_24f |
add wave -noupdate -divider {WATCHPOINT Signals} |
add wave -noupdate -divider {ns and sec} |
add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_acc_modulo_ns_ |
add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_reg_ns__delta |
add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_reg_sec_in_ |
add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/time_reg_ns_in_ |
40,7 → 39,6
add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/period_ns_ |
add wave -noupdate -format Literal -radix unsigned /rtc_timer_tb/period_adj_ns_ |
add wave -noupdate -divider {ns fraction} |
add wave -noupdate -format Literal /rtc_timer_tb/time_acc_modulo_ns_f |
add wave -noupdate -format Literal /rtc_timer_tb/time_reg_ns_in_f |
add wave -noupdate -format Literal /rtc_timer_tb/time_reg_ns_f |
add wave -noupdate -format Literal /rtc_timer_tb/period_ns_f |
49,7 → 47,7
add wave -noupdate -divider {New Divider} |
add wave -noupdate -divider {New Divider} |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {533 ns} 0} |
WaveRestoreCursors {{Cursor 1} {476 ns} 0} |
configure wave -namecolwidth 222 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
64,4 → 62,4
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {476 ns} {632 ns} |
WaveRestoreZoom {0 ns} {2100 ns} |
/rtc/sim.do
1,5 → 1,5
vlib work |
vlog -work work ../../rtl/rtc/rtc.v |
vlog -work work ../../rtl/rtc/rtc.v +initreg+0 |
vlog -work work rtc_timer_tb.v |
vsim -novopt work.rtc_timer_tb |
|
/tsu/gmii_rx_bfm.v
1,5 → 1,5
/* |
* $gmii_rx_bfm.v |
* gmii_rx_bfm.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
/tsu/gmii_tx_bfm.v
1,5 → 1,5
/* |
* $gmii_tx_bfm.v |
* gmii_tx_bfm.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
/tsu/tsu_queue_tb.v
1,5 → 1,5
/* |
* $tsu_queue_tb.v |
* tsu_queue_tb.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |