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URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

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  • This comparison shows the changes necessary to convert path 
    /ha1588/trunk/sim
    from Rev 38 to Rev 39
    ↔ Reverse comparison
  •

Rev 38 → Rev 39

/top/ptp_drv_bfm/ptp_drv_bfm.c
26,9 → 26,9
 
// define RTC address values
#define RTC_CTRL 0x00000000
#define RTC_NULL_0x4 0x00000004
#define RTC_NULL_0x8 0x00000008
#define RTC_NULL_0xC 0x0000000C
#define RTC_NULL_0x04 0x00000004
#define RTC_NULL_0x08 0x00000008
#define RTC_NULL_0x0C 0x0000000C
#define RTC_TIME_SEC_H 0x00000010
#define RTC_TIME_SEC_L 0x00000014
#define RTC_TIME_NSC_H 0x00000018
42,32 → 42,32
#define RTC_NULL_0x38 0x00000038
#define RTC_NULL_0x3C 0x0000003C
// define RTC control values
#define RTC_SET_CTRL_0 0x00
#define RTC_GET_TIME 0x01
#define RTC_SET_ADJ 0x02
#define RTC_SET_PERIOD 0x04
#define RTC_SET_TIME 0x08
#define RTC_SET_RESET 0x10
#define RTC_SET_CTRL_0 0x00
#define RTC_GET_TIME 0x01
#define RTC_SET_ADJ 0x02
#define RTC_SET_PERIOD 0x04
#define RTC_SET_TIME 0x08
#define RTC_SET_RESET 0x10
// define RTC data values
#define RTC_SET_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk
#define RTC_SET_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk
#define RTC_SET_PERIOD_L 0x0
// define RTC constant
#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit
#define RTC_ACCMOD_L 0x0 // 256 for 8bit
#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit
#define RTC_ACCMOD_L 0x0 // 256 for 8bit
 
// define TSU address values
#define TSU_CTRL 0x00000040
#define TSU_RXCTRL 0x00000040
#define TSU_RXQUE_STATUS 0x00000044
#define TSU_TXQUE_STATUS 0x00000048
#define TSU_NULL_0x48 0x00000048
#define TSU_NULL_0x4C 0x0000004C
#define TSU_NULL_0x50 0x00000050
#define TSU_NULL_0x54 0x00000054
#define TSU_NULL_0x58 0x00000058
#define TSU_NULL_0x5C 0x0000005C
#define TSU_RXQUE_DATA_HH 0x00000060
#define TSU_RXQUE_DATA_HL 0x00000064
#define TSU_RXQUE_DATA_LH 0x00000068
#define TSU_RXQUE_DATA_LL 0x0000006C
#define TSU_RXQUE_DATA_HH 0x00000050
#define TSU_RXQUE_DATA_HL 0x00000054
#define TSU_RXQUE_DATA_LH 0x00000058
#define TSU_RXQUE_DATA_LL 0x0000005C
#define TSU_TXCTRL 0x00000060
#define TSU_TXQUE_STATUS 0x00000064
#define TSU_NULL_0x68 0x00000068
#define TSU_NULL_0x6C 0x0000006C
#define TSU_TXQUE_DATA_HH 0x00000070
#define TSU_TXQUE_DATA_HL 0x00000074
#define TSU_TXQUE_DATA_LH 0x00000078
74,10 → 74,10
#define TSU_TXQUE_DATA_LL 0x0000007C
// define TSU control values
#define TSU_SET_CTRL_0 0x00
#define TSU_GET_RXQUE 0x01
#define TSU_SET_RXRST 0x02
#define TSU_GET_TXQUE 0x01
#define TSU_SET_TXRST 0x02
#define TSU_GET_RXQUE 0x04
#define TSU_SET_RXRST 0x08
 
int ptp_drv_bfm_c(double fw_delay)
{
230,14 → 230,22
int tx_queue_num;
 
// RESET TSU
cpu_addr_i = TSU_CTRL;
cpu_addr_i = TSU_RXCTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_RXRST + TSU_SET_TXRST;
cpu_addr_i = TSU_RXCTRL;
cpu_data_i = TSU_SET_RXRST;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_TXCTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_TXCTRL;
cpu_data_i = TSU_SET_TXRST;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// READ TSU
while (1) {
 
251,16 → 259,16
for (i=rx_queue_num; i>0; i--) {
 
// READ TSU RX FIFO
cpu_addr_i = TSU_CTRL;
cpu_addr_i = TSU_RXCTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_CTRL;
cpu_addr_i = TSU_RXCTRL;
cpu_data_i = TSU_GET_RXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = TSU_CTRL;
cpu_addr_i = TSU_RXCTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", cpu_data_o);
} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
324,16 → 332,16
for (i=tx_queue_num; i>0; i--) {
 
// READ TSU TX FIFO
cpu_addr_i = TSU_CTRL;
cpu_addr_i = TSU_TXCTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_CTRL;
cpu_addr_i = TSU_TXCTRL;
cpu_data_i = TSU_GET_TXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = TSU_CTRL;
cpu_addr_i = TSU_TXCTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", cpu_data_o);
} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);

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