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Rev 3 → Rev 4

/rtl/tsu/ptp_parser.v
0,0 → 1,109
`timescale 1ns/1ns
 
module ptp_parser (
input clk, rst,
input [31:0] ptp_data,
input ptp_valid,
input ptp_sop,
input ptp_eop,
input [ 1:0] ptp_mod,
input [79:0] ptp_time,
 
output reg ptp_found,
output reg [91:0] ptp_infor
);
 
reg [31:0] ptp_data_d1;
reg ptp_valid_d1;
reg ptp_sop_d1;
reg ptp_eop_d1;
reg [ 1:0] ptp_mod_d1;
always @(posedge rst or posedge clk) begin
if (rst) begin
ptp_data_d1 <= 32'h00000000;
ptp_valid_d1 <= 1'b0;
ptp_sop_d1 <= 1'b0;
ptp_eop_d1 <= 1'b0;
ptp_mod_d1 <= 2'b00;
end
else begin
if (ptp_valid) begin
ptp_data_d1 <= ptp_data;
ptp_mod_d1 <= ptp_mod;
end
ptp_valid_d1 <= ptp_valid;
ptp_sop_d1 <= ptp_sop;
ptp_eop_d1 <= ptp_eop;
end
end
 
reg [9:0] ptp_cnt;
reg ptp_vlan, ptp_ip, ptp_udp, ptp_port, ptp_event;
reg [3:0] ptp_msgid;
reg [7:0] ptp_seqid;
always @(posedge rst or posedge clk) begin
if (rst)
ptp_cnt <= 10'd0;
else
if (ptp_valid && ptp_sop)
ptp_cnt <= 10'd0;
else if (ptp_valid)
ptp_cnt <= ptp_cnt + 10'd1 - ptp_vlan;
end
 
always @(posedge rst or posedge clk) begin
if (rst) begin
ptp_vlan <= 1'b0;
ptp_ip <= 1'b0;
ptp_udp <= 1'b0;
ptp_port <= 1'b0;
ptp_event <= 1'b0;
ptp_seqid <= 8'd0;
end
else if (ptp_valid_d1 && ptp_sop_d1) begin
ptp_vlan <= 1'b0;
ptp_ip <= 1'b0;
ptp_udp <= 1'b0;
ptp_port <= 1'b0;
ptp_event <= 1'b0;
ptp_seqid <= 8'd0;
end
else begin
if (ptp_valid_d1 && ptp_cnt==10'd4) // ether_type == vlan
ptp_vlan <= ( ptp_data_d1[31:16]==16'h8100);
if (ptp_valid_d1 && ptp_cnt==10'd4) // ether_type == ip
ptp_ip <= ( ptp_data_d1[31:16]==16'h0800);
if (ptp_valid_d1 && ptp_cnt==10'd6) // ip_type == udp
ptp_udp <= ( ptp_data_d1[ 7: 0]== 8'h11 && ptp_ip);
if (ptp_valid_d1 && ptp_cnt==10'd10) // udp_dest_port == ptp_event
ptp_port <= ( ptp_data_d1[31:16]==16'h013f && ptp_udp);
if (ptp_valid_d1 && ptp_cnt==10'd11) // ptp_message_id == sync || delay_req
ptp_event <= ((ptp_data_d1[11: 8]== 4'h0 || ptp_data_d1[11:8]==4'h2) && ptp_port);
 
if (ptp_valid_d1 && ptp_cnt==10'd11) // ptp_sequence_id
ptp_msgid <= ptp_data_d1[11: 8];
if (ptp_valid_d1 && ptp_cnt==10'd19) // ptp_sequence_id
ptp_seqid <= ptp_data_d1[31:16];
end
end
 
always @(posedge rst or posedge clk) begin
if (rst) begin
ptp_found <= 1'b0;
ptp_infor <= 91'd0;
end
else if (ptp_valid_d1 && ptp_sop_d1) begin
ptp_found <= 1'b0;
ptp_infor <= 91'd0;
end
else if (ptp_valid_d1 && ptp_eop_d1) begin
ptp_found <= ptp_event;
ptp_infor <= {ptp_msgid, ptp_seqid, ptp_time};
end
else begin
ptp_found <= 1'b0;
ptp_infor <= 91'd0;
end
end
 
endmodule
/rtl/tsu/tsu_queue.v
0,0 → 1,181
`timescale 1ns/1ns
 
module tsu_queue (
input rst,
 
input gmii_clk,
input gmii_ctrl,
input [7:0] gmii_data,
input rtc_timer_clk,
input [79:0] rtc_timer_in,
 
input q_rst,
input q_clk,
input q_rd_en,
output [ 7:0] q_rd_stat,
output [91:0] q_rd_data
);
 
// buffer gmii input
reg int_gmii_ctrl;
reg int_gmii_ctrl_d1, int_gmii_ctrl_d2, int_gmii_ctrl_d3, int_gmii_ctrl_d4, int_gmii_ctrl_d5;
reg [7:0] int_gmii_data;
reg [7:0] int_gmii_data_d1;
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
int_gmii_ctrl <= 1'b0;
int_gmii_ctrl_d1 <= 1'b0;
int_gmii_ctrl_d2 <= 1'b0;
int_gmii_ctrl_d3 <= 1'b0;
int_gmii_ctrl_d4 <= 1'b0;
int_gmii_ctrl_d5 <= 1'b0;
int_gmii_data <= 8'h00;
int_gmii_data_d1 <= 8'h00;
end
else begin
int_gmii_ctrl <= gmii_ctrl;
int_gmii_ctrl_d1 <= int_gmii_ctrl;
int_gmii_ctrl_d2 <= int_gmii_ctrl_d1;
int_gmii_ctrl_d3 <= int_gmii_ctrl_d2;
int_gmii_ctrl_d4 <= int_gmii_ctrl_d3;
int_gmii_ctrl_d5 <= int_gmii_ctrl_d4;
int_gmii_data <= gmii_data;
int_gmii_data_d1 <= int_gmii_data;
end
end
 
// ptp CDC time stamping
wire ts_req = int_gmii_ctrl;
reg ts_req_d1, ts_req_d2, ts_req_d3;
always @(posedge rst or posedge rtc_timer_clk) begin
if (rst) begin
ts_req_d1 <= 1'b0;
ts_req_d2 <= 1'b0;
ts_req_d3 <= 1'b0;
end
else begin
ts_req_d1 <= ts_req;
ts_req_d2 <= ts_req_d1;
ts_req_d3 <= ts_req_d2;
end
end
reg [79:0] rtc_time_stamp;
always @(posedge rst or posedge rtc_timer_clk) begin
if (rst)
rtc_time_stamp <= 80'd0;
else
if (ts_req_d2 & !ts_req_d3)
rtc_time_stamp <= rtc_timer_in;
end
reg ts_ack, ts_ack_clr;
always @(posedge ts_ack_clr or posedge rtc_timer_clk) begin
if (ts_ack_clr)
ts_ack <= 1'b0;
else
if (ts_req_d2 & !ts_req_d3)
ts_ack <= 1'b1;
end
 
reg ts_ack_d1, ts_ack_d2, ts_ack_d3;
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
ts_ack_d1 <= 1'b0;
ts_ack_d2 <= 1'b0;
ts_ack_d3 <= 1'b0;
end
else begin
ts_ack_d1 <= ts_ack;
ts_ack_d2 <= ts_ack_d1;
ts_ack_d3 <= ts_ack_d2;
end
end
reg [79:0] gmii_time_stamp;
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
gmii_time_stamp <= 80'd0;
ts_ack_clr <= 1'b0;
end
else begin
if (ts_ack_d2 & !ts_ack_d3) begin
gmii_time_stamp <= rtc_time_stamp;
ts_ack_clr <= 1'b1;
end
else begin
gmii_time_stamp <= gmii_time_stamp;
ts_ack_clr <= 1'b0;
end
end
end
 
// 8b-32b datapath gearbox
reg int_valid;
reg int_sop, int_eop;
reg [ 1:0] int_bcnt, int_mod;
reg [31:0] int_data;
always @(posedge rst or posedge gmii_clk) begin
if (rst)
int_bcnt <= 2'd0;
else
if (int_gmii_ctrl_d1 | (int_bcnt!=2'd0))
int_bcnt <= int_bcnt + 2'd1;
else
int_bcnt <= 2'd0;
end
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
int_data <= 32'd0;
int_valid <= 1'b0;
int_mod <= 2'd0;
end
else begin
if (int_gmii_ctrl_d1) begin
int_data[ 7: 0] <= (int_bcnt==2'd3)? int_gmii_data_d1:int_data[ 7: 0];
int_data[15: 8] <= (int_bcnt==2'd2)? int_gmii_data_d1:int_data[15: 8];
int_data[23:16] <= (int_bcnt==2'd1)? int_gmii_data_d1:int_data[23:16];
int_data[31:24] <= (int_bcnt==2'd0)? int_gmii_data_d1:int_data[31:24];
end
 
if (int_bcnt==2'd3)
int_valid <= 1'b1;
else
int_valid <= 1'b0;
 
if (int_gmii_ctrl_d1 & !int_gmii_ctrl_d2)
int_mod <= 2'd0;
else if (!int_gmii_ctrl_d1 & int_gmii_ctrl_d2)
int_mod <= int_bcnt;
 
if (int_gmii_ctrl & !int_gmii_ctrl_d5 & int_bcnt==2'd3)
int_sop <= 1'b1;
else
int_sop <= 1'b0;
 
if (!int_gmii_ctrl & int_bcnt==2'd3)
int_eop <= 1'b1;
else
int_eop <= 1'b0;
 
end
end
 
// ptp packet parser here
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
wire ptp_found;
wire [91:0] ptp_infor;
ptp_parser parser(
.clk(gmii_clk),
.rst(rst),
.ptp_data(int_data),
.ptp_valid(int_valid),
.ptp_sop(int_sop),
.ptp_eop(int_eop),
.ptp_mod(int_mod),
.ptp_time(gmii_time_stamp),
.ptp_found(ptp_found),
.ptp_infor(ptp_infor)
);
 
// ptp time stamp dcfifo
 
endmodule
/sim/tsu/wave.do
0,0 → 1,57
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/gmii_clk
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/gmii_ctrl
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/gmii_data
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_req
add wave -noupdate -format Literal -radix hexadecimal /tsu_queue_tb/DUT_RX/rtc_time_stamp
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_ack
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_ack_clr
add wave -noupdate -format Literal -radix hexadecimal /tsu_queue_tb/DUT_RX/gmii_time_stamp
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_gmii_ctrl
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_gmii_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_bcnt
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_valid
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_sop
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_eop
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_mod
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_cnt
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_valid_d1
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_sop_d1
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_eop_d1
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_mod_d1
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_data_d1
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_vlan
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_ip
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_udp
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_port
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_event
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_seqid
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_found
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_infor
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {23897 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 165
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {20850 ns} {26445 ns}
/sim/tsu/gmii_rx_bfm.v
0,0 → 1,109
`timescale 1ns/1ns
 
module gmii_rx_bfm
(
output gmii_rxclk,
output reg gmii_rxctrl,
output reg [7:0] gmii_rxdata
);
 
reg gmii_rxclk_offset;
initial begin
gmii_rxclk_offset = 1'b0;
forever #4 gmii_rxclk_offset = !gmii_rxclk_offset;
end
assign #2 gmii_rxclk = gmii_rxclk_offset;
 
integer feeder_file_rx, r_rx;
integer start_addr_rx, end_addr_rx;
integer index_rx;
reg eof_rx;
reg pcap_endian_rx;
reg [31:0] pcap_4bytes_rx;
reg [31:0] packet_leng_rx;
reg [ 7:0] packet_byte_rx;
initial
begin : feeder_rx
gmii_rxctrl = 1'b0;
gmii_rxdata = 4'd0;
#100;
feeder_file_rx = $fopen("ptpdv2_rx.pcap","rb");
if (feeder_file_rx == 0)
begin
$display("Failed to open ptpdv2_rx.pcap!");
disable feeder_rx;
end
else
begin
// test pcap file endian
r_rx = $fread(pcap_4bytes_rx, feeder_file_rx);
pcap_endian_rx = (pcap_4bytes_rx == 32'ha1b2c3d4)? 1:0;
$fseek(feeder_file_rx, -4, 1);
// skip pcap file header 24*8
$fseek(feeder_file_rx, 24, 1);
// read packet content
eof_rx = 0;
while (!eof_rx & !$feof(feeder_file_rx))
begin : fileread_loop
// skip frame header (8+4)*8
start_addr_rx = $ftell(feeder_file_rx);
$fseek(feeder_file_rx, 8+4, 1);
// get frame length big endian 4*8
r_rx = $fread(packet_leng_rx, feeder_file_rx);
packet_leng_rx = pcap_endian_rx?
{packet_leng_rx[31:24], packet_leng_rx[23:16], packet_leng_rx[15: 8], packet_leng_rx[ 7: 0]}:
{packet_leng_rx[ 7: 0], packet_leng_rx[15: 8], packet_leng_rx[23:16], packet_leng_rx[31:24]};
// check whether end of file
if (r_rx == 0)
begin
eof_rx = 1;
@(posedge gmii_rxclk_offset);
gmii_rxctrl = 1'b0;
gmii_rxdata = 8'h00;
disable fileread_loop;
end
// send ifg 96bit=12*8
repeat (12)
begin
@(posedge gmii_rxclk_offset)
gmii_rxctrl = 1'b0;
gmii_rxdata = 8'h00;
end
// send frame pre-amble 555555d5=4*8
repeat (3)
begin
@(posedge gmii_rxclk_offset);
gmii_rxctrl = 1'b1;
gmii_rxdata = 8'h55;
end
@(posedge gmii_rxclk_offset)
gmii_rxctrl = 1'b1;
gmii_rxdata = 8'hd5;
// send frame content
for (index_rx=0; index_rx<packet_leng_rx; index_rx=index_rx+1)
begin
r_rx = $fread(packet_byte_rx, feeder_file_rx);
@(posedge gmii_rxclk_offset);
gmii_rxctrl = 1'b1;
gmii_rxdata = packet_byte_rx;
// check whether end of file
if (r_rx == 0)
begin
eof_rx = 1;
@(posedge gmii_rxclk_offset);
gmii_rxctrl = 1'b0;
gmii_rxdata = 8'h00;
disable fileread_loop;
end
end
end_addr_rx = $ftell(feeder_file_rx);
end
$fclose(feeder_file_rx);
gmii_rxctrl = 1'b0;
gmii_rxdata = 8'h00;
end
#100 $stop;
end
 
 
endmodule
/sim/tsu/gmii_tx_bfm.v
0,0 → 1,109
`timescale 1ns/1ns
 
module gmii_tx_bfm
(
output gmii_txclk,
output reg gmii_txctrl,
output reg [7:0] gmii_txdata
);
 
reg gmii_txclk_offset;
initial begin
gmii_txclk_offset = 1'b0;
forever #4 gmii_txclk_offset = !gmii_txclk_offset;
end
assign #2 gmii_txclk = gmii_txclk_offset;
 
integer feeder_file_tx, r_tx;
integer start_addr_tx, end_addr_tx;
integer index_tx;
reg eof_tx;
reg pcap_endian_tx;
reg [31:0] pcap_4bytes_tx;
reg [31:0] packet_leng_tx;
reg [ 7:0] packet_byte_tx;
initial
begin : feeder_tx
gmii_txctrl = 1'b0;
gmii_txdata = 4'd0;
#100;
feeder_file_tx = $fopen("ptpdv2_tx.pcap","rb");
if (feeder_file_tx == 0)
begin
$display("Failed to open ptpdv2_tx.pcap!");
disable feeder_tx;
end
else
begin
// test pcap file endian
r_tx = $fread(pcap_4bytes_tx, feeder_file_tx);
pcap_endian_tx = (pcap_4bytes_tx == 32'ha1b2c3d4)? 1:0;
$fseek(feeder_file_tx, -4, 1);
// skip pcap file header 24*8
$fseek(feeder_file_tx, 24, 1);
// read packet content
eof_tx = 0;
while (!eof_tx & !$feof(feeder_file_tx))
begin : fileread_loop
// skip frame header (8+4)*8
start_addr_tx = $ftell(feeder_file_tx);
$fseek(feeder_file_tx, 8+4, 1);
// get frame length big endian 4*8
r_tx = $fread(packet_leng_tx, feeder_file_tx);
packet_leng_tx = pcap_endian_tx?
{packet_leng_tx[31:24], packet_leng_tx[23:16], packet_leng_tx[15: 8], packet_leng_tx[ 7: 0]}:
{packet_leng_tx[ 7: 0], packet_leng_tx[15: 8], packet_leng_tx[23:16], packet_leng_tx[31:24]};
// check whether end of file
if (r_tx == 0)
begin
eof_tx = 1;
@(posedge gmii_txclk_offset);
gmii_txctrl = 1'b0;
gmii_txdata = 8'h00;
disable fileread_loop;
end
// send ifg 96bit=12*8
repeat (12)
begin
@(posedge gmii_txclk_offset)
gmii_txctrl = 1'b0;
gmii_txdata = 8'h00;
end
// send frame pre-amble 555555d5=4*8
repeat (3)
begin
@(posedge gmii_txclk_offset);
gmii_txctrl = 1'b1;
gmii_txdata = 8'h55;
end
@(posedge gmii_txclk_offset)
gmii_txctrl = 1'b1;
gmii_txdata = 8'hd5;
// send frame content
for (index_tx=0; index_tx<packet_leng_tx; index_tx=index_tx+1)
begin
r_tx = $fread(packet_byte_tx, feeder_file_tx);
@(posedge gmii_txclk_offset);
gmii_txctrl = 1'b1;
gmii_txdata = packet_byte_tx;
// check whether end of file
if (r_tx == 0)
begin
eof_tx = 1;
@(posedge gmii_txclk_offset);
gmii_txctrl = 1'b0;
gmii_txdata = 8'h00;
disable fileread_loop;
end
end
end_addr_tx = $ftell(feeder_file_tx);
end
$fclose(feeder_file_tx);
gmii_txctrl = 1'b0;
gmii_txdata = 8'h00;
end
#100 $stop;
end
 
 
endmodule
/sim/tsu/tsu_queue_tb.v
0,0 → 1,72
`timescale 1ns/1ns
 
module tsu_queue_tb;
 
reg rst;
wire gmii_rxclk;
wire gmii_rxctrl;
wire [7:0] gmii_rxdata;
wire gmii_txclk;
wire gmii_txctrl;
wire [7:0] gmii_txdata;
reg rtc_timer_clk;
reg [79:0] rtc_timer_in;
 
initial begin
DUT_RX.ts_ack = 1'b0;
 
rst = 1'b0;
#10 rst = 1'b1;
#20 rst = 1'b0;
end
 
initial begin
rtc_timer_clk = 1'b0;
forever #4 rtc_timer_clk = !rtc_timer_clk;
end
 
initial begin
rtc_timer_in = 80'd0;
forever @(posedge rtc_timer_clk) rtc_timer_in = rtc_timer_in +1;
end
 
tsu_queue DUT_RX
(
.rst(rst),
 
.gmii_clk(gmii_rxclk),
.gmii_ctrl(gmii_rxctrl),
.gmii_data(gmii_rxdata),
 
.rtc_timer_clk(rtc_timer_clk),
.rtc_timer_in(rtc_timer_in)
);
 
gmii_rx_bfm BFM_RX
(
.gmii_rxclk(gmii_rxclk),
.gmii_rxctrl(gmii_rxctrl),
.gmii_rxdata(gmii_rxdata)
);
 
tsu_queue DUT_TX
(
.rst(rst),
 
.gmii_clk(gmii_txclk),
.gmii_ctrl(gmii_txctrl),
.gmii_data(gmii_txdata),
 
.rtc_timer_clk(rtc_timer_clk),
.rtc_timer_in(rtc_timer_in)
);
 
gmii_tx_bfm BFM_TX
(
.gmii_txclk(gmii_txclk),
.gmii_txctrl(gmii_txctrl),
.gmii_txdata(gmii_txdata)
);
 
endmodule
 
/sim/tsu/sim.do
0,0 → 1,15
quit -sim
 
vlib work
vlog -work work ../../rtl/tsu/tsu_queue.v
vlog -work work ../../rtl/tsu/ptp_parser.v
vlog -work work gmii_rx_bfm.v
vlog -work work gmii_tx_bfm.v
vlog -work work tsu_queue_tb.v
vsim -novopt work.tsu_queue_tb
 
log -r */*
radix -hexadecimal
do wave.do
 
run -all
/sim/tsu/ptpdv2_rx.pcap Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/sim/tsu/ptpdv2_rx.pcap
sim/tsu/ptpdv2_rx.pcap Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sim/tsu/ptpdv2_tx.pcap =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sim/tsu/ptpdv2_tx.pcap =================================================================== --- sim/tsu/ptpdv2_tx.pcap (nonexistent) +++ sim/tsu/ptpdv2_tx.pcap (revision 4)
sim/tsu/ptpdv2_tx.pcap Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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