URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588/trunk
- from Rev 42 to Rev 43
- ↔ Reverse comparison
Rev 42 → Rev 43
/rtl/top/ha1588.v
56,10 → 56,12
|
wire rx_q_rst, rx_q_clk; |
wire rx_q_rd_en; |
wire [ 7:0] rx_q_ptp_msgid_mask; |
wire [ 7:0] rx_q_stat; |
wire [127:0] rx_q_data; |
wire tx_q_rst, tx_q_clk; |
wire tx_q_rd_en; |
wire [ 7:0] tx_q_ptp_msgid_mask; |
wire [ 7:0] tx_q_stat; |
wire [127:0] tx_q_data; |
|
88,11 → 90,13
.rx_q_rst_out(rx_q_rst), |
.rx_q_rd_clk_out(rx_q_clk), |
.rx_q_rd_en_out(rx_q_rd_en), |
.rx_q_ptp_msgid_mask_out(rx_q_ptp_msgid_mask), |
.rx_q_stat_in(rx_q_stat), |
.rx_q_data_in(rx_q_data), |
.tx_q_rst_out(tx_q_rst), |
.tx_q_rd_clk_out(tx_q_clk), |
.tx_q_rd_en_out(tx_q_rd_en), |
.tx_q_ptp_msgid_mask_out(tx_q_ptp_msgid_mask), |
.tx_q_stat_in(tx_q_stat), |
.tx_q_data_in(tx_q_data) |
); |
122,6 → 126,7
.gmii_clk(rx_gmii_clk), |
.gmii_ctrl(rx_gmii_ctrl), |
.gmii_data(rx_gmii_data), |
.ptp_msgid_mask(rx_q_ptp_msgid_mask), |
.rtc_timer_clk(rtc_clk), |
.rtc_timer_in(rtc_time_ptp_val), |
.q_rst(rx_q_rst), |
137,6 → 142,7
.gmii_clk(tx_gmii_clk), |
.gmii_ctrl(tx_gmii_ctrl), |
.gmii_data(tx_gmii_data), |
.ptp_msgid_mask(tx_q_ptp_msgid_mask), |
.rtc_timer_clk(rtc_clk), |
.rtc_timer_in(rtc_time_ptp_val), |
.q_rst(tx_q_rst), |
/rtl/tsu/tsu.v
27,6 → 27,8
input gmii_clk, |
input gmii_ctrl, |
input [7:0] gmii_data, |
|
input [7:0] ptp_msgid_mask, |
|
input rtc_timer_clk, |
input [79:0] rtc_timer_in, // timeStamp1s_48bit + timeStamp1ns_32bit |
216,6 → 218,7
.int_sop(int_sop_d1), |
.int_eop(int_eop_d1), |
.int_mod(int_mod_d1), |
.ptp_msgid_mask(ptp_msgid_mask), |
.ptp_found(ptp_found), |
.ptp_infor(ptp_infor) |
); |
/rtl/tsu/ptp_parser.v
29,6 → 29,8
input int_eop, |
input [ 1:0] int_mod, |
|
input [ 7:0] ptp_msgid_mask, |
|
output reg ptp_found, |
output reg [31:0] ptp_infor |
); |
166,10 → 168,10
|
// check if it is PTP Event message |
if (int_valid && (int_cnt==10'd3 || bypass_vlan && int_cnt==10'd4) && int_data[31:16]==16'h88F7 && |
(int_data[11: 8]>= 4'h0 && int_data[11:8]<=4'h7)) // ptp_message_id == ptp_event |
(ptp_msgid_mask[int_data[11: 8]])) // ptp_message_id == ptp_event |
ptp_event <= 1'b1; |
else if (int_valid && int_cnt==10'd4 && bypass_udp_cnt==10'd1 && ptp_l4 && |
(int_data[11: 8]>= 4'h0 && int_data[11:8]<=4'h7)) // ptp_message_id == ptp_event |
(ptp_msgid_mask[int_data[11: 8]])) // ptp_message_id == ptp_event |
ptp_event <= 1'b1; |
end |
end |
/rtl/reg/reg.v
46,6 → 46,7
output rx_q_rst_out, |
output rx_q_rd_clk_out, |
output rx_q_rd_en_out, |
output [ 7:0] rx_q_ptp_msgid_mask_out, |
input [ 7:0] rx_q_stat_in, |
input [127:0] rx_q_data_in, |
// tx tsu interface |
52,6 → 53,7
output tx_q_rst_out, |
output tx_q_rd_clk_out, |
output tx_q_rd_en_out, |
output [ 7:0] tx_q_ptp_msgid_mask_out, |
input [ 7:0] tx_q_stat_in, |
input [127:0] tx_q_data_in |
); |
251,11 → 253,11
wire perd_ld = reg_00[ 2]; |
wire adjt_ld = reg_00[ 1]; |
wire time_rd = reg_00[ 0]; |
assign time_reg_sec_out [47:0] = {reg_10[15: 0], reg_14[31: 0]}; |
assign time_reg_ns_out [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]}; |
assign period_out [39:0] = {reg_20[ 7: 0], reg_24[31: 0]}; |
assign period_adj_out [39:0] = {reg_28[ 7: 0], reg_2c[31: 0]}; |
assign adj_ld_data_out [31:0] = reg_30[31: 0]; |
assign time_reg_sec_out [47:0] = {reg_10[15: 0], reg_14[31: 0]}; |
assign time_reg_ns_out [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]}; |
assign period_out [39:0] = {reg_20[ 7: 0], reg_24[31: 0]}; |
assign period_adj_out [39:0] = {reg_28[ 7: 0], reg_2c[31: 0]}; |
assign adj_ld_data_out [31:0] = reg_30[31: 0]; |
|
// register mapping: TSU RX |
//wire = reg_40[ 7]; |
266,6 → 268,7
//wire = reg_40[ 2]; |
wire rxq_rst = reg_40[ 1]; |
wire rxqu_rd = reg_40[ 0]; |
assign rx_q_ptp_msgid_mask_out [7:0] = reg_44[31:24]; |
|
// register mapping: TSU TX |
//wire = reg_60[ 7]; |
276,7 → 279,7
//wire = reg_60[ 2]; |
wire txq_rst = reg_60[ 1]; |
wire txqu_rd = reg_60[ 0]; |
// TODO: add configurable PTP Event msgID value mask |
assign tx_q_ptp_msgid_mask_out [7:0] = reg_64[31:24]; |
// TODO: add configurable VLANTPID values |
|
// real time clock |
/doc/TSU MEMORY MAP.csv
6,7 → 6,8
, , 1, TSU_SET_RXRST, R/W, , 0, |
, , 0, TSU_GET_RXQUE, R/W, , 0, |
|
TSU_RXQUE_STATUS, 0x00000044, 31: 8, NULL, R/W, , 0, |
TSU_RXQUE_STATUS, 0x00000044, 31:24, TSU_SET_RXMSGID, R/W, , 0, |
, , 23: 8, NULL, R/W, , 0, |
, , 7: 0, TSU_RXQUE_NUMBER, R/W, , 0, |
|
TSU_NULL_0x48, 0x00000048, 31: 0, NULL, R/W, , 0, |
29,7 → 30,8
, , 1, TSU_SET_TXRST, R/W, , 0, |
, , 0, TSU_GET_TXQUE, R/W, , 0, |
|
TSU_TXQUE_STATUS, 0x00000064, 31: 8, NULL, R/W, , 0, |
TSU_TXQUE_STATUS, 0x00000064, 31:24, TSU_SET_TXMSGID, R/W, , 0, |
, , 23: 8, NULL, R/W, , 0, |
, , 7: 0, TSU_TXQUE_NUMBER, R/W, , 0, |
|
TSU_NULL_0x68, 0x00000068, 31: 0, NULL, R/W, , 0, |
/sim/top/ptp_drv_bfm/ptp_drv_bfm.c
73,11 → 73,13
#define TSU_TXQUE_DATA_LH 0x00000078 |
#define TSU_TXQUE_DATA_LL 0x0000007C |
// define TSU control values |
#define TSU_SET_CTRL_0 0x00 |
#define TSU_GET_RXQUE 0x01 |
#define TSU_SET_RXRST 0x02 |
#define TSU_GET_TXQUE 0x01 |
#define TSU_SET_TXRST 0x02 |
#define TSU_SET_CTRL_0 0x00 |
#define TSU_GET_RXQUE 0x01 |
#define TSU_SET_RXRST 0x02 |
#define TSU_SET_RXMSGID 0xFF000000 |
#define TSU_GET_TXQUE 0x01 |
#define TSU_SET_TXRST 0x02 |
#define TSU_SET_TXMSGID 0xFF000000 |
|
int ptp_drv_bfm_c(double fw_delay) |
{ |
229,6 → 231,15
int rx_queue_num; |
int tx_queue_num; |
|
// CONFIG TSU |
cpu_addr_i = TSU_RXQUE_STATUS; |
cpu_data_i = TSU_SET_RXMSGID; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
cpu_addr_i = TSU_TXQUE_STATUS; |
cpu_data_i = TSU_SET_TXMSGID; |
cpu_wr(cpu_addr_i, cpu_data_i); |
|
// RESET TSU |
cpu_addr_i = TSU_RXCTRL; |
cpu_data_i = TSU_SET_CTRL_0; |
252,7 → 263,7
// POLL TSU RX STATUS |
cpu_addr_i = TSU_RXQUE_STATUS; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
rx_queue_num = cpu_data_o; |
rx_queue_num = cpu_data_o & 0x00FFFFFF; |
//printf("%08x\n", rx_queue_num); |
|
if (rx_queue_num > 0x0) { |
325,7 → 336,7
// POLL TSU TX STATUS |
cpu_addr_i = TSU_TXQUE_STATUS; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
tx_queue_num = cpu_data_o; |
tx_queue_num = cpu_data_o & 0x00FFFFFF; |
//printf("%08x\n", tx_queue_num); |
|
if (tx_queue_num > 0x0) { |
/sim/tsu/tsu_queue_tb.v
70,6 → 70,8
.gmii_ctrl(gmii_rxctrl), |
.gmii_data(gmii_rxdata), |
|
.ptp_msgid_mask(8'b11111111), |
|
.rtc_timer_clk(rtc_timer_clk), |
.rtc_timer_in(rtc_timer_in), |
|
96,6 → 98,8
.gmii_ctrl(gmii_txctrl), |
.gmii_data(gmii_txdata), |
|
.ptp_msgid_mask(8'b11111111), |
|
.rtc_timer_clk(rtc_timer_clk), |
.rtc_timer_in(rtc_timer_in), |
|