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URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

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  • This comparison shows the changes necessary to convert path
    /ha1588/trunk
    from Rev 43 to Rev 44
    Reverse comparison

Rev 43 → Rev 44

/rtl/tsu/tsu.v
113,19 → 113,19
ts_ack_d3 <= ts_ack_d2;
end
end
reg [79:0] gmii_time_stamp;
reg [79:0] tsu_time_stamp;
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
gmii_time_stamp <= 80'd0;
tsu_time_stamp <= 80'd0;
ts_ack_clr <= 1'b0;
end
else begin
if (ts_ack_d2 & !ts_ack_d3) begin
gmii_time_stamp <= rtc_time_stamp;
tsu_time_stamp <= rtc_time_stamp;
ts_ack_clr <= 1'b1;
end
else begin
gmii_time_stamp <= gmii_time_stamp;
tsu_time_stamp <= tsu_time_stamp;
ts_ack_clr <= 1'b0;
end
end
226,7 → 226,7
// ptp time stamp dcfifo
wire q_wr_clk = gmii_clk;
wire q_wr_en = ptp_found && int_eop_d1;
wire [127:0] q_wr_data = {16'd0, gmii_time_stamp, ptp_infor}; // 16+80+32 bit
wire [127:0] q_wr_data = {16'd0, tsu_time_stamp, ptp_infor}; // 16+80+32 bit
wire [3:0] q_wrusedw;
wire [3:0] q_rdusedw;
 
/doc/DESCRIPTION.txt
1,36 → 1,40
General Description
Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packet transmitting and receiving is implemented by PTP SW protocol stack with any existing MAC function internal or external to the FPGA; The IP Core implements the Real-Time Clock (RTC) and Time Stamping of PTP event packets (TSU).
 
Hardware Assisted IEEE 1588 IP Core. The necessary FPGA logic to assist SW protocol stack in implementing the Precision Time Protocol (IEEE 1588-2008) on 1000M/100M/10M Ethernet networks. PTP packet transmitting and receiving is implemented with any existing MAC inside or outside the FPAG; The IP Core will implement the tunable Real-Time Clock and Time Stamping of PTP event packets (L2, UDP/IPv4/MPLS/VLAN and UDP/IPv6/MPLS/VLAN) in two-step-mode.
 
Feature Description
 
RTC: Real Time Clock.
* Standard PTP clock output with 2^48s and 2^32ns time resolution.
* Standard PTP clock output with 2^48s and 2^32ns time format.
* Tunable accumulator based clock with 2^-8ns time resolution and 2^-32ns period resolution.
** Direct ToD write, with 2^-8ns resolution.
** Direct time write, with 2^-8ns resolution.
** Direct frequency write, with 2^-32ns resolution.
** Timed temporary time adjustment, with 2^-8ns resolution and 2^32bit timer.
* Clock Domain Crossing hand-shaking, for SW read and write accesses.
** Timed temporary time adjustment, with 2^-8ns resolution and 32bit timer.
* Variety of input clock frequencies.
* Clock Domain Crossing hand-shaking, for SW read and write access.
TSU: Time Stamping Unit.
* Two-Step PTP operation.
* GMII interface monitor with line-speed PTP packet parsing.
* Variety of PTP packet formats supported.
** L2 PTP packet, with stacked VLAN tags.
** IPv4 and IPv6 UDP PTP packet, with stacked VLAN tags and/or stacked MPLS labels.
* Configurable 8bit mask to selectively timestamp PTP event packet based on message type value.
** 0: Sync
** 1: Delay_Req
** 2: Pdelay_Req
** 3: Pdelay_Resp
** 4 to 7: Reserved for future PTP event message types
* 32bit packet parser datapath for easier timing closure.
* 15-entry timestamp queue.
* 128bit timestamp format.
** 16bit extra information.
** 80bit timestamp.
** 32bit packet identity data.
* GMII interface tap with line-speed PTP event packet parsing.
** Sync
** Delay_Req
** Pdelay_Req
** Pdelay_Resp
* Variety of PTP packet formats support.
** L2 PTP packet with stacked VLAN tags.
** IPv4 and IPv6 UDP PTP packet with stacked VLAN tags and stacked MPLS labels.
* 32bit internal datapath for easier timing closure.
 
SystemVerilog DPI based simulation environment is included for SW driver development.
SystemVerilog DPI based simulation environment is included for SW driver development and co-simulation.
 
The IP Core can be used as an IP Component in Altera SOPC Builder.
PCAP file based stimulus input is used for verification with real-world traffic.
 
The only FPGA vendor dependent module is the timestamp queue. This Altera DCFIFO can be replaced by other FPGA vendor specific dual clock FIFO.
The IP Core can be used as an IP Component in Altera SOPC Builder. Example provided.
 
The only FPGA vendor dependent module is the timestamp queue. This Altera DCFIFO can be replaced by any equivalent dual clock FIFO from other FPGA vendors.
 
/sim/top/ptp_drv_bfm/ptp_drv_bfm.c
76,10 → 76,10
#define TSU_SET_CTRL_0 0x00
#define TSU_GET_RXQUE 0x01
#define TSU_SET_RXRST 0x02
#define TSU_SET_RXMSGID 0xFF000000
#define TSU_SET_RXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
#define TSU_GET_TXQUE 0x01
#define TSU_SET_TXRST 0x02
#define TSU_SET_TXMSGID 0xFF000000
#define TSU_SET_TXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
 
int ptp_drv_bfm_c(double fw_delay)
{
/sim/tsu/wave.do
1,79 → 1,79
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/gmii_clk
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/gmii_ctrl
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/gmii_data
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_req
add wave -noupdate -format Literal -radix hexadecimal /tsu_queue_tb/DUT_RX/rtc_time_stamp
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_ack
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_ack_clr
add wave -noupdate -format Literal -radix hexadecimal /tsu_queue_tb/DUT_RX/gmii_time_stamp
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_gmii_ctrl
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_gmii_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_bcnt
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_valid
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_sop
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_eop
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_mod
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/int_cnt
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/bypass_ipv4_cnt
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/bypass_ipv6_cnt
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/bypass_udp_cnt
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_valid_d1
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_sop_d1
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_eop_d1
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_mod_d1
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_data_d1
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_vlan
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_mpls
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_ipv4
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_ipv6
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_udp
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_l2
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_l4
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_event
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/int_data_d1
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/ptp_cnt
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_msgid
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_seqid
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_cksum
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_found
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_infor
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/q_wr_clk
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/q_wr_en
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/q_wr_data
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/q_wrusedw
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/queue/rdclk
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/queue/rdreq
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/queue/rdusedw
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/BFM_RX/num_rx
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/rx_ptp_event_cnt
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {39134000 ps} 0}
configure wave -namecolwidth 188
configure wave -valuecolwidth 165
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {27824653 ps}
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/gmii_clk
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/gmii_ctrl
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/gmii_data
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_req
add wave -noupdate -format Literal -radix hexadecimal /tsu_queue_tb/DUT_RX/rtc_time_stamp
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_ack
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/ts_ack_clr
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/tsu_time_stamp
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_gmii_ctrl
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_gmii_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_bcnt
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_valid
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_sop
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_eop
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_mod
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/int_cnt
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/bypass_ipv4_cnt
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/bypass_ipv6_cnt
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/bypass_udp_cnt
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_valid_d1
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_sop_d1
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/int_eop_d1
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_mod_d1
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/int_data_d1
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_vlan
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_mpls
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_ipv4
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_ipv6
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/bypass_udp
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_l2
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_l4
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_event
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/int_data_d1
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/parser/ptp_cnt
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_msgid
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_seqid
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_cksum
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_found
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_infor
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/q_wr_clk
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/q_wr_en
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/q_wr_data
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/q_wrusedw
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/queue/rdclk
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/queue/rdreq
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/queue/rdusedw
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/BFM_RX/num_rx
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/rx_ptp_event_cnt
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {39134000 ps} 0}
configure wave -namecolwidth 188
configure wave -valuecolwidth 165
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {175156 ps} {398339 ps}
/sim/tsu/tsu_queue_tb.v
157,18 → 157,21
@(posedge BFM_TX.eof_tx);
join
 
if (rx_ptp_event_cnt == 0)
if (rx_ptp_event_cnt == 0 || tx_ptp_event_cnt == 0) begin
if (rx_ptp_event_cnt == 0)
$display("RX Parser Test Fail: found 0 PTP-EVENT!");
 
if (tx_ptp_event_cnt == 0)
if (tx_ptp_event_cnt == 0)
$display("TX Parser Test Fail: found 0 PTP-EVENT!");
 
if (rx_ptp_mismatch_cnt > 0)
end
else if (rx_ptp_mismatch_cnt > 0 || tx_ptp_mismatch_cnt > 0) begin
if (rx_ptp_mismatch_cnt > 0)
$display("Rx Parser Mismatch Found: RX-PTP-EVENT-MISMATCH = %d", rx_ptp_mismatch_cnt);
else if (tx_ptp_mismatch_cnt > 0)
if (tx_ptp_mismatch_cnt > 0)
$display("Tx Parser Mismatch Found: TX-PTP-EVENT-MISMATCH = %d", tx_ptp_mismatch_cnt);
else
end
else begin
$display("RX and TX Parser Test Pass:\n RX-PTP-EVENT = %d\n TX-PTP-EVENT = %d", rx_ptp_event_cnt, tx_ptp_event_cnt);
end
 
#100 $stop;
end

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