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  • This comparison shows the changes necessary to convert path 
    /ha1588/trunk
    from Rev 45 to Rev 46
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  •

Rev 45 → Rev 46

/doc/RTC MEMORY MAP.csv
2,47 → 2,47
 
REG NAME, REG ADDR, BIT, NAME, R/W, DESCRIPTION, DEFAULT,
 
RTC_CTRL, 0x00000000, 31: 5, NULL, R/W, , 0,
, , 4, RTC_SET_RESET, R/W, , 0,
, , 3, RTC_SET_TIME, R/W, , 0,
, , 2, RTC_SET_PERIOD, R/W, , 0,
, , 1, RTC_SET_ADJ, R/W, , 0,
, , 0, RTC_GET_TIME, R/W, , 0,
RTC_CTRL, 0x00000000, 31: 5, NULL, N/A, , 0,
, , 4, RTC_SET_RESET, R/W, 0->1 , 0,
, , 3, RTC_SET_TIME, R/W, 0->1 , 0,
, , 2, RTC_SET_PERIOD, R/W, 0->1 , 0,
, , 1, RTC_SET_ADJ, R/W, 0->1 POLL , DONE=1 ,
, , 0, RTC_GET_TIME, R/W, 0->1 POLL , DONE=1 ,
 
RTC_NULL_0x04, 0x00000004, 31: 0, NULL, R/W, , 0,
RTC_NULL_0x04, 0x00000004, 31: 0, NULL, N/A, , 0,
 
RTC_NULL_0x08, 0x00000008, 31: 0, NULL, R/W, , 0,
RTC_NULL_0x08, 0x00000008, 31: 0, NULL, N/A, , 0,
 
RTC_NULL_0x0C, 0x0000000C, 31: 0, NULL, R/W, , 0,
RTC_NULL_0x0C, 0x0000000C, 31: 0, NULL, N/A, , 0,
 
RTC_TIME_SEC_H, 0x00000010, 31:16, NULL, R/W, , 0,
, , 15: 0, RTC_TIME_SEC_47_32, R/W, , 0,
RTC_TIME_SEC_H, 0x00000010, 31:16, NULL, N/A, , 0,
, , 15: 0, RTC_TIME_SEC_47_32, R/W, SET GET , 0,
 
RTC_TIME_SEC_L, 0x00000014, 31: 0, RTC_TIME_SEC_31_00, R/W, , 0,
RTC_TIME_SEC_L, 0x00000014, 31: 0, RTC_TIME_SEC_31_00, R/W, SET GET , 0,
 
RTC_TIME_NSC_H, 0x00000018, 31:30, NULL, R/W, , 0,
, , 29: 0, RTC_TIME_NSC_29_00, R/W, , 0,
RTC_TIME_NSC_H, 0x00000018, 31:30, NULL, N/A, , 0,
, , 29: 0, RTC_TIME_NSC_29_00, R/W, SET GET , 0,
 
RTC_TIME_NSC_L, 0x0000001C, 31: 8, NULL, R/W, , 0,
, , 7: 0, RTC_TIME_SUB_NSC_07_00, R/W, , 0,
RTC_TIME_NSC_L, 0x0000001C, 31: 8, NULL, N/A, , 0,
, , 7: 0, RTC_TIME_SUB_NSC_07_00, R/W, SET GET , 0,
 
RTC_PERIOD_H, 0x00000020, 31: 8, NULL, R/W, , 0,
, , 7: 0, RTC_PERIOD_NSC_07_00, R/W, , 0,
RTC_PERIOD_H, 0x00000020, 31: 8, NULL, N/A, , 0,
, , 7: 0, RTC_PERIOD_NSC_07_00, R/W, SET , 0,
 
RTC_PERIOD_L, 0x00000024, 31: 0, RTC_PERIOD_SUB_NSC_31_00, R/W, , 0,
RTC_PERIOD_L, 0x00000024, 31: 0, RTC_PERIOD_SUB_NSC_31_00, R/W, SET , 0,
 
RTC_ADJPER_H, 0x00000028, 31: 8, NULL, R/W, , 0,
, , 7: 0, RTC_ADJPER_NSC_07_00, R/W, , 0,
RTC_ADJPER_H, 0x00000028, 31: 8, NULL, N/A, , 0,
, , 7: 0, RTC_ADJPER_NSC_07_00, R/W, SET , 0,
 
RTC_ADJPER_L, 0x0000002C, 31: 0, RTC_ADJPER_SUB_NSC_31_00, R/W, , 0,
RTC_ADJPER_L, 0x0000002C, 31: 0, RTC_ADJPER_SUB_NSC_31_00, R/W, SET , 0,
 
RTC_ADJNUM, 0x00000030, 31: 0, RTC_ADJNUM_CNT_31_00, R/W, , 0,
RTC_ADJNUM, 0x00000030, 31: 0, RTC_ADJNUM_CNT_31_00, R/W, SET , 0,
 
RTC_NULL_0x34, 0x00000034, 31: 0, NULL, R/W, , 0,
RTC_NULL_0x34, 0x00000034, 31: 0, NULL, N/A, , 0,
 
RTC_NULL_0x38, 0x00000038, 31: 0, NULL, R/W, , 0,
RTC_NULL_0x38, 0x00000038, 31: 0, NULL, N/A, , 0,
 
RTC_NULL_0x3C, 0x0000003C, 31: 0, NULL, R/W, , 0,
RTC_NULL_0x3C, 0x0000003C, 31: 0, NULL, N/A, , 0,
 
 
 
/doc/TSU MEMORY MAP.csv
2,53 → 2,53
 
REG NAME, REG ADDR, BIT, NAME, R/W, DESCRIPTION, DEFAULT,
 
TSU_RXCTRL, 0x00000040, 31: 2, NULL, R/W, , 0,
, , 1, TSU_SET_RXRST, R/W, , 0,
, , 0, TSU_GET_RXQUE, R/W, , 0,
TSU_RXCTRL, 0x00000040, 31: 2, NULL, N/A, , 0,
, , 1, TSU_SET_RXRST, R/W, 0->1 , 0,
, , 0, TSU_GET_RXQUE, R/W, 0->1 POLL , DONE=1 ,
 
TSU_RXQUE_STATUS, 0x00000044, 31:24, TSU_SET_RXMSGID, R/W, , 0,
, , 23: 8, NULL, R/W, , 0,
, , 7: 0, TSU_RXQUE_NUMBER, R/W, , 0,
TSU_RXQUE_STATUS, 0x00000044, 31:24, TSU_MASK_RXMSGID, R/W, EN=1 , 0,
, , 23: 8, NULL, N/A, , 0,
, , 7: 0, TSU_RXQUE_NUMBER, R/O, , 0,
 
TSU_NULL_0x48, 0x00000048, 31: 0, NULL, R/W, , 0,
TSU_NULL_0x48, 0x00000048, 31: 0, NULL, N/A, , 0,
 
TSU_NULL_0x4C, 0x0000004C, 31: 0, NULL, R/W, , 0,
TSU_NULL_0x4C, 0x0000004C, 31: 0, NULL, N/A, , 0,
 
TSU_RXQUE_DATA_HH, 0x00000050, 31:16, NULL, R/W, , 0,
, , 15: 0, TSU_RXQUE_SEC_47_32, R/W, , 0,
TSU_RXQUE_DATA_HH, 0x00000050, 31:16, NULL, N/A, RESERVED , 0,
, , 15: 0, TSU_RXQUE_SEC_47_32, R/O, GET , 0,
 
TSU_RXQUE_DATA_HL, 0x00000054, 31: 0, TSU_RXQUE_SEC_31_00, R/W, , 0,
TSU_RXQUE_DATA_HL, 0x00000054, 31: 0, TSU_RXQUE_SEC_31_00, R/O, GET , 0,
 
TSU_RXQUE_DATA_LH, 0x00000058, 31:30, NULL, R/W, , 0,
, , 29: 0, TSU_RXQUE_NSC_29_00, R/W, , 0,
TSU_RXQUE_DATA_LH, 0x00000058, 31:30, NULL, N/A, RESERVED , 0,
, , 29: 0, TSU_RXQUE_NSC_29_00, R/O, GET , 0,
 
TSU_RXQUE_DATA_LL, 0x0000005C, 31:28, TSU_RXQUE_PTP_MSG_ID, R/W, , 0,
, , 27:16, TSU_RXQUE_PTP_CK_SUM, R/W, , 0,
, , 15: 0, TSU_RXQUE_PTP_SEQ_ID, R/W, , 0,
TSU_RXQUE_DATA_LL, 0x0000005C, 31:28, TSU_RXQUE_PTP_MSG_ID, R/O, GET , 0,
, , 27:16, TSU_RXQUE_PTP_CK_SUM, R/O, GET , 0,
, , 15: 0, TSU_RXQUE_PTP_SEQ_ID, R/O, GET , 0,
 
TSU_TXCTRL, 0x00000060, 31: 2, NULL, R/W, , 0,
, , 1, TSU_SET_TXRST, R/W, , 0,
, , 0, TSU_GET_TXQUE, R/W, , 0,
TSU_TXCTRL, 0x00000060, 31: 2, NULL, N/A, , 0,
, , 1, TSU_SET_TXRST, R/W, 0->1 , 0,
, , 0, TSU_GET_TXQUE, R/W, 0->1 POLL , DONE=1 ,
 
TSU_TXQUE_STATUS, 0x00000064, 31:24, TSU_SET_TXMSGID, R/W, , 0,
, , 23: 8, NULL, R/W, , 0,
, , 7: 0, TSU_TXQUE_NUMBER, R/W, , 0,
TSU_TXQUE_STATUS, 0x00000064, 31:24, TSU_MASK_TXMSGID, R/W, EN=1 , 0,
, , 23: 8, NULL, N/A, , 0,
, , 7: 0, TSU_TXQUE_NUMBER, R/O, , 0,
 
TSU_NULL_0x68, 0x00000068, 31: 0, NULL, R/W, , 0,
TSU_NULL_0x68, 0x00000068, 31: 0, NULL, N/A, , 0,
 
TSU_NULL_0x6C, 0x0000006C, 31: 0, NULL, R/W, , 0,
TSU_NULL_0x6C, 0x0000006C, 31: 0, NULL, N/A, , 0,
 
TSU_TXQUE_DATA_HH, 0x00000070, 31:16, NULL, R/W, , 0,
, , 15: 0, TSU_TXQUE_SEC_47_32, R/W, , 0,
TSU_TXQUE_DATA_HH, 0x00000070, 31:16, NULL, N/A, RESERVED , 0,
, , 15: 0, TSU_TXQUE_SEC_47_32, R/O, GET , 0,
 
TSU_TXQUE_DATA_HL, 0x00000074, 31: 0, TSU_TXQUE_SEC_31_00, R/W, , 0,
TSU_TXQUE_DATA_HL, 0x00000074, 31: 0, TSU_TXQUE_SEC_31_00, R/O, GET , 0,
 
TSU_TXQUE_DATA_LH, 0x00000078, 31:30, NULL, R/W, , 0,
, , 29: 0, TSU_TXQUE_NSC_29_00, R/W, , 0,
TSU_TXQUE_DATA_LH, 0x00000078, 31:30, NULL, N/A, RESERVED , 0,
, , 29: 0, TSU_TXQUE_NSC_29_00, R/O, GET , 0,
 
TSU_TXQUE_DATA_LL, 0x0000007C, 31:28, TSU_TXQUE_PTP_MSG_ID, R/W, , 0,
, , 27:16, TSU_TXQUE_PTP_CK_SUM, R/W, , 0,
, , 15: 0, TSU_TXQUE_PTP_SEQ_ID, R/W, , 0,
TSU_TXQUE_DATA_LL, 0x0000007C, 31:28, TSU_TXQUE_PTP_MSG_ID, R/O, GET , 0,
, , 27:16, TSU_TXQUE_PTP_CK_SUM, R/O, GET , 0,
, , 15: 0, TSU_TXQUE_PTP_SEQ_ID, R/O, GET , 0,
 
 
 
/sim/top/ptp_drv_bfm/ptp_drv_bfm.c
76,10 → 76,11
#define TSU_SET_CTRL_0 0x00
#define TSU_GET_RXQUE 0x01
#define TSU_SET_RXRST 0x02
#define TSU_SET_RXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
#define TSU_GET_TXQUE 0x01
#define TSU_SET_TXRST 0x02
#define TSU_SET_TXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
// define TSU data values
#define TSU_MASK_RXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
#define TSU_MASK_TXMSGID 0xFF000000 // FF to enable 0x0 to 0x7
 
int ptp_drv_bfm_c(double fw_delay)
{
233,11 → 234,11
 
// CONFIG TSU
cpu_addr_i = TSU_RXQUE_STATUS;
cpu_data_i = TSU_SET_RXMSGID;
cpu_data_i = TSU_MASK_RXMSGID;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_TXQUE_STATUS;
cpu_data_i = TSU_SET_TXMSGID;
cpu_data_i = TSU_MASK_TXMSGID;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// RESET TSU

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