URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
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/ha1588/trunk
- from Rev 47 to Rev 48
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Rev 47 → Rev 48
/rtl/top/ha1588.v
43,6 → 43,17
input [7:0] tx_gmii_data |
); |
|
parameter addr_is_in_word = 0; |
wire [ 5: 0] word_addr_in; |
wire [ 7: 0] byte_addr_in; |
generate |
if (addr_is_in_word) |
assign word_addr_in = addr_in[ 5: 0]; |
else |
assign word_addr_in = addr_in[ 7: 2]; |
endgenerate |
assign byte_addr_in = {word_addr_in, 2'b00}; |
|
wire rtc_rst; |
wire rtc_time_ld, rtc_period_ld, rtc_adj_ld, adj_ld_done; |
wire [37:0] rtc_time_reg_ns; |
71,7 → 82,7
.clk(clk), |
.wr_in(wr_in), |
.rd_in(rd_in), |
.addr_in(addr_in), |
.addr_in(byte_addr_in), |
.data_in(data_in), |
.data_out(data_out), |
.rtc_clk_in(rtc_clk), |
/rtl/top/ha1588_hw.tcl
60,6 → 60,16
# +----------------------------------- |
# | parameters |
# | |
add_parameter addr_is_in_word BOOLEAN true "" |
set_parameter_property addr_is_in_word DEFAULT_VALUE true |
set_parameter_property addr_is_in_word DISPLAY_NAME addr_is_in_word |
set_parameter_property addr_is_in_word WIDTH "" |
set_parameter_property addr_is_in_word TYPE BOOLEAN |
set_parameter_property addr_is_in_word ENABLED false |
set_parameter_property addr_is_in_word UNITS None |
set_parameter_property addr_is_in_word DESCRIPTION "" |
set_parameter_property addr_is_in_word AFFECTS_GENERATION false |
set_parameter_property addr_is_in_word HDL_PARAMETER true |
# | |
# +----------------------------------- |
|
/rtl/sopc/ha1588_inst.v
0,0 → 1,780
//megafunction wizard: %Altera SOPC Builder% |
//GENERATION: STANDARD |
//VERSION: WM1.0 |
|
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your |
//use of Altera Corporation's design tools, logic functions and other |
//software and tools, and its AMPP partner logic functions, and any |
//output files any of the foregoing (including device programming or |
//simulation files), and any associated documentation or information are |
//expressly subject to the terms and conditions of the Altera Program |
//License Subscription Agreement or other applicable license agreement, |
//including, without limitation, that your use is for the sole purpose |
//of programming logic devices manufactured by Altera and sold by Altera |
//or its authorized distributors. Please refer to the applicable |
//agreement for further details. |
|
// synthesis translate_off |
`timescale 1ns / 1ps |
// synthesis translate_on |
|
// turn off superfluous verilog processor warnings |
// altera message_level Level1 |
// altera message_off 10034 10035 10036 10037 10230 10240 10030 |
|
module ha1588_comp_avalon_slave_arbitrator ( |
// inputs: |
clk, |
ha1588_comp_avalon_slave_readdata, |
master_bfm_latency_counter, |
master_bfm_m0_address_to_slave, |
master_bfm_m0_read, |
master_bfm_m0_write, |
master_bfm_m0_writedata, |
reset_n, |
|
// outputs: |
d1_ha1588_comp_avalon_slave_end_xfer, |
ha1588_comp_avalon_slave_address, |
ha1588_comp_avalon_slave_read, |
ha1588_comp_avalon_slave_readdata_from_sa, |
ha1588_comp_avalon_slave_reset, |
ha1588_comp_avalon_slave_write, |
ha1588_comp_avalon_slave_writedata, |
master_bfm_granted_ha1588_comp_avalon_slave, |
master_bfm_qualified_request_ha1588_comp_avalon_slave, |
master_bfm_read_data_valid_ha1588_comp_avalon_slave, |
master_bfm_requests_ha1588_comp_avalon_slave |
) |
; |
|
output d1_ha1588_comp_avalon_slave_end_xfer; |
output [ 7: 0] ha1588_comp_avalon_slave_address; |
output ha1588_comp_avalon_slave_read; |
output [ 31: 0] ha1588_comp_avalon_slave_readdata_from_sa; |
output ha1588_comp_avalon_slave_reset; |
output ha1588_comp_avalon_slave_write; |
output [ 31: 0] ha1588_comp_avalon_slave_writedata; |
output master_bfm_granted_ha1588_comp_avalon_slave; |
output master_bfm_qualified_request_ha1588_comp_avalon_slave; |
output master_bfm_read_data_valid_ha1588_comp_avalon_slave; |
output master_bfm_requests_ha1588_comp_avalon_slave; |
input clk; |
input [ 31: 0] ha1588_comp_avalon_slave_readdata; |
input master_bfm_latency_counter; |
input [ 15: 0] master_bfm_m0_address_to_slave; |
input master_bfm_m0_read; |
input master_bfm_m0_write; |
input [ 31: 0] master_bfm_m0_writedata; |
input reset_n; |
|
reg d1_ha1588_comp_avalon_slave_end_xfer; |
reg d1_reasons_to_wait; |
reg enable_nonzero_assertions; |
wire end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave; |
wire [ 7: 0] ha1588_comp_avalon_slave_address; |
wire ha1588_comp_avalon_slave_allgrants; |
wire ha1588_comp_avalon_slave_allow_new_arb_cycle; |
wire ha1588_comp_avalon_slave_any_bursting_master_saved_grant; |
wire ha1588_comp_avalon_slave_any_continuerequest; |
wire ha1588_comp_avalon_slave_arb_counter_enable; |
reg ha1588_comp_avalon_slave_arb_share_counter; |
wire ha1588_comp_avalon_slave_arb_share_counter_next_value; |
wire ha1588_comp_avalon_slave_arb_share_set_values; |
wire ha1588_comp_avalon_slave_beginbursttransfer_internal; |
wire ha1588_comp_avalon_slave_begins_xfer; |
wire ha1588_comp_avalon_slave_end_xfer; |
wire ha1588_comp_avalon_slave_firsttransfer; |
wire ha1588_comp_avalon_slave_grant_vector; |
wire ha1588_comp_avalon_slave_in_a_read_cycle; |
wire ha1588_comp_avalon_slave_in_a_write_cycle; |
wire ha1588_comp_avalon_slave_master_qreq_vector; |
wire ha1588_comp_avalon_slave_non_bursting_master_requests; |
wire ha1588_comp_avalon_slave_read; |
wire [ 31: 0] ha1588_comp_avalon_slave_readdata_from_sa; |
reg ha1588_comp_avalon_slave_reg_firsttransfer; |
wire ha1588_comp_avalon_slave_reset; |
reg ha1588_comp_avalon_slave_slavearbiterlockenable; |
wire ha1588_comp_avalon_slave_slavearbiterlockenable2; |
wire ha1588_comp_avalon_slave_unreg_firsttransfer; |
wire ha1588_comp_avalon_slave_waits_for_read; |
wire ha1588_comp_avalon_slave_waits_for_write; |
wire ha1588_comp_avalon_slave_write; |
wire [ 31: 0] ha1588_comp_avalon_slave_writedata; |
wire in_a_read_cycle; |
wire in_a_write_cycle; |
wire master_bfm_granted_ha1588_comp_avalon_slave; |
wire master_bfm_m0_arbiterlock; |
wire master_bfm_m0_arbiterlock2; |
wire master_bfm_m0_continuerequest; |
wire master_bfm_qualified_request_ha1588_comp_avalon_slave; |
wire master_bfm_read_data_valid_ha1588_comp_avalon_slave; |
wire master_bfm_requests_ha1588_comp_avalon_slave; |
wire master_bfm_saved_grant_ha1588_comp_avalon_slave; |
wire [ 15: 0] shifted_address_to_ha1588_comp_avalon_slave_from_master_bfm_m0; |
wire wait_for_ha1588_comp_avalon_slave_counter; |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
d1_reasons_to_wait <= 0; |
else |
d1_reasons_to_wait <= ~ha1588_comp_avalon_slave_end_xfer; |
end |
|
|
assign ha1588_comp_avalon_slave_begins_xfer = ~d1_reasons_to_wait & ((master_bfm_qualified_request_ha1588_comp_avalon_slave)); |
//assign ha1588_comp_avalon_slave_readdata_from_sa = ha1588_comp_avalon_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign |
assign ha1588_comp_avalon_slave_readdata_from_sa = ha1588_comp_avalon_slave_readdata; |
|
assign master_bfm_requests_ha1588_comp_avalon_slave = ({master_bfm_m0_address_to_slave[15 : 10] , 10'b0} == 16'h0) & (master_bfm_m0_read | master_bfm_m0_write); |
//ha1588_comp_avalon_slave_arb_share_counter set values, which is an e_mux |
assign ha1588_comp_avalon_slave_arb_share_set_values = 1; |
|
//ha1588_comp_avalon_slave_non_bursting_master_requests mux, which is an e_mux |
assign ha1588_comp_avalon_slave_non_bursting_master_requests = master_bfm_requests_ha1588_comp_avalon_slave; |
|
//ha1588_comp_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux |
assign ha1588_comp_avalon_slave_any_bursting_master_saved_grant = 0; |
|
//ha1588_comp_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign |
assign ha1588_comp_avalon_slave_arb_share_counter_next_value = ha1588_comp_avalon_slave_firsttransfer ? (ha1588_comp_avalon_slave_arb_share_set_values - 1) : |ha1588_comp_avalon_slave_arb_share_counter ? (ha1588_comp_avalon_slave_arb_share_counter - 1) : 0; |
|
//ha1588_comp_avalon_slave_allgrants all slave grants, which is an e_mux |
assign ha1588_comp_avalon_slave_allgrants = |ha1588_comp_avalon_slave_grant_vector; |
|
//ha1588_comp_avalon_slave_end_xfer assignment, which is an e_assign |
assign ha1588_comp_avalon_slave_end_xfer = ~(ha1588_comp_avalon_slave_waits_for_read | ha1588_comp_avalon_slave_waits_for_write); |
|
//end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave arb share counter enable term, which is an e_assign |
assign end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave = ha1588_comp_avalon_slave_end_xfer & (~ha1588_comp_avalon_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle); |
|
//ha1588_comp_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign |
assign ha1588_comp_avalon_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave & ha1588_comp_avalon_slave_allgrants) | (end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave & ~ha1588_comp_avalon_slave_non_bursting_master_requests); |
|
//ha1588_comp_avalon_slave_arb_share_counter counter, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
ha1588_comp_avalon_slave_arb_share_counter <= 0; |
else if (ha1588_comp_avalon_slave_arb_counter_enable) |
ha1588_comp_avalon_slave_arb_share_counter <= ha1588_comp_avalon_slave_arb_share_counter_next_value; |
end |
|
|
//ha1588_comp_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
ha1588_comp_avalon_slave_slavearbiterlockenable <= 0; |
else if ((|ha1588_comp_avalon_slave_master_qreq_vector & end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave) | (end_xfer_arb_share_counter_term_ha1588_comp_avalon_slave & ~ha1588_comp_avalon_slave_non_bursting_master_requests)) |
ha1588_comp_avalon_slave_slavearbiterlockenable <= |ha1588_comp_avalon_slave_arb_share_counter_next_value; |
end |
|
|
//master_bfm/m0 ha1588_comp/avalon_slave arbiterlock, which is an e_assign |
assign master_bfm_m0_arbiterlock = ha1588_comp_avalon_slave_slavearbiterlockenable & master_bfm_m0_continuerequest; |
|
//ha1588_comp_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign |
assign ha1588_comp_avalon_slave_slavearbiterlockenable2 = |ha1588_comp_avalon_slave_arb_share_counter_next_value; |
|
//master_bfm/m0 ha1588_comp/avalon_slave arbiterlock2, which is an e_assign |
assign master_bfm_m0_arbiterlock2 = ha1588_comp_avalon_slave_slavearbiterlockenable2 & master_bfm_m0_continuerequest; |
|
//ha1588_comp_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_assign |
assign ha1588_comp_avalon_slave_any_continuerequest = 1; |
|
//master_bfm_m0_continuerequest continued request, which is an e_assign |
assign master_bfm_m0_continuerequest = 1; |
|
assign master_bfm_qualified_request_ha1588_comp_avalon_slave = master_bfm_requests_ha1588_comp_avalon_slave & ~((master_bfm_m0_read & ((master_bfm_latency_counter != 0)))); |
//local readdatavalid master_bfm_read_data_valid_ha1588_comp_avalon_slave, which is an e_mux |
assign master_bfm_read_data_valid_ha1588_comp_avalon_slave = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_read & ~ha1588_comp_avalon_slave_waits_for_read; |
|
//ha1588_comp_avalon_slave_writedata mux, which is an e_mux |
assign ha1588_comp_avalon_slave_writedata = master_bfm_m0_writedata; |
|
//master is always granted when requested |
assign master_bfm_granted_ha1588_comp_avalon_slave = master_bfm_qualified_request_ha1588_comp_avalon_slave; |
|
//master_bfm/m0 saved-grant ha1588_comp/avalon_slave, which is an e_assign |
assign master_bfm_saved_grant_ha1588_comp_avalon_slave = master_bfm_requests_ha1588_comp_avalon_slave; |
|
//allow new arb cycle for ha1588_comp/avalon_slave, which is an e_assign |
assign ha1588_comp_avalon_slave_allow_new_arb_cycle = 1; |
|
//placeholder chosen master |
assign ha1588_comp_avalon_slave_grant_vector = 1; |
|
//placeholder vector of master qualified-requests |
assign ha1588_comp_avalon_slave_master_qreq_vector = 1; |
|
//~ha1588_comp_avalon_slave_reset assignment, which is an e_assign |
assign ha1588_comp_avalon_slave_reset = ~reset_n; |
|
//ha1588_comp_avalon_slave_firsttransfer first transaction, which is an e_assign |
assign ha1588_comp_avalon_slave_firsttransfer = ha1588_comp_avalon_slave_begins_xfer ? ha1588_comp_avalon_slave_unreg_firsttransfer : ha1588_comp_avalon_slave_reg_firsttransfer; |
|
//ha1588_comp_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign |
assign ha1588_comp_avalon_slave_unreg_firsttransfer = ~(ha1588_comp_avalon_slave_slavearbiterlockenable & ha1588_comp_avalon_slave_any_continuerequest); |
|
//ha1588_comp_avalon_slave_reg_firsttransfer first transaction, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
ha1588_comp_avalon_slave_reg_firsttransfer <= 1'b1; |
else if (ha1588_comp_avalon_slave_begins_xfer) |
ha1588_comp_avalon_slave_reg_firsttransfer <= ha1588_comp_avalon_slave_unreg_firsttransfer; |
end |
|
|
//ha1588_comp_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign |
assign ha1588_comp_avalon_slave_beginbursttransfer_internal = ha1588_comp_avalon_slave_begins_xfer; |
|
//ha1588_comp_avalon_slave_read assignment, which is an e_mux |
assign ha1588_comp_avalon_slave_read = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_read; |
|
//ha1588_comp_avalon_slave_write assignment, which is an e_mux |
assign ha1588_comp_avalon_slave_write = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_write; |
|
assign shifted_address_to_ha1588_comp_avalon_slave_from_master_bfm_m0 = master_bfm_m0_address_to_slave; |
//ha1588_comp_avalon_slave_address mux, which is an e_mux |
assign ha1588_comp_avalon_slave_address = shifted_address_to_ha1588_comp_avalon_slave_from_master_bfm_m0 >> 2; |
|
//d1_ha1588_comp_avalon_slave_end_xfer register, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
d1_ha1588_comp_avalon_slave_end_xfer <= 1; |
else |
d1_ha1588_comp_avalon_slave_end_xfer <= ha1588_comp_avalon_slave_end_xfer; |
end |
|
|
//ha1588_comp_avalon_slave_waits_for_read in a cycle, which is an e_mux |
assign ha1588_comp_avalon_slave_waits_for_read = ha1588_comp_avalon_slave_in_a_read_cycle & ha1588_comp_avalon_slave_begins_xfer; |
|
//ha1588_comp_avalon_slave_in_a_read_cycle assignment, which is an e_assign |
assign ha1588_comp_avalon_slave_in_a_read_cycle = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_read; |
|
//in_a_read_cycle assignment, which is an e_mux |
assign in_a_read_cycle = ha1588_comp_avalon_slave_in_a_read_cycle; |
|
//ha1588_comp_avalon_slave_waits_for_write in a cycle, which is an e_mux |
assign ha1588_comp_avalon_slave_waits_for_write = ha1588_comp_avalon_slave_in_a_write_cycle & 0; |
|
//ha1588_comp_avalon_slave_in_a_write_cycle assignment, which is an e_assign |
assign ha1588_comp_avalon_slave_in_a_write_cycle = master_bfm_granted_ha1588_comp_avalon_slave & master_bfm_m0_write; |
|
//in_a_write_cycle assignment, which is an e_mux |
assign in_a_write_cycle = ha1588_comp_avalon_slave_in_a_write_cycle; |
|
assign wait_for_ha1588_comp_avalon_slave_counter = 0; |
|
//synthesis translate_off |
//////////////// SIMULATION-ONLY CONTENTS |
//ha1588_comp/avalon_slave enable non-zero assertions, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
enable_nonzero_assertions <= 0; |
else |
enable_nonzero_assertions <= 1'b1; |
end |
|
|
|
//////////////// END SIMULATION-ONLY CONTENTS |
|
//synthesis translate_on |
|
endmodule |
|
|
|
// turn off superfluous verilog processor warnings |
// altera message_level Level1 |
// altera message_off 10034 10035 10036 10037 10230 10240 10030 |
|
module master_bfm_m0_arbitrator ( |
// inputs: |
clk, |
d1_ha1588_comp_avalon_slave_end_xfer, |
ha1588_comp_avalon_slave_readdata_from_sa, |
master_bfm_granted_ha1588_comp_avalon_slave, |
master_bfm_m0_address, |
master_bfm_m0_read, |
master_bfm_m0_write, |
master_bfm_m0_writedata, |
master_bfm_qualified_request_ha1588_comp_avalon_slave, |
master_bfm_read_data_valid_ha1588_comp_avalon_slave, |
master_bfm_requests_ha1588_comp_avalon_slave, |
reset_n, |
|
// outputs: |
master_bfm_latency_counter, |
master_bfm_m0_address_to_slave, |
master_bfm_m0_readdata, |
master_bfm_m0_readdatavalid, |
master_bfm_m0_reset, |
master_bfm_m0_waitrequest |
) |
; |
|
output master_bfm_latency_counter; |
output [ 15: 0] master_bfm_m0_address_to_slave; |
output [ 31: 0] master_bfm_m0_readdata; |
output master_bfm_m0_readdatavalid; |
output master_bfm_m0_reset; |
output master_bfm_m0_waitrequest; |
input clk; |
input d1_ha1588_comp_avalon_slave_end_xfer; |
input [ 31: 0] ha1588_comp_avalon_slave_readdata_from_sa; |
input master_bfm_granted_ha1588_comp_avalon_slave; |
input [ 15: 0] master_bfm_m0_address; |
input master_bfm_m0_read; |
input master_bfm_m0_write; |
input [ 31: 0] master_bfm_m0_writedata; |
input master_bfm_qualified_request_ha1588_comp_avalon_slave; |
input master_bfm_read_data_valid_ha1588_comp_avalon_slave; |
input master_bfm_requests_ha1588_comp_avalon_slave; |
input reset_n; |
|
reg active_and_waiting_last_time; |
wire master_bfm_latency_counter; |
reg [ 15: 0] master_bfm_m0_address_last_time; |
wire [ 15: 0] master_bfm_m0_address_to_slave; |
reg master_bfm_m0_read_last_time; |
wire [ 31: 0] master_bfm_m0_readdata; |
wire master_bfm_m0_readdatavalid; |
wire master_bfm_m0_reset; |
wire master_bfm_m0_run; |
wire master_bfm_m0_waitrequest; |
reg master_bfm_m0_write_last_time; |
reg [ 31: 0] master_bfm_m0_writedata_last_time; |
wire pre_flush_master_bfm_m0_readdatavalid; |
wire r_0; |
//r_0 master_run cascaded wait assignment, which is an e_assign |
assign r_0 = 1 & (master_bfm_qualified_request_ha1588_comp_avalon_slave | ~master_bfm_requests_ha1588_comp_avalon_slave) & ((~master_bfm_qualified_request_ha1588_comp_avalon_slave | ~master_bfm_m0_read | (1 & ~d1_ha1588_comp_avalon_slave_end_xfer & master_bfm_m0_read))) & ((~master_bfm_qualified_request_ha1588_comp_avalon_slave | ~master_bfm_m0_write | (1 & master_bfm_m0_write))); |
|
//cascaded wait assignment, which is an e_assign |
assign master_bfm_m0_run = r_0; |
|
//optimize select-logic by passing only those address bits which matter. |
assign master_bfm_m0_address_to_slave = {6'b0, |
master_bfm_m0_address[9 : 0]}; |
|
//latent slave read data valids which may be flushed, which is an e_mux |
assign pre_flush_master_bfm_m0_readdatavalid = 0; |
|
//latent slave read data valid which is not flushed, which is an e_mux |
assign master_bfm_m0_readdatavalid = 0 | |
pre_flush_master_bfm_m0_readdatavalid | |
master_bfm_read_data_valid_ha1588_comp_avalon_slave; |
|
//master_bfm/m0 readdata mux, which is an e_mux |
assign master_bfm_m0_readdata = ha1588_comp_avalon_slave_readdata_from_sa; |
|
//actual waitrequest port, which is an e_assign |
assign master_bfm_m0_waitrequest = ~master_bfm_m0_run; |
|
//latent max counter, which is an e_assign |
assign master_bfm_latency_counter = 0; |
|
//~master_bfm_m0_reset assignment, which is an e_assign |
assign master_bfm_m0_reset = ~reset_n; |
|
|
//synthesis translate_off |
//////////////// SIMULATION-ONLY CONTENTS |
//master_bfm_m0_address check against wait, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
master_bfm_m0_address_last_time <= 0; |
else |
master_bfm_m0_address_last_time <= master_bfm_m0_address; |
end |
|
|
//master_bfm/m0 waited last time, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
active_and_waiting_last_time <= 0; |
else |
active_and_waiting_last_time <= master_bfm_m0_waitrequest & (master_bfm_m0_read | master_bfm_m0_write); |
end |
|
|
//master_bfm_m0_address matches last port_name, which is an e_process |
always @(posedge clk) |
begin |
if (active_and_waiting_last_time & (master_bfm_m0_address != master_bfm_m0_address_last_time)) |
begin |
$write("%0d ns: master_bfm_m0_address did not heed wait!!!", $time); |
$stop; |
end |
end |
|
|
//master_bfm_m0_read check against wait, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
master_bfm_m0_read_last_time <= 0; |
else |
master_bfm_m0_read_last_time <= master_bfm_m0_read; |
end |
|
|
//master_bfm_m0_read matches last port_name, which is an e_process |
always @(posedge clk) |
begin |
if (active_and_waiting_last_time & (master_bfm_m0_read != master_bfm_m0_read_last_time)) |
begin |
$write("%0d ns: master_bfm_m0_read did not heed wait!!!", $time); |
$stop; |
end |
end |
|
|
//master_bfm_m0_write check against wait, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
master_bfm_m0_write_last_time <= 0; |
else |
master_bfm_m0_write_last_time <= master_bfm_m0_write; |
end |
|
|
//master_bfm_m0_write matches last port_name, which is an e_process |
always @(posedge clk) |
begin |
if (active_and_waiting_last_time & (master_bfm_m0_write != master_bfm_m0_write_last_time)) |
begin |
$write("%0d ns: master_bfm_m0_write did not heed wait!!!", $time); |
$stop; |
end |
end |
|
|
//master_bfm_m0_writedata check against wait, which is an e_register |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
master_bfm_m0_writedata_last_time <= 0; |
else |
master_bfm_m0_writedata_last_time <= master_bfm_m0_writedata; |
end |
|
|
//master_bfm_m0_writedata matches last port_name, which is an e_process |
always @(posedge clk) |
begin |
if (active_and_waiting_last_time & (master_bfm_m0_writedata != master_bfm_m0_writedata_last_time) & master_bfm_m0_write) |
begin |
$write("%0d ns: master_bfm_m0_writedata did not heed wait!!!", $time); |
$stop; |
end |
end |
|
|
|
//////////////// END SIMULATION-ONLY CONTENTS |
|
//synthesis translate_on |
|
endmodule |
|
|
|
// turn off superfluous verilog processor warnings |
// altera message_level Level1 |
// altera message_off 10034 10035 10036 10037 10230 10240 10030 |
|
module ha1588_inst_reset_clk_0_domain_synch_module ( |
// inputs: |
clk, |
data_in, |
reset_n, |
|
// outputs: |
data_out |
) |
; |
|
output data_out; |
input clk; |
input data_in; |
input reset_n; |
|
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */; |
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */; |
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
data_in_d1 <= 0; |
else |
data_in_d1 <= data_in; |
end |
|
|
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
data_out <= 0; |
else |
data_out <= data_in_d1; |
end |
|
|
|
endmodule |
|
|
|
// turn off superfluous verilog processor warnings |
// altera message_level Level1 |
// altera message_off 10034 10035 10036 10037 10230 10240 10030 |
|
module ha1588_inst ( |
// 1) global signals: |
clk_0, |
reset_n, |
|
// the_ha1588_comp |
rtc_clk_to_the_ha1588_comp, |
rtc_time_ptp_ns_from_the_ha1588_comp, |
rtc_time_ptp_sec_from_the_ha1588_comp, |
rx_gmii_clk_to_the_ha1588_comp, |
rx_gmii_ctrl_to_the_ha1588_comp, |
rx_gmii_data_to_the_ha1588_comp, |
tx_gmii_clk_to_the_ha1588_comp, |
tx_gmii_ctrl_to_the_ha1588_comp, |
tx_gmii_data_to_the_ha1588_comp |
) |
; |
|
output [ 31: 0] rtc_time_ptp_ns_from_the_ha1588_comp; |
output [ 47: 0] rtc_time_ptp_sec_from_the_ha1588_comp; |
input clk_0; |
input reset_n; |
input rtc_clk_to_the_ha1588_comp; |
input rx_gmii_clk_to_the_ha1588_comp; |
input rx_gmii_ctrl_to_the_ha1588_comp; |
input [ 7: 0] rx_gmii_data_to_the_ha1588_comp; |
input tx_gmii_clk_to_the_ha1588_comp; |
input tx_gmii_ctrl_to_the_ha1588_comp; |
input [ 7: 0] tx_gmii_data_to_the_ha1588_comp; |
|
wire clk_0_reset_n; |
wire d1_ha1588_comp_avalon_slave_end_xfer; |
wire [ 7: 0] ha1588_comp_avalon_slave_address; |
wire ha1588_comp_avalon_slave_read; |
wire [ 31: 0] ha1588_comp_avalon_slave_readdata; |
wire [ 31: 0] ha1588_comp_avalon_slave_readdata_from_sa; |
wire ha1588_comp_avalon_slave_reset; |
wire ha1588_comp_avalon_slave_write; |
wire [ 31: 0] ha1588_comp_avalon_slave_writedata; |
wire master_bfm_granted_ha1588_comp_avalon_slave; |
wire master_bfm_latency_counter; |
wire [ 15: 0] master_bfm_m0_address; |
wire [ 15: 0] master_bfm_m0_address_to_slave; |
wire master_bfm_m0_read; |
wire [ 31: 0] master_bfm_m0_readdata; |
wire master_bfm_m0_readdatavalid; |
wire master_bfm_m0_reset; |
wire master_bfm_m0_waitrequest; |
wire master_bfm_m0_write; |
wire [ 31: 0] master_bfm_m0_writedata; |
wire master_bfm_qualified_request_ha1588_comp_avalon_slave; |
wire master_bfm_read_data_valid_ha1588_comp_avalon_slave; |
wire master_bfm_requests_ha1588_comp_avalon_slave; |
wire reset_n_sources; |
wire [ 31: 0] rtc_time_ptp_ns_from_the_ha1588_comp; |
wire [ 47: 0] rtc_time_ptp_sec_from_the_ha1588_comp; |
ha1588_comp_avalon_slave_arbitrator the_ha1588_comp_avalon_slave |
( |
.clk (clk_0), |
.d1_ha1588_comp_avalon_slave_end_xfer (d1_ha1588_comp_avalon_slave_end_xfer), |
.ha1588_comp_avalon_slave_address (ha1588_comp_avalon_slave_address), |
.ha1588_comp_avalon_slave_read (ha1588_comp_avalon_slave_read), |
.ha1588_comp_avalon_slave_readdata (ha1588_comp_avalon_slave_readdata), |
.ha1588_comp_avalon_slave_readdata_from_sa (ha1588_comp_avalon_slave_readdata_from_sa), |
.ha1588_comp_avalon_slave_reset (ha1588_comp_avalon_slave_reset), |
.ha1588_comp_avalon_slave_write (ha1588_comp_avalon_slave_write), |
.ha1588_comp_avalon_slave_writedata (ha1588_comp_avalon_slave_writedata), |
.master_bfm_granted_ha1588_comp_avalon_slave (master_bfm_granted_ha1588_comp_avalon_slave), |
.master_bfm_latency_counter (master_bfm_latency_counter), |
.master_bfm_m0_address_to_slave (master_bfm_m0_address_to_slave), |
.master_bfm_m0_read (master_bfm_m0_read), |
.master_bfm_m0_write (master_bfm_m0_write), |
.master_bfm_m0_writedata (master_bfm_m0_writedata), |
.master_bfm_qualified_request_ha1588_comp_avalon_slave (master_bfm_qualified_request_ha1588_comp_avalon_slave), |
.master_bfm_read_data_valid_ha1588_comp_avalon_slave (master_bfm_read_data_valid_ha1588_comp_avalon_slave), |
.master_bfm_requests_ha1588_comp_avalon_slave (master_bfm_requests_ha1588_comp_avalon_slave), |
.reset_n (clk_0_reset_n) |
); |
|
ha1588_comp the_ha1588_comp |
( |
.addr_in (ha1588_comp_avalon_slave_address), |
.clk (clk_0), |
.data_in (ha1588_comp_avalon_slave_writedata), |
.data_out (ha1588_comp_avalon_slave_readdata), |
.rd_in (ha1588_comp_avalon_slave_read), |
.rst (ha1588_comp_avalon_slave_reset), |
.rtc_clk (rtc_clk_to_the_ha1588_comp), |
.rtc_time_ptp_ns (rtc_time_ptp_ns_from_the_ha1588_comp), |
.rtc_time_ptp_sec (rtc_time_ptp_sec_from_the_ha1588_comp), |
.rx_gmii_clk (rx_gmii_clk_to_the_ha1588_comp), |
.rx_gmii_ctrl (rx_gmii_ctrl_to_the_ha1588_comp), |
.rx_gmii_data (rx_gmii_data_to_the_ha1588_comp), |
.tx_gmii_clk (tx_gmii_clk_to_the_ha1588_comp), |
.tx_gmii_ctrl (tx_gmii_ctrl_to_the_ha1588_comp), |
.tx_gmii_data (tx_gmii_data_to_the_ha1588_comp), |
.wr_in (ha1588_comp_avalon_slave_write) |
); |
|
master_bfm_m0_arbitrator the_master_bfm_m0 |
( |
.clk (clk_0), |
.d1_ha1588_comp_avalon_slave_end_xfer (d1_ha1588_comp_avalon_slave_end_xfer), |
.ha1588_comp_avalon_slave_readdata_from_sa (ha1588_comp_avalon_slave_readdata_from_sa), |
.master_bfm_granted_ha1588_comp_avalon_slave (master_bfm_granted_ha1588_comp_avalon_slave), |
.master_bfm_latency_counter (master_bfm_latency_counter), |
.master_bfm_m0_address (master_bfm_m0_address), |
.master_bfm_m0_address_to_slave (master_bfm_m0_address_to_slave), |
.master_bfm_m0_read (master_bfm_m0_read), |
.master_bfm_m0_readdata (master_bfm_m0_readdata), |
.master_bfm_m0_readdatavalid (master_bfm_m0_readdatavalid), |
.master_bfm_m0_reset (master_bfm_m0_reset), |
.master_bfm_m0_waitrequest (master_bfm_m0_waitrequest), |
.master_bfm_m0_write (master_bfm_m0_write), |
.master_bfm_m0_writedata (master_bfm_m0_writedata), |
.master_bfm_qualified_request_ha1588_comp_avalon_slave (master_bfm_qualified_request_ha1588_comp_avalon_slave), |
.master_bfm_read_data_valid_ha1588_comp_avalon_slave (master_bfm_read_data_valid_ha1588_comp_avalon_slave), |
.master_bfm_requests_ha1588_comp_avalon_slave (master_bfm_requests_ha1588_comp_avalon_slave), |
.reset_n (clk_0_reset_n) |
); |
|
master_bfm the_master_bfm |
( |
.avm_address (master_bfm_m0_address), |
.avm_read (master_bfm_m0_read), |
.avm_readdata (master_bfm_m0_readdata), |
.avm_readdatavalid (master_bfm_m0_readdatavalid), |
.avm_waitrequest (master_bfm_m0_waitrequest), |
.avm_write (master_bfm_m0_write), |
.avm_writedata (master_bfm_m0_writedata), |
.clk (clk_0), |
.reset (master_bfm_m0_reset) |
); |
|
//reset is asserted asynchronously and deasserted synchronously |
ha1588_inst_reset_clk_0_domain_synch_module ha1588_inst_reset_clk_0_domain_synch |
( |
.clk (clk_0), |
.data_in (1'b1), |
.data_out (clk_0_reset_n), |
.reset_n (reset_n_sources) |
); |
|
//reset sources mux, which is an e_mux |
assign reset_n_sources = ~(~reset_n | |
0); |
|
|
endmodule |
|
|
//synthesis translate_off |
|
|
|
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE |
|
// AND HERE WILL BE PRESERVED </ALTERA_NOTE> |
|
|
// If user logic components use Altsync_Ram with convert_hex2ver.dll, |
// set USE_convert_hex2ver in the user comments section above |
|
// `ifdef USE_convert_hex2ver |
// `else |
// `define NO_PLI 1 |
// `endif |
|
`include "c:/altera/10.1/quartus/eda/sim_lib/altera_mf.v" |
`include "c:/altera/10.1/quartus/eda/sim_lib/220model.v" |
`include "c:/altera/10.1/quartus/eda/sim_lib/sgate.v" |
// C:/altera/10.1/ip/altera/sopc_builder_ip/verification/lib/verbosity_pkg.sv |
// C:/altera/10.1/ip/altera/sopc_builder_ip/verification/lib/avalon_mm_pkg.sv |
// C:/altera/10.1/ip/altera/sopc_builder_ip/verification/altera_avalon_mm_master_bfm/altera_avalon_mm_master_bfm.sv |
|
`include "../../rtl/sopc/master_bfm.v" |
`include "../../rtl/top/ha1588.v" |
`include "../../rtl/reg/reg.v" |
`include "../../rtl/rtc/rtc.v" |
`include "../../rtl/tsu/tsu.v" |
`include "../../rtl/tsu/ptp_parser.v" |
`include "../../rtl/tsu/ptp_queue.v" |
`include "../../rtl/sopc/ha1588_comp.v" |
|
`timescale 1ns / 1ps |
|
module test_bench |
; |
|
|
wire clk; |
reg clk_0; |
reg reset_n; |
wire rtc_clk_to_the_ha1588_comp; |
wire [ 31: 0] rtc_time_ptp_ns_from_the_ha1588_comp; |
wire [ 47: 0] rtc_time_ptp_sec_from_the_ha1588_comp; |
wire rx_gmii_clk_to_the_ha1588_comp; |
wire rx_gmii_ctrl_to_the_ha1588_comp; |
wire [ 7: 0] rx_gmii_data_to_the_ha1588_comp; |
wire tx_gmii_clk_to_the_ha1588_comp; |
wire tx_gmii_ctrl_to_the_ha1588_comp; |
wire [ 7: 0] tx_gmii_data_to_the_ha1588_comp; |
|
|
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE |
// add your signals and additional architecture here |
// AND HERE WILL BE PRESERVED </ALTERA_NOTE> |
|
//Set us up the Dut |
ha1588_inst DUT |
( |
.clk_0 (clk_0), |
.reset_n (reset_n), |
.rtc_clk_to_the_ha1588_comp (rtc_clk_to_the_ha1588_comp), |
.rtc_time_ptp_ns_from_the_ha1588_comp (rtc_time_ptp_ns_from_the_ha1588_comp), |
.rtc_time_ptp_sec_from_the_ha1588_comp (rtc_time_ptp_sec_from_the_ha1588_comp), |
.rx_gmii_clk_to_the_ha1588_comp (rx_gmii_clk_to_the_ha1588_comp), |
.rx_gmii_ctrl_to_the_ha1588_comp (rx_gmii_ctrl_to_the_ha1588_comp), |
.rx_gmii_data_to_the_ha1588_comp (rx_gmii_data_to_the_ha1588_comp), |
.tx_gmii_clk_to_the_ha1588_comp (tx_gmii_clk_to_the_ha1588_comp), |
.tx_gmii_ctrl_to_the_ha1588_comp (tx_gmii_ctrl_to_the_ha1588_comp), |
.tx_gmii_data_to_the_ha1588_comp (tx_gmii_data_to_the_ha1588_comp) |
); |
|
initial |
clk_0 = 1'b0; |
always |
#10 clk_0 <= ~clk_0; |
|
initial |
begin |
reset_n <= 0; |
#200 reset_n <= 1; |
end |
|
endmodule |
|
|
//synthesis translate_on |
/rtl/sopc/ha1588_comp.v
0,0 → 1,46
// ha1588_comp.v |
|
// This file was auto-generated as part of a SOPC Builder generate operation. |
// If you edit it your changes will probably be lost. |
|
module ha1588_comp ( |
input wire clk, // clock.clk |
input wire rst, // clock_reset.reset |
input wire wr_in, // avalon_slave.write |
input wire rd_in, // .read |
input wire [7:0] addr_in, // .address |
input wire [31:0] data_in, // .writedata |
output wire [31:0] data_out, // .readdata |
input wire rtc_clk, // ref_clock.export |
output wire [31:0] rtc_time_ptp_ns, // .export |
output wire [47:0] rtc_time_ptp_sec, // .export |
input wire rx_gmii_clk, // gmii_monitor.export |
input wire rx_gmii_ctrl, // .export |
input wire [7:0] rx_gmii_data, // .export |
input wire tx_gmii_clk, // .export |
input wire tx_gmii_ctrl, // .export |
input wire [7:0] tx_gmii_data // .export |
); |
|
ha1588 #( |
.addr_is_in_word (1) |
) ha1588_comp ( |
.clk (clk), // clock.clk |
.rst (rst), // clock_reset.reset |
.wr_in (wr_in), // avalon_slave.write |
.rd_in (rd_in), // .read |
.addr_in (addr_in), // .address |
.data_in (data_in), // .writedata |
.data_out (data_out), // .readdata |
.rtc_clk (rtc_clk), // ref_clock.export |
.rtc_time_ptp_ns (rtc_time_ptp_ns), // .export |
.rtc_time_ptp_sec (rtc_time_ptp_sec), // .export |
.rx_gmii_clk (rx_gmii_clk), // gmii_monitor.export |
.rx_gmii_ctrl (rx_gmii_ctrl), // .export |
.rx_gmii_data (rx_gmii_data), // .export |
.tx_gmii_clk (tx_gmii_clk), // .export |
.tx_gmii_ctrl (tx_gmii_ctrl), // .export |
.tx_gmii_data (tx_gmii_data) // .export |
); |
|
endmodule |
/rtl/sopc/master_bfm.v
0,0 → 1,81
// master_bfm.v |
|
// This file was auto-generated as part of a SOPC Builder generate operation. |
// If you edit it your changes will probably be lost. |
// |
// The HDL file this wrapper is instantiating was not analysed successfully. |
// This can cause problems with the wrapper not matching the child module. |
// Please check that your hw.tcl file includes the following two commands: |
// `set_module_property TOP_LEVEL_HDL_FILE` and |
// `set_module_property TOP_LEVEL_HDL_MODULE` |
// Please also check that the HDL file does not contain syntax errors. |
|
module master_bfm ( |
input wire clk, // clk.clk |
input wire reset, // clk_reset.reset |
output wire [15:0] avm_address, // m0.address |
input wire [31:0] avm_readdata, // .readdata |
output wire [31:0] avm_writedata, // .writedata |
input wire avm_waitrequest, // .waitrequest |
output wire avm_write, // .write |
output wire avm_read, // .read |
input wire avm_readdatavalid // .readdatavalid |
); |
|
altera_avalon_mm_master_bfm #( |
.AV_ADDRESS_W (16), |
.AV_SYMBOL_W (8), |
.AV_NUMSYMBOLS (4), |
.AV_BURSTCOUNT_W (3), |
.AV_READRESPONSE_W (8), |
.AV_WRITERESPONSE_W (8), |
.USE_READ (1), |
.USE_WRITE (1), |
.USE_ADDRESS (1), |
.USE_BYTE_ENABLE (0), |
.USE_BURSTCOUNT (0), |
.USE_READ_DATA (1), |
.USE_READ_DATA_VALID (1), |
.USE_WRITE_DATA (1), |
.USE_BEGIN_TRANSFER (0), |
.USE_BEGIN_BURST_TRANSFER (0), |
.USE_WAIT_REQUEST (1), |
.USE_TRANSACTIONID (0), |
.USE_WRITERESPONSE (0), |
.USE_READRESPONSE (0), |
.USE_CLKEN (0), |
.AV_BURST_LINEWRAP (0), |
.AV_BURST_BNDR_ONLY (0), |
.AV_MAX_PENDING_READS (1), |
.AV_FIX_READ_LATENCY (0), |
.AV_READ_WAIT_TIME (0), |
.AV_WRITE_WAIT_TIME (0), |
.REGISTER_WAITREQUEST (0), |
.AV_REGISTERINCOMINGSIGNALS (0) |
) master_bfm ( |
.clk (clk), // clk.clk |
.reset (reset), // clk_reset.reset |
.avm_address (avm_address), // m0.address |
.avm_readdata (avm_readdata), // .readdata |
.avm_writedata (avm_writedata), // .writedata |
.avm_waitrequest (avm_waitrequest), // .waitrequest |
.avm_write (avm_write), // .write |
.avm_read (avm_read), // .read |
.avm_readdatavalid (avm_readdatavalid), // .readdatavalid |
.avm_burstcount (), // (terminated) |
.avm_begintransfer (), // (terminated) |
.avm_beginbursttransfer (), // (terminated) |
.avm_byteenable (), // (terminated) |
.avm_arbiterlock (), // (terminated) |
.avm_debugaccess (), // (terminated) |
.avm_transactionid (), // (terminated) |
.avm_readresponse (8'b00000000), // (terminated) |
.avm_readid (8'b00000000), // (terminated) |
.avm_writeresponserequest (), // (terminated) |
.avm_writeresponse (8'b00000000), // (terminated) |
.avm_writeresponsevalid (1'b0), // (terminated) |
.avm_writeid (8'b00000000), // (terminated) |
.avm_clken () // (terminated) |
); |
|
endmodule |
/rtl/sopc/ha1588_inst.sopc
10,7 → 10,7
type = "int"; |
} |
} |
element ha1588_0 |
element ha1588_comp |
{ |
datum _sortIndex |
{ |
21,7 → 21,7
element ha1588_inst |
{ |
} |
element mm_master_bfm_0 |
element master_bfm |
{ |
datum _sortIndex |
{ |
34,7 → 34,7
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> |
<parameter name="deviceFamily" value="CYCLONEIII" /> |
<parameter name="fabricMode" value="SOPC" /> |
<parameter name="generateLegacySim" value="true" /> |
<parameter name="generateLegacySim" value="false" /> |
<parameter name="generationId" value="0" /> |
<parameter name="globalResetBus" value="true" /> |
<parameter name="hdlLanguage" value="VERILOG" /> |
41,8 → 41,8
<parameter name="maxAdditionalLatency" value="0" /> |
<parameter name="projectName" value="ha1588_inst.qpf" /> |
<parameter name="sopcBorderPoints" value="true" /> |
<parameter name="systemHash" value="4608333994" /> |
<parameter name="timeStamp" value="1333703471124" /> |
<parameter name="systemHash" value="2156315500" /> |
<parameter name="timeStamp" value="1334738091063" /> |
<module kind="clock_source" version="10.1" enabled="1" name="clk_0"> |
<parameter name="clockFrequency" value="50000000" /> |
<parameter name="clockFrequencyKnown" value="true" /> |
49,7 → 49,8
<parameter name="inputClockFrequency" value="0" /> |
<parameter name="resetSynchronousEdges" value="NONE" /> |
</module> |
<module kind="ha1588" version="1.0" enabled="1" name="ha1588_0"> |
<module kind="ha1588" version="1.0" enabled="1" name="ha1588_comp"> |
<parameter name="addr_is_in_word" value="true" /> |
<parameter name="AUTO_CLOCK_CLOCK_RATE" value="50000000" /> |
</module> |
<module |
56,8 → 57,8
kind="altera_avalon_mm_master_bfm" |
version="10.1" |
enabled="1" |
name="mm_master_bfm_0"> |
<parameter name="AV_ADDRESS_W" value="32" /> |
name="master_bfm"> |
<parameter name="AV_ADDRESS_W" value="16" /> |
<parameter name="AV_SYMBOL_W" value="8" /> |
<parameter name="AV_NUMSYMBOLS" value="4" /> |
<parameter name="AV_BURSTCOUNT_W" value="3" /> |
66,7 → 67,7
<parameter name="USE_READ" value="1" /> |
<parameter name="USE_WRITE" value="1" /> |
<parameter name="USE_ADDRESS" value="1" /> |
<parameter name="USE_BYTE_ENABLE" value="1" /> |
<parameter name="USE_BYTE_ENABLE" value="0" /> |
<parameter name="USE_BURSTCOUNT" value="0" /> |
<parameter name="USE_READ_DATA" value="1" /> |
<parameter name="USE_READ_DATA_VALID" value="1" /> |
86,28 → 87,24
<parameter name="ASSERT_HIGH_WRITE" value="1" /> |
<parameter name="ASSERT_HIGH_BYTEENABLE" value="1" /> |
<parameter name="ASSERT_HIGH_READDATAVALID" value="1" /> |
<parameter name="ASSERT_HIGH_ARBITERLOCK" value="1" /> |
<parameter name="ASSERT_HIGH_ARBITERLOCK" value="0" /> |
<parameter name="AV_BURST_LINEWRAP" value="0" /> |
<parameter name="AV_BURST_BNDR_ONLY" value="0" /> |
<parameter name="AV_MAX_PENDING_READS" value="1" /> |
<parameter name="AV_FIX_READ_LATENCY" value="1" /> |
<parameter name="AV_READ_WAIT_TIME" value="1" /> |
<parameter name="AV_FIX_READ_LATENCY" value="0" /> |
<parameter name="AV_READ_WAIT_TIME" value="0" /> |
<parameter name="AV_WRITE_WAIT_TIME" value="0" /> |
<parameter name="REGISTER_WAITREQUEST" value="0" /> |
<parameter name="AV_REGISTERINCOMINGSIGNALS" value="0" /> |
<parameter name="ADDRESS_UNITS" value="SYMBOLS" /> |
</module> |
<connection kind="clock" version="10.1" start="clk_0.clk" end="ha1588_0.clock" /> |
<connection kind="clock" version="10.1" start="clk_0.clk" end="ha1588_comp.clock" /> |
<connection kind="clock" version="10.1" start="clk_0.clk" end="master_bfm.clk" /> |
<connection |
kind="clock" |
version="10.1" |
start="clk_0.clk" |
end="mm_master_bfm_0.clk" /> |
<connection |
kind="avalon" |
version="10.1" |
start="mm_master_bfm_0.m0" |
end="ha1588_0.avalon_slave"> |
start="master_bfm.m0" |
end="ha1588_comp.avalon_slave"> |
<parameter name="arbitrationPriority" value="1" /> |
<parameter name="baseAddress" value="0x0000" /> |
</connection> |
/sim/sopc/test_result.v
0,0 → 1,17
//change this file to perform different test result checkng function |
always @ go_check |
begin |
checked++; |
|
if(response_request == REQ_READ) |
begin |
expected_data = master_scoreboard.pop_front(); //get the expected data which was saved earlier |
|
if(response_data != expected_data) |
begin |
failure++; |
$sformat(message, "%m: Data mismatch at %0h: %0h with expected %0h\n", response_addr, response_data, expected_data); |
print(VERBOSITY_FAILURE, message); |
end |
end |
end |
/sim/sopc/test_input.v
0,0 → 1,26
//change this file for different test case |
initial |
begin |
@ start_test; |
command_addr = 0; //write address start from 0x0 |
byte_enable = '1; //all byte lanes are used |
idle = 0; //no idle cycle between each command of the master BFM |
init_latency = 0; //the command is launched to Avalon bus with no delay |
|
//First write NUM_TRANS of random data to the DUT |
for (int i = 0; i < `NUM_TRANS; i++) |
begin |
command_data = {$random()} % 8; |
master_scoreboard.push_back(command_data); //make a local copy of the write data |
master_set_and_push_command(REQ_WRITE, command_addr, command_data, byte_enable, idle, init_latency); |
command_addr = command_addr + 4; |
end |
|
//Next read back the data |
command_addr = 0; |
for (int i = 0; i < `NUM_TRANS; i++) |
begin |
master_set_and_push_command(REQ_READ, command_addr, 0, byte_enable, idle, init_latency); |
command_addr = command_addr + 4; |
end |
end |
/sim/sopc/wave.do
0,0 → 1,47
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -divider {Master BFM} |
add wave -noupdate -format Logic -radix hexadecimal /master_bfm_tb/tb/DUT/the_master_bfm/clk |
add wave -noupdate -format Logic -radix hexadecimal /master_bfm_tb/tb/DUT/the_master_bfm/reset |
add wave -noupdate -format Literal -radix hexadecimal /master_bfm_tb/tb/DUT/the_master_bfm/avm_address |
add wave -noupdate -format Logic -radix hexadecimal /master_bfm_tb/tb/DUT/the_master_bfm/avm_waitrequest |
add wave -noupdate -format Logic -radix hexadecimal /master_bfm_tb/tb/DUT/the_master_bfm/avm_write |
add wave -noupdate -format Literal -radix hexadecimal /master_bfm_tb/tb/DUT/the_master_bfm/avm_writedata |
add wave -noupdate -format Logic -radix hexadecimal /master_bfm_tb/tb/DUT/the_master_bfm/avm_read |
add wave -noupdate -format Literal -radix hexadecimal /master_bfm_tb/tb/DUT/the_master_bfm/avm_readdata |
add wave -noupdate -format Logic /master_bfm_tb/tb/DUT/the_master_bfm/avm_readdatavalid |
add wave -noupdate -divider {Slave HA1588} |
add wave -noupdate -format Logic /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/rst |
add wave -noupdate -format Logic /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/clk |
add wave -noupdate -format Logic /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/wr_in |
add wave -noupdate -format Logic /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/rd_in |
add wave -noupdate -format Literal /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/addr_in |
add wave -noupdate -format Literal /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/data_in |
add wave -noupdate -format Literal /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/data_out |
add wave -noupdate -divider {Reg HA1588} |
add wave -noupdate -format Logic /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/u_rgs/rst |
add wave -noupdate -format Logic /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/u_rgs/clk |
add wave -noupdate -format Logic /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/u_rgs/wr_in |
add wave -noupdate -format Logic /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/u_rgs/rd_in |
add wave -noupdate -format Literal /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/u_rgs/addr_in |
add wave -noupdate -format Literal /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/u_rgs/data_in |
add wave -noupdate -format Literal /master_bfm_tb/tb/DUT/the_ha1588_comp/ha1588_comp/u_rgs/data_out |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -divider {New Divider} |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {427662 ps} 0} |
configure wave -namecolwidth 358 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
configure wave -timelineunits ps |
update |
WaveRestoreZoom {187361 ps} {579613 ps} |
/sim/sopc/master_bfm_tb.v
0,0 → 1,141
//-------------------------------------------------------------------------- |
// master_bfm_tb.v |
// This test bench instantiates a master BFM and an onchip RAM |
// as the slave DUT. The test starts with master BFM writing an |
// amount of data to the slave according to the number of |
// transactions which is defined by user. |
// |
// Next, master BFM starts reading back the data from slave. |
// The read back data is compared with the desired data . |
// |
// The test case is defined in the test_input.v file while the |
// result checking rountine is defined in test_result.v file |
//-------------------------------------------------------------------------- |
|
// console messaging level |
`define VERBOSITY VERBOSITY_INFO |
|
//BFM hierachy |
`define MSTR_BFM tb.DUT.the_master_bfm.master_bfm |
|
//test bench parameters |
`define NUM_TRANS 5 //user-defined number of transactions to be performed |
`define INDEX_ZERO 0 //burst cycle with index zero for non-bursting transactions |
|
// BFM related parameters |
`define AV_ADDRESS_W 16 |
`define AV_SYMBOL_W 8 |
`define AV_NUMSYMBOLS 4 |
|
// derived parameters |
`define AV_DATA_W (`AV_SYMBOL_W * `AV_NUMSYMBOLS) |
|
|
//----------------------------------------------------------------------------- |
// Test Top Level begins here |
//----------------------------------------------------------------------------- |
module master_bfm_tb(); |
|
//importing verbosity and avalon_mm packages |
import verbosity_pkg::*; |
import avalon_mm_pkg::*; |
|
// instantiate SOPC system module |
test_bench tb(); |
|
//local variables |
Request_t command_request, response_request; |
reg [`AV_ADDRESS_W-1:0] command_addr, response_addr; |
reg [`AV_DATA_W-1:0] command_data, response_data; |
reg [`AV_NUMSYMBOLS-1:0] byte_enable; |
reg [`AV_DATA_W-1:0] idle; |
integer init_latency; |
reg [`AV_DATA_W-1:0] master_scoreboard [$]; |
reg [`AV_DATA_W-1:0] expected_data; |
integer failure = 0; |
integer checked = 0; |
event start_test; |
event go_check; |
|
//initialize the master BFM |
initial |
begin |
set_verbosity(`VERBOSITY); |
`MSTR_BFM.init(); |
//wait for reset to de-assert and trigger start_test event |
wait(`MSTR_BFM.reset == 0); |
-> start_test; |
end |
|
//check responses received by master BFM |
always @(posedge tb.clk_0) |
begin |
while (`MSTR_BFM.get_response_queue_size() > 0) |
begin |
//pop out the response desriptor from queue when queue is not empty |
master_pop_and_get_response(response_request, response_addr, response_data); |
//trigger event to check the response with expected data |
-> go_check; |
end |
end |
|
//simulation ends here |
//both write and read transactions do have response descriptors, so the number |
//of responses received by master BFM is double of NUM_TRANS |
initial |
begin |
while (checked != (`NUM_TRANS*2)) |
@(tb.clk_0); |
//we care only the result for read transactions |
$sformat(message, "%m: Test has completed. %0d pass, %0d fail", ((checked / 2) - failure), failure); |
print(VERBOSITY_INFO, message); |
$stop; |
end |
|
`include "test_input.v" |
`include "test_result.v" |
|
//---------------------------------------------------------------------------------- |
// tasks |
//---------------------------------------------------------------------------------- |
|
//this task sets the command descriptor for master BFM and push it to the queue |
task master_set_and_push_command; |
input Request_t request; |
input [`AV_ADDRESS_W-1:0] addr; |
input [`AV_DATA_W-1:0] data; |
input [`AV_NUMSYMBOLS-1:0] byte_enable; |
input [`AV_DATA_W-1:0] idle; |
input [31:0] init_latency; |
|
begin |
`MSTR_BFM.set_command_request(request); |
`MSTR_BFM.set_command_address(addr); |
`MSTR_BFM.set_command_byte_enable(byte_enable,`INDEX_ZERO); |
`MSTR_BFM.set_command_idle(idle, `INDEX_ZERO); |
`MSTR_BFM.set_command_init_latency(init_latency); |
|
if (request == REQ_WRITE) |
begin |
`MSTR_BFM.set_command_data(data, `INDEX_ZERO); |
end |
|
`MSTR_BFM.push_command(); |
end |
endtask |
|
//this task pops the response received by master BFM from queue |
task master_pop_and_get_response; |
output Request_t request; |
output [`AV_ADDRESS_W-1:0] addr; |
output [`AV_DATA_W-1:0] data; |
|
begin |
`MSTR_BFM.pop_response(); |
request = Request_t' (`MSTR_BFM.get_response_request()); |
addr = `MSTR_BFM.get_response_address(); |
data = `MSTR_BFM.get_response_data(`INDEX_ZERO); |
end |
endtask |
|
endmodule |
/sim/sopc/sim.do
0,0 → 1,20
quit -sim |
|
vlib work |
vdel -lib work -all |
|
vlib work |
vmap work work |
vlog -sv -work work $env(QUARTUS_ROOTDIR)/../ip/altera/sopc_builder_ip/verification/lib/verbosity_pkg.sv |
vlog -sv -work work $env(QUARTUS_ROOTDIR)/../ip/altera/sopc_builder_ip/verification/lib/avalon_mm_pkg.sv |
vlog -sv -work work $env(QUARTUS_ROOTDIR)/../ip/altera/sopc_builder_ip/verification/altera_avalon_mm_master_bfm/altera_avalon_mm_master_bfm.sv |
vlog -sv -work work ../../rtl/sopc/ha1588_inst.v |
vlog -sv -work work ./master_bfm_tb.v |
|
vsim -novopt work.master_bfm_tb |
|
log -r */* |
radix -hexadecimal |
do wave.do |
|
run 1000 ns |