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URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

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    /ha1588
    from Rev 19 to Rev 20
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Rev 19 → Rev 20

/trunk/rtl/top/ha1588_hw.tcl
0,0 → 1,141
# TCL File Generated by Component Editor 10.1sp1
# Sat Mar 31 15:26:56 CST 2012
# DO NOT MODIFY
 
 
# +-----------------------------------
# |
# | ha1588 "Hardware Assisted IEEE 1588 IP Core" v1.0
# | Walter EDN 2012.03.31.15:26:56
# | Hardware Assisted IEEE 1588 IP Core
# |
# | ha1588.v
# |
# | ../../rtl/top/ha1588.v syn, sim
# | ../../rtl/reg/reg.v syn, sim
# | ../../rtl/rtc/rtc.v syn, sim
# | ../../rtl/tsu/tsu.v syn, sim
# | ../../rtl/tsu/ptp_parser.v syn, sim
# | ../../rtl/tsu/ptp_queue.v syn, sim
# |
# +-----------------------------------
 
# +-----------------------------------
# | request TCL package from ACDS 10.1
# |
package require -exact sopc 10.1
# |
# +-----------------------------------
 
# +-----------------------------------
# | module ha1588
# |
set_module_property DESCRIPTION "Hardware Assisted IEEE 1588 IP Core"
set_module_property NAME ha1588
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR "Walter EDN"
set_module_property DISPLAY_NAME "Hardware Assisted IEEE 1588 IP Core"
set_module_property TOP_LEVEL_HDL_FILE ha1588.v
set_module_property TOP_LEVEL_HDL_MODULE ha1588
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# |
# +-----------------------------------
 
# +-----------------------------------
# | files
# |
add_file ../../rtl/top/ha1588.v {SYNTHESIS SIMULATION}
add_file ../../rtl/reg/reg.v {SYNTHESIS SIMULATION}
add_file ../../rtl/rtc/rtc.v {SYNTHESIS SIMULATION}
add_file ../../rtl/tsu/tsu.v {SYNTHESIS SIMULATION}
add_file ../../rtl/tsu/ptp_parser.v {SYNTHESIS SIMULATION}
add_file ../../rtl/tsu/ptp_queue.v {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
 
# +-----------------------------------
# | parameters
# |
# |
# +-----------------------------------
 
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point clock
# |
add_interface clock clock end
set_interface_property clock clockRate 0
 
set_interface_property clock ENABLED true
 
add_interface_port clock clk clk Input 1
add_interface_port clock rst reset Input 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point avalon_slave
# |
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressAlignment DYNAMIC
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave isMemoryDevice false
set_interface_property avalon_slave isNonVolatileStorage false
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave printableDevice false
set_interface_property avalon_slave readLatency 0
set_interface_property avalon_slave readWaitTime 1
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
 
set_interface_property avalon_slave ENABLED true
 
add_interface_port avalon_slave wr_in write Input 1
add_interface_port avalon_slave rd_in read Input 1
add_interface_port avalon_slave addr_in address Input 6
add_interface_port avalon_slave data_in writedata Input 32
add_interface_port avalon_slave data_out readdata Output 32
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point ref_clock
# |
add_interface ref_clock conduit end
 
set_interface_property ref_clock ENABLED true
 
add_interface_port ref_clock rtc_clk export Input 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point gmii_monitor
# |
add_interface gmii_monitor conduit end
 
set_interface_property gmii_monitor ENABLED true
 
add_interface_port gmii_monitor rx_gmii_clk export Input 1
add_interface_port gmii_monitor rx_gmii_ctrl export Input 1
add_interface_port gmii_monitor rx_gmii_data export Input 8
add_interface_port gmii_monitor tx_gmii_clk export Input 1
add_interface_port gmii_monitor tx_gmii_ctrl export Input 1
add_interface_port gmii_monitor tx_gmii_data export Input 8
# |
# +-----------------------------------
/trunk/rtl/sopc/ha1588_inst.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
# Date created = 15:10:26 March 31, 2012
#
# -------------------------------------------------------------------------- #
 
QUARTUS_VERSION = "10.1"
DATE = "15:10:26 March 31, 2012"
 
# Revisions
 
PROJECT_REVISION = "ha1588_inst"
/trunk/rtl/sopc/ha1588_inst.qsf
0,0 → 1,49
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
# Date created = 14:25:42 March 31, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ha1588_inst_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
 
 
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY ha1588_inst
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:25:42 MARCH 31, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name QIP_FILE ha1588_inst.qip
/trunk/rtl/sopc/ReadMe.txt
0,0 → 1,2
add the following path in SOPC -> Tools -> Options -> IP Search Path
../../rtl/top
/trunk/rtl/sopc/ha1588_inst.sopc
0,0 → 1,114
<?xml version="1.0" encoding="UTF-8"?>
<system name="ha1588_inst">
<parameter name="bonusData"><![CDATA[bonusData
{
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element ha1588_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element ha1588_inst
{
}
element mm_master_bfm_0
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="deviceFamily" value="CYCLONEIII" />
<parameter name="fabricMode" value="SOPC" />
<parameter name="generateLegacySim" value="true" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="true" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName" value="ha1588_inst.qpf" />
<parameter name="sopcBorderPoints" value="true" />
<parameter name="systemHash" value="478272704" />
<parameter name="timeStamp" value="1333178915255" />
<module kind="clock_source" version="10.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module kind="ha1588" version="1.0" enabled="1" name="ha1588_0">
<parameter name="AUTO_CLOCK_CLOCK_RATE" value="50000000" />
</module>
<module
kind="altera_avalon_mm_master_bfm"
version="10.1"
enabled="1"
name="mm_master_bfm_0">
<parameter name="AV_ADDRESS_W" value="32" />
<parameter name="AV_SYMBOL_W" value="8" />
<parameter name="AV_NUMSYMBOLS" value="4" />
<parameter name="AV_BURSTCOUNT_W" value="3" />
<parameter name="AV_READRESPONSE_W" value="8" />
<parameter name="AV_WRITERESPONSE_W" value="8" />
<parameter name="USE_READ" value="1" />
<parameter name="USE_WRITE" value="1" />
<parameter name="USE_ADDRESS" value="1" />
<parameter name="USE_BYTE_ENABLE" value="1" />
<parameter name="USE_BURSTCOUNT" value="1" />
<parameter name="USE_READ_DATA" value="1" />
<parameter name="USE_READ_DATA_VALID" value="1" />
<parameter name="USE_WRITE_DATA" value="1" />
<parameter name="USE_BEGIN_TRANSFER" value="0" />
<parameter name="USE_BEGIN_BURST_TRANSFER" value="0" />
<parameter name="USE_ARBITERLOCK" value="0" />
<parameter name="USE_DEBUGACCESS" value="0" />
<parameter name="USE_WAIT_REQUEST" value="1" />
<parameter name="USE_TRANSACTIONID" value="0" />
<parameter name="USE_WRITERESPONSE" value="0" />
<parameter name="USE_READRESPONSE" value="0" />
<parameter name="USE_CLKEN" value="0" />
<parameter name="ASSERT_HIGH_RESET" value="1" />
<parameter name="ASSERT_HIGH_WAITREQUEST" value="1" />
<parameter name="ASSERT_HIGH_READ" value="1" />
<parameter name="ASSERT_HIGH_WRITE" value="1" />
<parameter name="ASSERT_HIGH_BYTEENABLE" value="1" />
<parameter name="ASSERT_HIGH_READDATAVALID" value="1" />
<parameter name="ASSERT_HIGH_ARBITERLOCK" value="1" />
<parameter name="AV_BURST_LINEWRAP" value="1" />
<parameter name="AV_BURST_BNDR_ONLY" value="1" />
<parameter name="AV_MAX_PENDING_READS" value="1" />
<parameter name="AV_FIX_READ_LATENCY" value="1" />
<parameter name="AV_READ_WAIT_TIME" value="1" />
<parameter name="AV_WRITE_WAIT_TIME" value="0" />
<parameter name="REGISTER_WAITREQUEST" value="0" />
<parameter name="AV_REGISTERINCOMINGSIGNALS" value="0" />
<parameter name="ADDRESS_UNITS" value="SYMBOLS" />
</module>
<connection kind="clock" version="10.1" start="clk_0.clk" end="ha1588_0.clock" />
<connection
kind="clock"
version="10.1"
start="clk_0.clk"
end="mm_master_bfm_0.clk" />
<connection
kind="avalon"
version="10.1"
start="mm_master_bfm_0.m0"
end="ha1588_0.avalon_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
</connection>
</system>

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