URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588
- from Rev 22 to Rev 23
- ↔ Reverse comparison
Rev 22 → Rev 23
/trunk/rtl/reg/reg.v
145,10 → 145,11
reg [ 7:0] rx_q_stat_int; |
reg [55:0] tx_q_data_int; |
reg [ 7:0] tx_q_stat_int; |
reg time_ok; |
|
reg [31:0] data_out_reg; |
always @(posedge clk) begin |
if (rd_in && cs_00) data_out_reg <= reg_00; |
if (rd_in && cs_00) data_out_reg <= {reg_00[31:1], time_ok}; |
if (rd_in && cs_04) data_out_reg <= {8'd0, rx_q_stat_int[ 7: 0], 8'd0, tx_q_stat_int[ 7: 0]}; |
if (rd_in && cs_08) data_out_reg <= reg_08; |
if (rd_in && cs_0c) data_out_reg <= reg_0c; |
196,53 → 197,67
assign period_adj_out [39:0] = {reg_38[ 7: 0], reg_3c[31: 0]}; |
|
// real time clock |
reg rtc_rst_d1, rtc_rst_d2, rtc_rst_d3; |
assign rtc_rst_out = rtc_rst_d2 && !rtc_rst_d3; |
always @(posedge clk) begin |
rtc_rst_d1 <= rtc_rst; |
rtc_rst_d2 <= rtc_rst_d1; |
rtc_rst_d3 <= rtc_rst_d2; |
reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3; |
assign rtc_rst_out = rtc_rst_s2 && !rtc_rst_s3; |
always @(posedge rtc_clk_in) begin |
rtc_rst_s1 <= rtc_rst; |
rtc_rst_s2 <= rtc_rst_s1; |
rtc_rst_s3 <= rtc_rst_s2; |
end |
|
reg time_ld_d1, time_ld_d2, time_ld_d3; |
assign time_ld_out = time_ld_d2 && !time_ld_d3; |
always @(posedge clk) begin |
time_ld_d1 <= time_ld; |
time_ld_d2 <= time_ld_d1; |
time_ld_d3 <= time_ld_d2; |
reg time_ld_s1, time_ld_s2, time_ld_s3; |
assign time_ld_out = time_ld_s2 && !time_ld_s3; |
always @(posedge rtc_clk_in) begin |
time_ld_s1 <= time_ld; |
time_ld_s2 <= time_ld_s1; |
time_ld_s3 <= time_ld_s2; |
end |
|
reg perd_ld_d1, perd_ld_d2, perd_ld_d3; |
assign period_ld_out = perd_ld_d2 && !perd_ld_d3; |
always @(posedge clk) begin |
perd_ld_d1 <= perd_ld; |
perd_ld_d2 <= perd_ld_d1; |
perd_ld_d3 <= perd_ld_d2; |
reg perd_ld_s1, perd_ld_s2, perd_ld_s3; |
assign period_ld_out = perd_ld_s2 && !perd_ld_s3; |
always @(posedge rtc_clk_in) begin |
perd_ld_s1 <= perd_ld; |
perd_ld_s2 <= perd_ld_s1; |
perd_ld_s3 <= perd_ld_s2; |
end |
|
reg adjt_ld_d1, adjt_ld_d2, adjt_ld_d3; |
assign adj_ld_out = adjt_ld_d2 && !adjt_ld_d3; |
always @(posedge clk) begin |
adjt_ld_d1 <= adjt_ld; |
adjt_ld_d2 <= adjt_ld_d1; |
adjt_ld_d3 <= adjt_ld_d2; |
reg adjt_ld_s1, adjt_ld_s2, adjt_ld_s3; |
assign adj_ld_out = adjt_ld_s2 && !adjt_ld_s3; |
always @(posedge rtc_clk_in) begin |
adjt_ld_s1 <= adjt_ld; |
adjt_ld_s2 <= adjt_ld_s1; |
adjt_ld_s3 <= adjt_ld_s2; |
end |
|
reg time_rd_d1, time_rd_d2, time_rd_d3; |
wire time_reg_in_latch = time_rd_d2 && !time_rd_d3; |
// RTC time read CDC hand-shaking |
reg time_rd_s1, time_rd_s2, time_rd_s3; |
wire time_rd_ack = time_rd_s2 && !time_rd_s3; |
always @(posedge rtc_clk_in) begin |
time_rd_d1 <= time_rd; |
time_rd_d2 <= time_rd_d1; |
time_rd_d3 <= time_rd_d2; |
time_rd_s1 <= time_rd; |
time_rd_s2 <= time_rd_s1; |
time_rd_s3 <= time_rd_s2; |
end |
|
always @(posedge rtc_clk_in) begin |
if (time_reg_in_latch) begin |
if (time_rd_ack) begin |
time_reg_ns_int <= time_reg_ns_in; |
time_reg_sec_int <= time_reg_sec_in; |
end |
end |
|
reg time_rd_d1; |
wire time_rd_req = time_rd && !time_rd_d1; |
always @(posedge clk) begin |
time_rd_d1 <= time_rd; |
end |
|
always @(posedge clk or posedge time_rd_ack) begin |
if (time_rd_ack) |
time_ok <= 1'b1; |
else if (time_rd_req) |
time_ok <= 1'b0; |
end |
|
// rx time stamp queue |
assign rx_q_rd_clk_out = clk; |
|
/trunk/sim/top/ptp_drv_bfm/ptp_drv_bfm.c
22,18 → 22,18
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x4; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// RESET RTC |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// RESET RTC |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x10; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// LOAD RTC SEC AND NS |
cpu_addr_i = 0x00000010; |
cpu_data_i = 0x0; |
48,10 → 48,10
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x8; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_data_i = 0x8; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// LOAD RTC ADJ |
cpu_addr_i = 0x00000030; |
64,18 → 64,35
cpu_data_i = 0x20; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x2; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// READ RTC SEC AND NS |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
// READ RTC SEC AND NS |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x1; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_rd(cpu_addr_i, &cpu_data_o); |
cpu_addr_i = 0X00000040; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
cpu_addr_i = 0X00000044; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
cpu_addr_i = 0X00000048; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
cpu_addr_i = 0X0000004C; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
// READ RTC SEC AND NS |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x0; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_addr_i = 0x00000000; |
cpu_data_i = 0x1; |
cpu_wr(cpu_addr_i, cpu_data_i); |
cpu_rd(cpu_addr_i, &cpu_data_o); |
cpu_addr_i = 0X00000040; |
cpu_rd(cpu_addr_i, &cpu_data_o); |
cpu_addr_i = 0X00000044; |
/trunk/sim/top/wave.do
1,50 → 1,52
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/up_clk |
add wave -noupdate -format Logic /ha1588_tb/up_wr |
add wave -noupdate -format Logic /ha1588_tb/up_rd |
add wave -noupdate -format Literal /ha1588_tb/up_addr |
add wave -noupdate -format Literal /ha1588_tb/up_data_wr |
add wave -noupdate -format Literal /ha1588_tb/up_data_rd |
add wave -noupdate -format Logic /ha1588_tb/rtc_clk |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/addr_in |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/wr_in |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/rd_in |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/data_in |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/cs_00 |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/reg_00 |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/data_out_reg |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/period_ld_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/rtc_rst_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_ld_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/adj_ld_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_reg_in_latch |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/time_reg_ns |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rtc/time_acc_48s_inc |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/time_reg_sec |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rtc/adj_ld |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/adj_cnt |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/time_adj |
add wave -noupdate -divider {New Divider} |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {1452000 ps} 0} |
configure wave -namecolwidth 291 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {0 ps} {10500 ns} |
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/up_clk |
add wave -noupdate -format Logic /ha1588_tb/up_wr |
add wave -noupdate -format Logic /ha1588_tb/up_rd |
add wave -noupdate -format Literal /ha1588_tb/up_addr |
add wave -noupdate -format Literal /ha1588_tb/up_data_wr |
add wave -noupdate -format Literal /ha1588_tb/up_data_rd |
add wave -noupdate -format Logic /ha1588_tb/rtc_clk |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/addr_in |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/wr_in |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/rd_in |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/data_in |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/cs_00 |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/reg_00 |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rgs/data_out_reg |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/period_ld_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/rtc_rst_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_ld_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/adj_ld_out |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_rd_req |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_rd_ack |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rgs/time_ok |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/time_reg_ns |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rtc/time_acc_48s_inc |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/time_reg_sec |
add wave -noupdate -divider {New Divider} |
add wave -noupdate -format Logic /ha1588_tb/PTP_HA_DUT/u_rtc/adj_ld |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/adj_cnt |
add wave -noupdate -format Literal /ha1588_tb/PTP_HA_DUT/u_rtc/time_adj |
add wave -noupdate -divider {New Divider} |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {1082162 ps} 0} |
configure wave -namecolwidth 333 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {0 ps} {10500 ns} |