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    /ha1588
    from Rev 32 to Rev 33
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Rev 32 → Rev 33

/trunk/rtl/reg/reg.v
59,6 → 59,10
parameter const_54 = 8'h54;
parameter const_58 = 8'h58;
parameter const_5c = 8'h5C;
parameter const_60 = 8'h60;
parameter const_64 = 8'h64;
parameter const_68 = 8'h68;
parameter const_6c = 8'h6C;
 
wire cs_00 = (addr_in[7:2]==const_00[7:2])? 1'b1: 1'b0;
wire cs_04 = (addr_in[7:2]==const_04[7:2])? 1'b1: 1'b0;
84,9 → 88,13
wire cs_54 = (addr_in[7:2]==const_54[7:2])? 1'b1: 1'b0;
wire cs_58 = (addr_in[7:2]==const_58[7:2])? 1'b1: 1'b0;
wire cs_5c = (addr_in[7:2]==const_5c[7:2])? 1'b1: 1'b0;
wire cs_60 = (addr_in[7:2]==const_60[7:2])? 1'b1: 1'b0;
wire cs_64 = (addr_in[7:2]==const_64[7:2])? 1'b1: 1'b0;
wire cs_68 = (addr_in[7:2]==const_68[7:2])? 1'b1: 1'b0;
wire cs_6c = (addr_in[7:2]==const_6c[7:2])? 1'b1: 1'b0;
 
reg [31:0] reg_00; // ctrl 12 bit
reg [31:0] reg_04; // qsta 16 bit
reg [31:0] reg_00; // ctrl 5 bit
reg [31:0] reg_04; //
reg [31:0] reg_08; //
reg [31:0] reg_0c; //
reg [31:0] reg_10; // tout 16 s
105,10 → 113,14
reg [31:0] reg_44; // tmin 32 s
reg [31:0] reg_48; // tmin 30 ns
reg [31:0] reg_4c; // tmin 8 nsf
reg [31:0] reg_50; // rxqu 24 bit
reg [31:0] reg_54; // rxqu 32 bit
reg [31:0] reg_58; // txqu 24 bit
reg [31:0] reg_5c; // txqu 32 bit
reg [31:0] reg_50; // ctrl 4 bit
reg [31:0] reg_54; // qsta 8 bit
reg [31:0] reg_58; // qsta 8 bit
reg [31:0] reg_5c; //
reg [31:0] reg_60; // rxqu 32 bit
reg [31:0] reg_64; // rxqu 32 bit
reg [31:0] reg_68; // txqu 32 bit
reg [31:0] reg_6c; // txqu 32 bit
 
// write registers
always @(posedge clk) begin
136,6 → 148,10
if (wr_in && cs_54) reg_54 <= data_in;
if (wr_in && cs_58) reg_58 <= data_in;
if (wr_in && cs_5c) reg_5c <= data_in;
if (wr_in && cs_60) reg_60 <= data_in;
if (wr_in && cs_64) reg_64 <= data_in;
if (wr_in && cs_68) reg_68 <= data_in;
if (wr_in && cs_6c) reg_6c <= data_in;
end
 
// read registers
151,9 → 167,9
 
reg [31:0] data_out_reg;
always @(posedge clk) begin
if (rd_in && cs_00) data_out_reg <= {reg_00[31:12], reg_00[11], rxqu_ok, reg_00[9], txqu_ok, reg_00[ 7: 1], time_ok};
if (rd_in && cs_04) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
if (rd_in && cs_08) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
if (rd_in && cs_00) data_out_reg <= {reg_00[31:1 ], time_ok};
if (rd_in && cs_04) data_out_reg <= reg_04;
if (rd_in && cs_08) data_out_reg <= reg_08;
if (rd_in && cs_0c) data_out_reg <= reg_0c;
if (rd_in && cs_10) data_out_reg <= reg_10;
if (rd_in && cs_14) data_out_reg <= reg_14;
171,18 → 187,18
if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0];
if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
if (rd_in && cs_50) data_out_reg <= rx_q_data_int[63:32];
if (rd_in && cs_54) data_out_reg <= rx_q_data_int[31: 0];
if (rd_in && cs_58) data_out_reg <= tx_q_data_int[63:32];
if (rd_in && cs_5c) data_out_reg <= tx_q_data_int[31: 0];
if (rd_in && cs_50) data_out_reg <= {reg_50[31: 4], reg_50[ 3], rxqu_ok, reg_50[ 1], txqu_ok};
if (rd_in && cs_54) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
if (rd_in && cs_58) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
if (rd_in && cs_5c) data_out_reg <= reg_5c;
if (rd_in && cs_60) data_out_reg <= rx_q_data_int[63:32];
if (rd_in && cs_64) data_out_reg <= rx_q_data_int[31: 0];
if (rd_in && cs_68) data_out_reg <= tx_q_data_int[63:32];
if (rd_in && cs_6c) data_out_reg <= tx_q_data_int[31: 0];
end
assign data_out = data_out_reg;
 
// register mapping
wire rxq_rst = reg_00[11];
wire rxqu_rd = reg_00[10];
wire txq_rst = reg_00[ 9];
wire txqu_rd = reg_00[ 8];
// register mapping: RTC
//wire = reg_00[ 7];
//wire = reg_00[ 6];
//wire = reg_00[ 5];
197,6 → 213,15
assign time_acc_modulo_out[37:0] = {reg_28[29: 0], reg_2c[ 7: 0]};
assign adj_ld_data_out [31:0] = reg_30[31: 0];
assign period_adj_out [39:0] = {reg_38[ 7: 0], reg_3c[31: 0]};
// register mapping: TSU
//wire = reg_50[ 7];
//wire = reg_50[ 6];
//wire = reg_50[ 5];
//wire = reg_50[ 4];
wire rxq_rst = reg_50[ 3];
wire rxqu_rd = reg_50[ 2];
wire txq_rst = reg_50[ 1];
wire txqu_rd = reg_50[ 0];
 
// real time clock
reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
/trunk/sim/top/ptp_drv_bfm/ptp_drv_bfm.c
2,6 → 2,55
 
#include "svdpi.h"
#include "../dpiheader.h"
 
// define RTC address values
#define RTC_CTRL 0x00000000
#define RTC_NULL_0x4 0x00000004
#define RTC_NULL_0x8 0x00000008
#define RTC_NULL_0xC 0x0000000C
#define RTC_TIME_SEC_H_LOAD 0x00000010
#define RTC_TIME_SEC_L_LOAD 0x00000014
#define RTC_TIME_NSC_H_LOAD 0x00000018
#define RTC_TIME_NSC_L_LOAD 0x0000001C
#define RTC_PERIOD_H_LOAD 0x00000020
#define RTC_PERIOD_L_LOAD 0x00000024
#define RTC_ACCMOD_H_LOAD 0x00000028
#define RTC_ACCMOD_L_LOAD 0x0000002C
#define RTC_ADJNUM_LOAD 0x00000030
#define RTC_NULL_0x34 0x00000034
#define RTC_ADJPER_H_LOAD 0x00000038
#define RTC_ADJPER_L_LOAD 0x0000003C
#define RTC_TIME_SEC_H_READ 0x00000040
#define RTC_TIME_SEC_L_READ 0x00000044
#define RTC_TIME_NSC_H_READ 0x00000048
#define RTC_TIME_NSC_L_READ 0x0000004C
// define RTC data values
#define RTC_SET_CTRL_0 0x0
#define RTC_GET_TIME 0x1
#define RTC_SET_ADJ 0x2
#define RTC_SET_PERIOD 0x4
#define RTC_SET_TIME 0x8
#define RTC_SET_RESET 0x10
#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit
#define RTC_ACCMOD_L 0x0 // 256 for 8bit
#define RTC_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk
#define RTC_PERIOD_L 0x0
 
// define TSU address values
#define TSU_CTRL 0x00000050
#define TSU_RXQUE_STATUS 0x00000054
#define TSU_TXQUE_STATUS 0x00000058
#define TSU_NULL_0x5C 0x0000005C
#define TSU_RXQUE_DATA_H 0x00000060
#define TSU_RXQUE_DATA_L 0x00000064
#define TSU_TXQUE_DATA_H 0x00000068
#define TSU_TXQUE_DATA_L 0x0000006C
// define TSU data values
#define TSU_SET_CTRL_0 0x0
#define TSU_GET_TXQUE 0x1
#define TSU_GET_RXQUE 0x4
#define TSU_SET_RESET 0xA
 
int ptp_drv_bfm_c(double fw_delay)
{
unsigned int cpu_addr_i;
9,172 → 58,180
unsigned int cpu_data_o;
 
// LOAD RTC PERIOD AND ACC_MODULO
cpu_addr_i = 0x00000020;
cpu_data_i = 0x8;
cpu_addr_i = RTC_PERIOD_H_LOAD;
cpu_data_i = RTC_PERIOD_H;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000024;
cpu_data_i = 0x0;
cpu_addr_i = RTC_PERIOD_L_LOAD;
cpu_data_i = RTC_PERIOD_L;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000028;
cpu_data_i = 0x3B9ACA00;
cpu_addr_i = RTC_ACCMOD_H_LOAD;
cpu_data_i = RTC_ACCMOD_H;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x0000002C;
cpu_data_i = 0x0;
cpu_addr_i = RTC_ACCMOD_L_LOAD;
cpu_data_i = RTC_ACCMOD_L;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x0;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x4;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_PERIOD;
cpu_wr(cpu_addr_i, cpu_data_i);
// RESET RTC
cpu_addr_i = 0x00000000;
cpu_data_i = 0x0;
// RESET RTC AND TSU
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0xA10;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_RESET;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_RESET;
cpu_wr(cpu_addr_i, cpu_data_i);
// READ RTC SEC AND NS
cpu_addr_i = 0x00000000;
cpu_data_i = 0x0;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x1;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
do {
cpu_addr_i = 0x00000000;
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & 0x1) == 0x0);
cpu_addr_i = 0X00000040;
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
cpu_addr_i = 0X00000044;
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
cpu_addr_i = 0X00000048;
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
cpu_addr_i = 0X0000004C;
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
// LOAD RTC SEC AND NS
cpu_addr_i = 0x00000010;
cpu_addr_i = RTC_TIME_SEC_H_LOAD;
cpu_data_i = 0x0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000014;
cpu_addr_i = RTC_TIME_SEC_L_LOAD;
cpu_data_i = 0x1;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000018;
cpu_data_i = 0x3B9AC9F6;
cpu_addr_i = RTC_TIME_NSC_H_LOAD;
cpu_data_i = RTC_ACCMOD_H - 0xA;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x0000001C;
cpu_addr_i = RTC_TIME_NSC_L_LOAD;
cpu_data_i = 0x0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x0;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x8;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
// LOAD RTC ADJ
cpu_addr_i = 0x00000030;
cpu_addr_i = RTC_ADJNUM_LOAD;
cpu_data_i = 0x100;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000038;
cpu_addr_i = RTC_ADJPER_H_LOAD;
cpu_data_i = 0x1;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x0000003C;
cpu_addr_i = RTC_ADJPER_L_LOAD;
cpu_data_i = 0x20;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x0;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x2;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_ADJ;
cpu_wr(cpu_addr_i, cpu_data_i);
// READ RTC SEC AND NS
cpu_addr_i = 0x00000000;
cpu_data_i = 0x0;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x1;
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
do {
cpu_addr_i = 0x00000000;
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & 0x1) == 0x0);
cpu_addr_i = 0X00000040;
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
cpu_addr_i = 0X00000044;
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
cpu_addr_i = 0X00000048;
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
cpu_addr_i = 0X0000004C;
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
int i;
int rx_queue_num;
int tx_queue_num;
while (1) {
// POLL TSU RX STATUS
int rx_queue_num;
do {
cpu_addr_i = 0x00000004;
cpu_rd(cpu_addr_i, &cpu_data_o);
rx_queue_num = cpu_data_o;
//printf("%08x\n", rx_queue_num);
} while (!(rx_queue_num > 0x2));
// READ TSU RX FIFO
for (i=rx_queue_num; i>0; i--) {
cpu_addr_i = 0x00000000;
cpu_data_i = 0x0;
cpu_addr_i = TSU_RXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
rx_queue_num = cpu_data_o;
//printf("%08x\n", rx_queue_num);
if (rx_queue_num > 0x0) {
// READ TSU RX FIFO
for (i=rx_queue_num; i>0; i--) {
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x400;
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_RXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
do {
cpu_addr_i = 0x00000000;
cpu_addr_i = TSU_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & 0x400) == 0x0);
cpu_addr_i = 0x00000050;
} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
cpu_addr_i = TSU_RXQUE_DATA_H;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\nRx stamp: \n%08x\n", cpu_data_o);
cpu_addr_i = 0x00000054;
cpu_addr_i = TSU_RXQUE_DATA_L;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
}
}
// POLL TSU TX STATUS
int tx_queue_num;
do {
cpu_addr_i = 0x00000008;
cpu_rd(cpu_addr_i, &cpu_data_o);
tx_queue_num = cpu_data_o;
//printf("%08x\n", tx_queue_num);
} while (!(tx_queue_num > 0x2));
// READ TSU TX FIFO
for (i=tx_queue_num; i>0; i--) {
cpu_addr_i = 0x00000000;
cpu_data_i = 0x0;
cpu_addr_i = TSU_TXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
tx_queue_num = cpu_data_o;
//printf("%08x\n", tx_queue_num);
if (tx_queue_num > 0x0) {
// READ TSU TX FIFO
for (i=tx_queue_num; i>0; i--) {
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = 0x00000000;
cpu_data_i = 0x100;
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_TXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
do {
cpu_addr_i = 0x00000000;
cpu_addr_i = TSU_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & 0x100) == 0x0);
cpu_addr_i = 0x00000058;
} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
cpu_addr_i = TSU_TXQUE_DATA_H;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\nTx stamp: \n%08x\n", cpu_data_o);
cpu_addr_i = 0x0000005C;
cpu_addr_i = TSU_TXQUE_DATA_L;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
}
}
}
 
// READ BACK ALL REGISTERS
for (;;)
/trunk/sim/top/nic_drv_bfm/ptpdv2_rx.pcap Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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