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URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

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  • This comparison shows the changes necessary to convert path 
    /ha1588
    from Rev 36 to Rev 37
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  •

Rev 36 → Rev 37

/trunk/rtl/top/ha1588.v
1,7 → 1,7
/*
* $ha1588.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
54,12 → 54,12
 
wire rx_q_rst, rx_q_clk;
wire rx_q_rd_en;
wire [ 7:0] rx_q_stat;
wire [63:0] rx_q_data;
wire [ 7:0] rx_q_stat;
wire [127:0] rx_q_data;
wire tx_q_rst, tx_q_clk;
wire tx_q_rd_en;
wire [ 7:0] tx_q_stat;
wire [63:0] tx_q_data;
wire [ 7:0] tx_q_stat;
wire [127:0] tx_q_data;
 
rgs u_rgs
(
/trunk/rtl/top/ha1588_hw.tcl
6,7 → 6,7
# +-----------------------------------
# |
# | ha1588 "Hardware Assisted IEEE 1588 IP Core" v1.0
# | BBY&HW 2012.03.31.21:26:56
# | BABY&HW 2012.03.31.21:26:56
# | Hardware Assisted IEEE 1588 IP Core
# |
# | ha1588.v
35,7 → 35,7
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR "BBY&HW"
set_module_property AUTHOR "BABY&HW"
set_module_property DISPLAY_NAME "Hardware Assisted IEEE 1588 IP Core"
set_module_property TOP_LEVEL_HDL_FILE ha1588.v
set_module_property TOP_LEVEL_HDL_MODULE ha1588
/trunk/rtl/rtc/rtc.v
1,7 → 1,7
/*
* $rtc.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/trunk/rtl/tsu/tsu.v
1,7 → 1,7
/*
* $tsu.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
34,8 → 34,8
input q_rst,
input q_rd_clk,
input q_rd_en,
output [ 7:0] q_rd_stat,
output [63:0] q_rd_data // seqId_16bit + msgId_4bit + null_8bit + timeStamp1s_4bit + timeStamp1ns_32bit
output [ 7:0] q_rd_stat,
output [127:0] q_rd_data // null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit
);
 
// buffer gmii input
81,13 → 81,13
ts_req_d3 <= ts_req_d2;
end
end
reg [35:0] rtc_time_stamp;
reg [79:0] rtc_time_stamp;
always @(posedge rst or posedge rtc_timer_clk) begin
if (rst)
rtc_time_stamp <= 36'd0;
rtc_time_stamp <= 80'd0;
else
if (ts_req_d2 & !ts_req_d3)
rtc_time_stamp <= rtc_timer_in[35:0]; // 16.000,000,000 sec
rtc_time_stamp <= rtc_timer_in;
end
reg ts_ack, ts_ack_clr;
always @(posedge ts_ack_clr or posedge rtc_timer_clk) begin
111,10 → 111,10
ts_ack_d3 <= ts_ack_d2;
end
end
reg [35:0] gmii_time_stamp;
reg [79:0] gmii_time_stamp;
always @(posedge rst or posedge gmii_clk) begin
if (rst) begin
gmii_time_stamp <= 36'd0;
gmii_time_stamp <= 80'd0;
ts_ack_clr <= 1'b0;
end
else begin
207,7 → 207,7
// ptp packet parser here
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint
wire ptp_found;
wire [19:0] ptp_infor;
wire [31:0] ptp_infor;
ptp_parser parser(
.clk(gmii_clk),
.rst(rst),
223,7 → 223,7
// ptp time stamp dcfifo
wire q_wr_clk = gmii_clk;
wire q_wr_en = ptp_found && int_eop_d1;
wire [63:0] q_wr_data = {ptp_infor, 8'd0, gmii_time_stamp}; // 20+8+36 bit
wire [127:0] q_wr_data = {16'd0, gmii_time_stamp, ptp_infor}; // 16+80+32 bit
wire [3:0] q_wrusedw;
wire [3:0] q_rdusedw;
 
231,12 → 231,12
.aclr(q_rst),
 
.wrclk(q_wr_clk),
.wrreq(q_wr_en && q_wrusedw<=15), // write with overflow protection
.wrreq(q_wr_en && q_wrusedw<15), // write with overflow protection
.data(q_wr_data),
.wrusedw(q_wrusedw),
 
.rdclk(q_rd_clk),
.rdreq(q_rd_en && q_rdusedw>= 1), // read with underflow protection
.rdreq(q_rd_en && q_rdusedw>0 ), // read with underflow protection
.q(q_rd_data),
.rdusedw(q_rdusedw)
);
/trunk/rtl/tsu/ptp_parser.v
1,7 → 1,7
/*
* $ptp_parser.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
30,7 → 30,7
input [ 1:0] int_mod,
 
output reg ptp_found,
output reg [19:0] ptp_infor
output reg [31:0] ptp_infor
);
 
reg [31:0] int_data_d1;
48,8 → 48,6
// packet parser: counter
reg [ 9:0] int_cnt, bypass_ipv4_cnt, bypass_ipv6_cnt, bypass_udp_cnt, ptp_cnt;
reg bypass_vlan, ptp_l2, bypass_mpls, bypass_ipv4, bypass_ipv6, found_udp, bypass_udp, ptp_l4, ptp_event;
reg [ 3:0] ptp_msgid;
reg [15:0] ptp_seqid;
always @(posedge rst or posedge clk) begin
if (rst) begin
int_cnt <= 10'd0;
168,10 → 166,10
 
// check if it is PTP Event message
if (int_valid && (int_cnt==10'd3 || bypass_vlan && int_cnt==10'd4) && int_data[31:16]==16'h88F7 &&
(int_data[11: 8]== 4'h0 || int_data[11:8]==4'h2)) // ptp_message_id == sync || delay_req
(int_data[11: 8]>= 4'h0 && int_data[11:8]<=4'h7)) // ptp_message_id == ptp_event
ptp_event <= 1'b1;
else if (int_valid && int_cnt==10'd4 && bypass_udp_cnt==10'd1 && ptp_l4 &&
(int_data[11: 8]== 4'h0 || int_data[11:8]==4'h2)) // ptp_message_id == sync || delay_req
(int_data[11: 8]>= 4'h0 && int_data[11:8]<=4'h7)) // ptp_message_id == ptp_event
ptp_event <= 1'b1;
end
end
178,16 → 176,21
 
// ptp message
reg [31:0] ptp_data;
reg [ 3:0] ptp_msgid;
reg [15:0] ptp_seqid;
reg [11:0] ptp_cksum;
always @(posedge rst or posedge clk) begin
if (rst) begin
ptp_data <= 32'd0;
ptp_msgid <= 4'd0;
ptp_seqid <= 16'd0;
ptp_cksum <= 12'd0;
end
else if (int_valid && int_sop) begin
ptp_data <= 32'd0;
ptp_msgid <= 4'd0;
ptp_seqid <= 16'd0;
ptp_cksum <= 12'd0;
end
else begin
// get PTP identification information as additional information to Timestamp
196,10 → 199,17
ptp_data <= {int_data_d1[15:0], int_data[31:16]};
// message id
if (int_valid && ptp_cnt==10'd1)
ptp_msgid <= ptp_data[27:24];
ptp_msgid <= ptp_data[27:24];
// sequence id
if (int_valid && ptp_cnt==10'd8)
ptp_seqid <= ptp_data[15:0];
ptp_seqid <= ptp_data[15:0];
// sum up clock id and source port id
if (int_valid && ptp_cnt==10'd6)
ptp_cksum <= ptp_data[31:24] + ptp_data[23:16] + ptp_data[15: 8] + ptp_data[ 7: 0] + ptp_cksum;
if (int_valid && ptp_cnt==10'd7)
ptp_cksum <= ptp_data[31:24] + ptp_data[23:16] + ptp_data[15: 8] + ptp_data[ 7: 0] + ptp_cksum;
if (int_valid && ptp_cnt==10'd8)
ptp_cksum <= ptp_data[31:24] + ptp_data[23:16] + ptp_cksum;
end
end
 
207,15 → 217,15
always @(posedge rst or posedge clk) begin
if (rst) begin
ptp_found <= 1'b0;
ptp_infor <= 20'd0;
ptp_infor <= 32'd0;
end
else if (int_valid && int_sop) begin
ptp_found <= 1'b0;
ptp_infor <= 20'd0;
ptp_infor <= 32'd0;
end
else if (int_valid && ptp_cnt==10'd9) begin
ptp_found <= ptp_event;
ptp_infor <= {ptp_msgid, ptp_seqid}; // 4+16
ptp_infor <= {ptp_msgid, ptp_cksum, ptp_seqid}; // 4+12+16
end
end
 
/trunk/rtl/tsu/ptp_queue.v
48,12 → 48,12
wrusedw);
 
input aclr;
input [63:0] data;
input [127:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output [127:0] q;
output [3:0] rdusedw;
output [3:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
64,10 → 64,10
// synopsys translate_on
`endif
 
wire [63:0] sub_wire0;
wire [127:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] sub_wire2;
wire [63:0] q = sub_wire0[63:0];
wire [127:0] q = sub_wire0[127:0];
wire [3:0] wrusedw = sub_wire1[3:0];
wire [3:0] rdusedw = sub_wire2[3:0];
 
90,7 → 90,7
dcfifo_component.lpm_numwords = 16,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 64,
dcfifo_component.lpm_width = 128,
dcfifo_component.lpm_widthu = 4,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
124,11 → 124,11
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: Width NUMERIC "128"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "64"
// Retrieval info: PRIVATE: output_width NUMERIC "128"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
142,7 → 142,7
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
151,8 → 151,8
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]"
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL "rdusedw[3..0]"
160,12 → 160,12
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.v TRUE
/trunk/rtl/reg/reg.v
1,7 → 1,7
/*
* $reg.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
43,17 → 43,17
input [37:0] time_reg_ns_in,
input [47:0] time_reg_sec_in,
// rx tsu interface
output rx_q_rst_out,
output rx_q_rd_clk_out,
output rx_q_rd_en_out,
input [ 7:0] rx_q_stat_in,
input [63:0] rx_q_data_in,
output rx_q_rst_out,
output rx_q_rd_clk_out,
output rx_q_rd_en_out,
input [ 7:0] rx_q_stat_in,
input [127:0] rx_q_data_in,
// tx tsu interface
output tx_q_rst_out,
output tx_q_rd_clk_out,
output tx_q_rd_en_out,
input [ 7:0] tx_q_stat_in,
input [63:0] tx_q_data_in
output tx_q_rst_out,
output tx_q_rd_clk_out,
output tx_q_rd_en_out,
input [ 7:0] tx_q_stat_in,
input [127:0] tx_q_data_in
);
 
parameter const_00 = 8'h00;
84,6 → 84,10
parameter const_64 = 8'h64;
parameter const_68 = 8'h68;
parameter const_6c = 8'h6C;
parameter const_70 = 8'h70;
parameter const_74 = 8'h74;
parameter const_78 = 8'h78;
parameter const_7c = 8'h7C;
 
wire cs_00 = (addr_in[7:2]==const_00[7:2])? 1'b1: 1'b0;
wire cs_04 = (addr_in[7:2]==const_04[7:2])? 1'b1: 1'b0;
113,6 → 117,10
wire cs_64 = (addr_in[7:2]==const_64[7:2])? 1'b1: 1'b0;
wire cs_68 = (addr_in[7:2]==const_68[7:2])? 1'b1: 1'b0;
wire cs_6c = (addr_in[7:2]==const_6c[7:2])? 1'b1: 1'b0;
wire cs_70 = (addr_in[7:2]==const_70[7:2])? 1'b1: 1'b0;
wire cs_74 = (addr_in[7:2]==const_74[7:2])? 1'b1: 1'b0;
wire cs_78 = (addr_in[7:2]==const_78[7:2])? 1'b1: 1'b0;
wire cs_7c = (addr_in[7:2]==const_7c[7:2])? 1'b1: 1'b0;
 
reg [31:0] reg_00; // ctrl 5 bit
reg [31:0] reg_04; //
140,8 → 148,12
reg [31:0] reg_5c; //
reg [31:0] reg_60; // rxqu 32 bit
reg [31:0] reg_64; // rxqu 32 bit
reg [31:0] reg_68; // txqu 32 bit
reg [31:0] reg_6c; // txqu 32 bit
reg [31:0] reg_68; // rxqu 32 bit
reg [31:0] reg_6c; // rxqu 32 bit
reg [31:0] reg_70; // txqu 32 bit
reg [31:0] reg_74; // txqu 32 bit
reg [31:0] reg_78; // txqu 32 bit
reg [31:0] reg_7c; // txqu 32 bit
 
// write registers
always @(posedge clk) begin
173,15 → 185,19
if (wr_in && cs_64) reg_64 <= data_in;
if (wr_in && cs_68) reg_68 <= data_in;
if (wr_in && cs_6c) reg_6c <= data_in;
if (wr_in && cs_70) reg_70 <= data_in;
if (wr_in && cs_74) reg_74 <= data_in;
if (wr_in && cs_78) reg_78 <= data_in;
if (wr_in && cs_7c) reg_7c <= data_in;
end
 
// read registers
reg [37:0] time_reg_ns_int;
reg [47:0] time_reg_sec_int;
reg [63:0] rx_q_data_int;
reg [ 7:0] rx_q_stat_int;
reg [63:0] tx_q_data_int;
reg [ 7:0] tx_q_stat_int;
reg [127:0] rx_q_data_int;
reg [ 7:0] rx_q_stat_int;
reg [127:0] tx_q_data_int;
reg [ 7:0] tx_q_stat_int;
reg time_ok;
reg rxqu_ok;
reg txqu_ok;
188,7 → 204,8
 
reg [31:0] data_out_reg;
always @(posedge clk) begin
if (rd_in && cs_00) data_out_reg <= {reg_00[31:1 ], time_ok};
// register mapping: RTC
if (rd_in && cs_00) data_out_reg <= {reg_00[31:1 ], time_ok}; // TODO: add adjt_ok read back
if (rd_in && cs_04) data_out_reg <= reg_04;
if (rd_in && cs_08) data_out_reg <= reg_08;
if (rd_in && cs_0c) data_out_reg <= reg_0c;
204,18 → 221,23
if (rd_in && cs_34) data_out_reg <= reg_34;
if (rd_in && cs_38) data_out_reg <= reg_38;
if (rd_in && cs_3c) data_out_reg <= reg_3c;
if (rd_in && cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0];
if (rd_in && cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]}; // TODO: merge with reg_10 read back
if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0] ;
if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]};
if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]};
// register mapping: TSU // TODO: base address move to reg_40
if (rd_in && cs_50) data_out_reg <= {reg_50[31: 4], reg_50[ 3], rxqu_ok, reg_50[ 1], txqu_ok};
if (rd_in && cs_54) data_out_reg <= {24'd0, rx_q_stat_int[ 7: 0]};
if (rd_in && cs_58) data_out_reg <= {24'd0, tx_q_stat_int[ 7: 0]};
if (rd_in && cs_5c) data_out_reg <= reg_5c;
if (rd_in && cs_60) data_out_reg <= rx_q_data_int[63:32];
if (rd_in && cs_64) data_out_reg <= rx_q_data_int[31: 0];
if (rd_in && cs_68) data_out_reg <= tx_q_data_int[63:32];
if (rd_in && cs_6c) data_out_reg <= tx_q_data_int[31: 0];
if (rd_in && cs_60) data_out_reg <= rx_q_data_int[127: 96];
if (rd_in && cs_64) data_out_reg <= rx_q_data_int[ 95: 64];
if (rd_in && cs_68) data_out_reg <= rx_q_data_int[ 63: 32];
if (rd_in && cs_6c) data_out_reg <= rx_q_data_int[ 31: 0];
if (rd_in && cs_70) data_out_reg <= tx_q_data_int[127: 96];
if (rd_in && cs_74) data_out_reg <= tx_q_data_int[ 95: 64];
if (rd_in && cs_78) data_out_reg <= tx_q_data_int[ 63: 32];
if (rd_in && cs_7c) data_out_reg <= tx_q_data_int[ 31: 0];
end
assign data_out = data_out_reg;
 
231,9 → 253,10
assign time_reg_sec_out [47:0] = {reg_10[15: 0], reg_14[31: 0]};
assign time_reg_ns_out [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]};
assign period_out [39:0] = {reg_20[ 7: 0], reg_24[31: 0]};
assign time_acc_modulo_out[37:0] = {reg_28[29: 0], reg_2c[ 7: 0]};
assign time_acc_modulo_out[37:0] = {reg_28[29: 0], reg_2c[ 7: 0]}; // TODO: remove writable, set as constant parameter
assign adj_ld_data_out [31:0] = reg_30[31: 0];
assign period_adj_out [39:0] = {reg_38[ 7: 0], reg_3c[31: 0]};
 
// register mapping: TSU
//wire = reg_50[ 7];
//wire = reg_50[ 6];
243,6 → 266,7
wire rxqu_rd = reg_50[ 2];
wire txq_rst = reg_50[ 1];
wire txqu_rd = reg_50[ 0];
// TODO: add configurable VLANTPID values
 
// real time clock
reg rtc_rst_s1, rtc_rst_s2, rtc_rst_s3;
/trunk/sim/top/ptp_drv_bfm/ptp_drv_bfm.c
1,7 → 1,7
/*
* $ptp_drv_bfm.c
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
54,23 → 54,28
#define RTC_SET_RESET 0x10
#define RTC_ACCMOD_H 0x3B9ACA00 // 1,000,000,000 for 30bit
#define RTC_ACCMOD_L 0x0 // 256 for 8bit
#define RTC_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk
#define RTC_PERIOD_H 0x8 // 8ns for 125MHz rtc_clk
#define RTC_PERIOD_L 0x0
 
// define TSU address values
#define TSU_CTRL 0x00000050
#define TSU_RXQUE_STATUS 0x00000054
#define TSU_TXQUE_STATUS 0x00000058
#define TSU_NULL_0x5C 0x0000005C
#define TSU_RXQUE_DATA_H 0x00000060
#define TSU_RXQUE_DATA_L 0x00000064
#define TSU_TXQUE_DATA_H 0x00000068
#define TSU_TXQUE_DATA_L 0x0000006C
#define TSU_CTRL 0x00000050
#define TSU_RXQUE_STATUS 0x00000054
#define TSU_TXQUE_STATUS 0x00000058
#define TSU_NULL_0x5C 0x0000005C
#define TSU_RXQUE_DATA_HH 0x00000060
#define TSU_RXQUE_DATA_HL 0x00000064
#define TSU_RXQUE_DATA_LH 0x00000068
#define TSU_RXQUE_DATA_LL 0x0000006C
#define TSU_TXQUE_DATA_HH 0x00000070
#define TSU_TXQUE_DATA_HL 0x00000074
#define TSU_TXQUE_DATA_LH 0x00000078
#define TSU_TXQUE_DATA_LL 0x0000007C
// define TSU data values
#define TSU_SET_CTRL_0 0x0
#define TSU_GET_TXQUE 0x1
#define TSU_GET_RXQUE 0x4
#define TSU_SET_RESET 0xA
#define TSU_SET_RXRST 0x8
#define TSU_SET_TXRST 0x2
 
int ptp_drv_bfm_c(double fw_delay)
{
82,114 → 87,140
cpu_addr_i = RTC_PERIOD_H_LOAD;
cpu_data_i = RTC_PERIOD_H;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_PERIOD_L_LOAD;
cpu_data_i = RTC_PERIOD_L;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_ACCMOD_H_LOAD;
cpu_data_i = RTC_ACCMOD_H;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_ACCMOD_L_LOAD;
cpu_data_i = RTC_ACCMOD_L;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_PERIOD;
cpu_wr(cpu_addr_i, cpu_data_i);
// RESET RTC AND TSU
 
// RESET RTC
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_RESET;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_RESET;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// READ RTC SEC AND NS
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
// LOAD RTC SEC AND NS
cpu_addr_i = RTC_TIME_SEC_H_LOAD;
cpu_data_i = 0x0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_TIME_SEC_L_LOAD;
cpu_data_i = 0x1;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_TIME_NSC_H_LOAD;
cpu_data_i = RTC_ACCMOD_H - 0xA;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_TIME_NSC_L_LOAD;
cpu_data_i = 0x0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// LOAD RTC ADJ
cpu_addr_i = RTC_ADJNUM_LOAD;
cpu_data_i = 0x100;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_ADJPER_H_LOAD;
cpu_data_i = 0x1;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_ADJPER_L_LOAD;
cpu_data_i = 0x20;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_ADJ;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// READ RTC SEC AND NS
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
197,68 → 228,171
int i;
int rx_queue_num;
int tx_queue_num;
 
// RESET TSU
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_RXRST + TSU_SET_TXRST;
cpu_wr(cpu_addr_i, cpu_data_i);
 
// READ TSU
while (1) {
// POLL TSU RX STATUS
cpu_addr_i = TSU_RXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
rx_queue_num = cpu_data_o;
//printf("%08x\n", rx_queue_num);
if (rx_queue_num > 0x0) {
// READ TSU RX FIFO
for (i=rx_queue_num; i>0; i--) {
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_RXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
do {
 
// POLL TSU RX STATUS
cpu_addr_i = TSU_RXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
rx_queue_num = cpu_data_o;
//printf("%08x\n", rx_queue_num);
 
if (rx_queue_num > 0x0) {
for (i=rx_queue_num; i>0; i--) {
 
// READ TSU RX FIFO
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_RXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = TSU_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
 
cpu_addr_i = TSU_RXQUE_DATA_HH;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & TSU_GET_RXQUE) == 0x0);
cpu_addr_i = TSU_RXQUE_DATA_H;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\nRx stamp: \n%08x\n", cpu_data_o);
cpu_addr_i = TSU_RXQUE_DATA_L;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
printf("\nRx stamp: \n%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_RXQUE_DATA_HL;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_RXQUE_DATA_LH;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_RXQUE_DATA_LL;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
// READ RTC SEC AND NS
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
}
}
}
// POLL TSU TX STATUS
cpu_addr_i = TSU_TXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
tx_queue_num = cpu_data_o;
//printf("%08x\n", tx_queue_num);
if (tx_queue_num > 0x0) {
// READ TSU TX FIFO
for (i=tx_queue_num; i>0; i--) {
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_TXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
do {
 
// POLL TSU TX STATUS
cpu_addr_i = TSU_TXQUE_STATUS;
cpu_rd(cpu_addr_i, &cpu_data_o);
tx_queue_num = cpu_data_o;
//printf("%08x\n", tx_queue_num);
 
if (tx_queue_num > 0x0) {
for (i=tx_queue_num; i>0; i--) {
 
// READ TSU TX FIFO
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = TSU_CTRL;
cpu_data_i = TSU_GET_TXQUE;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = TSU_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
 
cpu_addr_i = TSU_TXQUE_DATA_HH;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & TSU_GET_TXQUE) == 0x0);
cpu_addr_i = TSU_TXQUE_DATA_H;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\nTx stamp: \n%08x\n", cpu_data_o);
cpu_addr_i = TSU_TXQUE_DATA_L;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
printf("\nTx stamp: \n%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_TXQUE_DATA_HL;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_TXQUE_DATA_LH;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = TSU_TXQUE_DATA_LL;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
// READ RTC SEC AND NS
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_SET_CTRL_0;
cpu_wr(cpu_addr_i, cpu_data_i);
 
cpu_addr_i = RTC_CTRL;
cpu_data_i = RTC_GET_TIME;
cpu_wr(cpu_addr_i, cpu_data_i);
 
do {
cpu_addr_i = RTC_CTRL;
cpu_rd(cpu_addr_i, &cpu_data_o);
//printf("%08x\n", (cpu_data_o & 0x1));
} while ((cpu_data_o & RTC_GET_TIME) == 0x0);
 
cpu_addr_i = RTC_TIME_SEC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("\ntime: \n%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_SEC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_H_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
 
cpu_addr_i = RTC_TIME_NSC_L_READ;
cpu_rd(cpu_addr_i, &cpu_data_o);
printf("%08x\n", cpu_data_o);
}
}
}
}
 
// READ BACK ALL REGISTERS
for (;;)
{
int t;
for (t=0; t<=0x5c; t=t+4)
for (t=0; t<=0xff; t=t+4)
{
cpu_hd(10);
 
/trunk/sim/top/ptp_drv_bfm/ptp_drv_bfm.v
1,7 → 1,7
/*
* $ptp_drv_bfm.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/trunk/sim/top/wave.do
76,4 → 76,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {18099011 ps} {18680581 ps}
WaveRestoreZoom {0 ps} {52500 ns}
/trunk/sim/top/ha1588_tb.v
1,7 → 1,7
/*
* $ha1588_tb.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/trunk/sim/top/nic_drv_bfm/gmii_rx_bfm.v
1,7 → 1,7
/*
* $gmii_rx_bfm.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
35,7 → 35,7
end
assign #2 gmii_rxclk = gmii_rxclk_offset;
 
integer feeder_file_rx, r_rx;
integer feeder_file_rx, r_rx, s_rx;
integer start_addr_rx, end_addr_rx;
integer index_rx, num_rx;
reg eof_rx;
59,9 → 59,9
// test pcap file endian
r_rx = $fread(pcap_4bytes_rx, feeder_file_rx);
pcap_endian_rx = (pcap_4bytes_rx == 32'ha1b2c3d4)? 1:0;
$fseek(feeder_file_rx, -4, 1);
s_rx = $fseek(feeder_file_rx, -4, 1);
// skip pcap file header 24*8
$fseek(feeder_file_rx, 24, 1);
s_rx = $fseek(feeder_file_rx, 24, 1);
// read packet content
eof_rx = 0;
num_rx = 0;
69,7 → 69,7
begin : fileread_loop
// skip frame header (8+4)*8
start_addr_rx = $ftell(feeder_file_rx);
$fseek(feeder_file_rx, 8+4, 1);
s_rx = $fseek(feeder_file_rx, 8+4, 1);
// get frame length big endian 4*8
r_rx = $fread(packet_leng_rx, feeder_file_rx);
packet_leng_rx = pcap_endian_rx?
/trunk/sim/top/nic_drv_bfm/gmii_tx_bfm.v
1,7 → 1,7
/*
* $gmii_tx_bfm.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
35,7 → 35,7
end
assign #2 gmii_txclk = gmii_txclk_offset;
 
integer feeder_file_tx, r_tx;
integer feeder_file_tx, r_tx, s_tx;
integer start_addr_tx, end_addr_tx;
integer index_tx, num_tx;
reg eof_tx;
59,9 → 59,9
// test pcap file endian
r_tx = $fread(pcap_4bytes_tx, feeder_file_tx);
pcap_endian_tx = (pcap_4bytes_tx == 32'ha1b2c3d4)? 1:0;
$fseek(feeder_file_tx, -4, 1);
s_tx = $fseek(feeder_file_tx, -4, 1);
// skip pcap file header 24*8
$fseek(feeder_file_tx, 24, 1);
s_tx = $fseek(feeder_file_tx, 24, 1);
// read packet content
eof_tx = 0;
num_tx = 0;
69,7 → 69,7
begin : fileread_loop
// skip frame header (8+4)*8
start_addr_tx = $ftell(feeder_file_tx);
$fseek(feeder_file_tx, 8+4, 1);
s_tx = $fseek(feeder_file_tx, 8+4, 1);
// get frame length big endian 4*8
r_tx = $fread(packet_leng_tx, feeder_file_tx);
packet_leng_tx = pcap_endian_tx?
/trunk/sim/rtc/rtc_timer_tb.v
1,7 → 1,7
/*
* $rtc_timer_tb.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/trunk/sim/tsu/wave.do
45,6 → 45,7
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_msgid
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_seqid
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_cksum
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/parser/ptp_found
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/parser/ptp_infor
51,13 → 52,16
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/q_wr_clk
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/q_wr_en
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/q_wr_data
add wave -noupdate -format Literal /tsu_queue_tb/DUT_RX/q_wrusedw
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/q_wrusedw
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/queue/rdclk
add wave -noupdate -format Logic /tsu_queue_tb/DUT_RX/queue/rdreq
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/DUT_RX/queue/rdusedw
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/BFM_RX/num_rx
add wave -noupdate -format Literal -radix unsigned /tsu_queue_tb/rx_ptp_event_cnt
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {535600 ps} 0}
WaveRestoreCursors {{Cursor 1} {39134000 ps} 0}
configure wave -namecolwidth 188
configure wave -valuecolwidth 165
configure wave -justifyvalue left
72,4 → 76,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {389986800 ps}
WaveRestoreZoom {0 ps} {27824653 ps}
/trunk/sim/tsu/gmii_rx_bfm.v
1,7 → 1,7
/*
* $gmii_rx_bfm.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/trunk/sim/tsu/ptpdv2_rx.txt
1,53 → 1,173
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/trunk/sim/tsu/gmii_tx_bfm.v
1,7 → 1,7
/*
* $gmii_tx_bfm.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/trunk/sim/tsu/ptpdv2_tx.txt
1,21 → 1,35
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67
69
/trunk/sim/tsu/tsu_queue_tb.v
1,7 → 1,7
/*
* $tsu_queue_tb.v
*
* Copyright (c) 2012, BBY&HW. All rights reserved.
* Copyright (c) 2012, BABY&HW. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
32,10 → 32,10
wire [ 7:0] gmii_txdata;
reg rtc_timer_clk;
reg [79:0] rtc_timer_in;
reg q_rd_clk;
reg q_rd_en;
wire [ 7:0] q_rd_stat;
wire [63:0] q_rd_data;
reg q_rd_clk;
reg q_rd_en;
wire [ 7:0] q_rd_stat;
wire [127:0] q_rd_data;
 
initial begin
// emulate the hardware behavior when power-up
/trunk/sim/tsu/ReadMe.txt
1,7 → 1,7
This folder contains testbench for TSU module.
 
The PCAP files are read by the BFM to generate stimulus to the GMII interface.
The PCAP files can be filtered by "ptp.v2.messageid == 0x00 || ptp.v2.messageid == 0x02" and exported to TXT files as golden references.
The PCAP files can be filtered by "ptp.v2.messageid >= 0x00 && ptp.v2.messageid <= 0x07" and exported to TXT files as golden references.
 
The TX and RX TSU outputs are monitored and compared to the respective golden reference for the parser validation.
Any mismatch will be reported as Warning in the transcript.

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