URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/ha1588
- from Rev 66 to Rev 67
- ↔ Reverse comparison
Rev 66 → Rev 67
/trunk/rtl/bus/qsys/ha1588_hw.tcl
93,64 → 93,64
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point avalon_slave |
# | connection point reg_interface |
# | |
add_interface avalon_slave avalon end |
set_interface_property avalon_slave addressAlignment DYNAMIC |
set_interface_property avalon_slave addressUnits WORDS |
set_interface_property avalon_slave associatedClock clock |
set_interface_property avalon_slave burstOnBurstBoundariesOnly false |
set_interface_property avalon_slave explicitAddressSpan 0 |
set_interface_property avalon_slave holdTime 0 |
set_interface_property avalon_slave isMemoryDevice false |
set_interface_property avalon_slave isNonVolatileStorage false |
set_interface_property avalon_slave linewrapBursts false |
set_interface_property avalon_slave maximumPendingReadTransactions 0 |
set_interface_property avalon_slave printableDevice false |
set_interface_property avalon_slave readLatency 0 |
set_interface_property avalon_slave readWaitTime 1 |
set_interface_property avalon_slave setupTime 0 |
set_interface_property avalon_slave timingUnits Cycles |
set_interface_property avalon_slave writeWaitTime 0 |
add_interface reg_interface avalon end |
set_interface_property reg_interface addressAlignment DYNAMIC |
set_interface_property reg_interface addressUnits WORDS |
set_interface_property reg_interface associatedClock clock |
set_interface_property reg_interface burstOnBurstBoundariesOnly false |
set_interface_property reg_interface explicitAddressSpan 0 |
set_interface_property reg_interface holdTime 0 |
set_interface_property reg_interface isMemoryDevice false |
set_interface_property reg_interface isNonVolatileStorage false |
set_interface_property reg_interface linewrapBursts false |
set_interface_property reg_interface maximumPendingReadTransactions 0 |
set_interface_property reg_interface printableDevice false |
set_interface_property reg_interface readLatency 0 |
set_interface_property reg_interface readWaitTime 1 |
set_interface_property reg_interface setupTime 0 |
set_interface_property reg_interface timingUnits Cycles |
set_interface_property reg_interface writeWaitTime 0 |
|
set_interface_property avalon_slave ENABLED true |
set_interface_property reg_interface ENABLED true |
|
add_interface_port avalon_slave wr_in write Input 1 |
add_interface_port avalon_slave rd_in read Input 1 |
add_interface_port avalon_slave addr_in address Input 8 |
add_interface_port avalon_slave data_in writedata Input 32 |
add_interface_port avalon_slave data_out readdata Output 32 |
add_interface_port reg_interface wr_in write Input 1 |
add_interface_port reg_interface rd_in read Input 1 |
add_interface_port reg_interface addr_in address Input 8 |
add_interface_port reg_interface data_in writedata Input 32 |
add_interface_port reg_interface data_out readdata Output 32 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point ref_clock |
# | connection point rtc_interface |
# | |
add_interface ref_clock conduit end |
add_interface rtc_interface conduit end |
|
set_interface_property ref_clock ENABLED true |
set_interface_property rtc_interface ENABLED true |
|
add_interface_port ref_clock rtc_clk export Input 1 |
add_interface_port ref_clock rtc_time_ptp_ns export Output 32 |
add_interface_port ref_clock rtc_time_ptp_sec export Output 48 |
add_interface_port ref_clock rtc_time_one_pps export Output 1 |
add_interface_port rtc_interface rtc_clk export Input 1 |
add_interface_port rtc_interface rtc_time_ptp_ns export Output 32 |
add_interface_port rtc_interface rtc_time_ptp_sec export Output 48 |
add_interface_port rtc_interface rtc_time_one_pps export Output 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point gmii_monitor |
# | connection point tsu_interface |
# | |
add_interface gmii_monitor conduit end |
add_interface tsu_interface conduit end |
|
set_interface_property gmii_monitor ENABLED true |
set_interface_property tsu_interface ENABLED true |
|
add_interface_port gmii_monitor rx_gmii_clk export Input 1 |
add_interface_port gmii_monitor rx_gmii_ctrl export Input 1 |
add_interface_port gmii_monitor rx_gmii_data export Input 8 |
add_interface_port gmii_monitor rx_giga_mode export Input 1 |
add_interface_port gmii_monitor tx_gmii_clk export Input 1 |
add_interface_port gmii_monitor tx_gmii_ctrl export Input 1 |
add_interface_port gmii_monitor tx_gmii_data export Input 8 |
add_interface_port gmii_monitor tx_giga_mode export Input 1 |
add_interface_port tsu_interface rx_gmii_clk export Input 1 |
add_interface_port tsu_interface rx_gmii_ctrl export Input 1 |
add_interface_port tsu_interface rx_gmii_data export Input 8 |
add_interface_port tsu_interface rx_giga_mode export Input 1 |
add_interface_port tsu_interface tx_gmii_clk export Input 1 |
add_interface_port tsu_interface tx_gmii_ctrl export Input 1 |
add_interface_port tsu_interface tx_gmii_data export Input 8 |
add_interface_port tsu_interface tx_giga_mode export Input 1 |
# | |
# +----------------------------------- |
/trunk/rtl/bus/wishbone/wb_slv_wrapper.v
30,7 → 30,7
input [31:0] dat_i, |
output [31:0] dat_o, |
// localbus side |
output rst,clk |
output rst,clk, |
output wr_out,rd_out, |
output [ 7:0] addr_out, // in byte |
output [31:0] data_out, |
/trunk/rtl/bus/wishbone/ha1588_wb.v
0,0 → 1,98
/* |
* ha1588_wb.v |
* |
* Copyright (c) 2012, BABY&HW. All rights reserved. |
* |
* This library is free software; you can redistribute it and/or |
* modify it under the terms of the GNU Lesser General Public |
* License as published by the Free Software Foundation; either |
* version 2.1 of the License, or (at your option) any later version. |
* |
* This library is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
* Lesser General Public License for more details. |
* |
* You should have received a copy of the GNU Lesser General Public |
* License along with this library; if not, write to the Free Software |
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
* MA 02110-1301 USA |
*/ |
|
`timescale 1ns/1ns |
|
module ha1588_wb ( |
// reg_interface |
input rst_i,clk_i, |
input stb_i,we_i, |
output ack_o, |
input [31:0] adr_i, // in byte |
input [31:0] dat_i, |
output [31:0] dat_o, |
// rtc_interface |
input rtc_clk, |
output [31:0] rtc_time_ptp_ns, |
output [47:0] rtc_time_ptp_sec, |
output rtc_time_one_pps, |
// tsu_interface |
input rx_gmii_clk, |
input rx_gmii_ctrl, |
input [7:0] rx_gmii_data, |
input rx_giga_mode, |
input tx_gmii_clk, |
input tx_gmii_ctrl, |
input [7:0] tx_gmii_data, |
input tx_giga_mode |
); |
|
wire rst, up_clk; |
wire up_wr, up_rd; |
wire [ 7:0] up_addr; |
wire [31:0] up_data_wr, up_data_rd; |
|
wb_slv_wrapper wb_slv( |
// wishbone side |
.rst_i(rst_i), |
.clk_i(clk_i), |
.stb_i(stb_i), |
.we_i(we_i), |
.ack_o(ack_o), |
.adr_i(adr_i), // in byte |
.dat_i(dat_i), |
.dat_o(dat_o), |
// localbus side |
.rst(rst), |
.clk(up_clk), |
.wr_out(up_wr), |
.rd_out(up_rd), |
.addr_out(up_addr), // in byte |
.data_out(up_data_wr), |
.data_in(up_data_rd) |
); |
|
ha1588 ha1588_inst ( |
.rst(rst), |
.clk(up_clk), |
.wr_in(up_wr), |
.rd_in(up_rd), |
.addr_in(up_addr), |
.data_in(up_data_wr), |
.data_out(up_data_rd), |
|
.rtc_clk(rtc_clk), |
.rtc_time_ptp_ns(rtc_time_ptp_ns), |
.rtc_time_ptp_sec(rtc_time_ptp_sec), |
.rtc_time_one_pps(rtc_time_one_pps), |
|
.rx_gmii_clk(rx_gmii_clk), |
.rx_gmii_ctrl(rx_gmii_ctrl), |
.rx_gmii_data(rx_gmii_data), |
.rx_giga_mode(giga_mode), |
.tx_gmii_clk(tx_gmii_clk), |
.tx_gmii_ctrl(tx_gmii_ctrl), |
.tx_gmii_data(tx_gmii_data), |
.tx_giga_mode(giga_mode) |
); |
|
endmodule |
|