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  • This comparison shows the changes necessary to convert path 
    /hamming/branches/avendor/ham_7_4_dec
    from Rev 12 to Rev 15
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  •

Rev 12 → Rev 15

/bench/ham_7_4_dec_tb.v
0,0 → 1,83
module stimulus(
clk,
reset,
datain,
dvin,
code,
dvout);
 
 
input dvout;
input code;
 
output clk, reset, dvin;
reg clk, reset, dvin;
 
output datain;
reg datain;
 
initial
begin
reset = 0;
#200
reset = 1;
end
 
initial clk = 1;
 
always
begin
#20
clk = !clk;
end
 
initial
begin
datain = 0;
#300
datain = 0;
#40
datain = 1;
#40
datain = 0;
#40
datain = 0;
#40
datain = 0;
#40
datain = 0;
#40
datain = 0;
#40
datain = 0;
#40
datain = 0;
 
 
 
 
end
 
initial
begin
dvin = 1;
#300
dvin = 0;
#280
dvin = 1;
end
 
initial #10000 $finish;
 
ham_7_4_dec ham_7_4_dec_0(
 
.clk(clk),
.reset(reset),
.datain(datain),
.dvin(dvin),
.code(code),
.dvout(dvout));
 
 
endmodule
 
/bench/timescale.v
0,0 → 1,83
`timescale 1ns / 100ps
/rtl/verilog/ham_7_4_dec.v
0,0 → 1,200
///
module ham_7_4_dec(
 
clk,
reset,
datain,
dvin,
dvout,
code);
 
input clk, reset, datain, dvin;
output dvout;
reg dvout;
output code;
reg code;
 
 
 
reg [6:0]
datareg;
reg [6:0]
outdatareg;
 
 
reg [2:0]
cntr,
ocntr,
scntr;
 
reg [2:0]
s_;
 
reg ocntr_en;
 
wire
and2,
and1,
and0,
xor2,
xor1,
xor0,
err;
 
assign and2 = datareg[0] & cntr[2];
assign and1 = datareg[0] & cntr[1];
assign and0 = datareg[0] & cntr[0];
 
assign xor2 = and2 ^ s_[2];
assign xor1 = and1 ^ s_[1];
assign xor0 = and0 ^ s_[0];
 
assign err = (!scntr[2])&(!scntr[1])&scntr[0];
 
/////////////////////////////////////////////////
 
 
always@(posedge clk or negedge reset)
 
if (!reset)
 
s_<=0;
 
else if (cntr==0)
 
s_<=0;
 
else if ( (!dvin)||(cntr==7) )
 
s_<={xor2,xor1,xor0};
 
/////////////////////////////////////////////////
always@(posedge clk or negedge reset)
 
if (!reset)
 
scntr<=0;
 
else if (cntr==7)
 
scntr<={xor2, xor1, xor0};
 
else if (scntr!=0)
 
scntr<=scntr-1;
 
/////////////////////////////////////////////////
 
always@(posedge clk or negedge reset)
 
if (!reset)
 
cntr<=0;
 
else if (cntr==7)
 
cntr<=0;
 
else if (!dvin)
 
cntr<=cntr+1;
 
/////////////////////////////////////////////////
 
always@(posedge clk or negedge reset)
 
if(!reset)
 
datareg<=0;
 
else if (!dvin)
 
datareg<={datareg[5:0], datain};
 
 
/////////////////////////////////////////////////
always@(posedge clk or negedge reset)
 
if (!reset)
 
ocntr<=0;
 
else if (ocntr_en)
 
ocntr<=ocntr+1;
 
 
/////////////////////////////////////////////////
always@(posedge clk or negedge reset)
 
if (!reset)
 
ocntr_en<=0;
 
else if (cntr==7)
 
ocntr_en<=1;
 
else if ( (ocntr==7)&&(cntr!=7) )
 
ocntr_en<=0;
 
/////////////////////////////////////////////////
 
always@(posedge clk or negedge reset)
 
if (!reset)
 
dvout<=1;
 
else if (ocntr==7)
 
dvout<=1;
 
else if (ocntr_en)
 
dvout<=0;
 
 
/////////////////////////////////////////////////
always@(posedge clk or negedge reset)
 
if (!reset)
 
outdatareg<=0;
 
else if (cntr==7)
 
outdatareg<=datareg;
 
else if (ocntr_en)
 
outdatareg<={outdatareg[5:0],1'b0};
 
/////////////////////////////////////////////////
always@(posedge clk or negedge reset)
 
if (!reset)
 
code<=0;
 
else
 
code<=outdatareg[6]^err;
 
/////////////////////////////////////////////////
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 

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