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    /hdlc/trunk/CODE/RX
    from Rev 9 to Rev 17
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Rev 9 → Rev 17

/CORE/RxChannel.vhd
0,0 → 1,132
-------------------------------------------------------------------------------
-- Title : Rx Channel
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : RxChannel.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update: 2001/04/27
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description: receive Channel
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 30 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : RXEN bug fixed
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 27 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : FrameAvailable port added to Zero_detect
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
LIBRARY hdlc;
use hdlc.hdlc_components_pkg.all;
 
entity RxChannel_ent is
 
port (
Rxclk : in std_logic; -- Rx Clock
rst : in std_logic; -- system reset
Rx : in std_logic; -- RX input serial data
RxData : out std_logic_vector(7 downto 0); -- Rx backedn Data bus
ValidFrame : out std_logic; -- Valid Frame
FrameError : out std_logic; -- Frame Error (Indicates error in the
-- next byte at the backend
AbortSignal : out std_logic; -- Abort signal
Readbyte : in std_logic; -- backend read byte
rdy : out std_logic; -- backend ready signal
RxEn : in std_logic); -- Rx Enable (Flow control)
 
end RxChannel_ent;
 
architecture RxChannel_beh of RxChannel_ent is
 
signal RxD_i : std_logic; -- RXD internal signal
signal enable_i : std_logic; -- Internal enable signal
signal aval_i : std_logic; -- Available internal signal
signal FlagDetect_i : std_logic; -- flag Detect internal
signal Abort_i : std_logic; -- Internal Abort signal
signal initzero_i : std_logic; -- Init Zero detect block
signal rxen_i : std_logic; -- RXenable internal
 
-- New
signal ValidFrame_i : std_logic; -- Internal Valid Frame
begin -- RxChannel_beh
 
-------------------------------------------------------------------------------
ValidFrame <= ValidFrame_i;
 
Controller : rxcont_ent
port map (
RxClk => RxClk,
rst => rst,
RxEn => RxEn_i,
AbortedFrame => AbortSignal,
Abort => Abort_i,
FlagDetect => FlagDetect_i,
ValidFrame => ValidFrame_i, --New
FrameError => FrameError,
aval => aval_i,
initzero => initzero_i,
enable => enable_i);
-------------------------------------------------------------------------------
zero_backend : ZeroDetect_ent
port map (
ValidFrame => ValidFrame_i, --New
Readbyte => Readbyte,
aval => aval_i,
enable => enable_i,
StartofFrame => initzero_i,
rdy => rdy,
rst => rst,
RxClk => RxClk,
RxD => RxD_i,
RxData => RxData);
-------------------------------------------------------------------------------
flag_detect : FlagDetect_ent
port map (
Rxclk => Rxclk,
rst => rst,
FlagDetect => FlagDetect_i,
Abort => Abort_i,
RXEN => RXEN,
RxEN_o => RXEN_i,
RXD => RXD_i,
RX => RX);
-------------------------------------------------------------------------------
 
 
end RxChannel_beh;
/CORE/Zero_detect.vhd
0,0 → 1,220
-------------------------------------------------------------------------------
-- Title : Zero Detection
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : zero_detect.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/28
-- Last update: 2001/04/27
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: FPGA express 3
-- Target :
-- Dependency : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description: Zero Detection
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 28 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- ToOptimize : Needs large external buffer (1 byte internal buffer)
-- for low speed backend interface
-- (flow control is used to manage this problem)
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Enable bug fixed
-- ToOptimize : Needs large external buffer (1 byte internal buffer)
-- for low speed backend interface
-- (flow control is used to manage this problem)
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 27 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Available and enable bugs fixed
-- ToOptimize :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity ZeroDetect_ent is
 
port (
ValidFrame : in std_logic; -- Valid Frame strobe
Readbyte : in std_logic; -- Back end read byte
aval : out std_logic; -- can get more data (connected to flow
-- controller
enable : in std_logic; -- enable (Driven by flow controller)
 
rdy : out std_logic; -- data ready
rst : in std_logic; -- system reset
StartofFrame : in std_logic; -- start of Frame
RxClk : in std_logic; -- RX clock
RxD : in std_logic; -- RX data
RxData : out std_logic_vector(7 downto 0)); -- Receive Data bus
 
end ZeroDetect_ent;
 
architecture ZeroDetect_beh of ZeroDetect_ent is
signal DataRegister : std_logic_vector(7 downto 0);
-- Data register
signal flag : std_logic; -- 8 Bits data ready
 
begin -- ZeroDetect_beh
 
-- purpose: Detect zero
-- type : sequential
-- inputs : RxClk, rst
-- outputs:
detect_proc : process (RxClk, rst)
 
variable ZeroDetected : std_logic; -- Zero Detected
variable tempRegister : std_logic_vector(7 downto 0); -- Data Register
variable counter : integer range 0 to 7; -- Counter
 
variable checkreg : std_logic_vector(5 downto 0); -- Check register
 
begin -- process detect
if rst = '0' then -- asynchronous reset (active low)
 
counter := 0;
tempRegister := (others => '0');
 
DataRegister <= (others => '0');
 
flag <= '0';
ZeroDetected := '0';
 
checkreg := (others => '0');
 
elsif RxClk'event and RxClk = '1' then -- rising clock edge
if enable = '1' then -- No overflow on the backend
 
-- add new bit to the register
-- tempRegister(counter) := RxD;
 
if StartofFrame = '0' then
 
-- add new bit to the check register
checkreg := RxD & checkreg(5 downto 1);
tempRegister(counter) := RxD;
else
-- reset the check register
checkreg := (RxD, others => '0');
counter := 0;
tempRegister(counter) := RxD;
end if;
 
-- check if we got 5 ones
ZeroDetected := not checkreg(5) and checkreg(4) and checkreg(3) and checkreg(2) and checkreg(1) and checkreg(0);
 
 
if ZeroDetected = '1' then
 
flag <= '0';
 
else
 
if counter = 7 then
 
DataRegister <= tempRegister;
 
counter := 0;
 
flag <= '1';
 
 
else
 
counter := counter + 1;
 
flag <= '0';
 
end if;
 
end if;
 
end if;
 
end if;
end process detect_proc;
-------------------------------------------------------------------------------
-- purpose: Backend process
-- type : sequential
-- inputs : Rxclk, rst
-- outputs:
backend_proc : process (Rxclk, rst)
 
variable status : std_logic; -- Status
variable rdy_var : std_logic; -- temp variable for Rdy
 
begin -- process backend_proc
if rst = '0' then -- asynchronous reset (active low)
 
 
RxData <= (others => '0');
 
status := '0';
aval <= '1';
 
rdy_var := '0';
 
rdy <= '0';
 
elsif Rxclk'event and Rxclk = '1' then -- rising clock edge
if enable = '1' then
 
if flag = '1' then
 
status := '1'; -- Can not take more
 
RxData <= DataRegister;
rdy_var := '1';
 
end if; -- flag
 
end if; -- enable
if readbyte = '1' then
 
status := '0'; -- can take more data
 
rdy_var := '0';
 
end if; -- readbyte
 
rdy <= rdy_var;
 
if ValidFrame = '0' then
aval <= '1';
else
 
aval <= not status;
end if;
 
 
end if; -- clk
 
 
end process backend_proc;
 
-------------------------------------------------------------------------------
 
end ZeroDetect_beh;
/CORE/Rxcont.vhd
0,0 → 1,179
-------------------------------------------------------------------------------
-- Title : Rx Controller
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : Rxcont.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update: 2001/04/27
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description: receive Controller
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 30 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 27 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Enable and Available Bugs fixed
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity rxcont_ent is
 
port (
RxClk : in std_logic; -- Rx Clcok
rst : in std_logic; -- system Reset
RxEn : in std_logic; -- Rx Enable
AbortedFrame : out std_logic; -- Aborted frame
Abort : in std_logic; -- Abort detected
FlagDetect : in std_logic; -- Flag Detect
ValidFrame : out std_logic; -- Valid Frame
FrameError : out std_logic; -- Frame Error (Indicates error in the
-- next byte at the backend
aval : in std_logic; -- Can accept more data
initzero : out std_logic; -- init Zero detect block
enable : out std_logic); -- Enable
 
end rxcont_ent;
 
architecture rxcont_beh of rxcont_ent is
 
-- signal validFrame_i : std_logic; -- Internal Valid Frame signal
 
begin -- rxcont_beh
-- purpose: Enable controller
-- type : sequential
-- inputs : Rxclk, rst
-- outputs:
enable_proc : process (Rxclk, rst)
variable counter : integer range 0 to 7; -- Counter
variable FlagCounter : integer range 0 to 7; -- Flag bits counter
variable FrameStatus : std_logic; -- Frame Status
variable FlagInit : std_logic; -- Init flag counter
variable FrameStatusReg : std_logic_vector(7 downto 0);
-- Delay for Frame Status
begin -- process enable_proc
if rst = '0' then -- asynchronous reset (active low)
 
enable <= '0';
FrameStatus := '0';
ValidFrame <= '0';
AbortedFrame <= '0';
Counter := 0;
FlagInit := '0';
initzero <= '0';
FrameStatusReg := (others => '0');
FrameError <= '0';
FlagCounter := 0;
 
elsif Rxclk'event and Rxclk = '1' then -- rising clock edge
-------------------------------------------------------------------------------
-- This is the Valid frame machine
if FlagDetect = '1' then
FlagInit := '1';
FrameStatus := '0';
FlagCounter := 0;
AbortedFrame <= '0';
end if;
 
if FlagInit = '1' then
 
if FlagCounter = 7 then
FrameStatus := '1';
FlagCounter := 0;
initzero <= '1';
FlagInit := '0';
else
FlagCounter := FlagCounter + 1;
initzero <= '0';
end if;
else
initzero <= '0';
end if;
 
if Abort = '1' then
FrameStatus := '0';
AbortedFrame <= '1';
end if;
ValidFrame <= FrameStatusReg(0);
 
FrameStatusReg(7 downto 0) := FrameStatus & FrameStatusReg(7 downto 1);
 
 
 
 
 
 
-------------------------------------------------------------------------------
-- This is the enable machine
if RxEn = '1' then
 
if FrameStatus = '1' then
 
if aval = '1' then
 
enable <= '1';
Counter := 0;
FrameError <= '0';
else
 
if counter = 5 then
 
enable <= '0';
counter := 0;
FrameError <= '1';
 
else
 
enable <= '1';
 
Counter := Counter +1;
FrameError <= '0';
end if; -- counter
 
end if; -- aval
else
FrameError <= '0';
enable <= '0';
-- Counter := 0;
 
end if; -- validframe
else
FrameError <= '0';
enable <= '0';
-- Counter := 0;
 
end if; -- rxen
 
end if; -- clock
end process enable_proc;
 
-------------------------------------------------------------------------------
end rxcont_beh;
/CORE/flag_detect.vhd
0,0 → 1,117
-------------------------------------------------------------------------------
-- Title : HDLC flag detection
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : flag_detect.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/28
-- Last update: 2001/01/12
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description: Flag detection
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 28 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 10 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Code clean
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 3
-- Version : 0.3
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : RXEN bug fixed
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity FlagDetect_ent is
 
port (
Rxclk : in std_logic; -- Rx clock
rst : in std_logic; -- system reset
FlagDetect : out std_logic; -- Flag detected
Abort : out std_logic; -- Abort signal detected
RxEn : in std_logic; -- RX enable
RXEn_O : out std_logic; -- RXEN output signal
RXD : out std_logic; -- RXD output
RX : in std_logic); -- RX signal
 
end FlagDetect_ent;
 
architecture FlagDetect_beh of FlagDetect_ent is
 
signal ShiftReg : std_logic_vector(7 downto 0); -- Shift Register
 
begin -- FlagDetect_beh
 
-- purpose: Flag detection
-- type : sequential
-- inputs : RXclk, rst
-- outputs:
bitstreem_proc : process (RXclk, rst)
 
variable FlagVar : std_logic; -- Flag detected variable
variable Enable_Reg : std_logic_vector(7 downto 0); -- Enable Register
 
begin -- process bitstreem_proc
if rst = '0' then -- asynchronous reset (active low)
 
FlagDetect <= '0';
Abort <= '0';
 
RXD <= '0';
 
FlagVar := '0';
 
ShiftReg <= (others => '0');
 
RXEN_O <= '1';
Enable_Reg := (others => '1');
 
elsif RXclk'event and RXclk = '1' then -- rising clock edge
 
FlagVar := not ShiftReg(0) and ShiftReg(1) and ShiftReg(2) and ShiftReg(3) and ShiftReg(4) and ShiftReg(5) and ShiftReg(6) and not ShiftReg(7);
 
FlagDetect <= FlagVar;
 
Abort <= not ShiftReg(0) and ShiftReg(1) and ShiftReg(2) and ShiftReg(3) and ShiftReg(4) and ShiftReg(5) and ShiftReg(6) and ShiftReg(7);
 
 
ShiftReg(7 downto 0) <= RX & ShiftReg(7 downto 1);
RXD <= ShiftReg(0);
 
RXEN_O <= Enable_Reg(0);
 
Enable_Reg(7 downto 0) := RXEN & Enable_Reg(7 downto 1);
 
end if;
end process bitstreem_proc;
 
end FlagDetect_beh;
/TB/Rx_tb.vhd
0,0 → 1,148
-------------------------------------------------------------------------------
-- Title : Rx Channel test bench
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : Rx_tb.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/30
-- Last update: 2001/01/12
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description: receive Channel test bench
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 30 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- ToOptimize : Add an input procedure to insert data pattern
-- Bugs :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 12 Jan 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Rx Enable and delayed Read tests are added
-- ToOptimize : Add an input procedure to insert data pattern
-- Bugs :
-------------------------------------------------------------------------------
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use work.hdlc_components_pkg.all;
 
entity rx_tb_ent is
 
end rx_tb_ent;
 
architecture rx_tb_beh of rx_tb_ent is
constant DataStreem : std_logic_vector(88 downto 0) := "11111111011111100100110011011111010001010011111101111000111101001101001011011011001111110";
 
-- "1_11111110_11111100_10011001_10111110_10001010_01111110_11110001_11101001_10100101_10110110_01111110"
 
signal Rxclk_i : std_logic := '0'; -- system clock
signal rst_i : std_logic := '0'; -- system reset
signal Rx_i : std_logic; -- internal Rx serial data
 
signal RxData_i : std_logic_vector(7 downto 0); -- backend data bus
signal ValidFrame_i : std_logic; -- backedn Valid frame signal
signal AbortSignal_i : std_logic; -- backend abort signal
signal Readbyte_i : std_logic; -- backend read byte
signal rdy_i : std_logic; -- backend ready signal
signal RxEn_i : std_logic; -- receive enable
signal FrameError_i : std_logic; -- Frame Error
begin -- rx_tb_beh
-------------------------------------------------------------------------------
 
Rxclk_i <= not Rxclk_i after 20 ns;
 
rst_i <= '0',
'1' after 30 ns;
 
RxEn_i <= '1',
'0' after 960 ns,
'1' after 1280 ns;
-------------------------------------------------------------------------------
 
-- purpose: Serial interface stimulus
-- type : sequential
-- inputs :
-- outputs:
serial_proc : process
variable count : integer := 0; -- Counter
begin -- process backend_proc
 
 
wait until Rxclk_i = '0';
 
rx_i <= DataStreem(count);
 
if count = DataStreem'length-1 then
count := 0;
else
count := count +1;
end if;
 
end process serial_proc;
-------------------------------------------------------------------------------
-- purpose: Backend stimulus
-- type : combinational
-- inputs :
-- outputs:
backend_proc : process(rdy_i)
variable counter : integer := 0; -- Counter
begin -- process backend_proc
if rdy_i = '1' then
-- Counter is used to generate Readbyte signal at different delays
if not((counter > 20) and (counter < 40)) then
Readbyte_i <= '1' after 60 ns;
elsif(counter mod 2 = 0) then
-- data bits will be lost in this case
Readbyte_i <= '1' after 350 ns;
else
Readbyte_i <= '1' after 60 ns;
end if;
counter := counter+1;
else
Readbyte_i <= '0';
end if;
 
 
 
end process backend_proc;
 
-------------------------------------------------------------------------------
 
uut : RxChannel_ent
port map (
Rxclk => Rxclk_i,
rst => rst_i,
Rx => Rx_i,
RxData => RxData_i,
ValidFrame => ValidFrame_i,
FrameError => FrameError_i,
AbortSignal => AbortSignal_i,
Readbyte => Readbyte_i,
rdy => rdy_i,
RxEn => RxEn_i);
 
 
end rx_tb_beh;
/SCRIPTS/WAVE.DO
0,0 → 1,20
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /rx_tb_ent/rxclk_i
add wave -noupdate -format Logic /rx_tb_ent/rst_i
add wave -noupdate -format Logic /rx_tb_ent/rx_i
add wave -noupdate -format Logic /rx_tb_ent/uut/rxd_i
add wave -noupdate -format Literal /rx_tb_ent/rxdata_i
add wave -noupdate -format Logic /rx_tb_ent/readbyte_i
add wave -noupdate -format Logic /rx_tb_ent/rdy_i
add wave -noupdate -format Logic /rx_tb_ent/rxen_i
add wave -noupdate -format Logic /rx_tb_ent/uut/enable_i
add wave -noupdate -format Logic /rx_tb_ent/uut/aval_i
add wave -noupdate -format Logic /rx_tb_ent/uut/flagdetect_i
add wave -noupdate -format Logic /rx_tb_ent/validframe_i
add wave -noupdate -format Logic /rx_tb_ent/uut/initzero_i
add wave -noupdate -format Logic /rx_tb_ent/frameerror_i
add wave -noupdate -format Logic /rx_tb_ent/abortsignal_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {806902 ps}
WaveRestoreZoom {0 ps} {2940 ns}

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