OpenCores
URL https://opencores.org/ocsvn/hdlc/hdlc/trunk

Subversion Repositories hdlc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /hdlc/trunk/CODE/TOP/core
    from Rev 10 to Rev 17
    ↔ Reverse comparison
  •

Rev 10 → Rev 17

/RxFCS.vhd
0,0 → 1,202
-------------------------------------------------------------------------------
-- Title : Rx FCS
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : RxFCS.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created :2001/04/05
-- Last update: 2001/04/20
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98,NC-SIM/Linux
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164, ieee.std_logic_unsigned
-- hdlc.PCK_CRC16_D8
-------------------------------------------------------------------------------
-- Description: HDLC RX FCS-16 checking
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 5 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2001/04/20 18:29:01 jamil
-- Sencetivity list bug fixed
--
-- Revision 1.1 2001/04/14 15:02:25 jamil
-- Initial Release
--
-------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
LIBRARY hdlc;
USE hdlc.PCK_CRC16_D8.ALL;
 
 
ENTITY RxFCS_ent IS
GENERIC (
FCS_TYPE : INTEGER := 2); -- 2= FCS 16
-- 4= FCS 32
-- 0= disable FCS
PORT (
clk : IN STD_LOGIC; -- system clock
rst_n : IN STD_LOGIC; -- system reset
RxD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Data bus
ValidFrame : IN STD_LOGIC; -- Frame Strobe
rdy : IN STD_LOGIC; -- rdy to send byte
Readbyte : OUT STD_LOGIC; -- Read byte
DataBuff : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx output data
WrBuff : OUT STD_LOGIC; -- Write to buffer
EOF : OUT STD_LOGIC; -- End of Frame pulse
FCSen : IN STD_LOGIC; -- FCs enable
FCSerr : OUT STD_LOGIC); -- FCS error
 
END RxFCS_ent;
 
ARCHITECTURE RxFCS_rtl OF RxFCS_ent IS
 
TYPE STATES_typ IS (IDLE_st, RUN_st, READ_st, EOF_st); -- Internal states
SIGNAL p_state : STATES_typ; -- Present state
SIGNAL n_state : STATES_typ; -- Next state
 
SIGNAL FCS_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); -- FCS register
SIGNAL FCS_value : STD_LOGIC_VECTOR(15 DOWNTO 0); -- FCS value
 
SIGNAL WrBuff_i : STD_LOGIC; -- Internal WrBuff
SIGNAL EOF_i : STD_LOGIC; -- Internal EOF
 
BEGIN -- RxFCS_rtl
-- purpose: FSM
-- type : sequential
-- inputs : clk, rst_n
-- outputs:
fsm : PROCESS (clk, rst_n)
 
BEGIN -- PROCESS fsm
 
IF rst_n = '0' THEN -- asynchronous reset (active low)
p_state <= IDLE_st;
FCS_reg <= (OTHERS => '1');
WrBuff <= '0';
DataBuff <= (OTHERS => '1');
EOF <= '0';
ELSIF clk'event AND clk = '1' THEN -- rising clock edge
p_state <= n_state;
FCS_reg <= FCS_value;
DataBuff <= RxD;
WrBuff <= WrBuff_i;
EOF <= EOF_i;
END IF;
 
END PROCESS fsm;
 
 
-- purpose: fsm combination input/output logic
-- type : combinational
-- inputs : p_state,ValidFrame,rdy
-- outputs:
fsm_logic : PROCESS (p_state, ValidFrame, rdy, FCS_reg, FCSen,RxD)
 
BEGIN -- PROCESS fsm_logic
 
CASE p_state IS
 
WHEN IDLE_st =>
 
FCSerr <= '0';
WrBuff_i <= '0';
FCS_value <= (OTHERS => '1');
Readbyte <= '0';
EOF_i <= '0';
IF (ValidFrame = '1') THEN
n_state <= RUN_st;
ELSE
n_state <= IDLE_st;
END IF;
 
WHEN RUN_st =>
FCSerr <= '0';
WrBuff_i <= '0';
IF (ValidFrame = '1') THEN
 
FCS_value <= FCS_reg;
EOF_i <= '0';
 
IF (rdy = '1') THEN
n_state <= READ_st;
Readbyte <= '0';
ELSE
n_state <= RUN_st;
Readbyte <= '0';
END IF;
 
ELSE
n_state <= EOF_st;
Readbyte <= '0';
FCS_value <= FCS_reg;
EOF_i <= '1';
 
END IF;
 
WHEN EOF_st =>
 
n_state <= IDLE_st;
Readbyte <= '0';
WrBuff_i <= '0';
FCSerr <= FCSen AND
NOT (NOT FCS_reg(15) AND NOT FCS_reg(14)AND NOT FCS_reg(13) AND FCS_reg(12)
AND FCS_reg(11) AND FCS_reg(10) AND NOT FCS_reg(9) AND FCS_reg(8)
AND NOT FCS_reg(7) AND NOT FCS_reg(6) AND NOT FCS_reg(5) AND NOT FCS_reg(4)
AND FCS_reg(3) AND FCS_reg(2) AND FCS_reg(1) AND FCS_reg(0)
);
-- 0001 1101 0000 1111
 
FCS_value <= (OTHERS => '1');
EOF_i <= '0';
 
WHEN READ_st =>
 
FCSerr <= '0';
EOF_i <= '0';
 
IF (rdy = '1') THEN
 
n_state <= READ_st;
FCS_value <= FCS_reg;
WrBuff_i <= '0';
Readbyte <= '1';
 
ELSE -- Data valid
 
n_state <= RUN_st;
FCS_value <= nextCRC16_D8 ( RxD, FCS_reg ); --FCS_reg;
WrBuff_i <= '1';
Readbyte <= '0';
 
END IF;
 
WHEN OTHERS => NULL;
END CASE;
 
END PROCESS fsm_logic;
 
 
 
END RxFCS_rtl;
/RxSync.vhd
0,0 → 1,158
-------------------------------------------------------------------------------
-- Title : Rx Synchronizer
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : RxSync.vhd
-- Author : Jamil Khatib <khatib@ieee.org>
-- Organization: OpenCores Project
-- Created : 2001/04/04
-- Last update: 2001/04/04
-- Platform :
-- Simulators : Modelsim/Win98 , NC-sim/Linux
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic
-------------------------------------------------------------------------------
-- Description: Rx Synchronizer
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 2001/04/04
-- Modifier : Jamil Khatib <khatib@ieee.org>
-- Desccription : Created
-- ToOptimize :
-- Known Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2001/04/14 15:02:25 jamil
-- Initial Release
--
-------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY RxSynch_ent IS
-- D1 Domain 1 = Serial line
-- D2 Domain 2 = System interface
PORT (
rst_n : IN STD_LOGIC; -- System reset
clk_D1 : IN STD_LOGIC; -- Domain 1 clock
clk_D2 : IN STD_LOGIC; -- Domain 2 clock
rdy_D1 : IN STD_LOGIC; -- Domain 1 ready
rdy_D2 : OUT STD_LOGIC; -- Domain 2 ready
RXD_D1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Domain 1 Rx Data bus
RXD_D2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Domain 2 Rx Data Bus
ValidFrame_D1 : IN STD_LOGIC; -- Domain 1 Valid Frame
ValidFrame_D2 : OUT STD_LOGIC; -- Domain 2 Valid Frame
AbortSignal_D1 : IN STD_LOGIC; -- Domain 1 Abort signal
AbortSignal_D2 : OUT STD_LOGIC; -- Domain 2 Abort signal
FrameError_D1 : IN STD_LOGIC; -- Domain 1 Frame Error
FrameError_D2 : OUT STD_LOGIC; -- Domain 2 Frame Error
ReadByte_D1 : OUT STD_LOGIC; -- Domain 1 Read Byte
ReadByte_D2 : IN STD_LOGIC -- Domain 2 Read Byte
 
);
 
END RxSynch_ent;
-------------------------------------------------------------------------------
 
ARCHITECTURE RxSynch_rtl OF RxSynch_ent IS
 
BEGIN -- ARCHITECTURE RxSynch_rtl
 
-- Data bus does not need synchronization
RXD_D2 <= RXD_D1;
 
-- purpose: rdy signal
-- type : sequential
-- inputs : clk_D2, rst_n
-- outputs:
Rdy_signal : PROCESS (clk_D2, rst_n)
VARIABLE FF1 : STD_LOGIC;
BEGIN -- PROCESS Rdy_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
rdy_D2 <= '0';
ELSIF clk_D2'event AND clk_D2 = '1' THEN -- rising clock edge
rdy_D2 <= FF1;
FF1 := rdy_D1;
END IF;
 
END PROCESS Rdy_signal;
 
-- purpose: Read bytes signal
-- type : sequential
-- inputs : clk_D1, rst_n
-- outputs:
Read_signal : PROCESS (clk_D1, rst_n)
VARIABLE FF1 : STD_LOGIC;
BEGIN -- PROCESS Read_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
ReadByte_D1 <= '0';
ELSIF clk_D1'event AND clk_D1 = '1' THEN -- rising clock edge
ReadByte_D1 <= FF1;
FF1 := ReadByte_D2;
END IF;
END PROCESS Read_signal;
 
 
-- purpose: Valid Frame signal
-- type : sequential
-- inputs : clk_D2, rst_n
-- outputs:
ValidFrame_signal : PROCESS (clk_D2, rst_n)
VARIABLE FF1 : STD_LOGIC;
BEGIN -- PROCESS ValidFrame_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
ValidFrame_D2 <= '0';
ELSIF clk_D2'event AND clk_D2 = '1' THEN -- rising clock edge
ValidFrame_D2 <= FF1;
FF1 := ValidFrame_D1;
END IF;
END PROCESS ValidFrame_signal;
 
-- purpose: Abort signal
-- type : sequential
-- inputs : clk_D2, rst_n
-- outputs:
Abort_signal : PROCESS (clk_D2, rst_n)
VARIABLE FF1 : STD_LOGIC;
BEGIN -- PROCESS AbortedTrans_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
AbortSignal_D2 <= '0';
ELSIF clk_D2'event AND clk_D2 = '1' THEN -- rising clock edge
AbortSignal_D2 <= FF1;
FF1 := AbortSignal_D1;
END IF;
END PROCESS Abort_signal;
 
 
-- purpose: Error signal
-- type : sequential
-- inputs : clk_D2, rst_n
-- outputs:
Error_signal : PROCESS (clk_D2, rst_n)
VARIABLE FF1 : STD_LOGIC;
BEGIN -- PROCESS FrameError_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
FrameError_D2 <= '0';
ELSIF clk_D2'event AND clk_D2 = '1' THEN -- rising clock edge
FrameError_D2 <= FF1;
FF1 := FrameError_D1;
END IF;
END PROCESS Error_signal;
 
END RxSynch_rtl;
/WB_IF.vhd
0,0 → 1,502
-------------------------------------------------------------------------------
-- Title : WISHBONE bus interface
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : WB_IF.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created :2001/04/11
-- Last update:2001/04/18
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98,NC-SIM/Linux
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description: Wishbone bus interface
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 11 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2001/04/27 18:21:59 jamil
-- After Prelimenray simulation
--
-- Revision 1.2 2001/04/22 20:08:16 jamil
-- Top level simulation
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY WB_IF_ent IS
GENERIC (
ADD_WIDTH : integer := 7); -- Address width
 
PORT (
-- WB Bus ports
CLK_I : IN std_logic; -- System Clock
RST_I : IN std_logic; -- System Reset
ACK_O : OUT std_logic; -- acknowledge
ADR_I : IN std_logic_vector(2 DOWNTO 0); -- address
CYC_I : IN std_logic; -- Bus cycle
DAT_I : IN std_logic_vector(31 DOWNTO 0); -- Input data
DAT_O : OUT std_logic_vector(31 DOWNTO 0); -- Output data
RTY_O : OUT std_logic; -- retry
STB_I : IN std_logic; -- strobe
WE_I : IN std_logic; -- Write
TAG0_O : OUT std_logic; -- TAG0 (TxDone)
TAG1_O : OUT std_logic; -- TAG1_O (RxRdy)
 
-- Internal ports
-- Tx
TxEnable : OUT std_logic; -- TxEnable (Write Frame completed)
TxDone : IN std_logic; -- Transmission Done (Read Frame completed)
TxDataInBuff : OUT std_logic_vector(7 DOWNTO 0); -- Input Data
Txwr : OUT std_logic; -- Tx Write Buffer
TxAborted : IN std_logic; -- Aborted Frame
TxAbort : OUT std_logic; -- Abort Transmission
TxOverflow : IN std_logic; -- Tx Buffer Overflow
TxFCSen : OUT std_logic; -- FCS enable;
 
-- Rx
RxFrameSize : IN std_logic_vector(ADD_WIDTH-1 DOWNTO 0); -- Frame Length
RxRdy : IN std_logic; -- Rx Ready
RxDataBuffOut : IN std_logic_vector(7 DOWNTO 0); -- Output Rx Buffer
RxOverflow : IN std_logic; -- Rx Buffer Overflow
RxFrameError : IN std_logic; -- Frame Error
RxFCSErr : IN std_logic; -- Rx FCS Error
RxRd : OUT std_logic; -- Rx Read data
RxAbort : IN std_logic -- Received Abort signal
 
);
 
END WB_IF_ent;
 
ARCHITECTURE WB_IF_rtl OF WB_IF_ent IS
SIGNAL ack_0 : std_logic; -- ack Reg 0
SIGNAL ack_1 : std_logic; -- ack Reg 1
SIGNAL ack_2 : std_logic; -- ack Reg 2
SIGNAL ack_3 : std_logic; -- ack Reg 3
SIGNAL ack_4 : std_logic; -- ack Reg 4
 
SIGNAL DATO_0 : std_logic_vector(31 DOWNTO 0); -- data out 0
SIGNAL DATO_1 : std_logic_vector(31 DOWNTO 0); -- data out 1
SIGNAL DATO_2 : std_logic_vector(31 DOWNTO 0); -- data out 2
SIGNAL DATO_3 : std_logic_vector(31 DOWNTO 0); -- data out 3
SIGNAL DATO_4 : std_logic_vector(31 DOWNTO 0); -- data out 4
 
SIGNAL en_0 : std_logic; -- Enable reg 0
SIGNAL en_1 : std_logic; -- Enable reg 1
SIGNAL en_2 : std_logic; -- Enable reg 2
SIGNAL en_3 : std_logic; -- Enable reg 3
SIGNAL en_4 : std_logic; -- Enable reg 4
 
SIGNAL counter : integer RANGE 0 TO 7; -- System counter
SIGNAL rst_count : std_logic; -- Reset counter
 
BEGIN -- WB_IF_rtl
 
-- purpose: WB fsm
-- type : sequential
-- inputs : CLK_I, RST_I
-- outputs:
WB_fsm : PROCESS (CLK_I, RST_I)
 
BEGIN -- PROCESS WB_fsm
IF (CLK_I'event AND CLK_I = '1') THEN
RTY_O <= '0';
 
IF (RST_I = '1') THEN -- synchronous reset
 
ACK_O <= '0';
DAT_O <= (OTHERS => '0');
RTY_O <= '0';
TAG0_O <= '0';
TAG1_O <= '0';
 
en_0 <= '0';
en_1 <= '0';
en_2 <= '0';
en_3 <= '0';
en_4 <= '0';
rst_count <= '1';
 
ELSE
TAG0_O <= TxDone;
TAG1_O <= RxRdy;
 
IF (CYC_I = '1' AND STB_I = '1') THEN
 
CASE ADR_I IS
WHEN "000" => -- Tx_SC
ACK_O <= ack_0;
DAT_O <= DATO_0;
 
en_0 <= '1';
en_1 <= '0';
en_2 <= '0';
en_3 <= '0';
en_4 <= '0';
rst_count <= '1';
 
WHEN "001" => -- Tx_Buff
ACK_O <= ack_1;
DAT_O <= DATO_1;
 
en_0 <= '0';
en_1 <= '1' and not ack_1;
en_2 <= '0';
en_3 <= '0';
en_4 <= '0';
 
IF counter = 4 THEN
rst_count <= '1';
else
rst_count <= '0';
END IF;
 
WHEN "010" => -- Rx_SC
ACK_O <= ack_2;
DAT_O <= DATO_2;
 
en_0 <= '0';
en_1 <= '0';
en_2 <= '1';
en_3 <= '0';
en_4 <= '0';
 
WHEN "011" => -- Rx_Buff
ACK_O <= ack_3;
DAT_O <= DATO_3;
 
en_0 <= '0';
en_1 <= '0';
en_2 <= '0';
en_3 <= '1' and not ack_3;
en_4 <= '0';
 
IF counter = 7 THEN
rst_count <= '1';
else
rst_count <= '0';
END IF;
WHEN "100" => -- Rx_len
ACK_O <= ack_4;
DAT_O <= DATO_4;
 
en_0 <= '0';
en_1 <= '0';
en_2 <= '0';
en_3 <= '0';
en_4 <= '1';
 
WHEN OTHERS =>
DAT_O <= (OTHERS => '0');
ACK_O <= '1';
 
en_0 <= '0';
en_1 <= '0';
en_2 <= '0';
en_3 <= '0';
en_4 <= '0';
 
END CASE;
 
ELSE
 
DAT_O <= (OTHERS => '0');
ACK_O <= '0';
 
en_0 <= '0';
en_1 <= '0';
en_2 <= '0';
en_3 <= '0';
en_4 <= '0';
 
END IF; -- cycle
 
END IF; --clock
 
END IF; -- reset
 
END PROCESS WB_fsm;
 
-------------------------------------------------------------------------------
-- purpose: Register0
-- type : sequential
-- inputs : CLK_I, RST_I
-- outputs:
reg0 : PROCESS (CLK_I, RST_I)
 
BEGIN -- PROCESS reg0
IF (CLK_I'event AND CLK_I = '1') THEN
 
IF (RST_I = '1') THEN
ack_0 <= '0';
DATO_0 <= (OTHERS => '0');
TxEnable <= '0';
TxAbort <= '0';
TxFCSen <= '1';
 
ELSE
DATO_0 <= "000000000000000000000000"&
"00" & '0'& TxOverflow & TxAborted & "00" & TxDone;
ack_0 <= en_0;
 
IF (en_0 = '1' AND WE_I = '1') THEN
 
TxEnable <= DAT_I(1);
TxAbort <= DAT_I(2);
TxFCSen <= DAT_I(5);
 
END IF; -- Write and en_0
 
 
END IF; -- rst
END IF; -- clk
 
END PROCESS reg0;
-------------------------------------------------------------------------------
-- purpose: Register1
-- type : sequential
-- inputs : CLK_I, RST_I
-- outputs:
reg1 : PROCESS (CLK_I, RST_I)
 
-- VARIABLE counter : integer RANGE 0 TO 3; -- Internal counter
 
BEGIN -- PROCESS reg1
IF (CLK_I'event AND CLK_I = '1') THEN
 
IF (RST_I = '1') THEN
ack_1 <= '0';
DATO_1 <= (OTHERS => '0');
-- counter := 0;
 
ELSE -- reset
DATO_1 <= (OTHERS => '0');
 
IF (WE_I = '1' AND en_1 = '1') THEN
 
-- Txwr <= '1';
CASE counter IS
WHEN 0 =>
Txwr <= '1';
TxDataInBuff <= DAT_I(7 DOWNTO 0);
ack_1 <= '0';
-- counter := counter + 1;
WHEN 1 =>
Txwr <= '1';
TxDataInBuff <= DAT_I(15 DOWNTO 8);
ack_1 <= '0';
-- counter := counter + 1;
WHEN 2 =>
Txwr <= '1';
TxDataInBuff <= DAT_I(23 DOWNTO 16);
ack_1 <= '0';
-- counter := counter + 1;
WHEN 3 =>
Txwr <= '1';
TxDataInBuff <= DAT_I(31 DOWNTO 24);
ack_1 <= '1';
-- counter := 0;
WHEN OTHERS =>
Txwr <= '0';
TxDataInBuff <= (others=> '0');
ack_1 <= '0';
END CASE;
 
ELSE -- WE_I
 
TxDataInBuff <= (OTHERS => '0');
-- counter := 0;
Txwr <= '0';
ack_1 <= '0';
END IF; -- WE_I and en_1
 
 
END IF; -- rst
END IF; -- clk
 
END PROCESS reg1;
 
-------------------------------------------------------------------------------
-- purpose: Register2
-- type : sequential
-- inputs : CLK_I, RST_I
-- outputs:
reg2 : PROCESS (CLK_I, RST_I)
 
BEGIN -- PROCESS reg3
IF (CLK_I'event AND CLK_I = '1') THEN
 
IF (RST_I = '1') THEN
ack_2 <= '0';
DATO_2 <= (OTHERS => '0');
 
ELSE
DATO_2 <= "000000000000000000000000"&
"000"& RxOverflow & RxAbort & RxFrameError & RxFCSErr & RxRdy;
ack_2 <= en_2;
 
END IF; -- rst
END IF; -- clk
 
END PROCESS reg2;
-------------------------------------------------------------------------------
-- purpose: Register3
-- type : sequential
-- inputs : CLK_I, RST_I
-- outputs:
reg3 : PROCESS (CLK_I, RST_I)
 
-- VARIABLE count : integer RANGE 0 TO 5; -- Internal counter
 
BEGIN -- PROCESS reg1
IF (CLK_I'event AND CLK_I = '1') THEN
 
IF (RST_I = '1') THEN
ack_3 <= '0';
DATO_3 <= (OTHERS => '0');
-- count := 0;
 
ELSE
 
IF (en_3 = '1' AND WE_I = '0') THEN
 
-- if (WE_I = '0') then
 
CASE counter IS
WHEN 0 =>
RxRd <= '1';
DATO_3 <= (OTHERS => '0');
ack_3 <= '0';
-- count := count + 1;
 
WHEN 1 =>
RxRd <= '1';
-- DATO_3 <= "000000000000000000000000" & RxDataBuffOut;
DATO_3 <= RxDataBuffOut & DATO_3(31 downto 8);
-- DATO_3 <= (OTHERS => '0');
ack_3 <= '0';
-- count := count + 1;
 
WHEN 2 =>
RxRd <= '1';
DATO_3 <= RxDataBuffOut & DATO_3(31 DOWNTO 8);
ack_3 <= '0';
-- count := count + 1;
 
WHEN 3 =>
RxRd <= '0';
 
DATO_3 <= RxDataBuffOut & DATO_3(31 DOWNTO 8);
ack_3 <= '0';
-- count := count + 1;
WHEN 4 =>
RxRd <= '0';
 
DATO_3 <= RxDataBuffOut & DATO_3(31 DOWNTO 8);
ack_3 <= '0';
-- count := count +1;
WHEN 5 =>
RxRd <= '0';
 
DATO_3 <= RxDataBuffOut & DATO_3(31 DOWNTO 8);
ack_3 <= '1';
---- count := 0;
 
WHEN OTHERS =>
RxRd <= '0';
 
DATO_3 <= (others=>'0');
ack_3 <= '0';
END CASE;
 
-- else
-- DATO_3 <= (others => '0');
-- counter := 0;
-- RxRd <= '0';
-- ack_3 <= '0';
 
-- end if; -- Write
 
ELSE
DATO_3 <= (OTHERS => '0');
-- count := 0;
RxRd <= '0';
ack_3 <= '0';
 
END IF; -- en
 
END IF; -- rst
END IF; -- clk
 
END PROCESS reg3;
 
-----------------------------------------------------------------------------
-- purpose: Register4
-- type : sequential
-- inputs : CLK_I, RST_I
-- outputs:
reg4 : PROCESS (CLK_I, RST_I)
 
BEGIN -- PROCESS reg4
IF (CLK_I'event AND CLK_I = '1') THEN
 
IF (RST_I = '1') THEN
ack_4 <= '0';
DATO_4 <= (OTHERS => '0');
 
ELSE
DATO_4 <= "000000000000000000000000"&
'0' & RxFrameSize;
ack_4 <= en_4;
 
END IF; -- rst
END IF; -- clk
 
END PROCESS reg4;
-----------------------------------------------------------------------------
 
-- purpose: system counter
-- type : sequential
-- inputs : CLK_I
-- outputs:
sys_counter : PROCESS (CLK_I)
BEGIN -- process sys_counter
 
IF CLK_I'event AND CLK_I = '1' THEN -- rising clock edge
IF rst_count = '1' THEN
counter <= 0;
ELSIF en_1 = '1' OR en_3 = '1' THEN
counter <= counter +1;
 
ELSE
counter <= 0;
END IF;
END IF;
END PROCESS sys_counter;
-----------------------------------------------------------------------------
END WB_IF_rtl;
/TxFCS.vhd
0,0 → 1,327
-------------------------------------------------------------------------------
-- Title : Tx FCS
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : TxFCS.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created :2001/03/09
-- Last update: 2001/04/24
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98,NC-SIM/Linux
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
-- hdlc.PCK_CRC16_D8
-------------------------------------------------------------------------------
-- Description: HDLC TX FCS-16 generation
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 9 March 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.11
-- Date : 21 March 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Ack signal added to fix any possible handshake error on
-- slow devices
-- slow hdlc controller can cause rdy signal to be asserted
-- for long time so ack signal indicates that the
-- controller has accepted the new data
-- ToOptimize : Reduce number of states
-- Bugs :
-------------------------------------------------------------------------------
-- Revision Number : 3
-- Version : 0.2
-- Date : 9 April 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Added FCS enable (to tranmist FCS or not)
-- FCS bit inversion fixed
-- ToOptimize : Reduce number of states, Check the FCSen operation
-- Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2001/04/27 18:21:59 jamil
-- After Prelimenray simulation
--
-- Revision 1.4 2001/04/14 15:18:05 jamil
-- Generic FCS added
--
-- Revision 1.3 2001/04/08 21:03:31 jamil
-- Added FCS enable (to tranmist FCS or not)
-- FCS bit inversion fixed
--
-- Revision 1.2 2001/03/21 22:47:05 jamil
-- ACK slow devices bug fixed
--
-- Revision 1.1 2001/03/21 20:19:43 jamil
-- Initial Release
--
-------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
LIBRARY hdlc;
USE hdlc.PCK_CRC16_D8.ALL;
 
ENTITY Txfcs_ent IS
GENERIC (
FCS_TYPE : INTEGER := 2); -- 2= FCS 16
-- 4= FCS 32
-- 0= Disable FCS
PORT (
TxClk : IN STD_LOGIC; -- Tx Clock
rst_n : IN STD_LOGIC; -- System Reset
FCSen : IN STD_LOGIC; -- FCS enable
ValidFrame : OUT STD_LOGIC; -- Valid Frame
WriteByte : OUT STD_LOGIC; -- Write Byte
rdy : IN STD_LOGIC; -- Ready to send data
ack : IN STD_LOGIC; -- Acknowlege
TxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Data
 
TxDataAvail : IN STD_LOGIC; -- Tx Data is available in the buffer
-- (reflected from TxEnable bit in Tx register)
RdBuff : OUT STD_LOGIC; -- Read Tx data buffer
TxDataBuff : IN STD_LOGIC_VECTOR(7 DOWNTO 0)); -- Tx Data buffer
 
 
END Txfcs_ent;
 
 
ARCHITECTURE Txfcs_beh OF Txfcs_ent IS
 
BEGIN -- Txfcs_sync_beh
-------------------------------------------------------------------------------
-- purpose: Main State machine
-- type : sequential
-- inputs : TxClk, rst_n
-- outputs:
FSM_proc : PROCESS (TxClk, rst_n)
VARIABLE FCS_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); -- FCS register
TYPE States_types IS (IDLE_st, READ_st, WRITE_st, WAIT_st, SETZ1_st, WRITEZ1_st, SETZ2_st, WAIT2_st, WAIT_STATE1_st, WAIT_STATE2_st, WAIT_STATE3_st);
-- Internal states
VARIABLE state : States_types; -- State register
 
VARIABLE Data2FCS : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Input data to FCS reg
 
BEGIN -- process FSM_proc
IF rst_n = '0' THEN -- asynchronous reset (active low)
Data2FCS := (OTHERS => '0');
FCS_reg := (OTHERS => '1');
 
ValidFrame <= '0';
WriteByte <= '0';
TxData <= (OTHERS => '0');
 
RdBuff <= '0';
 
state := IDLE_st;
 
ELSIF TxClk'event AND TxClk = '1' THEN -- rising clock edge
 
 
 
CASE state IS
WHEN IDLE_st =>
 
FCS_reg := (OTHERS => '1');
Data2FCS := (OTHERS => '1');
 
ValidFrame <= TxDataAvail;--'0';
 
WriteByte <= '0';
TxData <= (OTHERS => '0');
 
IF rdy = '1' then --AND TxDataAvail = '1' THEN
state := READ_st;
RdBuff <= '1';
 
ELSE
state := IDLE_st;
RdBuff <= '0';
 
END IF;
-- -- -- -- --
WHEN READ_st =>
Data2FCS := TxDataBuff;
-- FCS calculation
FCS_reg := nextCRC16_D8 ( Data2FCS, FCS_reg );
 
ValidFrame <= '1';
WriteByte <= '1';
TxData <= TxDataBuff;
 
RdBuff <= '0';
 
state := WAIT_STATE1_st;
-- -- -- -- --
WHEN WAIT_STATE1_st =>
-- this state does nothing but registers all output signals till ack is valid
-- IF ( ack = '1') THEN
IF ( rdy = '0') THEN
state := WAIT_st;
ELSE
state := WAIT_STATE1_st;
END IF;
 
-- -- -- -- --
WHEN WAIT_st =>
 
ValidFrame <= '1';
WriteByte <= '0';
 
IF TxDataAvail = '1' THEN -- Data Available (wait for rdy)
TxData <= TxDataBuff;
Data2FCS := TxDataBuff;
IF rdy = '1' THEN -- ready to accept new data
 
RdBuff <= '1';
state := READ_st;
 
ELSE
RdBuff <= '0';
state := WAIT_st;
 
END IF;
 
ELSE
-- No data is available
IF (FCSen = '1') THEN
TxData <= (OTHERS => '1');
Data2FCS := (OTHERS => '1');
FCS_reg := nextCRC16_D8 ( Data2FCS, FCS_reg );
 
RdBuff <= '0';
state := SETZ1_st;
ELSE
TxData <= (OTHERS => '1');
Data2FCS := (OTHERS => '1');
FCS_reg := (OTHERS => '1');
 
RdBuff <= '0';
state := IDLE_st;
 
END IF;
 
END IF;
 
-- -- -- -- --
WHEN SETZ1_st =>
Data2FCS := (OTHERS => '1');
-- FCS calculation
FCS_reg := nextCRC16_D8 ( Data2FCS, FCS_reg );
ValidFrame <= '1';
 
WriteByte <= '0';
TxData <= (OTHERS => '1');
 
RdBuff <= '0';
state := SETZ2_st;
-- -- -- -- --
WHEN SETZ2_st =>
 
Data2FCS := (OTHERS => '1');
 
ValidFrame <= '1';
RdBuff <= '0';
 
IF rdy = '1' THEN
 
WriteByte <= '1';
 
TxData(7) <= NOT FCS_reg(8);
TxData(6) <= NOT FCS_reg(9);
TxData(5) <= NOT FCS_reg(10);
TxData(4) <= NOT FCS_reg(11);
TxData(3) <= NOT FCS_reg(12);
TxData(2) <= NOT FCS_reg(13);
TxData(1) <= NOT FCS_reg(14);
TxData(0) <= NOT FCS_reg(15);
 
 
state := WAIT_STATE2_st;
 
ELSE
-- This the normal case when the other device reply to write
-- signals by deasserting rdy signal
TxData <= (OTHERS => '1');
WriteByte <= '0';
state := SETZ2_st;
END IF;
-- -- -- -- --
 
WHEN WAIT_STATE2_st =>
-- this state does nothing but registers all output signals till ack is valid
-- IF (ack = '1') THEN
IF ( rdy = '0') THEN
state := WAIT2_st;
ELSE
state := WAIT_STATE2_st;
END IF;
 
-- -- -- -- --
WHEN WAIT2_st =>
Data2FCS := (OTHERS => '1');
 
ValidFrame <= '1';
RdBuff <= '0';
 
IF rdy = '1' THEN
 
WriteByte <= '1';
 
TxData(7) <= NOT FCS_reg(0);
TxData(6) <= NOT FCS_reg(1);
TxData(5) <= NOT FCS_reg(2);
TxData(4) <= NOT FCS_reg(3);
TxData(3) <= NOT FCS_reg(4);
TxData(2) <= NOT FCS_reg(5);
TxData(1) <= NOT FCS_reg(6);
TxData(0) <= NOT FCS_reg(7);
 
 
state := WAIT_STATE3_st;
 
ELSE
TxData <= (OTHERS => '1');
WriteByte <= '0';
state := WAIT2_st;
END IF;
-- -- -- -- --
 
WHEN WAIT_STATE3_st =>
-- this state does nothing but registers all output signals till ack is valid
-- IF (ack = '1') THEN
IF ( rdy = '0') THEN
state := IDLE_st;
ELSE
state := WAIT_STATE3_st;
END IF;
-- -- -- -- --
 
WHEN OTHERS => NULL;
END CASE;
 
 
END IF;
END PROCESS FSM_proc;
 
 
END Txfcs_beh;
 
/TxSync.vhd
0,0 → 1,176
-------------------------------------------------------------------------------
-- Title : Tx Synchronizer
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : TxSync.vhd
-- Author : Jamil Khatib <khatib@ieee.org>
-- Organization: OpenIPCore Project
-- Created : 2001/03/22
-- Last update: 2001/03/22
-- Platform :
-- Simulators : Modelsim/Win98 , NC-sim/Linux
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic
-------------------------------------------------------------------------------
-- Description: Tx Synchronizer
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 2001/03/22
-- Modifier : Jamil Khatib <khatib@ieee.org>
-- Desccription : Created
-- ToOptimize :
-- Known Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2001/03/22 21:58:01 jamil
-- Initial release
--
-------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY txSynch_ent IS
-- D1 Domain 1 = Serial line
-- D2 Domain 2 = System interface
PORT (
rst_n : IN std_logic; -- System reset
clk_D1 : IN std_logic; -- Domain 1 clock
clk_D2 : IN std_logic; -- Domain 2 clock
rdy_D1 : IN std_logic; -- Domain 1 ready
rdy_D2 : OUT std_logic; -- Domain 2 ready
ack : OUT std_logic; -- Acknowldege signals
TXD_D1 : OUT std_logic_vector(7 DOWNTO 0); -- Domain 1 Tx Data bus
TXD_D2 : IN std_logic_vector(7 DOWNTO 0); -- Domain 2 Tx Data Bus
ValidFrame_D1 : OUT std_logic; -- Domain 1 Valid Frame
ValidFrame_D2 : IN std_logic; -- Domain 2 Valid Frame
AbortedTrans_D1 : IN std_logic; -- Domain 1 Aborted Transmission
AbortedTrans_D2 : OUT std_logic; -- Domain 2 Aborted Transmission
AbortFrame_D1 : OUT std_logic; -- Domain 1 Abort Frame
AbortFrame_D2 : IN std_logic; -- Domain 2 Abort Frame
WriteByte_D1 : OUT std_logic; -- Domain 1 Write Byte
WriteByte_D2 : IN std_logic -- Domain 2 Write Byte
 
);
 
END txSynch_ent;
-------------------------------------------------------------------------------
 
ARCHITECTURE TxSynch_rtl OF txSynch_ent IS
SIGNAL ack_i : std_logic; -- ack signal
 
BEGIN -- ARCHITECTURE TxSynch_rtl
 
-- Data bus does not need synchronization
TXD_D1 <= TXD_D2;
 
-- purpose: rdy signal
-- type : sequential
-- inputs : clk_D2, rst_n
-- outputs:
Rdy_signal : PROCESS (clk_D2, rst_n)
VARIABLE FF1 : std_logic;
BEGIN -- PROCESS Rdy_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
rdy_D2 <= '0';
ELSIF clk_D2'event AND clk_D2 = '1' THEN -- rising clock edge
rdy_D2 <= FF1;
FF1 := rdy_D1;
END IF;
 
END PROCESS Rdy_signal;
 
-- purpose: write bytes signal
-- type : sequential
-- inputs : clk_D1, rst_n
-- outputs:
Write_signal : PROCESS (clk_D1, rst_n)
VARIABLE FF1 : std_logic;
BEGIN -- PROCESS Write_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
WriteByte_D1 <= '0';
ack_i <= '0';
ELSIF clk_D1'event AND clk_D1 = '1' THEN -- rising clock edge
ack_i <= FF1;
WriteByte_D1 <= FF1;
FF1 := WriteByte_D2;
END IF;
END PROCESS Write_signal;
 
-- purpose: ack signal
-- type : sequential
-- inputs : clk_D2, rst_n
-- outputs:
ack_signal : PROCESS (clk_D2, rst_n)
VARIABLE FF1 : std_logic;
BEGIN -- PROCESS ack_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
ack <= '0';
ELSIF clk_D2'event AND clk_D2 = '1' THEN -- rising clock edge
ack <= FF1;
FF1 := ack_i;
END IF;
END PROCESS ack_signal;
-- purpose: Abort Frame signal
-- type : sequential
-- inputs : clk_D1, rst_n
-- outputs:
AbortFrame_signal : PROCESS (clk_D1, rst_n)
VARIABLE FF1 : std_logic;
BEGIN -- PROCESS AbortFrame_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
AbortFrame_D1 <= '0';
ELSIF clk_D1'event AND clk_D1 = '1' THEN -- rising clock edge
AbortFrame_D1 <= FF1;
FF1 := AbortFrame_D2;
END IF;
END PROCESS AbortFrame_signal;
 
-- purpose: Valid Frame signal
-- type : sequential
-- inputs : clk_D1, rst_n
-- outputs:
ValidFrame_signal : PROCESS (clk_D1, rst_n)
VARIABLE FF1 : std_logic;
BEGIN -- PROCESS ValidFrame_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
ValidFrame_D1 <= '0';
ELSIF clk_D1'event AND clk_D1 = '1' THEN -- rising clock edge
ValidFrame_D1 <= FF1;
FF1 := ValidFrame_D2;
END IF;
END PROCESS ValidFrame_signal;
 
-- purpose: Aborted Trans signal
-- type : sequential
-- inputs : clk_D2, rst_n
-- outputs:
AbortedTrans_signal : PROCESS (clk_D2, rst_n)
VARIABLE FF1 : std_logic;
BEGIN -- PROCESS AbortedTrans_signal
IF rst_n = '0' THEN -- asynchronous reset (active low)
FF1 := '0';
AbortedTrans_D2 <= '0';
ELSIF clk_D2'event AND clk_D2 = '1' THEN -- rising clock edge
AbortedTrans_D2 <= FF1;
FF1 := AbortedTrans_D1;
END IF;
END PROCESS AbortedTrans_signal;
 
END TxSynch_rtl;
/hdlc.vhd
0,0 → 1,303
-------------------------------------------------------------------------------
-- Title : HDLC core
-- Project : HDLC Standalone controller with buffers
-------------------------------------------------------------------------------
-- File : hdlc.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenCores Project
-- Created :2001/03/022
-- Last update: 2001/03/22
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98,NC-SIM/Linux
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
-- hdlc.hdlc_components_pkg
-------------------------------------------------------------------------------
-- Description: HDLC controller
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 22 March 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2001/04/22 20:08:16 jamil
-- Top level simulation
--
-- Revision 1.1 2001/03/22 21:58:01 jamil
-- Initial release
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
LIBRARY hdlc;
USE hdlc.hdlc_components_pkg.ALL;
 
ENTITY hdlc_ent IS
GENERIC (
FCS_TYPE : INTEGER := 2; -- FCS 16
ADD_WIDTH : INTEGER := 7); -- Internal buffer address width
PORT (
Txclk : IN STD_LOGIC; -- Tx Clock
RxClk : IN STD_LOGIC; -- Rx Clock
Tx : OUT STD_LOGIC; -- Tx setial line
Rx : IN STD_LOGIC; -- Rx serial line
TxEN : IN STD_LOGIC; -- Tx Enable
RxEn : IN STD_LOGIC; -- Rx Enable
RST_I : IN STD_LOGIC; -- WB reset
CLK_I : IN STD_LOGIC; -- WB clock
ADR_I : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- WB address
DAT_O : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- WB output data
DAT_I : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- WB input data
WE_I : IN STD_LOGIC; -- WB write/read signal
STB_I : IN STD_LOGIC; -- WB strobe
ACK_O : OUT STD_LOGIC; -- WB acknowledge
CYC_I : IN STD_LOGIC; -- WB cycle
RTY_O : OUT STD_LOGIC; -- WB Retry
TAG0_O : OUT STD_LOGIC; -- WB TAG (TxDone interrupt)
TAG1_O : OUT STD_LOGIC); -- WB TAG (RxReady interrupt)
 
END hdlc_ent;
 
ARCHITECTURE hdlc_str OF hdlc_ent IS
SIGNAL rst_n : STD_LOGIC; -- Internal Reset
 
SIGNAL Tx_rdy_D1 : STD_LOGIC; -- Tx rdy signal (Domain 1)
SIGNAL Tx_rdy_D2 : STD_LOGIC; -- Tx rdy signal (Domain 2)
SIGNAL Tx_ack : STD_LOGIC; -- Tx Acknowledge signal
SIGNAL TXD_D1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Data bus (Domain 1)
SIGNAL TXD_D2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Data Bus (Domain 2)
SIGNAL Tx_ValidFrame_D1 : STD_LOGIC; -- Tx Valid Frame (Domain 1)
SIGNAL Tx_ValidFrame_D2 : STD_LOGIC; -- Tx Valid Frame (Domain 2)
SIGNAL Tx_AbortedTrans_D1 : STD_LOGIC; -- Tx Aborted Transmission (Domain 1)
SIGNAL Tx_AbortedTrans_D2 : STD_LOGIC; -- Tx Aborted Transmission (Domain 2)
SIGNAL Tx_AbortFrame_D1 : STD_LOGIC; -- Tx Abort Frame (Domain 1)
SIGNAL Tx_AbortFrame_D2 : STD_LOGIC; -- Tx Abort Frame (Domain 2)
SIGNAL Tx_WriteByte_D1 : STD_LOGIC; -- Tx Write bytes (Domain 1)
SIGNAL Tx_WriteByte_D2 : STD_LOGIC; -- Tx Write Byte (Domain 2)
 
SIGNAL Rx_ValidFrame_D1 : STD_LOGIC; -- Rx Valid Frame (Domain1)
SIGNAL Rx_ValidFrame_D2 : STD_LOGIC; -- Rx Valid Frame (Domain 2)
 
SIGNAL RxD_D1 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Data bus (Domain 1)
SIGNAL RXD_D2 : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx data bus (Domain 2)
 
SIGNAL Rx_FrameError_D1 : STD_LOGIC; -- Rx Frame Error (Domain 1)
SIGNAL Rx_FrameError_D2 : STD_LOGIC; -- Rx Frame Error (Domain 2)
 
SIGNAL Rx_AbortSignal_D1 : STD_LOGIC; -- Rx Abort signal (Domain 1)
SIGNAL Rx_AbortSignal_D2 : STD_LOGIC; -- Rx Abort signal (Domain 2)
 
SIGNAL Rx_Readbyte_D1 : STD_LOGIC; -- Rx Read Byte (Domain 1)
SIGNAL Rx_Readbyte_D2 : STD_LOGIC; -- Rx Read Byte (Domain 2)
 
SIGNAL Rx_rdy_D1 : STD_LOGIC; -- Rx rdy (Domain 1)
SIGNAL Rx_rdy_D2 : STD_LOGIC; -- Rx rdy (Domain 2)
 
 
SIGNAL TxDataAvail : STD_LOGIC; -- Tx Data Available from the Buffer
SIGNAL Tx_RdBuff : STD_LOGIC; -- Tx Read Byte from the buffer
SIGNAL TxDone : STD_LOGIC; -- TxDone bit (Interrupt)
SIGNAL TxEnable : STD_LOGIC; -- TxEnable Bit
SIGNAL Tx_Full : STD_LOGIC; -- Tx Full Buffer Bit
SIGNAL TxDataInBuff : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Tx input data to buffer
SIGNAL TxDataOutBuff : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Tx Data output from buffer
SIGNAL Tx_Wr_Buff : STD_LOGIC; -- Write to Tx Buffer
 
SIGNAL FCSen : STD_LOGIC; -- FCS Enable (both Tx & Rx)
 
SIGNAL Rx_WrBuff : STD_LOGIC; -- Write to Rx Buffer
SIGNAL Rx_EOF : STD_LOGIC; -- RX End Of Frame
SIGNAL Rx_FrameSize : STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
-- Rx Frame size
SIGNAL Rx_DataBuff : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Input data buffer
SIGNAL Rx_Buff_Overflow : STD_LOGIC; -- Rx Buffer overflow
SIGNAL Rx_FCSerr : STD_LOGIC; -- Rx FCS error
SIGNAL RxDataBuffOut : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Data BUFFER output
 
SIGNAL Rx_Rd_Buff : STD_LOGIC; -- Rx Read Data Buffer
SIGNAL RxRdy_int : STD_LOGIC; -- Rx Ready interrupt
 
BEGIN -- hdlc_str
 
rst_n <= NOT RST_I;
 
WB_host : WB_IF_ent
GENERIC MAP (
ADD_WIDTH => ADD_WIDTH)
PORT MAP (
CLK_I => CLK_I,
RST_I => RST_I,
ACK_O => ACK_O,
ADR_I => ADR_I,
CYC_I => CYC_I,
DAT_I => DAT_I,
DAT_O => DAT_O,
RTY_O => RTY_O,
STB_I => STB_I,
WE_I => WE_I,
TAG0_O => TAG0_O,
TAG1_O => TAG1_O,
TxEnable => TxEnable,
TxDone => TxDone,
TxDataInBuff => TxDataInBuff,
Txwr => Tx_Wr_Buff,
TxAborted => Tx_AbortedTrans_D2,
TxAbort => Tx_AbortFrame_D2,
TxOverflow => Tx_Full,
TxFCSen => FCSen,
RxFrameSize => Rx_FrameSize,
RxRdy => RxRdy_int,
RxDataBuffOut => RxDataBuffOut,
RxOverflow => Rx_Buff_Overflow,
RxFrameError => Rx_FrameError_D2,
RxFCSErr => Rx_FCSErr,
RxRd => Rx_Rd_Buff,
RxAbort => Rx_AbortSignal_D2);
 
TxSynch : txSynch_ent
PORT MAP (
rst_n => rst_n,
clk_D1 => Txclk,
clk_D2 => CLK_I,
rdy_D1 => Tx_rdy_D1,
rdy_D2 => Tx_rdy_D2,
ack => Tx_ack,
TXD_D1 => TXD_D1,
TXD_D2 => TXD_D2,
ValidFrame_D1 => Tx_ValidFrame_D1,
ValidFrame_D2 => Tx_ValidFrame_D2,
AbortedTrans_D1 => Tx_AbortedTrans_D1,
AbortedTrans_D2 => Tx_AbortedTrans_D2,
AbortFrame_D1 => Tx_AbortFrame_D1,
AbortFrame_D2 => Tx_AbortFrame_D2,
WriteByte_D1 => Tx_WriteByte_D1,
WriteByte_D2 => Tx_WriteByte_D2);
 
TxBuff : TxBuff_ent
GENERIC MAP (
ADD_WIDTH => ADD_WIDTH)
PORT MAP (
TxClk => CLK_I,
rst_n => rst_n,
RdBuff => Tx_RdBuff,
Wr => Tx_Wr_Buff,
TxDataAvail => TxDataAvail,
TxEnable => TxEnable,
TxDone => TxDone,
TxDataOutBuff => TxDataOutBuff,
TxDataInBuff => TxDataInBuff,
Full => Tx_Full);
 
TxFCS : Txfcs_ent
GENERIC MAP (
FCS_TYPE => FCS_TYPE)
PORT MAP (
TxClk => CLK_I,
rst_n => rst_n,
FCSen => FCSen,
ValidFrame => Tx_ValidFrame_D2,
WriteByte => Tx_WriteByte_D2,
rdy => Tx_rdy_D2,
ack => Tx_ack,
TxData => TXD_D2,
TxDataAvail => TxDataAvail,
RdBuff => Tx_RdBuff,
TxDataBuff => TxDataOutBuff);
 
 
TxCore : TxChannel_ent
PORT MAP (
TxClk => TxClk,
rst_n => rst_n,
TXEN => TXEN,
Tx => Tx,
ValidFrame => Tx_ValidFrame_D1,
AbortFrame => Tx_AbortFrame_D1,
AbortedTrans => Tx_AbortedTrans_D1,
WriteByte => Tx_WriteByte_D1,
rdy => Tx_rdy_D1,
TxData => TxD_D1);
 
RxChannel : RxChannel_ent
PORT MAP (
Rxclk => Rxclk,
rst => rst_n,
Rx => Rx,
RxData => RxD_D1,
ValidFrame => Rx_ValidFrame_D1,
FrameError => Rx_FrameError_D1,
AbortSignal => Rx_AbortSignal_D1,
Readbyte => Rx_Readbyte_D1,
rdy => Rx_rdy_D1,
RxEn => RxEn);
 
 
RxSynch : RxSynch_ent
PORT MAP (
rst_n => rst_n,
clk_D1 => Rxclk,
clk_D2 => CLK_I,
rdy_D1 => Rx_rdy_D1,
rdy_D2 => Rx_rdy_D2,
RXD_D1 => RxD_D1,
RXD_D2 => RXD_D2,
ValidFrame_D1 => Rx_ValidFrame_D1,
ValidFrame_D2 => Rx_ValidFrame_D2,
AbortSignal_D1 => Rx_AbortSignal_D1,
AbortSignal_D2 => Rx_AbortSignal_D2,
FrameError_D1 => Rx_FrameError_D1,
FrameError_D2 => Rx_FrameError_D2,
ReadByte_D1 => Rx_ReadByte_D1,
ReadByte_D2 => Rx_ReadByte_D2);
 
RxBuff : RxBuff_ent
GENERIC MAP (
FCS_TYPE => FCS_TYPE,
ADD_WIDTH => ADD_WIDTH)
PORT MAP (
Clk => CLK_I,
rst_n => rst_n,
DataBuff => Rx_DataBuff,
EOF => Rx_EOF,
WrBuff => Rx_WrBuff,
FrameSize => Rx_FrameSize,
RxRdy => RxRdy_int,
RxDataBuffOut => RxDataBuffOut,
Overflow => Rx_Buff_Overflow,
Rd => Rx_Rd_Buff);
 
 
RxFCS : RxFCS_ent
GENERIC MAP (
FCS_TYPE => FCS_TYPE)
PORT MAP (
clk => CLK_I,
rst_n => rst_n,
RxD => RxD_D2,
ValidFrame => Rx_ValidFrame_D2,
rdy => Rx_rdy_D2,
Readbyte => Rx_Readbyte_D2,
DataBuff => Rx_DataBuff,
WrBuff => Rx_WrBuff,
EOF => Rx_EOF,
FCSen => FCSen,
FCSerr => Rx_FCSerr);
 
 
END hdlc_str;
/RxBuff.vhd
0,0 → 1,266
------------------------------------------------------------------------------
-- Title : HDLC Rx Buffer
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : RxBuff.vhd
-- Author : Jamil Khatib <khatib@ieee.org>
-- Organization: OpenIPCore Project
-- Created : 2001/04/06
-- Last update: 2001/04/25
-- Platform :
-- Simulators : Modelsim/Windows98, NC-sim/Linux
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
-- memLib.mem_pkg
-------------------------------------------------------------------------------
-- Description: HDLC Receive Buffer
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 2001/04/06
-- Modifier : Jamil Khatib <khatib@ieee.org>
-- Desccription : Created
-- ToOptimize :
-- Known Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2001/04/27 18:21:59 jamil
-- After Prelimenray simulation
--
-- Revision 1.2 2001/04/22 20:08:16 jamil
-- Top level simulation
--
-- Revision 1.1 2001/04/14 15:02:25 jamil
-- Initial Release
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
LIBRARY memLib;
USE memLib.mem_Pkg.ALL;
 
ENTITY RxBuff_ent IS
 
GENERIC (
FCS_TYPE : INTEGER := 2; -- 2 = FCS 16
-- 4 = FCS 32
-- 0 = FCS disabled
ADD_WIDTH : INTEGER := 7); -- Internal Address width
 
PORT (
Clk : IN STD_LOGIC; -- System Clock
rst_n : IN STD_LOGIC; -- System reset
DataBuff : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Rx Data
EOF : IN STD_LOGIC; -- End of Frame pulse
WrBuff : IN STD_LOGIC; -- Write buffer
FrameSize : OUT STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0); -- Frame Length
RxRdy : OUT STD_LOGIC; -- Rx Ready
RxDataBuffOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Output Rx Buffer
Overflow : OUT STD_LOGIC; -- Buffer Overflow
Rd : IN STD_LOGIC); -- Read buffer
 
END RxBuff_ent;
 
 
ARCHITECTURE RxBuff_rtl OF RxBuff_ent IS
 
SIGNAL load_FrSize : STD_LOGIC; -- Load Frame Size
SIGNAL en_Count : STD_LOGIC; -- Enable Counter
 
SIGNAL Data_In_i : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Internal Data in
SIGNAL Data_Out_i : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Internal Data out
CONSTANT MAX_ADDRESS : STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
-- MAX Address
 
SIGNAL Count : STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0); -- Counter
SIGNAL rst_count : STD_LOGIC; -- Reset Counter
 
SIGNAL cs : STD_LOGIC := '1'; -- dummy signal
 
SIGNAL WR_i : STD_LOGIC; -- Internal Read/Write signal
SIGNAL Address : STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
-- Internal Address bus
SIGNAL FrameSize_i : STD_LOGIC_VECTOR(ADD_WIDTH-1 DOWNTO 0);
-- Internal Frame Size
SIGNAL Overflow_i : STD_LOGIC; -- Internal Overflow
SIGNAL RxRdy_i : STD_LOGIC; -- Internal RxRdy
 
TYPE states_typ IS (IDLE_st, WRITE_st, READ_st); -- states types
 
SIGNAL p_state : states_typ; -- Present state
SIGNAL n_state : states_typ; -- Next State
 
 
BEGIN -- RxBuff_rtl
-------------------------------------------------------------------------------
 
Data_In_i <= DataBuff;
RxDataBuffOut <= Data_Out_i;
 
-------------------------------------------------------------------------------
-- Full <= '1' WHEN Address = MAX_ADDRESS ELSE '0';
Address <= Count;
 
-------------------------------------------------------------------------------
-- purpose: Byte counter
-- type : sequential
-- inputs : Clk, rst_n
-- outputs:
counter_proc : PROCESS (Clk, rst_n)
BEGIN -- process counter_proc
IF rst_n = '0' THEN -- asynchronous reset (active low)
count <= (OTHERS => '0');
ELSIF Clk'event AND Clk = '1' THEN -- rising clock edge
IF rst_count = '1' THEN -- Synchronouse Reset (active high)
count <= (OTHERS => '0');
ELSIF en_Count = '1' THEN
count <= count +1;
END IF;
END IF;
END PROCESS counter_proc;
-------------------------------------------------------------------------------
-- purpose: Frame Size register
-- type : sequential
-- inputs : Clk, rst_n
-- outputs:
FrameSize_reg : PROCESS (Clk, rst_n)
BEGIN -- process FrameSize_reg
IF rst_n = '0' THEN -- asynchronous reset (active low)
FrameSize <= (OTHERS => '0');
FrameSize_i <= (OTHERS => '0');
ELSIF Clk'event AND Clk = '1' THEN -- rising clock edge
IF load_FrSize = '1' THEN
FrameSize <= address - FCS_TYPE;
FrameSize_i <= address - FCS_TYPE;
END IF;
END IF;
END PROCESS FrameSize_reg;
-------------------------------------------------------------------------------
 
-- purpose: fsm process
-- type : sequential
-- inputs : Clk, rst_n
-- outputs:
fsm_proc : PROCESS (Clk, rst_n)
BEGIN -- process fsm_proc
IF rst_n = '0' THEN -- asynchronous reset (active low)
p_state <= IDLE_st;
Overflow <= '0';
RxRdy <= '0';
ELSIF Clk'event AND Clk = '1' THEN -- rising clock edge
p_state <= n_state;
Overflow <= Overflow_i;
RxRdy <= RxRdy_i;
END IF;
END PROCESS fsm_proc;
-------------------------------------------------------------------------------
-- purpose: FSM Combinational logic
-- type : combinational
-- inputs : p_state,WrBuff,Rd
-- outputs:
ReadWrite : PROCESS (p_state, WrBuff, Rd, EOF, FrameSize_i, address)
 
BEGIN -- PROCESS ReadWrite
 
CASE p_state IS
 
WHEN IDLE_st =>
RxRdy_i <= '0';
load_FrSize <= '0';
wr_i <= NOT WrBuff;
Overflow_i <= '0';
IF WrBuff = '1' THEN
n_state <= WRITE_st;
en_Count <= '1';
rst_count <= '0';
ELSE
n_state <= IDLE_st;
en_Count <= '0';
rst_count <= '1';
END IF;
 
WHEN WRITE_st =>
IF (Address = MAX_ADDRESS) THEN
Overflow_i <= '1';
ELSE
Overflow_i <= '0';
END IF;
 
 
-- RxRdy_i <= '0';
wr_i <= NOT WrBuff;
en_Count <= WrBuff;
 
IF (EOF = '1') OR (address = MAX_ADDRESS) THEN
RxRdy_i <= '1';
n_state <= READ_st;
load_FrSize <= '1';
rst_count <= '1';
ELSE
RxRdy_i <= '0';
n_state <= WRITE_st;
load_FrSize <= '0';
rst_count <= '0';
END IF;
 
WHEN READ_st =>
 
wr_i <= '1';
en_Count <= Rd;
load_FrSize <= '0';
 
IF address = FrameSize_i THEN
Overflow_i <= '0';
RxRdy_i <= '0';
n_state <= IDLE_st;
rst_count <= '1';
ELSE
IF (WrBuff = '1') THEN
Overflow_i <= '1';
n_state <= WRITE_st;
rst_count <= '1';
ELSE
Overflow_i <= '0';
n_state <= READ_st;
rst_count <= '0';
END IF;
RxRdy_i <= '1';
 
END IF;
 
END CASE;
 
END PROCESS ReadWrite;
 
 
Buff : Spmem_ent
GENERIC MAP (
USE_RESET => FALSE,
USE_CS => FALSE,
DEFAULT_OUT => '1',
OPTION => 0,
ADD_WIDTH => ADD_WIDTH,
WIDTH => 8)
PORT MAP (
cs => cs,
clk => clk,
reset => rst_n,
add => Address,
Data_In => Data_In_i,
Data_Out => Data_Out_i,
WR => WR_i);
 
END RxBuff_rtl;
/TxBuff.vhd
0,0 → 1,249
-------------------------------------------------------------------------------
-- Title : Tx buffer
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : TxBuff.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created :2001/03/08
-- Last update: 2001/03/18
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98,NC-SIM/Linux
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
-- memLib.mem_pkg
-------------------------------------------------------------------------------
-- Description: HDLC controller
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 8 March 2001
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- ToOptimize :
-- Bugs :
-------------------------------------------------------------------------------
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2001/03/21 20:19:43 jamil
-- Initial Release
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library memLib;
use memLib.mem_pkg.all;
 
entity TxBuff_ent is
generic (
ADD_WIDTH : integer := 7); -- Internal address width
 
port (
TxClk : in std_logic; -- Tx Clock
rst_n : in std_logic; -- System reset
RdBuff : in std_logic; -- Read byte
Wr : in std_logic; -- Write Byte
TxDataAvail : out std_logic; -- Data Available to be read
TxEnable : in std_logic; -- TxEnable (Write Frame completed)
TxDone : out std_logic; -- Transmission Done (Read Frame completed)
TxDataOutBuff : out std_logic_vector(7 downto 0); -- Output Data
TxDataInBuff : in std_logic_vector(7 downto 0); -- Input Data
Full : out std_logic); -- Full Buffer (no more write is allowed)
 
end TxBuff_ent;
-------------------------------------------------------------------------------
 
architecture TxBuff_beh of TxBuff_ent is
 
signal WR_i : std_logic; -- Internal Read/Write signal
signal Address : std_logic_vector(ADD_WIDTH-1 downto 0);
-- Internal Address bus
type states_typ is (IDLE_typ, WRITE_typ, READ_typ); -- states types
 
signal p_state : states_typ; -- Present state
signal n_state : states_typ; -- Next State
 
signal FrameSize : std_logic_vector(ADD_WIDTH-1 downto 0); -- Frame Size
signal load_FrSize : std_logic; -- Load Frame Size
signal en_Count : std_logic; -- Enable Counter
 
signal Data_In_i : std_logic_vector(7 downto 0);
-- Internal Data in
signal Data_Out_i : std_logic_vector(7 downto 0);
-- Internal Data out
constant MAX_ADDRESS : std_logic_vector(ADD_WIDTH-1 downto 0) := (others => '1');
-- MAX Address
 
signal Count : std_logic_vector(ADD_WIDTH-1 downto 0); -- Counter
signal rst_count : std_logic; -- Reset Counter
 
signal cs_i : std_logic := '1'; -- Internal chip select
begin -- TxBuff_beh
 
Spmem_core : Spmem_ent
generic map (
USE_RESET => false,
USE_CS => false,
DEFAULT_OUT => '0',
OPTION => 0,
ADD_WIDTH => ADD_WIDTH,
WIDTH => 8)
port map (
cs => cs_i,
clk => TxClk,
reset => rst_n,
add => Address,
Data_In => Data_In_i,
Data_Out => Data_Out_i,
WR => WR_i);
-------------------------------------------------------------------------------
 
Data_In_i <= TxDataInBuff;
TxDataOutBuff <= Data_Out_i;
 
-------------------------------------------------------------------------------
Full <= '1' when Address = MAX_ADDRESS else '0';
Address <= Count;
 
-------------------------------------------------------------------------------
-- purpose: Byte counter
-- type : sequential
-- inputs : TxClk, rst_n
-- outputs:
counter_proc : process (TxClk, rst_n)
-- variable count : std_logic_vector(ADD_WIDTH-1 downto 0); -- Counter
begin -- process counter_proc
if rst_n = '0' then -- asynchronous reset (active low)
 
count <= (others => '0');
 
elsif TxClk'event and TxClk = '1' then -- rising clock edge
if rst_count = '1' then
count <= (others => '0');
elsif en_Count = '1' then
count <= count +1;
end if;
 
end if;
end process counter_proc;
-------------------------------------------------------------------------------
-- purpose: Frame Size register
-- type : sequential
-- inputs : TxClk, rst_n
-- outputs:
FrameSize_reg : process (TxClk, rst_n)
begin -- process FrameSize_reg
if rst_n = '0' then -- asynchronous reset (active low)
FrameSize <= (others => '0');
 
elsif TxClk'event and TxClk = '1' then -- rising clock edge
if load_FrSize = '1' then
FrameSize <= address;
end if;
end if;
end process FrameSize_reg;
 
-------------------------------------------------------------------------------
 
-- purpose: fsm process
-- type : sequential
-- inputs : TxClk, rst_n
-- outputs:
fsm_proc : process (TxClk, rst_n)
begin -- process fsm_proc
if rst_n = '0' then -- asynchronous reset (active low)
 
p_state <= IDLE_typ;
 
elsif TxClk'event and TxClk = '1' then -- rising clock edge
p_state <= n_state;
end if;
end process fsm_proc;
-------------------------------------------------------------------------------
-- purpose: Read write machine
-- type : combinational
-- inputs : strobe
-- outputs:
read_write_proc : process (TxEnable, Wr, Address, p_state, RdBuff, FrameSize)
 
begin -- process read_write_proc
 
case p_state is
 
when IDLE_typ =>
 
TxDone <= '1';
TxDataAvail <= '0';
load_FrSize <= '0';
 
wr_i <= not wr;
 
 
if wr = '1' then
n_state <= WRITE_typ;
en_Count <= '1';
rst_count <= '0';
else
n_state <= IDLE_typ;
en_Count <= '0';
rst_count <= '1';
end if;
 
when WRITE_typ =>
TxDone <= '0';
TxDataAvail <= '0';
 
wr_i <= not wr;
en_Count <= wr;
 
if (TxEnable = '1') or (address = MAX_ADDRESS) then
 
n_state <= READ_typ;
load_FrSize <= '1';
rst_count <= '1';
else
n_state <= WRITE_typ;
load_FrSize <= '0';
rst_count <= '0';
end if;
 
when READ_typ =>
 
wr_i <= '1';
en_Count <= RdBuff;
load_FrSize <= '0';
TxDataAvail <= '1';
 
if address = FrameSize then
TxDone <= '1';
n_state <= IDLE_typ;
rst_count <= '1';
else
TxDone <= '0';
n_state <= READ_typ;
rst_count <= '0';
end if;
 
when others =>
wr_i <= '1';
en_Count <= '0';
load_FrSize <= '0';
TxDataAvail <= '0';
TxDone <= '0';
rst_count <= '1';
end case;
 
end process read_write_proc;
end TxBuff_beh;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.