OpenCores
URL https://opencores.org/ocsvn/hdlc/hdlc/trunk

Subversion Repositories hdlc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /hdlc/trunk/CODE/TOP/scripts
    from Rev 10 to Rev 17
    ↔ Reverse comparison
  •

Rev 10 → Rev 17

/model/wave.do
0,0 → 1,80
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /hdlc_tb/txclk
add wave -noupdate -format Logic /hdlc_tb/rxclk
add wave -noupdate -format Logic /hdlc_tb/tx
add wave -noupdate -format Logic /hdlc_tb/rx
add wave -noupdate -format Logic /hdlc_tb/dut/rxchannel/flag_detect/flagdetect
add wave -noupdate -format Logic /hdlc_tb/rst_i
add wave -noupdate -format Logic /hdlc_tb/clk_i
add wave -noupdate -format Literal /hdlc_tb/adr_i
add wave -noupdate -format Literal /hdlc_tb/dat_o
add wave -noupdate -format Literal /hdlc_tb/dat_i
add wave -noupdate -format Logic /hdlc_tb/we_i
add wave -noupdate -format Logic /hdlc_tb/stb_i
add wave -noupdate -format Logic /hdlc_tb/ack_o
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/ack_0
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/ack_1
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/ack_2
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/ack_3
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/ack_4
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/en_0
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/en_1
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/en_2
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/en_3
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/en_4
add wave -noupdate -format Literal /hdlc_tb/dut/wb_host/counter
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/rst_count
add wave -noupdate -format Logic /hdlc_tb/dut/rxbuff/rd
add wave -noupdate -format Logic /hdlc_tb/cyc_i
add wave -noupdate -format Logic /hdlc_tb/rty_o
add wave -noupdate -format Logic /hdlc_tb/tag0_o
add wave -noupdate -format Logic /hdlc_tb/tag1_o
add wave -noupdate -format Literal /hdlc_tb/dut/rxbuff/p_state
add wave -noupdate -format Literal /hdlc_tb/dut/rxbuff/address
add wave -noupdate -format Literal /hdlc_tb/dut/rxbuff/rxdatabuffout
add wave -noupdate -format Literal /hdlc_tb/dut/rxbuff/databuff
add wave -noupdate -format Logic /hdlc_tb/dut/rxbuff/wrbuff
add wave -noupdate -format Literal /hdlc_tb/dut/txbuff/p_state
add wave -noupdate -format Logic /hdlc_tb/dut/txbuff/rdbuff
add wave -noupdate -format Logic /hdlc_tb/dut/txbuff/wr
add wave -noupdate -format Literal /hdlc_tb/dut/txbuff/address
add wave -noupdate -format Literal /hdlc_tb/dut/txbuff/txdataoutbuff
add wave -noupdate -format Literal /hdlc_tb/dut/txbuff/txdatainbuff
add wave -noupdate -format Logic /hdlc_tb/dut/wb_host/txenable
add wave -noupdate -format Literal /hdlc_tb/dut/txbuff/spmem_core/data
add wave -noupdate -format Logic /hdlc_tb/dut/txbuff/txdataavail
add wave -noupdate -format Logic /hdlc_tb/dut/txfcs/validframe
add wave -noupdate -format Literal /hdlc_tb/dut/txfcs/fsm_proc/state
add wave -noupdate -format Logic /hdlc_tb/dut/txfcs/rdy
add wave -noupdate -format Literal /hdlc_tb/dut/txfcs/txdata
add wave -noupdate -format Literal /hdlc_tb/dut/rxbuff/data_out_i
add wave -noupdate -format Literal /hdlc_tb/dut/rxbuff/address
add wave -noupdate -format Literal /hdlc_tb/dut/rxbuff/framesize_i
add wave -noupdate -format Logic /hdlc_tb/dut/rxfcs/validframe
add wave -noupdate -format Literal /hdlc_tb/dut/rxbuff/databuff
add wave -noupdate -format Literal /hdlc_tb/dut/rxfcs/rxd
add wave -noupdate -format Logic /hdlc_tb/dut/rxfcs/rdy
add wave -noupdate -format Logic /hdlc_tb/dut/rxfcs/readbyte
add wave -noupdate -format Logic /hdlc_tb/dut/rxchannel/zero_backend/readbyte
add wave -noupdate -format Logic /hdlc_tb/dut/rxchannel/zero_backend/rdy
add wave -noupdate -format Logic /hdlc_tb/dut/rxchannel/zero_backend/rxd
add wave -noupdate -format Literal /hdlc_tb/dut/rxchannel/zero_backend/rxdata
add wave -noupdate -format Literal /hdlc_tb/dut/rxchannel/zero_backend/dataregister
add wave -noupdate -format Logic /hdlc_tb/dut/rxchannel/zero_backend/flag
add wave -noupdate -format Literal /hdlc_tb/dut/rxchannel/zero_backend/detect_proc/tempregister
add wave -noupdate -format Literal /hdlc_tb/dut/rxchannel/zero_backend/detect_proc/counter
add wave -noupdate -format Logic /hdlc_tb/dut/rxchannel/zero_backend/detect_proc/zerodetected
add wave -noupdate -format Literal /hdlc_tb/dut/rxchannel/zero_backend/detect_proc/checkreg
add wave -noupdate -format Logic /hdlc_tb/dut/rxchannel/zero_backend/startofframe
add wave -noupdate -format Logic /hdlc_tb/dut/rxchannel/zero_backend/aval
add wave -noupdate -format Logic /hdlc_tb/dut/rxchannel/zero_backend/enable
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {146050 ns}
WaveRestoreZoom {146015 ns} {146179 ns}
configure wave -namecolwidth 224
configure wave -valuecolwidth 112
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
/model/build_TxFCS_Buff.do
0,0 → 1,36
# Remove all old libraries
echo Cleaning old libraries
vdel -lib work -all -verbose
vdel -lib utility -all -verbose
vdel -lib hdlc -all -verbose
vdel -lib memLib -all -verbose
# Build
echo building new libraries
vlib work
vlib utility
vlib hdlc
vlib memLib
echo mapping new libraries
vmap work work
vmap utility utility
vmap hdlc hdlc
vmap memLib memLib
# Compile files
# Utility Files
vcom -work utility tools_pkg.vhd
#hdlc lib files
vcom -work hdlc PCK_CRC16_D8.vhd
 
#memLib lib files
vcom -work memLib spmem.vhd
vcom -work memLib mem_pkg.vhd
 
#Core files
vcom -work work TxFCS.vhd
vcom -work work TxBuff.vhd
 
#Simulation core files
vcom -work work TxTop_tb.vhd
 
#Load
#vsim work.txtop_ent_tb
/model/build_hdlc_top.do
0,0 → 1,70
vlib work
vlib utility
vlib hdlc
vlib memLib
 
vmap work
vmap utility
vmap hdlc
vmap memLib
 
 
# Utility files
vcom -work utility ../code/tools_pkg.vhd
 
 
#memLib
vcom -work memLib ../code/spmem.vhd
 
vcom -work memLib ../code/mem_pkg.vhd
 
 
#HDLC files
vcom -work hdlc ../code/libs/PCK_CRC16_D8.vhd
 
vcom -work hdlc ../code/libs/hdlc_components_pkg.vhd
 
#Work files
#Rx
vcom -work work ../code/TOP/core/RxFCS.vhd
 
vcom -work work ../code/TOP/core/RxBuff.vhd -explicit
 
vcom -work work ../code/Rx/core/Zero_detect.vhd
 
vcom -work work ../code/Rx/core/flag_detect.vhd
 
vcom -work work ../code/Rx/core/Rxcont.vhd
 
 
vcom -work work ../code/Rx/core/RxChannel.vhd
 
vcom -work work ../code/TOP/core/RxSync.vhd
 
 
#Tx
vcom -work work ../code/TOP/core/TxFCS.vhd
 
vcom -work work ../code/TOP/core/TxBuff.vhd -explicit
 
vcom -work work ../code/Tx/core/flag_ins.vhd
 
vcom -work work ../code/Tx/core/zero_ins.vhd
 
vcom -work work ../code/Tx/core/TXcont.vhd
 
 
vcom -work work ../code/Tx/core/TxChannel.vhd
 
vcom -work work ../code/TOP/core/TxSync.vhd
 
 
#WB and host
vcom -work work ../code/TOP/core/WB_IF.vhd
 
vcom -work work ../code/TOP/core/hdlc.vhd
 
# Test bench
vcom -work work ../code/TOP/tb/hdlc_tb.vhd -explicit
 
 
/nc-sim/build_RxFCS_Buff.csh
0,0 → 1,32
#! /bin/tcsh -f
mkdir -p work
mkdir -p utility
mkdir -p hdlc
mkdir -p memLib
 
# Utility files
ncvhdl -work utility -cdslib ./cds.lib -logfile ncvhdl.log -errormax 15 -append_log -v93 -linedebug -messages -status ./tools_pkg.vhd
 
 
#memLib
ncvhdl -work memLib -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./spmem.vhd
 
ncvhdl -work memLib -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./mem_pkg.vhd
 
 
 
#HDLC files
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./PCK_CRC16_D8.vhd
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./hdlc_components_pkg.vhd
 
#Work files
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./RxFCS.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./RxBuff.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./RxTop_tb.vhd
 
 
#elaborating design
ncelab -work work -cdslib /home/jamil/Designs/hdlc/cds.lib -logfile ncelab.log -errormax 15 -messages -status -v93 -coverage work.rxtop_ent_tb:rxtop_beh_tb
/nc-sim/build_TxFCS_Buff.csh
0,0 → 1,30
#! /bin/tcsh -f
mkdir -p work
mkdir -p utility
mkdir -p hdlc
mkdir -p memLib
 
# Utility files
ncvhdl -work utility -cdslib ./cds.lib -logfile ncvhdl.log -errormax 15 -append_log -v93 -linedebug -messages -status ./tools_pkg.vhd
 
 
#memLib
ncvhdl -work memLib -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./spmem.vhd
 
ncvhdl -work memLib -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./mem_pkg.vhd
 
 
 
#HDLC files
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./PCK_CRC16_D8.vhd
 
#Work files
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./TxFCS.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./TxBuff.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ./Txtop_tb.vhd
 
 
#elaborating design
ncelab -work work -cdslib /home/jamil/Designs/hdlc/cds.lib -logfile ncelab.log -errormax 15 -messages -status -v93 work.txtop_ent_tb:txtop_beh_tb
/nc-sim/build_hdlc_top.csh
0,0 → 1,68
#! /bin/tcsh -f
mkdir -p work
mkdir -p utility
mkdir -p hdlc
mkdir -p memLib
 
# Utility files
ncvhdl -work utility -cdslib ./cds.lib -logfile ncvhdl.log -errormax 15 -append_log -v93 -linedebug -messages -status ../code/tools_pkg.vhd
 
 
#memLib
ncvhdl -work memLib -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/spmem.vhd
 
ncvhdl -work memLib -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/mem_pkg.vhd
 
 
 
#HDLC files
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/libs/PCK_CRC16_D8.vhd
 
ncvhdl -work hdlc -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/libs/hdlc_components_pkg.vhd
 
#Work files
#Rx
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TOP/core/RxFCS.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TOP/core/RxBuff.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/RX/core/Zero_detect.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/RX/core/flag_detect.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/RX/core/Rxcont.vhd
 
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/RX/core/RxChannel.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TOP/core/RxSync.vhd
 
 
#Tx
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TOP/core/TxFCS.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TOP/core/TxBuff.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TX/core/flag_ins.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TX/core/zero_ins.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TX/core/TXcont.vhd
 
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TX/core/TxChannel.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TOP/core/TxSync.vhd
 
 
 
#WB and host
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TOP/core/WB_IF.vhd
 
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TOP/core/hdlc.vhd
 
# Test bench
ncvhdl -work work -cdslib ./cds.lib -logfile ncvhdl.log -append_log -errormax 15 -update -v93 -linedebug -messages -status ../code/TOP/tb/hdlc_tb.vhd
 
#elaborating design
ncelab -work work -cdslib ./cds.lib -logfile ncelab.log -errormax 15 -messages -status -v93 work.hdlc_tb:hdlc_beh_tb
/nc-sim/cds.lib
0,0 → 1,7
include $CDS_INST_DIR/tools/inca/files/cds.lib
 
undefine ambit
define work ./work
define utility ./utility
define hdlc ./hdlc
define memLib ./memLib
/nc-sim/hdl.var
0,0 → 1,4
DEFINE work work
DEFINE hdlc hdlc
DEFINE memLib memLib
DEFINE utility utility

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.