URL
https://opencores.org/ocsvn/hdlc/hdlc/trunk
Subversion Repositories hdlc
Compare Revisions
- This comparison shows the changes necessary to convert path
/hdlc/trunk/CODE/TX
- from Rev 15 to Rev 17
- ↔ Reverse comparison
Rev 15 → Rev 17
/core/TxChannel.vhd
0,0 → 1,113
------------------------------------------------------------------------------- |
-- Title : Tx Channel |
-- Project : HDLC controller |
------------------------------------------------------------------------------- |
-- File : Txchannel.vhd |
-- Author : Jamil Khatib (khatib@ieee.org) |
-- Organization: OpenIPCore Project |
-- Created :2001/01/11 |
-- Last update: 2001/01/26 |
-- Platform : |
-- Simulators : Modelsim 5.3XE/Windows98 |
-- Synthesizers: |
-- Target : |
-- Dependency : ieee.std_logic_1164 |
-- |
------------------------------------------------------------------------------- |
-- Description: Transmit Channel |
------------------------------------------------------------------------------- |
-- Copyright (c) 2000 Jamil Khatib |
-- |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- You can check the draft license at |
-- http://www.opencores.org/OIPC/license.shtml |
|
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : 1 |
-- Version : 0.1 |
-- Date : 16 Jan 2001 |
-- Modifier : Jamil Khatib (khatib@ieee.org) |
-- Desccription : Created |
-- ToOptimize : |
-- Bugs : |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
library hdlc; |
use hdlc.hdlc_components_pkg.all; |
|
entity TxChannel_ent is |
|
port ( |
TxClk : in std_logic; -- Tx Clock |
rst_n : in std_logic; -- System Reset |
TXEN : in std_logic; -- Tx Enable |
Tx : out std_logic; -- Tx serial Output |
ValidFrame : in std_logic; -- Valid Frame |
AbortFrame : in std_logic; -- Abort Frame |
AbortedTrans : out std_logic; -- Aborted transmission |
WriteByte : in std_logic; -- Write byte |
rdy : out std_logic; -- Ready signal |
TxData : in std_logic_vector(7 downto 0)); -- Tx Data bus |
|
end TxChannel_ent; |
|
|
architecture Txchannel_str of TxChannel_ent is |
|
signal TXD_i : std_logic; -- Internal TX signal |
signal enable_i : std_logic; -- Internal Enable |
signal abortedTrans_i : std_logic; -- Backend no valid data |
signal AbortTrans_i : std_logic; -- Internal Abort transmission signal |
signal Frame_i : std_logic; |
-- Internal Frame strobe to flag insert block |
signal inProgress_i : std_logic; -- In progress internal signal |
|
signal BackendEnable_i : std_logic; -- Backend Enable |
begin -- Txchannel_str |
|
AbortedTrans <= abortedTrans_i; |
|
FlagMachine : flag_ins_ent |
port map ( |
TXclk => TXclk, |
rst_n => rst_n, |
TX => TX, |
TXEN => TXEN, |
TXD => TXD_i, |
AbortFrame => AbortTrans_i, |
Frame => Frame_i); |
|
BackendMachine : ZeroIns_ent |
port map ( |
TxClk => TxClk, |
rst_n => rst_n, |
enable => TXEN, |
BackendEnable => BackendEnable_i, |
abortedTrans => abortedTrans_i, |
inProgress => inProgress_i, |
ValidFrame => ValidFrame, |
Writebyte => Writebyte, |
rdy => rdy, |
TXD => TXD_i, |
Data => TxData); |
|
Txcontroller : TxCont_ent |
port map ( |
TXclk => TXclk, |
rst_n => rst_n, |
TXEN => TXEN, |
enable => enable_i, |
BackendEnable => BackendEnable_i, |
abortedTrans => abortedTrans_i, |
inProgress => inProgress_i, |
Frame => Frame_i, |
ValidFrame => ValidFrame, |
AbortFrame => AbortFrame, |
AbortTrans => AbortTrans_i); |
|
end Txchannel_str; |
/core/TXcont.vhd
0,0 → 1,201
------------------------------------------------------------------------------- |
-- Title : TX controller |
-- Project : HDLC controller |
------------------------------------------------------------------------------- |
-- File : TxCont.vhd |
-- Author : Jamil Khatib (khatib@ieee.org) |
-- Organization: OpenIPCore Project |
-- Created :2001/01/15 |
-- Last update:2001/10/26 |
-- Platform : |
-- Simulators : Modelsim 5.3XE/Windows98 |
-- Synthesizers: |
-- Target : |
-- Dependency : ieee.std_logic_1164 |
-- |
------------------------------------------------------------------------------- |
-- Description: Transmit controller |
------------------------------------------------------------------------------- |
-- Copyright (c) 2000 Jamil Khatib |
-- |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- You can check the draft license at |
-- http://www.opencores.org/OIPC/license.shtml |
|
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : 1 |
-- Version : 0.1 |
-- Date : 15 Jan 2001 |
-- Modifier : Jamil Khatib (khatib@ieee.org) |
-- Desccription : Created |
-- ToOptimize : |
-- Bugs : |
------------------------------------------------------------------------------- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
ENTITY TxCont_ent IS |
|
PORT ( |
TXclk : IN STD_LOGIC; -- TX clock |
rst_n : IN STD_LOGIC; -- System Reset |
TXEN : IN STD_LOGIC; -- TX enable |
enable : OUT STD_LOGIC; -- Enable control |
BackendEnable : OUT STD_LOGIC; -- Backend Enable |
abortedTrans : IN STD_LOGIC; -- No Valid data from the backend |
inProgress : IN STD_LOGIC; -- Data in progress |
ValidFrame : IN STD_LOGIC; -- Valid Frame |
Frame : OUT STD_LOGIC; -- Frame strobe |
AbortFrame : IN STD_LOGIC; -- AbortFrame |
AbortTrans : OUT STD_LOGIC); -- Abort data transmission |
|
END TxCont_ent; |
------------------------------------------------------------------------------- |
ARCHITECTURE TxCont_beh OF TxCont_ent IS |
|
BEGIN -- TxCont_beh |
|
-- purpose: Abort Machine |
-- type : sequential |
-- inputs : Txclk, rst_n |
-- outputs: |
abort_proc : PROCESS (Txclk, rst_n) |
|
VARIABLE counter : INTEGER RANGE 0 TO 14; -- Counter |
|
VARIABLE state : STD_LOGIC; -- Internal State |
-- state ==> '0' No abort signal |
-- state ==> '1' Abort signal |
BEGIN -- process abort_proc |
IF rst_n = '0' THEN -- asynchronous reset (active low) |
AbortTrans <= '0'; |
Counter := 0; |
enable <= '1'; |
state := '0'; |
ELSIF Txclk'event AND Txclk = '1' THEN -- rising clock edge |
IF TXEN = '1' THEN |
|
CASE state IS |
|
WHEN '0' => |
IF abortedTrans = '1' OR AbortFrame = '1' THEN |
state := '1'; |
Counter := 0; |
END IF; |
AbortTrans <= '0'; |
|
WHEN '1' => |
IF counter = 8 THEN |
counter := 0; |
IF abortedTrans = '0' AND AbortFrame = '0' THEN |
|
state := '0'; |
AbortTrans <= '0'; |
ELSE |
AbortTrans <= '1'; |
END IF; |
|
ELSE |
counter := counter +1; |
END IF; -- counter |
|
WHEN OTHERS => NULL; |
|
END CASE; |
END IF; -- TXEN |
enable <= TXEN; |
|
END IF; -- TXclk |
END PROCESS abort_proc; |
|
-- purpose: Flag Controller |
-- type : sequential |
-- inputs : Txclk, rst_n |
-- outputs: |
Flag_proc : PROCESS (Txclk, rst_n) |
|
VARIABLE state : STD_LOGIC_VECTOR(2 DOWNTO 0); -- Internal State machine |
VARIABLE counter : INTEGER RANGE 0 TO 16; -- Internal counter |
|
BEGIN -- process Flag_proc |
IF rst_n = '0' THEN -- asynchronous reset (active low) |
Frame <= '0'; |
state := (OTHERS => '0'); |
counter := 0; |
BackendEnable <= '0'; |
ELSIF Txclk'event AND Txclk = '1' THEN -- rising clock edge |
IF TXEN = '1' THEN |
|
CASE state IS |
WHEN "000" => -- Check Valid Frame |
Frame <= '0'; |
IF ValidFrame = '1' THEN |
state := "001"; |
BackendEnable <= '1'; |
ELSE |
BackendEnable <= '0'; |
END IF; |
counter := 0; |
|
WHEN "001" => |
|
IF counter > 1 AND inProgress = '0' THEN |
state := "010"; |
Frame <= '1'; |
ELSE |
Frame <= '0'; |
END IF; |
|
IF inProgress = '0' THEN |
counter := counter +1; |
END IF; |
|
BackendEnable <= '1'; |
|
WHEN "010" => -- Check ValidFrame |
|
Frame <= '1'; |
|
IF ValidFrame = '0' THEN |
state := "011"; |
BackendEnable <= '0'; |
ELSE |
BackendEnable <= '1'; |
END IF; |
|
counter := 0; |
|
WHEN "011" => |
IF counter > 2 AND inProgress = '0' THEN |
state := "100"; |
END IF; |
Frame <= '1'; |
|
IF inProgress = '0' THEN |
counter := counter +1; |
END IF; |
|
BackendEnable <= '0'; |
|
WHEN "100" => |
|
IF counter = 10 THEN |
counter := 0; |
state := "000"; |
Frame <= '0'; |
ELSE |
counter := counter + 1; |
Frame <= '1'; |
END IF; |
|
BackendEnable <= '0'; |
|
WHEN OTHERS => NULL; |
END CASE; |
END IF; -- TXEN |
END IF; |
END PROCESS Flag_proc; |
------------------------------------------------------------------------------- |
END TxCont_beh; |
/core/zero_ins.vhd
0,0 → 1,187
------------------------------------------------------------------------------- |
-- Title : Zero Insertion |
-- Project : HDLC controller |
------------------------------------------------------------------------------- |
-- File : zero_ins.vhd |
-- Author : Jamil Khatib (khatib@ieee.org) |
-- Organization: OpenIPCore Project |
-- Created : 2001/01/12 |
-- Last update:2001/10/20 |
-- Platform : |
-- Simulators : Modelsim 5.3XE/Windows98 |
-- Synthesizers: |
-- Target : |
-- Dependency : ieee.std_logic_1164 |
-- |
------------------------------------------------------------------------------- |
-- Description: Zero Insertion |
------------------------------------------------------------------------------- |
-- Copyright (c) 2000 Jamil Khatib |
-- |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- You can check the draft license at |
-- http://www.opencores.org/OIPC/license.shtml |
|
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : 1 |
-- Version : 0.1 |
-- Date : 12 Jan 2001 |
-- Modifier : Jamil Khatib (khatib@ieee.org) |
-- Desccription : Created |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : 2 |
-- Version : 0.2 |
-- Date : 27 May 2001 |
-- Modifier : Jamil Khatib (khatib@ieee.org) |
-- Desccription : Tx zero insertion bug fixed |
-- Zero is inserted after 5 sequence of 1's insted of 6 1's |
------------------------------------------------------------------------------- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.2 2001/05/28 19:14:22 khatib |
-- TX zero insertion bug fixed |
-- |
------------------------------------------------------------------------------- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
ENTITY ZeroIns_ent IS |
|
PORT ( |
TxClk : IN STD_LOGIC; -- Tx clock |
rst_n : IN STD_LOGIC; -- system reset |
enable : IN STD_LOGIC; -- enable (Driven by controller) |
inProgress : OUT STD_LOGIC; -- Data in progress |
BackendEnable : IN STD_LOGIC; -- Backend Enable |
-- backend interface |
abortedTrans : OUT STD_LOGIC; -- aborted Transmission |
ValidFrame : IN STD_LOGIC; -- Valid Frame signal |
Writebyte : IN STD_LOGIC; -- Back end write byte |
rdy : OUT STD_LOGIC; -- data ready |
TXD : OUT STD_LOGIC; -- TX serial data |
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0)); -- TX data bus |
|
END ZeroIns_ent; |
------------------------------------------------------------------------------- |
ARCHITECTURE zero_ins_beh OF ZeroIns_ent IS |
|
SIGNAL data_reg : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Data register (used as |
-- internal buffer) |
SIGNAL flag : STD_LOGIC; -- control signal between processes |
SIGNAL delay_TX : STD_LOGIC; -- Delayed output |
|
BEGIN -- zero_ins_beh |
|
|
-- purpose: Parallel to Serial |
-- type : sequential |
-- inputs : TxClk, rst_n |
-- outputs: |
P2S_proc : PROCESS (TxClk, rst_n) |
VARIABLE tmp_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); -- Temp Shift register |
VARIABLE counter : INTEGER RANGE 0 TO 8; -- Counter |
VARIABLE OnesDetected : STD_LOGIC; -- 6 ones detected |
|
BEGIN -- process P2S_proc |
IF rst_n = '0' THEN -- asynchronous reset (active low) |
|
tmp_reg := (OTHERS => '0'); |
Counter := 0; |
flag <= '1'; |
OnesDetected := '0'; |
TXD <= '1'; |
delay_TX <= '1'; |
inProgress <= '0'; |
|
ELSIF TxClk'event AND TxClk = '1' THEN -- rising clock edge |
IF enable = '1' THEN |
|
OnesDetected := tmp_reg(0) AND tmp_reg(1) AND tmp_reg(2) AND tmp_reg(3) AND tmp_reg(4); |
|
delay_TX <= tmp_reg(0); |
TXD <= delay_TX; |
|
IF OnesDetected = '1' THEN |
-- Zero insertion |
tmp_reg(4 DOWNTO 0) := '0' & tmp_reg(4 DOWNTO 1); |
|
ELSE |
-- Total Shift |
tmp_reg(15 DOWNTO 0) := '0' & tmp_reg(15 DOWNTO 1); |
|
Counter := Counter +1; |
|
END IF; -- ones detected |
|
IF counter = 8 THEN |
|
counter := 0; |
flag <= '1'; |
inProgress <= '0'; |
|
tmp_reg(15 DOWNTO 8) := data_reg; |
ELSE |
inProgress <= '1'; |
flag <= '0'; |
END IF; -- counter |
END IF; -- enable |
END IF; -- clk |
END PROCESS P2S_proc; |
------------------------------------------------------------------------------- |
|
-- purpose: Backend Interface |
-- type : sequential |
-- inputs : TxClk, rst_n |
-- outputs: |
Backend_proc : PROCESS (TxClk, rst_n) |
VARIABLE state : STD_LOGIC; -- Backend state |
|
BEGIN -- process Backend_proc |
IF rst_n = '0' THEN -- asynchronous reset (active low) |
state := '0'; |
data_reg <= (OTHERS => '0'); |
rdy <= '0'; |
abortedTrans <= '0'; |
ELSIF TxClk'event AND TxClk = '1' THEN -- rising clock edge |
IF enable = '1' THEN |
IF BackendEnable = '1' THEN |
CASE state IS |
WHEN '0' => -- wait for reading the register |
IF flag = '1' THEN -- Register has been read |
state := '1'; |
rdy <= '1'; |
data_reg <= "00000000"; -- set register to known pattern to |
-- avoid invalid read (upon valid |
-- read this value will be overwritten) |
END IF; |
|
WHEN '1' => |
IF WriteByte = '1' THEN |
state := '0'; |
rdy <= '0'; |
data_reg <= Data; |
ELSIF flag = '1' THEN -- Another flag but without read |
state := '0'; |
rdy <= '0'; |
data_reg <= "00000000"; |
abortedTrans <= '1'; |
END IF; |
|
WHEN OTHERS => NULL; |
END CASE; |
|
ELSE |
rdy <= '0'; |
state := '0'; |
abortedTrans <= '0'; |
END IF; -- Backend enable |
|
END IF; -- enable |
END IF; -- Txclk |
END PROCESS Backend_proc; |
|
|
END zero_ins_beh; |
/core/flag_ins.vhd
0,0 → 1,122
------------------------------------------------------------------------------- |
-- Title : Flag insertion block |
-- Project : HDLC controller |
------------------------------------------------------------------------------- |
-- File : flag_ins.vhd |
-- Author : Jamil Khatib (khatib@ieee.org) |
-- Organization: OpenIPCore Project |
-- Created :2001/01/11 |
-- Last update: 2001/01/26 |
-- Platform : |
-- Simulators : Modelsim 5.3XE/Windows98 |
-- Synthesizers: |
-- Target : |
-- Dependency : ieee.std_logic_1164 |
-- |
------------------------------------------------------------------------------- |
-- Description: Transmit and insert flag and idle patterns |
------------------------------------------------------------------------------- |
-- Copyright (c) 2000 Jamil Khatib |
-- |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- You can check the draft license at |
-- http://www.opencores.org/OIPC/license.shtml |
|
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : 1 |
-- Version : 0.1 |
-- Date : 11 Jan 2001 |
-- Modifier : Jamil Khatib (khatib@ieee.org) |
-- Desccription : Created |
-- ToOptimize : |
-- Bugs : |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity flag_ins_ent is |
|
port ( |
TXclk : in std_logic; -- TX clock |
rst_n : in std_logic; -- system reset |
TX : out std_logic; -- TX data |
TXEN : in std_logic; -- TX enable |
TXD : in std_logic; -- TX input data |
AbortFrame : in std_logic; -- Abort Current Frame |
Frame : in std_logic); -- Valid Frame |
|
end flag_ins_ent; |
|
|
architecture flag_ins_beh of flag_ins_ent is |
|
begin -- flag_ins_beh |
|
-- purpose: Tranmit process |
-- type : sequential |
-- inputs : TXclk, rst_n |
-- outputs: |
process (TXclk, rst_n) |
|
variable transmit_reg : std_logic_vector(7 downto 0); -- Transmit Register |
variable state : std_logic; -- Internal state |
|
begin -- process |
if rst_n = '0' then -- asynchronous reset (active low) |
|
transmit_reg := (others => '1'); |
state := '0'; |
TX <= '1'; |
|
elsif TXclk'event and TXclk = '1' then -- rising clock edge |
|
if TXEN = '1' then |
|
case state is |
-- idle state |
when '0' => |
|
TX <= transmit_reg(0); |
|
transmit_reg(7 downto 0) := '1' & transmit_reg(7 downto 1); |
|
if Frame = '1' and AbortFrame = '0' then |
state := '1'; |
transmit_reg := "01111110"; |
end if; |
|
-- Normal operation |
when '1' => |
|
TX <= transmit_reg(0); |
|
transmit_reg(7 downto 0) := TXD & transmit_reg(7 downto 1); |
|
if AbortFrame = '1' then |
|
transmit_reg := "11111110"; |
state := '0'; |
|
elsif Frame = '0' then |
|
transmit_reg := "01111110"; |
state := '0'; |
|
end if; |
|
when others => null; |
|
end case; |
|
else |
|
TX <= '1'; |
|
end if; -- end TXEN |
end if; -- end TXclk |
end process; |
|
end flag_ins_beh; |
/tb/tx_tb.vhd
0,0 → 1,157
------------------------------------------------------------------------------- |
-- Title : Tx Channel test bench |
-- Project : HDLC controller |
------------------------------------------------------------------------------- |
-- File : tx_tb.vhd |
-- Author : Jamil Khatib (khatib@ieee.org) |
-- Organization: OpenIPCore Project |
-- Created :2001/01/16 |
-- Last update: 2001/01/26 |
-- Platform : |
-- Simulators : Modelsim 5.3XE/Windows98 |
-- Synthesizers: |
-- Target : |
-- Dependency : ieee.std_logic_1164 |
-- |
------------------------------------------------------------------------------- |
-- Description: Transmit Channel test bench |
------------------------------------------------------------------------------- |
-- Copyright (c) 2000 Jamil Khatib |
-- |
-- This VHDL design file is an open design; you can redistribute it and/or |
-- modify it and/or implement it after contacting the author |
-- You can check the draft license at |
-- http://www.opencores.org/OIPC/license.shtml |
|
------------------------------------------------------------------------------- |
-- Revisions : |
-- Revision Number : 1 |
-- Version : 0.1 |
-- Date : 16 Jan 2001 |
-- Modifier : Jamil Khatib (khatib@ieee.org) |
-- Desccription : Created |
-- ToOptimize : |
-- Bugs : |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
library hdlc; |
use hdlc.hdlc_components_pkg.all; |
|
entity tx_tb_ent is |
|
end tx_tb_ent; |
|
architecture tx_tb_beh of tx_tb_ent is |
type streem is array (0 to 3) of std_logic_vector(7 downto 0); |
constant dataStreem : streem := ("10010110", "11111111", "01101101", "10010011"); |
|
signal TxClk : std_logic := '0'; -- System clock |
signal rst_n : std_logic := '0'; -- system reset |
signal TXEN : std_logic; -- TX enable |
signal TX : std_logic; -- Transmit serial data |
signal ValidFrame : std_logic := '0'; -- ValidFrame |
signal AbortFrame : std_logic; -- Abort Frame |
signal AbortedTrans : std_logic; -- Aborted transmission |
signal WriteByte : std_logic := '0'; -- Backend Write byte |
signal rdy : std_logic; -- Backend Ready |
signal TxData : std_logic_vector(7 downto 0); -- Backend data bus |
|
begin -- tx_tb_beh |
|
uut : TxChannel_ent |
port map ( |
TxClk => TxClk, |
rst_n => rst_n, |
TXEN => TXEN, |
Tx => Tx, |
ValidFrame => ValidFrame, |
AbortFrame => AbortFrame, |
AbortedTrans => AbortedTrans, |
WriteByte => WriteByte, |
rdy => rdy, |
TxData => TxData); |
|
------------------------------------------------------------------------------- |
|
Txclk <= not Txclk after 20 ns; |
|
rst_n <= '0', |
'1' after 30 ns; |
|
TxEn <= '1'; --, |
-- '0' after 960 ns, |
-- '1' after 1280 ns; |
|
AbortFrame <= '0'; |
|
------------------------------------------------------------------------------- |
-- purpose: Serial Interface |
-- type : sequential |
-- inputs : TxClk, rst |
-- outputs: |
Serial_Interface : process (TxClk, rst_n) |
variable output : std_logic_vector(7 downto 0) := "00000000"; |
-- Output regieter |
variable counter : integer := 0; -- Counter |
|
begin -- process Serial Interface |
if rst_n = '0' then -- asynchronous reset (active low) |
|
output := (others => '0'); |
Counter := 0; |
|
elsif TxClk'event and TxClk = '1' then -- rising clock edge |
|
output := TX & output(7 downto 1); |
Counter := Counter +1; |
|
if counter = 7 then |
counter := 0; |
end if; |
|
end if; |
end process Serial_Interface; |
----------------------------------------------------------------------------- |
|
-- purpose: Backend process |
-- type : combinational |
-- inputs : |
-- outputs: |
backend_proc : process |
variable counter : integer := 6; -- counter |
|
begin -- process backend_proc |
|
for i in 0 to dataStreem'length-1 loop |
|
if counter = 6 then |
ValidFrame <= '0' after 330 ns, |
'1' after 640 ns; |
counter := 0; |
end if; |
|
wait until rdy = '1'; |
|
WriteByte <= '1' after 30 ns; |
|
TxData <= dataStreem(i); |
|
counter := counter +1; |
|
wait until rdy = '0'; |
WriteByte <= '0' after 10 ns; |
|
end loop; -- i |
|
end process backend_proc; |
--Used to check the Abort Condition |
-- WriteByte <= '1' after 730 ns, |
-- '0' after 750 ns, |
-- '1' after 1310 ns, |
-- '0' after 1340 ns, |
-- '1' after 1980 ns, |
-- '0' after 2000 ns; |
end tx_tb_beh; |
/scripts/wave.do
0,0 → 1,29
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
virtual signal -install /tx_tb_ent/uut/flagmachine { (context /tx_tb_ent/uut/flagmachine )(line__62/transmit_reg & txd )} TransmitLine |
virtual signal -install /tx_tb_ent/uut/backendmachine { (context /tx_tb_ent/uut/backendmachine )(p2s_proc/tmp_reg & txd )} toTrans |
add wave -noupdate -format Logic /tx_tb_ent/txen |
add wave -noupdate -format Logic /tx_tb_ent/txclk |
add wave -noupdate -format Logic /tx_tb_ent/rst_n |
add wave -noupdate -format Logic /tx_tb_ent/abortframe |
add wave -noupdate -format Logic /tx_tb_ent/abortedtrans |
add wave -noupdate -format Logic /tx_tb_ent/uut/flagmachine/abortframe |
add wave -noupdate -format Logic /tx_tb_ent/uut/txcontroller/abortedtrans |
add wave -noupdate -format Logic /tx_tb_ent/writebyte |
add wave -noupdate -format Logic /tx_tb_ent/rdy |
add wave -noupdate -format Logic /tx_tb_ent/validframe |
add wave -noupdate -format Logic /tx_tb_ent/uut/txcontroller/frame |
add wave -noupdate -format Logic /tx_tb_ent/uut/backendmachine/backendenable |
add wave -noupdate -format Logic /tx_tb_ent/uut/backendmachine/inprogress |
add wave -noupdate -format Logic /tx_tb_ent/uut/backendmachine/enable |
add wave -noupdate -format Literal /tx_tb_ent/txdata |
add wave -noupdate -format Literal /tx_tb_ent/backend_proc/counter |
add wave -noupdate -format Literal /tx_tb_ent/serial_interface/output |
add wave -noupdate -format Literal -label TransmitLine /tx_tb_ent/uut/flagmachine/TransmitLine |
add wave -noupdate -format Literal -label toTrans /tx_tb_ent/uut/backendmachine/toTrans |
add wave -noupdate -format Literal /tx_tb_ent/uut/txcontroller/flag_proc/state |
add wave -noupdate -format Literal /tx_tb_ent/uut/flagmachine/line__62/transmit_reg |
add wave -noupdate -format Literal /tx_tb_ent/uut/backendmachine/p2s_proc/tmp_reg |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {1700 ns} |
WaveRestoreZoom {0 ps} {7051122 ps} |