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URL https://opencores.org/ocsvn/hf-risc/hf-risc/trunk

Subversion Repositories hf-risc

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  • This comparison shows the changes necessary to convert path 
    /hf-risc/trunk/hf-risc/platform/spartan3e_nexys2
    from Rev 15 to Rev 18
    ↔ Reverse comparison
  •

Rev 15 → Rev 18

/spartan3e_nexys2.vhd
2,7 → 2,7
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity hellfire_cpu_if is
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
14,11 → 14,11
uart_read: in std_logic;
uart_write: out std_logic
);
end hellfire_cpu_if;
end hfrisc_soc;
 
architecture interface of hellfire_cpu_if is
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
begin
69,13 → 69,10
port map( clock => clock,
reset => reset,
stall => stall_cpu,
busy => busy_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
inst_addr => inst_addr_cpu,
inst_in => inst_in_cpu,
data_addr => data_addr_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
94,13 → 91,10
stall => stall,
 
stall_cpu => stall_cpu,
busy_cpu => busy_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
inst_addr_cpu => inst_addr_cpu,
inst_in_cpu => inst_in_cpu,
data_addr_cpu => data_addr_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
185,5 → 179,5
data_o => data_read_ram(31 downto 24)
);
 
end interface;
end top_level;
 
/spartan3e_nexys2_xtea.vhd
2,7 → 2,7
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity hellfire_cpu_if is
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
14,11 → 14,11
uart_read: in std_logic;
uart_write: out std_logic
);
end hellfire_cpu_if;
end hfrisc_soc;
 
architecture interface of hellfire_cpu_if is
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
 
68,33 → 68,39
 
 
 
process (data_addr_cpu, key, input, output)
process (clock, reset, address_cpu, key, input, output)
begin
case data_addr_cpu(7 downto 4) is
when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
data_read_xtea <= x"000000" & "00000" & ready & control;
when "0001" => -- key[0] 0xfa000010
data_read_xtea <= key(127 downto 96);
when "0010" => -- key[1] 0xfa000020
data_read_xtea <= key(95 downto 64);
when "0011" => -- key[2] 0xfa000030
data_read_xtea <= key(63 downto 32);
when "0100" => -- key[3] 0xfa000040
data_read_xtea <= key(31 downto 0);
when "0101" => -- input[0] 0xfa000050
data_read_xtea <= input(63 downto 32);
when "0110" => -- input[1] 0xfa000060
data_read_xtea <= input(31 downto 0);
when "0111" => -- output[0] 0xfa000070
data_read_xtea <= output(63 downto 32);
when "1000" => -- output[1] 0xfa000080
data_read_xtea <= output(31 downto 0);
when others =>
data_read_xtea <= (others => '0');
end case;
if reset = '1' then
data_read_xtea <= (others => '0');
elsif clock'event and clock = '1' then
if (ext_periph = '1') then -- XTEA is at 0xfa000000
case address_cpu(7 downto 4) is
when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
data_read_xtea <= x"000000" & "00000" & ready & control;
when "0001" => -- key[0] 0xfa000010
data_read_xtea <= key(127 downto 96);
when "0010" => -- key[1] 0xfa000020
data_read_xtea <= key(95 downto 64);
when "0011" => -- key[2] 0xfa000030
data_read_xtea <= key(63 downto 32);
when "0100" => -- key[3] 0xfa000040
data_read_xtea <= key(31 downto 0);
when "0101" => -- input[0] 0xfa000050
data_read_xtea <= input(63 downto 32);
when "0110" => -- input[1] 0xfa000060
data_read_xtea <= input(31 downto 0);
when "0111" => -- output[0] 0xfa000070
data_read_xtea <= output(63 downto 32);
when "1000" => -- output[1] 0xfa000080
data_read_xtea <= output(31 downto 0);
when others =>
data_read_xtea <= (others => '0');
end case;
end if;
end if;
end process;
 
process (clock, reset, data_addr_cpu, control, key, input, output)
process (clock, reset, address_cpu, control, key, input, output)
begin
if reset = '1' then
key <= (others => '0');
102,7 → 108,7
control <= "00";
elsif clock'event and clock = '1' then
if (ext_periph = '1' and data_we /= "0000") then -- XTEA is at 0xfa000000
case data_addr_cpu(7 downto 4) is
case address_cpu(7 downto 4) is
when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
control <= data_write(1 downto 0);
when "0001" => -- key[0] 0xfa000010
123,8 → 129,6
end if;
end process;
 
 
 
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
137,13 → 141,10
port map( clock => clock,
reset => reset,
stall => stall_cpu,
busy => busy_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
inst_addr => inst_addr_cpu,
inst_in => inst_in_cpu,
data_addr => data_addr_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
162,13 → 163,10
stall => stall,
 
stall_cpu => stall_cpu,
busy_cpu => busy_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
inst_addr_cpu => inst_addr_cpu,
inst_in_cpu => inst_in_cpu,
data_addr_cpu => data_addr_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
265,5 → 263,5
data_o => data_read_ram(31 downto 24)
);
 
end interface;
end top_level;
 

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