URL
https://opencores.org/ocsvn/hf-risc/hf-risc/trunk
Subversion Repositories hf-risc
Compare Revisions
- This comparison shows the changes necessary to convert path
/hf-risc/trunk/hf-risc/platform/virtex4_ml403
- from Rev 13 to Rev 18
- ↔ Reverse comparison
Rev 13 → Rev 18
/virtex4ml403.vhd
2,7 → 2,7
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
entity hellfire_cpu_if is |
entity hfrisc_soc is |
generic( |
address_width: integer := 16; |
memory_file : string := "code.txt"; |
13,16 → 13,14
uart_read: in std_logic; |
uart_write: out std_logic |
); |
end hellfire_cpu_if; |
end hfrisc_soc; |
|
architecture interface of hellfire_cpu_if is |
signal clock, reset, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly: std_logic; |
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0); |
architecture top_level of hfrisc_soc is |
signal clock, reset, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, rff1, ram_dly: std_logic; |
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0); |
signal ext_irq: std_logic_vector(7 downto 0); |
signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0); |
begin |
reset <= not reset_in; |
|
-- clock divider (50MHz clock from 100MHz main clock for ML403 kit) |
process (reset, clk_in, clock) |
begin |
69,13 → 67,10
port map( clock => clock, |
reset => reset, |
stall => stall_cpu, |
busy => busy_cpu, |
irq_vector => irq_vector_cpu, |
irq => irq_cpu, |
irq_ack => irq_ack_cpu, |
inst_addr => inst_addr_cpu, |
inst_in => inst_in_cpu, |
data_addr => data_addr_cpu, |
address => address_cpu, |
data_in => data_in_cpu, |
data_out => data_out_cpu, |
data_w => data_w_cpu, |
94,13 → 89,10
stall => stall, |
|
stall_cpu => stall_cpu, |
busy_cpu => busy_cpu, |
irq_vector_cpu => irq_vector_cpu, |
irq_cpu => irq_cpu, |
irq_ack_cpu => irq_ack_cpu, |
inst_addr_cpu => inst_addr_cpu, |
inst_in_cpu => inst_in_cpu, |
data_addr_cpu => data_addr_cpu, |
address_cpu => address_cpu, |
data_in_cpu => data_in_cpu, |
data_out_cpu => data_out_cpu, |
data_w_cpu => data_w_cpu, |
185,5 → 177,5
data_o => data_read_ram(31 downto 24) |
); |
|
end interface; |
end top_level; |
|