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URL https://opencores.org/ocsvn/hf-risc/hf-risc/trunk

Subversion Repositories hf-risc

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  • This comparison shows the changes necessary to convert path 
    /hf-risc/trunk/hf-risc/sim
    from Rev 13 to Rev 18
    ↔ Reverse comparison
  •

Rev 13 → Rev 18

/hf-risc_tb.vhd
10,15 → 10,15
address_width: integer := 16;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "yes"
uart_support : string := "no"
);
end tb;
 
architecture tb of tb is
signal clock_in, reset, busy_cpu, stall_cpu, data, stall, stall_sig: std_logic := '0';
signal clock_in, reset, stall_cpu, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
begin
62,13 → 62,10
port map( clock => clock_in,
reset => reset,
stall => stall_cpu,
busy => busy_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
inst_addr => inst_addr_cpu,
inst_in => inst_in_cpu,
data_addr => data_addr_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
88,13 → 85,10
stall => stall_sig,
 
stall_cpu => stall_cpu,
busy_cpu => busy_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
inst_addr_cpu => inst_addr_cpu,
inst_in_cpu => inst_in_cpu,
data_addr_cpu => data_addr_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
227,7 → 221,7
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, data_addr_cpu)
process(clock_in, address_cpu)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
235,7 → 229,7
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if data_addr_cpu = x"f00000d0" and data = '0' then
if address_cpu = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(6 downto 0));
if index /= 10 then

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