URL
https://opencores.org/ocsvn/hf-risc/hf-risc/trunk
Subversion Repositories hf-risc
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- This comparison shows the changes necessary to convert path
/hf-risc/trunk/hf-risc/ucore
- from Rev 13 to Rev 17
- ↔ Reverse comparison
Rev 13 → Rev 17
/datapath.vhd
32,7 → 32,7
signal read_reg1, read_reg2, write_reg, rs, rt, rd, target: std_logic_vector(4 downto 0); |
signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0); |
signal imm: std_logic_vector(15 downto 0); |
signal wreg, zero, less_than, br_link_ctl, branch_taken, branch_taken_dly, jump_taken, jump_taken_dly, stall_reg: std_logic; |
signal wreg, zero, less_than, br_link_ctl, branch_taken, jump_taken, stall_reg: std_logic; |
signal irq_ack_s, irq_ack_s_dly, bds: std_logic; |
|
-- control signals |
67,7 → 67,7
pc <= pc_next; |
pc_last <= pc; |
else |
if (reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1') and branch_taken_dly = '0' and jump_taken_dly = '0' then |
if (reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1') and bds = '0' then |
pc <= pc_last; |
end if; |
end if; |
94,8 → 94,6
if reset = '1' then |
irq_ack_s_dly <= '0'; |
bds <= '0'; |
branch_taken_dly <= '0'; |
jump_taken_dly <= '0'; |
mem_to_reg_ctl_dly <= '0'; |
stall_reg <= '0'; |
elsif clock'event and clock = '1' then |
109,8 → 107,6
else |
bds <= '0'; |
end if; |
branch_taken_dly <= branch_taken; |
jump_taken_dly <= jump_taken; |
end if; |
end if; |
end if; |
194,7 → 190,7
shift_ctl_r <= '0'; |
else |
if busy = '0' then |
if reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' or branch_taken_dly = '1' or jump_taken_dly = '1' then |
if reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' or bds = '1' then |
rs_r <= (others => '0'); |
rt_r <= (others => '0'); |
rd_r <= (others => '0'); |
/peripherals_busmux.vhd
1,4 → 1,4
-- HF-RISC v3.3 |
-- HF-RISC v3.4 |
-- Sergio Johann Filho, 2011 - 2016 |
-- |
-- *This is a quick and dirty organization of a 3-stage pipelined MIPS microprocessor. All registers / memory |
157,7 → 157,7
signal data_read_uart, data_write_uart: std_logic_vector(7 downto 0); |
signal enable_uart, enable_uart_read, enable_uart_write, uart_write_busy, uart_data_avail: std_logic; |
|
type pulse_state_type is (irq_idle, irq_intdly1, irq_intdly2, irq_int, irq_req, irq_ackn, irq_done); |
type pulse_state_type is (irq_idle, irq_int, irq_req, irq_ackn, irq_done); |
signal pulse_state: pulse_state_type; |
signal pulse_next_state: pulse_state_type; |
|
206,7 → 206,7
inst_in_cpu <= data_read_mem; |
|
-- peripheral register logic, write to peripheral registers |
process(clock, reset, counter_reg, data_addr_cpu, data_out_cpu, periph_access, periph_access_we, irq) |
process(clock, reset, counter_reg, data_addr_cpu, data_out_cpu, periph_access, periph_access_we, irq_ack_cpu) |
begin |
if reset = '1' then |
irq_vector_reg <= x"00000000"; |
227,29 → 227,28
if compare2_reg = counter_reg(23 downto 0) then |
compare2_trig <= '1'; |
end if; |
if irq = '0' then |
if periph_access = '1' and periph_access_we = '1' then |
case data_addr_cpu(7 downto 4) is |
when "0000" => -- IRQ_VECTOR |
irq_vector_reg <= data_out_cpu; |
when "0010" => -- IRQ_MASK |
irq_mask_reg <= data_out_cpu(15 downto 0); |
when "0011" => -- IRQ_STATUS |
irq_status_reg <= data_out_cpu(7 downto 0); |
when "0110" => -- IRQ_COMPARE |
compare_reg <= data_out_cpu; |
compare_trig <= '0'; |
when "0111" => -- IRQ_COMPARE2 |
compare2_reg <= data_out_cpu(23 downto 0); |
compare2_trig <= '0'; |
when "1001" => -- EXTIO_OUT |
extio_out_reg <= data_out_cpu(7 downto 0); |
when "1111" => -- UART_DIVISOR |
uart_divisor <= data_out_cpu(15 downto 0); |
when others => |
end case; |
end if; |
else |
if periph_access = '1' and periph_access_we = '1' then |
case data_addr_cpu(7 downto 4) is |
when "0000" => -- IRQ_VECTOR |
irq_vector_reg <= data_out_cpu; |
when "0010" => -- IRQ_MASK |
irq_mask_reg <= data_out_cpu(15 downto 0); |
when "0011" => -- IRQ_STATUS |
irq_status_reg <= data_out_cpu(7 downto 0); |
when "0110" => -- IRQ_COMPARE |
compare_reg <= data_out_cpu; |
compare_trig <= '0'; |
when "0111" => -- IRQ_COMPARE2 |
compare2_reg <= data_out_cpu(23 downto 0); |
compare2_trig <= '0'; |
when "1001" => -- EXTIO_OUT |
extio_out_reg <= data_out_cpu(7 downto 0); |
when "1111" => -- UART_DIVISOR |
uart_divisor <= data_out_cpu(15 downto 0); |
when others => |
end case; |
end if; |
if irq_ack_cpu = '1' then |
irq_status_reg(0) <= '0'; -- IRQ_STATUS (clear master int bit on interrupt) |
end if; |
end if; |
279,15 → 278,9
pulse_state <= pulse_next_state; |
case pulse_state is |
when irq_idle => |
if interrupt = '1' then |
pulse_next_state <= irq_intdly1; |
if interrupt = '1' and irq_status_reg(0) = '1' then |
pulse_next_state <= irq_int; |
end if; |
when irq_intdly1 => |
if irq_status_reg(0) = '1' then |
pulse_next_state <= irq_intdly2; |
end if; |
when irq_intdly2 => |
pulse_next_state <= irq_int; |
when irq_int => |
irq <= '1'; |
pulse_next_state <= irq_req; |